TWI602055B - Semiconductor memory device and programming method thereof - Google Patents

Description

Semiconductor storage device and programming method thereof

The present invention relates to a semiconductor storage device, and more particularly to a reverse (NAND) type flash memory and a programming method thereof.

In the NAND type flash memory, by repeatedly programming or erasing data, the charge retention characteristics are deteriorated due to the deterioration of the tunnel insulating film, or the threshold value is changed due to the charge trapped by the tunnel insulating film, thereby causing Bit error. An error detection correction (ECC) circuit is mounted as a countermeasure against such a bit error in Japanese Patent Laid-Open Publication No. 2010-152989. In addition, Japanese Patent Laid-Open Publication No. 2008-165805 discloses an error correction scheme for a multi-bit data of a NAND type flash memory in which a memory cell stores multibit data. Further, Japanese Laid-Open Patent Publication No. 2010-79486 discloses a flash memory in which a physical block having a corrected number of errors equal to or greater than a threshold is registered as a warning block to a table, and data is written. Lowers the priority order of the selection of the warning block.

Fig. 1 shows a main part of a NAND type flash memory in which an ECC circuit is mounted on a wafer. The programming data input from the external input/output terminal is loaded into the page buffer/sense circuit 10, and the loaded programming data is transferred to the ECC circuit 30 via the transfer circuit 20. The transfer circuit 20 includes a plurality of transistors capable of bidirectional data transfer, and each transistor is driven by a common control signal TG connected to the gate. The ECC circuit 30 performs an operation of the transferred program data, generates an error correction symbol for error detection and correction, and writes the error correction symbol back to a predetermined area of the page buffer/readout circuit 10. Next, the programming data and error correction symbols held by the page buffer/readout circuit 10 are programmed on the select page of the memory array.

2 is a flow chart of a conventional programming action. A program pulse is applied to the word line of the selected page, a voltage corresponding to the program material is set to the bit line, and a program pulse is applied to the selected page (S10). Next, a program verify (verify) of the selection page is performed (S20), thereby judging whether or not the programming of all the storage cells of the selected page is acceptable (S30). In the case where it is determined that the programming of all the storage cells is acceptable, the programming ends. In the case where there is a storage cell programmed to be unacceptable, it is determined whether the number of application of the program pulse reaches NMAX (S40). Here, NMAX refers to the maximum time allowed for programming or the number of times the maximum programming pulse is allowed to be programmed. In the case where NMAX is reached, the state of the program failure is notified to the external controller, and the block is managed as a bad block. On the other hand, if NMAX is not reached, a stepping pulse (Incremental Step Program Pulse, ISPP) is generated to generate a step pulse having a step voltage greater than the previous programming pulse (S50). , thereby applying the programming pulse to the selection page.

In an ECC function that does not use an external controller or the like, or a flash memory that does not have an ECC, the pass of the program check is based on the acceptance of all the bits. On the other hand, in the ECC function of the controller mounted on the outside or the flash memory in which the ECC is mounted on the chip, even if there is a part of the defective bit in the verification (the storage of the "0" programming failure) The cell can also be considered as qualified by repairing the condition with ECC. For example, if error detection and correction of m bits can be performed by ECC, it is theoretically possible to repair the defective bits of m bits at the maximum. When the maximum number of bits that can be repaired by ECC is set to Ncc, the maximum number of defective bits that can be regarded as qualified in the verification is Np, and the number of actual unqualified bits is set to Nf. Np is set in the manner of Ncc≧Np, and is preferably set to Ncc>Np. When Np≧Nf, the selection page contains the unqualified bit, but the unqualified bit can be repaired by the ECC, so the verification is judged to be suspected. Further, when the reading of the selected page is performed, the defective bit included in the selected page is detected as an error, and the data is corrected.

By making a suspected pass judgment, the program failure or bad block is reduced, the yield is improved, and the program disturb can be reduced by suppressing the number of times the program pulse is applied.

However, there is a problem as described below using a conventional programming method that is suspected to be qualified. For example, when the unqualified bit up to the k-bit is regarded as suspected to be qualified (Np=k), if the number of times the application pulse is applied before NMAX, the actual number of defective bits Nf is less than that at the time of verification. The programming is automatically terminated when it can be regarded as the time point of the largest number of unqualified bits Np that is suspected to be qualified. In other words, even if the number of times the programming pulse is applied is sufficiently smaller than NMAX, there is still room for the number of times that can be applied, and if Nf ≦ Np, it is judged to be suspected and the programming is completed. However, in a memory cell in which the programming is set to fail, there is also a pass that can be passed by the application of the next programming pulse. In the original case, such a memory cell is preferably not determined to be a defective bit. It is judged as a qualified bit. If there are many unqualified bits in the suspected pass, the other functions of the ECC are greatly limited.

The present invention has been made to solve such a conventional problem, and an object of the invention is to provide a semiconductor storage device capable of improving the yield of a programming failure and performing repair of defective storage cells.

The programming method of the NAND type flash memory of the present invention has the following steps: applying a program pulse to the selected page; determining whether the programming of the selected page is qualified or not; and when the determination is unqualified, the number of times the programming pulse is applied is not less than In the case of programming the optimum value of the allowable maximum value, a programming pulse is further applied to the selected page, and if the number of times the programming pulse is applied reaches the optimal value, if the selected page is a pre-specified number of defective bits, Then it is judged to be suspected to be qualified.

The programming method of the NAND type flash memory of the present invention comprises the steps of: receiving data to be programmed; determining whether the number of bits programmed by using the material to be programmed is a repair that can be repaired by using an error detecting and correcting component The number of bits is below; the error correction symbol is generated by the error detection and correction component; and the number of bits to be programmed when the data to be programmed is determined is the number of the repair bits In the following, programming for the selected page is ended by programming the normal error area of the selected page without programming the error correction symbol in the spare area.

The semiconductor storage device of the present invention includes: a memory array; an error detection and correction unit that generates an error correction symbol of the material to be programmed; and a programming component that reads the information to be programmed on the selection page of the memory array and The error correction symbol is programmed, and the programming component performs a process of applying a programming pulse to the selected page, and when it is determined that the programming of the selected page is unacceptable, the number of application of the programming pulse does not reach less than the allowable maximum of the programming. In the case of the optimum value, a program pulse is further applied to the selected page, and when the number of times the program pulse is applied reaches the optimum value, if the selected page is a predetermined number of defective bits, it is determined to be a pass.

The semiconductor storage device of the present invention includes: a memory array; an error detecting and correcting unit that generates an error correction symbol of the material to be programmed; and a programming component that corresponds to the programmed data and the error on the selected page of the memory array The correction symbol is programmed, and the number of bits of the programming component programmed by using the material to be programmed is less than the number of repair bits that can be repaired by the error detection/correction component, and is not in the normal area of the selected page. Programming is performed and the error correction symbols are programmed in the spare area to end programming of the selected page.

According to the present invention, the following processing is performed: when it is judged to be unacceptable in the verification of the program, in the case where the number of application of the program pulse does not reach the optimum value smaller than the allowable maximum value, the program pulse is further applied, in the case of the programming pulse When the number of times of application reaches the optimum value, if the selected page is the number of unqualified bits specified in advance, it is determined that the page is suspected to be qualified. Therefore, at least until the programming pulse reaches the optimum value, the pass or fail determination of all the bits is guaranteed. . As a result, it is possible to repair a memory cell that is otherwise acceptable from the failure determination.

Next, embodiments of the present invention will be described in detail with reference to the drawings. Here, a NAND type flash memory is exemplified as a preferred embodiment. In addition, it should be noted that in the drawings, the parts are emphasized in order to facilitate understanding, and the ratio to the actual elements is not the same.

A typical configuration of the flash memory in the embodiment of the present invention is shown in Fig. 3. However, the configuration of the flash memory shown here is an example, and the present invention is not necessarily limited to such a configuration. The flash memory 100 of the present embodiment comprises the following: a memory array 110 in which a plurality of memory cells are arranged in a matrix; an input/output buffer 120 connected to an external input/output terminal I/O, holding input /output data; ECC circuit 130, performing error detection and correction of data programmed in the memory array 110 or data read from the memory array 110; the address register 140 is received from the input/output buffer 120 The address data; the control unit 150 receives the command data from the input/output buffer 120 or a control signal from the outside to control each part; the word line selection circuit 160 receives the column address information Ax from the address register 140. Decoding the column address information Ax, selecting a block and selecting a word line based on the decoding result, etc.; the page buffer/readout circuit 170, holding the page read by the free word line selection circuit 160 Data, or keep the write data for the selected page; the row selection circuit 180 receives the row address information Ay from the address register 140, decodes the row address information Ay, and based on the decoding node The selection of data in the page buffer/readout circuit 170 is performed, and the internal voltage generating circuit 190 generates various voltages required for reading, programming, and erasing of data (write voltage Vpgm, pass voltage Vpass). , read voltage Vread, erase voltage Vers, etc.).

The memory array 110 has m memory blocks BLK(0), BLK(1), ..., BLK(m-1) arranged in the row direction. A page buffer/readout circuit 170 is disposed close to the block BLK(0). In addition to such a configuration, the page buffer/readout circuit 170 may be disposed at the other end of the block or at the ends on both sides.

In one memory block, as shown in FIG. 4, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed, and n+1 string units NU are arranged in a column direction in one memory block. The string unit NU includes: a plurality of storage cells MCi (i = 0, 1, ..., 31) connected in series; a selection transistor TD connected to the drain side of the storage cell MC31 as one of the ends; and a connection In the selection transistor TS as the source side of the memory cell MC0 at the other end, the drain of the selection transistor TD is connected to the corresponding one of the bit lines GBL, and the source of the selection transistor TS is connected to the common source. Source line SL.

The control gate of the memory cell MCi is connected to the word line WLi, and the gate of the selection transistor TD, the selection transistor TS is connected to the selection gate line SGD and the selection gate line SGS which are arranged in parallel with the word line WL. When the word line selection circuit 160 selects a block based on the column address information Ax or the converted address information, the selection transistor TD is selectively selected via the selection gate line SGS of the block, the selection gate line SGD. The transistor TS is driven. Figure 4 shows the construction of a typical string unit, but the string unit can also contain one or more dummy cells within the NAND string.

Typically, the memory cell has a metal oxide semiconductor structure including: a source/drain as an N-type diffusion region, formed in the P-well; tunneling an oxide film formed between the source/drain On the channel; a floating gate (charge accumulation layer) formed on the tunnel oxide film; and a control gate formed on the floating gate via the dielectric film. When no charge is accumulated in the floating gate, that is, when the data "1" is written, the threshold is in a negative state, and the storage cell is normally on. When a charge is accumulated in the floating gate, that is, when the data "0" is written, the threshold shift is positive, and the memory cell is normally off. However, the storage cell may be a single-level cell (SLC) type that stores 1-bit (binary data), or a multi-level cell (MLC) type in which multiple bits are stored. .

Table 1 is a table showing an example of a bias voltage applied when each operation of the flash memory is performed. In the read operation, a positive voltage is applied to the bit line, a certain voltage (for example, 0 V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5 V) is applied to the unselected word line to select the gate. A positive voltage (for example, 4.5 V) is applied to the gate line SGD and the selection gate line SGS, so that the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line. In the programming (write) operation, a high voltage programming voltage Vprog (15 V to 20 V) is applied to the selected word line, and an intermediate potential (for example, 10 V) is applied to the unselected word line to make the bit The line selection transistor TD is turned on to disconnect the source line selection transistor TS, and the potential corresponding to the material "0" or "1" is supplied to the bit line GBL. In the erasing action, 0 V is applied to the selected word line in the block, a high voltage (for example, 20 V) is applied to the P well, and the electrons of the floating gate are extracted to the substrate, thereby being wiped in units of blocks. In addition to data.

When the input data Di is loaded to the page buffer/readout circuit 170 via the input/output buffer 120 during the programming operation, the ECC circuit 130 operates on the input data Di transferred from the page buffer/readout circuit 170. To generate an error correction symbol or a parity bit required for error detection correction of the input data Di. The calculation of the ECC is performed by, for example, a well-known method such as Hamming code or Reed-Solomon, and the input data Di of the input k-bit or k-byte is converted into p=k. +q. In the present specification, "q" is referred to as an error correction symbol or a parity bit required for error detection correction of the input data Di. In a preferred embodiment, the ECC circuit 130 sets the error correction symbols to the spare area of the page buffer/readout circuit 170. Thus, the input data Di and the error correction symbols set in the page buffer/readout circuit 170 are programmed on the selection page of the memory array 110.

When the material read from the selected page of the memory array 110 at the time of the read operation is held by the page buffer/readout circuit 170, the ECC circuit 130 performs based on the error correction symbol transferred from the page buffer/readout circuit 170. When the error of the read data is detected or corrected, when the error is detected, the corrected data is set in the page buffer/readout circuit 170. Moreover, the material held in the page buffer/readout circuit 170 is output via the input/output buffer 120.

Next, the programming operation in the first embodiment of the present invention will be described with reference to the flow of Fig. 5 . When the control section 150 receives a program command via the input/output buffer 120, a sequence for programming is started. The input data Di is loaded into the page buffer/readout circuit 170 via the input/output buffer 120, and then the ECC processing of the input material Di is performed by the ECC circuit 130 (S100).

An example of ECC processing is shown in FIG. When the flash memory 100 has an external input/output terminal of ×8, data from the external input/output terminal P-0 to the external input/output terminal P-7 via the respective I/O buffers 110-1 to I/O The buffer 110-7 is loaded into the page buffer/readout circuit 170. The page buffer/readout circuit 170 has, for example, a normal area 300 divided into eight sectors of sector 0 to sector 7, and is divided into four sectors of spare 0, spare 1, spare 2, and spare 3 Spare area 310.

One sector of the normal area 300 is composed of, for example, 256 bytes, in which case the eight sectors of the normal area 300 as a whole can hold programming data of about 2K bytes. One sector of the spare area 310 is composed of, for example, 16 bytes, and in this case, four sectors (alternate 0 to spare 3) as a whole can hold 64-bit data. One sector of the spare area 310 has, for example, an area 311 for storing information for identifying bad blocks containing bad storage cells, an area 312 for storing information related to user data, and an area 313, area 314 for storing common areas. An error correction symbol (parity check bit) of two sectors of 300; and an area 315 stores an error correction symbol (parity check bit) when the ECC operation is performed on the spare area 310. The area 313 and the area 314 of the spare 0 of the spare area 310 respectively store the sector 0 of the normal area 300, the error correction symbol (parity bit) of the sector 1, and the area 313 and the area 314 of the spare area 310 of the spare area 310 are stored in the normal area. Error correction symbols (parity bits) for sector 2 and sector 3 of region 300. Similarly, the spare 2 of the spare area 310 stores the sector 4 of the normal area 300, the parity bit of the sector 5, the spare 3 of the spare area 310 stores the sector 6 of the normal area 300, and the parity bit of the sector 7. .

An input/output buffer 110-0 to an input/output buffer 110-7 are allocated in one sector of the normal area 300, that is, 256 bits are allocated in one external input/output terminal (256 bit × 8 = 1 sector). The row selection circuit 180 decodes the row address information Ay received during the program operation, and selects the input from the external input/output terminal P-0 to the external input/output terminal P-7 based on the decoding result. The sector of the data. Fig. 6 shows an example in which the data received by the external input/output terminal P-0 to the external input/output terminal P-7 is loaded to the sector 0 in accordance with the row address information Ay.

In the example shown here, ECC circuit 130 includes a write circuit to write error correction symbols. Preferably, the ECC circuit 130 can perform an ECC operation on the data of the number of bytes equal to one sector of the normal area 300. If one sector of the normal area 300 is 256 bytes, the ECC circuit performs an ECC operation on the data of the 256-bit tuple to generate an error correction symbol that corrects the error of the 4-bit element.

The ECC circuit 130 writes the generated error correction symbols to the region 313 or region 314 of the corresponding sector of the spare region 310. In the example shown in FIG. 6, the program material is loaded to the sector 0 of the normal area 300, so the error correction symbol is written to the area 313 in which the parity of the spare 0 is stored.

The ECC processing of the data of the spare area 310 is illustrated in FIG. When the ECC processing is ended for each sector of the normal area 300, then each sector of the spare area 310 is subjected to ECC processing. The ECC processing for which material included in one sector of the spare area 310 is performed is arbitrary, but in this example, the data of the area 312 to the area 314 is subjected to ECC processing. Therefore, the data of the area 312 to the area 314 of the spare 0 is transferred to the ECC circuit 130, and the error correction symbol generated by the ECC processing is written to the area 315 of the spare 0 by the ECC circuit 130. The same processing is performed for the other spare 1 to standby 3.

Referring again to FIG. 5, when the ECC processing ends (S100), programming for the memory array 110 is started. The word line of the memory array 110 is selected by the word line selection circuit 160, the voltage corresponding to the material held by the page buffer/readout circuit 170 is supplied to the bit line, and a program pulse is applied to the selected page (S110) ). Next, program verification is performed (S120), and it is checked whether the threshold of the memory cell programmed with the data "0" is a fixed value or more. The result of the check is that if all the bits of the selected page pass, the programming ends. On the other hand, when all the bits are unsatisfactory, the control unit 150 determines whether or not the number of times the program pulse is applied reaches the optimum number Nop (S130).

Here, the optimal number of times Nop is less than the maximum number of application times or the maximum programming time allowed for programming, that is, the value of NMAX. Preferably, when the memory cell is determined to be unsatisfactory in programming, The number of programming pulses that should be applied minimally. For example, if the maximum time allowed for programming is 700 μs and the time required to apply a programming pulse is set to 50 μs, NMAX = 700 μs or NMAX = 14 times. The optimal number of times, Nop, can be determined based on the number of times a typical memory cell is programmed to be programmed. For example, when a statistical method is used to calculate the average number of times Nav of programming pulses applied to a programmed qualified storage cell, the optimal number of times Nop can be set to Nop=Nav. The optimal number of times Nop can be set by, for example, a command received from an external controller, and the set value is held by a register or the like of the control unit 150.

When the number of times the application pulse is applied does not reach the optimal number Nop (S140), the control unit 150 applies a programming pulse larger than the previous large DV to the selection page in accordance with ISPP (S150). On the other hand, when the number of times the application pulse is applied reaches the optimal number of times Nop (S140), the control unit 150 performs a step of determining whether or not the selected page is suspected to be qualified (S160). As described above, the maximum number of defective bits Np that is considered to be qualified is less than the maximum number of bits that can be repaired by ECC, and the number of defective bits at the time of verification, that is, the actual number generated on the selected page. When the number of qualified bits Nf is equal to or less than the maximum number of defective bits Np (Nf ≦ Np) which is suspected to be acceptable, it is determined that the number of qualified bits is equal (S160). When it is determined that the test is successful, the programming operation ends, and the defective bits of "0" are directly stored in the selection page.

On the other hand, when it is determined that the suspected pass is not achieved (S160), the control unit 150 determines whether the number of times the application pulse is applied reaches NMAX (S170), and if not, applies the program pulse to the selection page in accordance with the ISPP (S150, S110). In the case where the number of application of the program pulse reaches NMAX, the state of the program failure is notified to the external controller, and the block including the selected page is managed as a bad block. In this case, the discrimination information as a bad block is stored in the area 311 of the spare area.

Next, an operation when reading data from a page programmed according to the suspected qualification will be described with reference to the flow of FIG. First, the page of the memory array 110 is selected, and the material of the selected page is read by the page buffer/readout circuit 170 (S200). Next, the material held by the spare area of the page buffer/readout circuit 170 is transferred to the ECC circuit 130 (S210). For example, when the error detection and correction of the sector 0 is performed, the data of the spare 0 shown in FIG. 6 is transferred to the ECC circuit 130. The ECC circuit 130 first performs error detection and correction of the material held by the area 313 and the area 314 based on the error correction symbols (parity) held by the area 315.

Next, the material of the normal area of the page buffer/readout circuit 170 is transferred to the ECC circuit 130 (S220). For example, the data of sector 0 shown in FIG. 6 is transferred to the ECC circuit 130. The ECC circuit 130 performs error detection of the material of the sector 0 based on the error correction symbols stored in the area 313 of the spare 0 (S230). If the number of failed bits in the case of a suspected pass is included in the sector 0, the defective bit is detected as an error. In the case where the ECC circuit 130 detects an error, it is corrected to the correct material, and the corrected data is set to the page buffer/readout circuit 170 (S240). This processing is performed in units of sectors (S250).

As described above, according to the present embodiment, when the number of times the application pulse is applied reaches the optimal number of times Nop, it is determined whether or not the suspect is qualified, so that the determination is not performed until the optimal number of times Nop, and the determination that all the bits of the selected page are qualified is guaranteed. . Thus, the conventionally determined storage cells that are unqualified are highly likely to be repaired in an acceptable manner, and the ECC process can ensure the margin of the number of bits repaired by other processes, and the programming can be successful. The yield is improved.

Next, the programming operation of the second embodiment of the present invention will be described with reference to the flow of Fig. 9 . In the second embodiment, steps S300, S310, and S320 are newly added to the flow of Fig. 2 . At the time of the programming operation, the control unit 150 determines whether or not it is suspected to be qualified based on the input programming data (S300). Here, it is assumed that the selection page is programmed for the storage cells (the data are all "1") which are all in the erased state. When the number of bits of the data "0" included in the programming data of one sector is equal to or less than the maximum number of defective bits Np that can be regarded as qualified, the control unit 150 determines that the number of the bits is suspected to be acceptable, and is not the case. In the case of the same procedure as in the flow of FIG. 2 is performed.

When it is determined that the authentication is successful, the program data held by the page buffer/readout circuit 170 is transferred to the ECC circuit 130, where the ECC processing is performed (S310). The ECC circuit 130 writes an error correction symbol generated by the operation to the spare area of the page buffer/readout circuit. Next, the error correction symbols held by the page buffer/readout circuit 170 are programmed in the spare area of the selection page. At this time, the storage cells of the normal area of the selected page hold the data "1", and the bit line of the normal area of the selected page is supplied with the voltage prohibiting programming. When the error correction symbol is programmed in the spare area, the programming action ends. Since the normal area is forbidden to program, the influence of the coupling between adjacent bit lines disappears, and the program disturb characteristics are improved as compared with the conventional programming in which the programmed bit lines exist.

The reading of the page regarded as the eligibility is performed in the same manner as the reading in the first embodiment. That is, the material read from the selection page is held by the page buffer/readout circuit 170. The data of the normal area is "1", and the programming data has the data "0" below the number of unqualified bits Np. The ECC circuit 130 receives the data of the spare area of the page buffer/readout circuit 170, and detects the error bit from all the data "1" of the normal area based on the error correction symbols contained therein, that is, the program data "0" should be programmed. The bit is thus corrected to the material "1" to the material "0" and set in the page buffer/readout circuit 170.

As described above, according to the second embodiment, in the case where the data to be programmed is equal to or less than the number of bits that can be repaired by the ECC circuit 130, unlike the normal programming sequence, programming data is not programmed in the normal area. Only the error correction symbols are programmed in the spare area, the program disturb characteristics in the normal area are improved, and the programming time can be shortened. Furthermore, in step S320 of FIG. 9, when the error correction symbol is programmed in the spare area, the verification step is also performed as in the normal programming, in which case, as shown by the broken line K of FIG. It is also possible to execute a programming routine using ISPP.

Next, a third embodiment of the present invention will be described. The third embodiment is a combination of the first embodiment and the second embodiment, and the operation flow thereof is shown in Fig. 10. The flow of FIG. 10 is the same as the operation of the first embodiment and the second embodiment, and the steps S300, S310, and S320 of the second embodiment are added to the flow of FIG. In step S320 of FIG. 10, when the error correction symbol is programmed in the spare area, as in the case of FIG. 9, the programming sequence using ISPP can also be performed, in which case the error correction symbols are all qualified, so By setting the optimal number Nop to be larger than the optimal number Nop when the suspected pass is not achieved, it is possible to increase the possibility of determining that all the bits are qualified, and it is also possible to make the suspected pass in step S160 difficult to achieve.

Furthermore, the NAND type flash memory is programmed in units of pages, but the size of the input programming material does not necessarily need to be equal to one page, that is, the size of eight sectors of the normal area 300 shown in FIG. 6 is not necessarily required. equal. For example, the size of the programming material can be one sector size. Generally, from the viewpoint of program disturb, there is a limit in the number of times of programming (No. of Programs) that is allowed to be continuously performed on the same page, and it is possible to divide a page of data in accordance with the NOP for programming. When the NOP is 4, one page of data can be divided into, for example, 2 sectors, 1 sector, 3 sectors, and 2 sectors, and input to the flash memory 10.

The preferred embodiments of the present invention have been described in detail. The present invention is not limited to the specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

10‧‧‧Page Buffer/Readout Circuit
20‧‧‧Transfer circuit
30‧‧‧ECC circuit

100‧‧‧flash memory

110‧‧‧Memory array

120‧‧‧Input/Output Buffer

130‧‧‧ECC circuit

140‧‧‧ address register

150‧‧‧Control Department

160‧‧‧Word line selection circuit

170‧‧‧Page buffer/readout circuit

180‧‧‧ row selection circuit

190‧‧‧Internal voltage generation circuit

300‧‧‧Common area

310‧‧‧ spare area

311, 312, 313, 314, 315‧‧‧ areas

Ax‧‧‧Listing address information

Ay‧‧‧ Location Information

BLK (0), BLK (1), ..., BLK (m-1) ‧ ‧ storage blocks

Di‧‧‧ Input data

GBL‧‧‧ bit line

K‧‧‧ dotted line

MC0~MC31‧‧‧ storage cells

NU‧‧‧string unit

P-0~P-7‧‧‧ external input/output terminals

110-0~110-7‧‧‧I/O buffer

S10, S20, S30, S40, S50, S100, S110, S120, S130, S140, S150, S160, S170, S200, S210, S220, S230, S240, S250, S300, S310, S320‧‧

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

TD‧‧‧ bit line selection transistor

TS‧‧‧Source line selection transistor

TG‧‧‧ control signal

Vers‧‧‧ erase voltage

Vpass‧‧‧ pass voltage

Vpgm‧‧‧ write voltage

Vread‧‧‧ readout voltage

WL‧‧‧ character line

FIG. 1 is a view for explaining an ECC operation of a conventional flash memory. 2 is a flow chart for explaining a conventional programming operation of a flash memory. 3 is a view showing an overall schematic configuration of a NAND flash memory in an embodiment of the present invention. 4 is a circuit diagram showing a configuration of a NAND string of a memory cell array in an embodiment of the present invention. Fig. 5 is a flow chart for explaining a programming operation of the flash memory in the first embodiment of the present invention. Fig. 6 is a view for explaining ECC processing in a normal area in the programming operation of the first embodiment of the present invention. FIG. 7 is a view for explaining ECC processing of the spare area in the programming operation of the first embodiment of the present invention. Fig. 8 is a flow chart for explaining a reading operation of the first embodiment of the present invention. Fig. 9 is a flow chart for explaining a programming operation of the flash memory in the second embodiment of the present invention. Fig. 10 is a flow chart for explaining a programming operation of the flash memory in the third embodiment of the present invention.

S100, S110, S120, S130, S140, S150, S160, S170‧‧ steps

Claims (15)

A method for programming a reverse flash memory, comprising the steps of: applying a programming pulse to a selected page; determining whether the programming of the selected page is acceptable; and applying the programming pulse when the determination is unqualified If the number of times does not reach an optimal value less than the programmed allowable maximum value, the programming pulse is further applied to the selected page, if the number of times the programming pulse is applied reaches the optimal value, If the selected page is a pre-specified number of failed bits, it is determined to be suspected to be qualified. The method for programming a reverse flash memory according to claim 1, wherein the programming method further comprises the step of: selecting more than the pre-specified number of defective bits in the selected page. In case, it is determined whether the number of times the programming pulse is applied reaches the allowable maximum value, and if the allowable maximum value is not reached, the programming pulse is further applied to the selected page, and the allowable maximum value is reached. In the case of programming, the programming ends in the form of programming failure. The method for programming an inverse type flash memory according to claim 2, wherein the allowable maximum value is a maximum number of application times of the programming pulse allowed by programming of the selected page. The method for programming a reverse flash memory according to claim 1, wherein the pre-specified number of defective bits is capable of passing error detection. The number of bits corrected by the correction is below. The method for programming a reverse flash memory according to the first or second aspect of the invention, wherein the optimum value can be set by an external controller. The method for programming a reverse flash memory according to the first or second aspect of the invention, wherein the programming method further comprises the steps of: generating an error correction symbol of the data to be programmed, and on the selection page. Programming data and the error correction symbols are programmed. A method for programming a reverse flash memory, and the programming method comprises the steps of: receiving data to be programmed; determining whether the number of bits programmed by using the data to be programmed is capable of utilizing error detection. Correcting the number of repair bits repaired by the component; using the error detection. Correcting component to generate an error correction symbol of the material to be programmed; and when determining that the number of bits to be programmed by using the material to be programmed is less than the number of repair bits, by not in the normal area of the selection page Programming, while the error correction symbols are programmed in the spare area to end programming for the selected page. The method for programming an inverse type flash memory according to claim 7, wherein the programming method further comprises the step of: determining that more bits are programmed by using the material to be programmed; When the number of bits is repaired, the program-programmed material is programmed in the normal area of the selection page. A method for programming a reverse flash memory, the programming method comprising the steps of: receiving data to be programmed; determining whether the number of bits programmed by using the data to be programmed is capable of utilizing error detection. The number of repair bits repaired by the correcting component is below; using the error detection. Correcting component to generate an error correction symbol of the material to be programmed; when it is determined that the number of bits programmed by using the material to be programmed is less than the number of repair bits, programming is not performed in a normal area of the selection page, And programming the error correction symbol in the spare area to end programming for the selected page; and when determining that the number of bits to be programmed by using the material to be programmed is greater than the number of repair bits, The normal area of the selection page is programmed to program the material to be programmed, the programming method further comprising the steps of: applying a programming pulse to the selected page; determining whether the programming of the selected page is qualified or not; When it is determined to be unqualified, the programming pulse is further applied to the selected page when the number of times the application pulse is applied does not reach an optimum value less than the programmed maximum value, and the number of times of the programming pulse is applied. When the optimal value is reached, if the selected page is a predetermined number of defective bits, it is determined that the selected page is suspected to be qualified. A semiconductor storage device comprising: a memory array; error detection. a correction component that generates an error correction symbol of the material to be programmed; and a programming component that programs the program to be programmed and the error correction symbol on the selection page of the memory array, and the programming component performs the following Processing: applying a programming pulse to the selected page, when it is determined that the programming of the selected page is unqualified, if the number of times the programming pulse is applied does not reach an optimal value less than the programmed maximum value, The selection page further applies the programming pulse. When the number of times the programming pulse is applied reaches the optimal value, if the selected page is a predetermined number of defective bits, it is determined to be a pass. The semiconductor storage device of claim 10, wherein the programming component further determines the number of times the programming pulse is applied if the selected page is more than the pre-specified number of failed bits. Whether the allowable maximum value is reached, the programming pulse is further applied to the selected page if the allowable maximum value is not reached, and the programming is terminated in the form of programming failure if the allowable maximum value is reached . The semiconductor storage device of claim 10, wherein the predetermined number of failed bits is capable of detecting by the error. The number of bits to be repaired by correcting the component is below. A semiconductor storage device comprising: Memory array; error detection. a correction component that generates an error correction symbol of the material to be programmed; and a programming component that programs the program to be programmed and the error correction symbol on the selection page of the memory array, and the programming component is utilized The number of bits programmed for the data to be programmed is capable of utilizing the error detection. When the number of repair bits repaired by the correcting component is below, the programming of the selected page is ended by programming the error correction symbol in the spare area by not programming in the normal area of the selected page. The semiconductor storage device of claim 13, wherein the programming component further selects the number of bits to be programmed by using the material to be programmed more than the number of repair bits. The normal area of the page programs the material to be programmed. The semiconductor storage device of claim 14, wherein the programming component further performs processing of applying a programming pulse to the selected page, and when determining that the programming of the selected page is unacceptable, The programming pulse is further applied to the selected page if the number of times the application pulse is applied does not reach an optimum value less than the programmed maximum value, in the case where the number of times the programming pulse is applied reaches the optimal value If the selected page is a predetermined number of unqualified bits, it is determined to be suspected to be qualified.