Nothing Special   »   [go: up one dir, main page]

TWI699840B - 形成扇出互連結構與互連結構的方法 - Google Patents

形成扇出互連結構與互連結構的方法 Download PDF

Info

Publication number
TWI699840B
TWI699840B TW107137251A TW107137251A TWI699840B TW I699840 B TWI699840 B TW I699840B TW 107137251 A TW107137251 A TW 107137251A TW 107137251 A TW107137251 A TW 107137251A TW I699840 B TWI699840 B TW I699840B
Authority
TW
Taiwan
Prior art keywords
conductive
substrate
active device
semiconductor active
interconnect
Prior art date
Application number
TW107137251A
Other languages
English (en)
Other versions
TW201935581A (zh
Inventor
理查 普拉維德
藍章益
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201935581A publication Critical patent/TW201935581A/zh
Application granted granted Critical
Publication of TWI699840B publication Critical patent/TWI699840B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731Ceramic materials or glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732Diamonds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02379Fan-out arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05657Cobalt [Co] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/11845Chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13157Cobalt [Co] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81416Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

可施行處理方法以形成扇出互連結構。方法可包含形成疊加於第一基板上的半導體主動裝置結構。半導體主動裝置結構可包含第一導電接點。方法可包含形成疊加於第二基板上的互連結構。互連結構可包含第二導電接點。方法亦可包含使第一基板與第二基板接合。接合可包含使第一導電接點與第二導電接點耦接。互連結構可延伸超過半導體主動裝置結構之橫向尺寸。

Description

形成扇出互連結構與互連結構的方法
本技術是有關於半導體系統、製程與裝置。具體而言,本技術是有關於用以生產扇出互連結構的方法與裝置。
藉由於基板表面上生產複雜圖案化的材料層之製程使積體電路成為可能。隨著積體電路持續縮小以適應更小的終端裝置,這些積體電路之後端金屬化變得更加複雜。例如,隨著積體電路之尺寸縮小,其電阻增加,電阻增加可能會影響裝置性能。雖然一些技術已試圖改良金屬化,裝置之佔地面積(footprint)持續影響互連構成與裝置性能之許多方面。
從而,需要可用以生產高品質之裝置與結構的改良的系統與方法。本技術可滿足這些需求與其他需求。
可施行多個處理方法以形成扇出互連結構。方法可包含形成疊加於第一基板上之半導體主動裝置結構。半導體主動裝置結構可包含多個第一導電接點。方法可包含形成疊加於第二基板上之互連 結構。互連結構可包含多個第二導電接點。方法亦可包含使第一基板與第二基板接合。接合可包含使多個第一導電接點與多個第二導電接點耦接。互連結構可延伸超過半導體主動裝置結構之橫向尺寸。
在一些實施例中,半導體主動裝置結構可包含疊加於多個半導體主動裝置層上之金屬化層。互連結構可包含形成於複數個介電材料層內的多個全域互連。互連結構可以反向製程來形成,在反向製程中,最後全域互連層形成於半全域或中間互連層之前。多個第一導電接點可包含自半導體主動裝置結構之第一表面延伸的複數個導電柱,半導體主動裝置結構之第一表面相對於第二表面,第二表面相鄰於第一基板。互連結構之第一表面可定義出複數個存取通孔,互連結構之第一表面相對於耦接第二基板之第二表面。每一存取通孔之特徵可為自互連結構之第一表面逐漸縮減的一錐形。每一存取通孔可包含導電襯墊。多個第二導電接點可包含導電填充物,導電填充物包含於複數個存取通孔內。在一些實施例中,接合可進一步包含使包含於複數個存取通孔內的導電填充物接觸複數個導電柱。接合亦可包含加熱導電填充物以使導電填充物熔化(melt)且流經導電柱以使導電填充物與導電柱電耦接。
多個第二導電接點可包含沿著互連結構之第一表面定義出的複數個導電平台,互連結構之第一表面相對於耦接第二基板之第二表面。接合包含使複數個導電柱與複數個導電平台黏接(bonding)。在一些實施例中,互連結構可包含多個第三導電接點。方法可進一步包含形成疊加於第三基板上的第二半導體主動裝置結構。 第二半導體主動裝置結構可包含多個第四導電接點。方法亦可包含使第三基板與第二基板接合。接合可包含使多個第四導電接點與多個第三導電接點耦接。
本技術之實施例亦可包含形成互連結構之方法。方法可包含於互連基板上方形成用於一或更多主動裝置之反向互連結構。反向互連結構可包含形成於複數個介電材料層內之導電材料。方法可包含沿著反向互連結構之第一表面形成複數個通孔,反向互連結構之第一表面相對於第二表面,第二表面相鄰於互連基板。通孔可提供路徑至導電材料。方法可包含以導電材料作為複數個通孔中的每一者之內襯。方法亦可包含以導電填充物材料至少部分填充每一通孔。
在一些實施例中,方法亦可包含使第一半導體主動裝置之複數個導電延伸部定位於複數個通孔之一子集內。方法可包含使導電填充物材料熔化以使第一半導體主動裝置之多個導電延伸部與反向互連結構之導電材料電耦接。方法可包含使複數個第二半導體主動裝置之導電延伸部定位於複數個通孔之第二子集內。方法亦可包含使複數個通孔之第二子集內的導電填充物材料熔化以使第二半導體主動裝置之導電延伸部與反向互連結構之導電材料電耦接。方法亦可包含使反向互連結構之第一表面平坦化以使導電填充物材料限制於複數個通孔內。
本技術之實施例亦涉及形成互連結構之方法。方法可包含於互連基板上方形成用於一或更多主動裝置之反向互連結構。反向互連結構可包含形成於複數個介電材料層內之導電材料。方法亦可包 含沿著反向互連結構之第一表面形成複數個接觸平台,反向互連結構之第一表面相對於第二表面,第二表面相鄰於互連基板。接觸平台可提供路徑至導電材料。複數個接觸平台之每一接觸平台之尺寸可大於一或更多半導體主動裝置結構之對應導電延伸部。
在一些實施例中,接觸平台可延伸超過介電材料,介電材料定義出反向互連結構之第一表面。方法亦可包含使半導體主動裝置之複數個導電延伸部定位於相鄰複數個接觸平台。方法亦可包含使複數個導電延伸部與複數個接觸平台黏接以使半導體主動裝置之導電延伸部與反向互連結構之導電材料電耦接。反向互連結構可延伸超過半導體主動裝置之橫向尺寸。
這樣的技術相較於傳統系統與技術可提供許多益處。例如,藉由使互連結構從主動裝置之佔地面積解耦(decoupling),可形成尺寸增加之互連導線與通孔,可改善裝置性能。此外,後端可需要較少的金屬層,減少橫跨與通過裝置之總體傳導長度。以下將搭配說明與附圖更詳細描述這些實施例與其他實施例,以及其許多優勢與特點。
100:方法
105、110、115:操作
200、400:主動裝置結構
205:第一基板
210、410:主動裝置層
215、415:金屬化層
216、265:導電材料
218:介電材料層
250、300、600:互連結構
255、305、405、605:基板
260、315、420:介電材料
270、307:層
275:半全域層
280:中間層
310:反向互連結構
320、435:通孔
322:通道
325:導電襯墊
330:導電填充物
400a:第一主動裝置
400b:第二主動裝置
405b:第三基板
425:互連材料
430:犧牲層
440、440b、620:導電延伸部
500:第一扇出互連結構
550:裝置
610:接觸平台
700:扇出互連結構
配合以下說明書與圖示,可進一步理解所揭露之技術的本質與優勢。
第1圖繪示根據本技術之一些實施例的形成扇出互連結構的方法之示例性操作
第2A-2B圖繪示根據本技術之一些實施例形成的示例性基板的剖面示意圖。
第3A-3D圖繪示根據本技術之一些實施例發展的示例性互連結構的剖面示意圖。
第4A-4F圖繪示根據本技術之一些實施例的示例性主動裝置結構的剖面示意圖。
第5A-5B圖繪示根據本技術之多個實施例的示例性扇出互連結構的剖面示意圖。
第6A-6B圖繪示根據本技術之一些實施例發展的示例性互連結構的剖面示意圖。
第7圖繪示根據本技術之多個實施例的示例性扇出互連結構的剖面示意圖。
包含幾張圖示以作為示意圖。應理解的是,圖示僅用於說明之目的,除非特別說明為比例,否則不應視為比例。此外,作為示意圖,圖示提供以幫助理解,且相較於實際情況可能不包含所有方面或資訊,且可能為了說明之目的包含誇大的材料。
在附圖中,相似的元件及/或特徵可具有相同的元件符號。進一步地,相同類型之數種不同的元件可藉由於元件符號後面加一字母來區別相似的元件。一旦元件符號第一次用於說明書中,其說明適用於任何一個具有相同元件符號(不考慮字母)之相似元件。
在後段製程(back-end-of-line)處理期間,金屬與其他導電材料可填入基板上的多個結構層。隨著電晶體結構持續縮小,及深寬比(aspect ratios)持續增加,互連線也持續縮小。因為典型用於加工 之導電材料的特性,隨著導線(wires)、跡線(traces)與通孔之尺寸降低,它們的線路電阻往往會增加。對可具有數英里(miles)長的互連導線之典型的積體電路而言,線路電阻的少量增加可導致無法容忍的性能下降。
再者,典型的加工製程可能進一步限制生產。例如,裝置加工通常包含形成垂直穿過主動裝置層的互連結構。在電晶體、記憶體或其他裝置結構已形成之後,金屬化可開始形成通過疊加的介電材料層之互連結構。當晶圓上的裝置密度持續增加,同時裝置之佔地面積持續縮小,可能產生更多金屬層,且因此產生更長的導電路徑,此對於裝置性能有負面影響。加工製程可包含連接主動裝置層結構之任意數量金屬層。可然後形成中間金屬化,接著是半全域與最終全域導線,每一部分垂直建造於疊加層上。以這種方法,所有導線可限制於主動裝置之佔地面積內。
為了適應一些此類損失,一些技術利用有多個額外金屬層形成於環氧成型化合物(epoxy mold compound)中的扇出金屬結構,使金屬接點得以稍微延伸超過主動裝置之佔地面積。雖然為晶圓級封裝(wafer level packaging)提供了額外的空間,此技術也可能產生問題。例如,額外的金屬化,稱為重佈層(redistribution layers),增加額外的金屬層,進一步增加導電路徑長度與金屬層數量。此外,環氧成型化合物通常特徵在於其熱膨脹係數與接觸的矽結構之熱膨脹係數不同。因此,加熱此結構可導致層間不同程度的應力,導致彎曲與遍及裝置之其他剪切力(shear forces)。
本技術可藉由在自主動裝置分離之基板上形成互連結構來克服這些問題與其他問題。雖然主動裝置可包含一或更多金屬層,多數全域導線可施行於分離基板上。藉由使互連結構從主動裝置基板解耦,互連可不侷限於主動裝置之佔地面積內。這可使正常的扇出製程得以施行而不需要額外的金屬化層、環氧成型化合物或重佈層。因此,可提供裝置性能之改良,還可提供使數個主動裝置耦接至單一扇出互連基板之附加能力。
雖然以下揭露將例行地檢視根據所揭露之技術的特定互連結構,將能輕易理解的是,系統與方法同樣適用於各種其他產品、製程與系統。因此,技術不應視為僅限於用於扇出互連製程。在提供可藉由本技術發展與涵蓋的示例性結構之前,本揭露將探討用以生產根據本技術之結構的示例性製程。
第1圖繪示根據本技術之一些實施例的形成扇出互連結構的方法100之示例性操作。方法可包含在列出的操作之前或之後的額外操作,且亦可於方法內包含額外操作。方法100可包含於操作105形成半導體主動裝置結構。半導體主動裝置結構可形成為疊加於第一基板上,且可包含形成第一導電接點。方法100亦可包含於操作110形成疊加於第二基板上的互連結構。互連結構可包含第二導電接點。
於操作115,方法可包含使第一基板與第二基板接合。於操作115的接合可以若干種方法施行,以下將搭配附圖說明這些方法,且可包含使第一導電接點與第二導電接點電耦接或機械耦接。藉由施行方法100的多個操作,總體裝置之互連結構延伸超過半導體主動 裝置結構之橫向尺寸。以這種方法,本技術可使主動裝置結構自互連結構解耦,可使扇出互連結構形成為具有金屬化層,而非發展額外的傳統扇出技術之重佈層。
轉向第2A-2B圖,第2A-2B圖繪示根據本技術之一些實施例形成的示例性基板的剖面示意圖。第2A圖繪示根據本技術之一些實施例的示例性半導體主動裝置結構200。應理解的是,繪示之結構並非用以作為侷限,而可能展現本技術涵蓋之各種不同的結構的多個方面。如圖所示,半導體主動裝置結構200可形成於第一基板205上方。第一基板205可為含矽材料(silicon-containing material)、含鍺材料(germanium-containing material)或任何使半導體主動裝置結構可形成於其上的其他材料。
主動裝置層210可包含可形成於半導體加工中之任意數量的材料或結構。例如,主動裝置層210可包含類比或數位結構、任意形式的電晶體結構、任意形式的記憶體結構,且可包含形成於半導體加工中之任意二維或三維結構。因此,雖然沒有繪示具體材料,主動裝置層210僅代表可形成於第一基板205上方的結構群。應理解的是,如本領域技術人員所理解的,任意數量的材料可併入此層內。同樣地,主動裝置層210可能不代表一些可能涵蓋於主動裝置層210中的主動結構之厚度。例如,儘管二維電晶體結構可具有相對薄的剖面,三維記憶體結構可具有許多疊層。無論如何,這些半導體主動材料中無論哪個或任意其他半導體主動材料皆可發展於前段處理操作(front-end processing operations)中且涵蓋於主動裝置層210中。
半導體主動裝置結構200亦可包含疊加於半導體主動裝置層210上之金屬化層215。在許多不同的半導體結構中,金屬化可形成於結構化的層中以使形成於基板205上方之數種不同的元件互連。金屬化可包含一系列介電材料層218,例如垂直堆疊的層間介電質或一些其他絕緣材料。介電材料層內可有形成為數種不同的導線與通孔之導電材料216,以提供導電路徑,導電路徑用來以無數種方法使半導體主動層210之多個層面充電。金屬化層可包含任意數量的金屬或導電材料,包含銅(copper)、鎢(tungsten)、鈷(cobalt)或可使用於半導體互連構成中的任意其他導電材料。
金屬化層可包含形成為半導體主動裝置結構200的一部分之任意數量的金屬層。例如,如本領域技術人員所理解的,可取決於主動裝置層210的複雜度與布局形成若干卑金屬(base metal)層。例如,示例性半導體主動裝置結構可包含大於或約等於1、大於或約等於2、大於或約等於3、大於或約等於4、大於或約等於5、大於或約等於6、大於或約等於7、大於或約等於8、大於或約等於9、大於或約等於10、大於或約等於12、大於或約等於15、或更多個具有導電材料216的介電材料層218,具有導電材料216的介電材料層218視互連結構而定以不同圖案(patterns)設置於每一層內。應理解的是,金屬化層215可包含這些層中的任意一或多者。
在許多後段加工製程中,金屬化形成於經常稱為初始金屬層、中間互連層、半全域層與互連導線全域層的群組中。通常,隨著這些層從主動裝置層延伸,這些層的厚度會增加。在傳統加工中, 這些層形成為每一層疊加於前一層上,同時所有層維持於主動裝置層或基板區之佔地面積內。隨著裝置尺寸縮小,以及裝置布局之複雜度增加,這些互連可能形成為通過愈來愈多層而愈來愈靠近彼此。扇出互連設計通常實施於由於緊靠的全域導線使晶圓級封裝凸塊或球柵陣列封裝(ball grid arrays)難以接合(landing)的情況。然而,如前所述,這些傳統扇出互連結構通常在此階段形成更多個僅延伸超過主動裝置層之佔地面積的金屬層,這些金屬層經常稱為重佈層。
本技術可藉由在達到最終全域層之前停止垂直互連構成結構來克服這些問題。因為不同結構可包含不同數量的金屬層,本技術可於疊加於主動裝置層210上的金屬化層215內形成一或多個金屬或中間層。在一些實施例中,基板205上的金屬化層可以標準製程形成,在標準製程中,中間層依序形成於金屬層形成之後。雖然在一些實施例中,互連之半全域及/或全域層亦可形成為疊加於結構上,在其他實施例中,這些層可能不包含於半導體主動裝置結構內。
雖然形成為疊加於主動裝置層上的金屬層的數量可能隨著形成的結構、所需的金屬層的數量與其他參數而改變,這些層可根據某些參數形成一階層。例如,在一些實施例中,金屬化可形成一階層,在此階層中形成的通孔之特徵在於具有大於或約等於200奈米(nm)、大於或約等於500奈米、大於或約等於750奈米、大於或約等於1微米(μm)、大於或約等於2微米、大於或約等於3微米、大於或約等於4微米、大於或約等於5微米、大於或約等於6微米或更大的一直徑。此可能取決於取放設備(pick-and-place equipment)之精密度(precision) 與準確度(accuracy),取放設備將舉例說明於後。此外,包含於金屬化層215中的金屬化階層的數量可能取決於其他因素,例如可迅速形成於主動裝置層之佔地面積內的層的數量。
剩下的互連層可能形成於分離基板上,如第2B圖所示。如圖所示,互連結構250可形成為疊加於基板255上,基板255與形成於基板205上方的主動裝置結構分離。基板255可為扇出互連晶圓,且可包含任意數量的不同材料,包含玻璃或載體材料、晶圓或相似於基板205之基板、或其他導電基板,其他導電基板例如中介層(interposers)或其他具有導電材料通過結構形成之基板,在此結構中,晶圓級封裝,例如錫銲凸塊(solder bumps),可直接耦接基板255之背面。用於半導體主動裝置結構200之剩餘互連結構可疊加於基板255之相對側。
互連結構250可包含若干個介電材料260之互連層,介電材料260例如層間介電材料或其他絕緣材料,介電材料260之互連層具有以不同圖案設置之導電材料265,用以產生主動裝置結構之導電路徑。互連結構可相較於傳統構成以反向形成。例如,可以最高全域互連導線直接疊加於基板255,接著是半全域層275與中間層280,最高全域互連導線可包含若干層270。互連結構250還可包含任意初始金屬層,或者多個金屬層及/或多個中間層中的一些可分散於基板205上方的主動裝置結構200與基板255上方的互連結構之間。在此反向製程中,全域導線可形成於半全域導線之前,若包含中間導線,半全域導線可形成於中間導線之前,若包含初始金屬層,中間導線可形成於初始金屬層之前。
可為扇出互連晶圓的基板255之尺寸可能與基板205不相似。例如,在實施例中,基板255可大於或小於基板205,這樣可使結構尺寸增加或減小,相較於傳統的主動層上方之絕對垂直互連構成。基板255可比基板205大至少約5%,且在一些實施例中,基板255可比基板205大至少約10%、大至少約20%、大至少約30%、大至少約40%、大至少約50%、大至少約60%、大至少約70%、大至少約80%、大至少約90%、大至少約100%、大至少約200%或更多。例如,如同以下將進一步討論的,在一些實施例中,多個半導體主動裝置結構可接合單一互連結構250,以產生系統級封裝(system-in-package)結構或其他多元件裝置。因此,基板255可為任意尺寸以適應特定終端裝置需要的結構之數量。結構200與250中的一者或兩者之最高層或暴露層可形成以適應接合操作115,在操作115中,結構200與結構250耦接。例如,結構200之最高層可包含第一導電接點,且結構250之最高層可包含第二導電接點。下列圖示將描述示例性第一導電接點與第二導電接點以及示例性耦接過程。
第3A-3D圖繪示根據本技術之一些實施例發展的示例性互連結構300的剖面示意圖。互連結構300可包含前述之互連結構250之任意結構或層,且可包含耦接數個主動裝置結構。雖然以下將討論單一結構,應理解的是,互連結構300可包含十個、百個、千個、百萬個或更多類似結構,每一者裝配以適應一主動裝置結構或一單一主動裝置結構之一特定第一導電接點。互連結構300可包含基板305,反向互連結構310可通過前述之介電材料315形成於基板305上方。取決於基 板之類型,且不論基板305是否將併入最後的裝置結構,可包含額外的層307以附接及移除基板305。在一些實施例中,可不包含層307,如此一來球柵陣列封裝或其他晶圓級封裝如前述施行於基板305之背面。
如第3A圖所繪示,互連結構300可包含插口(receptacle)作為第二導電接點,此第二導電接點裝配以適應具有第一導電接點之主動裝置結構。第二導電接點可為(或包含)通孔320,通孔320係通過互連結構300之第一表面上的介電材料315加以定義,互連結構300之第一表面相對於相鄰或耦接基板305之第二表面。在一些實施例中,可形成一層額外的介電材料315疊加於導線或反向互連結構310之最高層。通孔可以任意數量之製程加以蝕刻,包含溼式蝕刻(wet etches)、乾式蝕刻(dry etches)、反應離子刻蝕(reactive-ion etching)或可用於生產通孔320之其他蝕刻或移除操作。通孔320可形成以提供路徑至反向互連結構310之頂層。在一些實施例中,複數個通孔可形成為遍及互連結構300之表面,可提供數個第二導電接點。通孔320之特徵可為包含直的側壁之任意形狀。在一些繪示之實施例中,通孔320之特徵可為錐形通道322,錐形通道322可為(或包含)通往通孔320之倒角(chamfered)或斜切(beveled)邊緣。如下所述,錐形通道322可在接合過程中使主動裝置結構定位。錐形通道322可定義為自互連結構300之第一表面開始,例如通過介電材料315,且可部分或全部延伸通過通孔320。
一旦複數個通孔320形成,導電襯墊325可形成為橫越互連結構300,如第3B圖所示。導電襯墊325可為與互連材料相同的材料,或在多個實施例中可為不同的材料。例如,導電襯墊325可為前面 提及之任意金屬,以及其他可促進主動裝置結構與互連結構300之間的轉移之導電材料。一旦襯墊沉積完成,導電填充物330可沉積於襯墊上方、橫越互連結構300之第一表面,如第3C圖所示。導電填充物330可為任意數量的材料,且在一些實施例中,導電填充物330可為具有相對低的熔點之導電材料。例如,導電填充物330可為銲錫(solder)或可熔化以使主動裝置之第一導電接點材料接合或黏接於互連結構之通孔320內的其他材料。在多個示例性實施例中,導電填充物330可包含鉛(lead)、錫(tin)或一些其他材料或材料組合以提供具有低於或約為200℃的一熔點之材料。在一些實施例中,導電填充物330之特徵可為具有低於或約為180℃的一熔點、具有低於或約為160℃的一熔點、具有低於或約為140℃的一熔點、具有低於或約為120℃的一熔點、具有低於或約為100℃的一熔點、具有低於或約為80℃的一熔點、具有低於或約為60℃的一熔點、具有低於或約為50℃的一熔點,或具有更低的熔點。
在一些實施例中,導電填充物330可為第二導電接點的一部分,或可為第二導電接點,如同導電填充物可為直接接觸、耦接、黏接或以其他方式接合主動裝置結構與互連結構之間的金屬化之材料。在多個實施例中,導電填充物330可能不會完全填滿通孔320,為了在接合操作期間限制或避免導電填充物330從通孔320流出。因此,在一些實施例中,導電填充物330可僅部分填充通孔320。可藉由任意數量的已知操作方式來形成或沉積導電襯墊325與導電填充物330,例如,已知操作方式包含化學或物理沉積、電鍍(plating)或基於電的沉積技術。一旦導電填充物已沉積或形成於通孔320內,可施行拋光 (polishing)操作,例如化學機械研磨(chemical-mechanical polishing),以自互連結構之第一表面移除導電填充物330或襯墊325中的一者或二者,如第3D圖所示。藉由施行拋光操作,可為後續的裝置接合提供實質平坦化的表面。一旦導電填充物形成於複數個通孔320內,互連結構可接收具有額外導電延伸部之主動裝置,額外導電延伸部以相似於複數個通孔320之圖案配置。
第4A-4F圖繪示根據本技術之一些實施例的示例性主動裝置結構400的剖面示意圖。主動裝置結構400可相似於前述之主動裝置結構200。例如,主動裝置結構400可包含基板405,主動裝置層410可形成於基板405上方,如第4A圖所示。如前所述,主動裝置層410可為或包含任意數量的半導體結構。一或多個金屬化層415可形成為疊加於主動裝置層410上,且可包含任意數量的金屬或金屬中間層。結構可被拋光以產生平坦化結構。後續形成的特別互聯金屬結構、介電材料(例如層間介電材料420)可延伸於互連材料425的上方,如第4B圖所示。
如第4C圖所示,犧牲層430可形成為疊加於介電材料420上。犧牲層430可為光阻劑(photoresist)、介電質或可圖案化之一些其他材料。圖案可施加於犧牲層430,且若干個通孔435可形成通過犧牲層430並疊加於介電材料420上,如第4D圖所示。通孔435可於數個位置提供路徑至互連材料425,即便圖示僅繪示單一通孔。額外的導電材料可沉積於通孔內以產生自主動裝置結構延伸的複數個導電延伸部440或柱,如第4E圖所示。在多個實施例中,多個導電柱可對應插口或接觸平台之圖案形成,插口或接觸平台形成於互連晶圓上,如同配合 其他圖示所述那般。導電延伸部440可為與互連材料425相同的材料,或在一些實施例中可為不同的導電材料,且可為任意前述之材料。
沉積或形成可包含若干種操作,取決於所使用的材料。作為一種非限制的示例,銅延伸部可形成於一實施例中,但可相似地使用任意其他導電金屬或材料。金屬襯墊可首先形成於通孔435內,在施行電化學沉積以用金屬填充通孔435之前。可接著施行化學機械研磨操作以使主動裝置結構之表面平坦化,且自裝置結構的表面移除剩餘的材料。此舉亦可能有助於使形成為遍及主動裝置表面之複數個導電延伸部440產生實質上一致的高度,可包含十個、百個或千個類似的導電延伸部440。一旦導電延伸部形成,可移除犧牲層430以暴露出自主動裝置結構之第一表面延伸的複數個延伸部440,主動裝置結構之第一表面相對於接觸基板405之表面,如第4F圖所示。
在主動裝置結構與互連結構形成後,以及第一導電接點與第二導電接點形成後,可接合兩結構。第5A-5B圖繪示根據本技術之多個實施例的示例性扇出互連結構的剖面示意圖。圖示包含結構,例如結構300與400,但仍相似地包含本技術描述之任意其他結構。第5A圖繪示第一扇出互連結構500,在第一扇出互連結構500中,半導體主動裝置結構400可為倒置且接合互連結構300。如圖所示,導電延伸部440可定位於通孔320內以接觸導電填充物330。在一些實施例中,主動裝置之放置可為自動化製程的一部份。主動裝置結構可包含對準遮罩,對準遮罩可被取放機器(pick-and-place machine)所利用,例如,用以使主動裝置適當地定向,如此一來每一個導電延伸部440適當地對 準對應通孔320。因為加工工具之精確度極限,通孔320之特徵可為直徑或側壁間的橫向距離大於橫越導電延伸部之直徑或橫向尺寸。例如,通孔320之直徑可比導電延伸部440之直徑大至少約5%,且在一些實施例中,通孔的直徑可大至少約10%、大至少約20%、大至少約30%、大至少約40%、大至少約50%、大至少約60%、大至少約70%、大至少約80%、大至少約90%、大至少約100%、大至少約150%、大至少約200%、或更大,取決於導電延伸部440之尺寸。
一旦主動裝置400與互連結構300適當地定位,可施行加熱操作以熔化導電填充物330。一旦導電填充物330已熔化,導電填充物可繞著導電延伸部440流動或回流(reflow)以立體的(three-dimensional)且360°耦接至導電延伸部440,可透過導電填充物使主動裝置與互連裝置電耦接。作為額外的益處,當導電填充物330熔化,液體材料的表面張力可幫助適當地推動主動裝置使其到位,且調整任意主動裝置之錯位(misalignment)。通孔320之錐形通道亦可適應主動裝置定位之位移誤差(displacement error),以避免損傷結構。此亦可有利於使主動裝置安置於通孔320內。在多個實施例中,主動裝置可能完全靠著互連結構安置或不完全靠著互連結構安置。例如,雖然可能發生介電材料之直接接觸,在一些實施例中,兩結構之兩介電材料之間可維持一間隙。
第5B圖繪示使第二主動裝置400b耦接至互連結構300以產生裝置550。第二主動裝置400b可和第一主動裝置400a相同或不同,且第二主動裝置400b可包含形成於第三基板405b上方且具有第四 導電接點之結構,第四導電接點可為額外的導電延伸部440b。如所述,互連結構300可包含額外的通孔作為第三導電接點,第三導電接點圖案化以對應第二主動裝置400b之導電延伸部。在一些實施例中,主動裝置結構400皆可為前面提及之任意半導體結構,且互連結構300可裝配以適應任意數量之此類主動裝置以產生若干包含系統級封裝設計之最後裝置。一旦主動裝置已放置,可施行導電填充物330之回流以使主動裝置耦接與安置於互連結構內。
如第5A圖與第5B圖皆繪示的,在扇出互連結構中,互連結構300可形成於比主動裝置更大的佔地面積上,此可使互連延伸超過佔地面積。不像傳統扇出結構,繪示之結構可不包含重佈層,此可降低裝置形成之金屬層總體數量。此可降低導電路徑長度、降低線路電阻,且提升總體性能。環氧材料亦可限制於結構中或不包含於結構中,此可降低或限制材料之熱效能差異。此外,加工期間,主動裝置之測試可更早施行,以確保適當功能化早於進一步金屬化或互連形成之前。仍有更多的益處,包含在運作期間之熱差異兼容性。例如,主動裝置的熱可能在操作期間增加,導致主動裝置結構400之隆起(swelling)或移動。藉由維持主動裝置結構400與互連結構300之間的垂直抵銷,熱膨脹與應變(strain)可被多個導電延伸部吸收,可使多個導電延伸部偏轉(deflection),而不會是剪切應力作用於整個裝置結構上。
第6A-6B圖繪示根據本技術之一些實施例發展的示例性互連結構600的剖面示意圖。結構600可包含前述之互連結構300之任意材料,但可能有其他的第二導電接點配置。例如,如第6A圖所示, 結構600可沿著互連結構之第一表面形成接觸平台610,互連結構之第一表面相對於相鄰或耦接基板605之第二表面,而非形成導電延伸部可能設置於其中之插口。接觸平台610可藉由任意已知技術來形成且可包含前述之相似操作。接觸平台610可填充延伸至第一表面的通孔,或可具有如所述之橫向延伸之接觸墊以產生較大的接觸區域來適應放置誤差。在一些實施例中,接觸平台之特徵可為具有一直徑大於對應導電延伸部之直徑。接觸平台610可與第一表面齊平,且可伴隨拋光操作加以形成或完成以確保複數個平台之間的垂直一致性。
第6B圖繪示另外的配置,在此配置中,導電延伸部620形成為延伸超過互連結構之第一表面。導電延伸部620可藉由和前述之導電延伸部440相似的製程來形成。在另外的多個實施例中,任一組導電延伸部可藉由施行選擇蝕刻(selective etch)以使互連結構內填滿的通孔之介電質凹陷。
第7圖繪示根據本技術之多個實施例的示例性扇出互連結構700的剖面示意圖。扇出互連結構700可繪示額外的接合操作,在此接合操作中,主動裝置結構400之導電延伸部440與互連結構600之導電延伸部620接合。延伸部可以數種方法接合。例如,微凸塊(microbumps)可形成於兩個導電延伸部之間以使兩結構接合。此外,兩導電延伸部可直接耦接或黏接在一起。例如,一旦主動裝置結構400放置於互連結構600上,導電延伸部可以超音波黏接製程(ltrasonic bonding process)加以黏接,在超音波黏接製程中,可使用壓力與/或震動以引起兩導電延伸部之間的黏接接合以完成總體扇出互連結構 700。應理解的是,結構500與700僅為本技術包含之耦接方案的示例,且可類似地施行其他接合操作。根據本技術之多個實施例,藉由使互連結構自主動裝置結構解耦,扇出結構可提供優越的性能及相較於傳統結構降低的熱缺陷(thermal deficiencies)。
在前面描述中,為了解釋之目的,已經闡述了許多細節以便提供對本技術的各種實施例之理解。然而,對於本領域技術人員很顯然的是,某些實施例可以在沒有這些細節中的一些或者具有附加細節的情況下而施行。
縱然已揭露數個實施例,本領域技術人員應理解可於不背離這些實施例之精神下使用各種不同的變形、替代結構與同等物。此外,為了避免無謂的混淆本技術,不再說明許多已知的製程與元件。因此,上述說明不應視為本技術之範圍之限制。
在提供數值範圍的情況下,應該理解的是,除非文中另有明確規定,在該範圍的上限和下限之間的每個中介值至下限單位的最小部分也被具體揭露。涵蓋了任何較窄範圍,其在一表述範圍內的任何表述數值或未表述之中介值到任何表述範圍內的任何其他表述值或中介值之間。這些較小範圍的上限和下限可以獨立地包括在該範圍內或排除在外,並且其中任一範圍、或兩者皆非、或兩個範圍都包括在較小範圍內的各個範圍也包含在本技術內,但受限於表述範圍中任何具體排除之限制。如果表述的範圍包括一個或兩個限制值,則排除這些限制值中的一個或兩個限制值的範圍也包括在內。
此處與所附之申請專利範圍使用之單數形式「一」、「一個」與「該」包含複數含意(plural references),除非內文另有明確指示。從而,舉例來說,提及「一層」包含複數個這類的層,且提及「該材料」包含一或更多前驅物(precursors)與本領域技術人員習知的同等物等。
此外,當於此說明書與所附之申請專利範圍中使用詞「包含」與「包括」,是用以指定所述特徵、整體、零件或操作之存在,但並不排除存在或增加一或更多特徵、整體、零件、操作、動作或其群組。
105、110、115:操作
100:方法

Claims (18)

  1. 一種形成一扇出互連結構的方法,包含:形成一疊加於一第一基板上的半導體主動裝置結構,其中該半導體主動裝置結構包含多個第一導電接點;形成一疊加於一第二基板上的互連結構,其中該互連結構包含多個第二導電接點;及使該第一基板與該第二基板接合,其中使該第一基板與該第二基板接合之步驟包含使該些第一導電接點與該些第二導電接點耦接,且其中該互連結構延伸超過該半導體主動裝置結構之橫向尺寸,其中該互連結構包含多個全域互連形成於複數個介電材料層內,該互連結構係以一反向製程來形成,在該反向製程中,一最後全域互連層形成於一半全域或中間互連層之前。
  2. 如申請專利範圍第1項所述之方法,其中該半導體主動裝置結構包含一金屬化(metallization)層疊加於多個半導體主動裝置層上。
  3. 如申請專利範圍第1項所述之方法,其中該些第一導電接點包含複數個導電柱自該半導體主動裝置結構之一第一表面延伸,該半導體主動裝置結構之該第一表面相對於一第二表面,該第二表面相鄰於該第一基板。
  4. 如申請專利範圍第3項所述之方法,其中該互連結構之一第一表面定義出複數個存取通孔,該互連結構之該第一表面相對於耦接該第二基板的一第二表面。
  5. 如申請專利範圍第4項所述之方法,其中每一該複數個存取通孔為自該互連結構之該第一表面逐漸縮減的一錐形。
  6. 如申請專利範圍第5項所述之方法,其中每一該複數個存取通孔包含一導電襯墊。
  7. 如申請專利範圍第6項所述之方法,其中該些第二導電接點包含一導電填充物,該導電填充物包含於該複數個存取通孔內。
  8. 如申請專利範圍第7項所述之方法,其中使該第一基板與該第二基板接合之步驟更包含:使包含於該複數個存取通孔內的該導電填充物接觸該複數個導電柱;及加熱該導電填充物以使該導電填充物熔化(melt)且流經該複數個導電柱以使該導電填充物與該複數個導電柱電耦接。
  9. 如申請專利範圍第3項所述之方法,其中該些第二導電接點包含沿著該互連結構之一第一表面定義出的複數個導電平台,該互連結構之該第一表面相對於耦接該第二基板的該第二表面。
  10. 如申請專利範圍第9項所述之方法,其中使該第一基板與該第二基板接合之步驟包含使該複數個導電柱黏接至該複數個導電平台。
  11. 如申請專利範圍第1項所述之方法,其中該互連結構包含多個第三導電接點,且其中該方法更包含:形成一疊加於一第三基板上的第二半導體主動裝置結構,其中該第二半導體主動裝置結構包含多個第四導電接點;及使該第三基板與該第二基板接合,其中使該第三基板與該第二基板接合之步驟包含使該些第四導電接點與該些第三導電接點耦接。
  12. 一種形成一互連結構的方法,包含:形成一用於一或更多半導體主動裝置的反向互連結構於一互連基板上方,其中該反向互連結構包含一導電材料,該導電材料形成於複數個介電材料層內;沿著該反向互連結構之一第一表面形成複數個通孔,該反向互連結構之該第一表面相對於一第二表面,該第二表面相鄰於該互連基板,其中該複數個通孔提供路徑至該導電材料;以該導電材料作為該複數個通孔中的每一者之內襯;及以一導電填充物材料至少部分填充該複數個通孔中的每一者,其中該複數個介電材料層中相鄰於該第二表面的一介電材料層形成於該複數個介電材料層中相鄰於該第一表面的一介電材料層之前。
  13. 如申請專利範圍第12項所述之方法,更包含:使一第一半導體主動裝置之複數個導電延伸部定位於該複數個通孔之一子集內;及使該導電填充物材料熔化以使該第一半導體主動裝置之該些導電延伸部與該反向互連結構之該導電材料電耦接。
  14. 如申請專利範圍第13項所述之方法,更包含:使一第二半導體主動裝置之複數個導電延伸部定位於該複數個通孔之一第二子集內;及使該複數個通孔之該第二子集內的該導電填充物材料熔化以使該第二半導體主動裝置之該些導電延伸部與該反向互連結構之該導電材料電耦接。
  15. 如申請專利範圍第12項所述之方法,更包含使該反向互連結構之該第一表面平坦化以使該導電填充物材料限制於該複數個通孔內。
  16. 一種形成一互連結構的方法,包含:形成一用於一或更多半導體主動裝置的反向互連結構於一互連基板上方,其中該反向互連結構包含一導電材料,該導電材料形成於複數個介電材料層內;及沿著該反向互連結構之一第一表面形成複數個接觸平台,該反向互連結構之該第一表面相對於一第二表面,該第二表面相鄰於該互連基板,其中該複數個接觸平台提供路徑至該導電材料,且 其中該複數個接觸平台中的每一者之尺寸大於該一或更多半導體主動裝置之一對應導電延伸部,其中該複數個介電材料層中相鄰於該第二表面的一介電材料層形成於該複數個介電材料層中相鄰於該第一表面的一介電材料層之前。
  17. 如申請專利範圍第16項所述之方法,其中該複數個接觸平台延伸超過一介電材料,該介電材料定義出該反向互連結構之該第一表面。
  18. 如申請專利範圍第16項所述之方法,更包含:使一半導體主動裝置之複數個導電延伸部定位於相鄰該複數個接觸平台;及使該複數個導電延伸部與該複數個接觸平台黏接以使該半導體主動裝置之該複數個導電延伸部與該反向互連結構之該導電材料電耦接,其中該反向互連結構延伸超過該半導體主動裝置之橫向尺寸。
TW107137251A 2017-10-23 2018-10-22 形成扇出互連結構與互連結構的方法 TWI699840B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762575977P 2017-10-23 2017-10-23
US62/575,977 2017-10-23

Publications (2)

Publication Number Publication Date
TW201935581A TW201935581A (zh) 2019-09-01
TWI699840B true TWI699840B (zh) 2020-07-21

Family

ID=66171186

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107137251A TWI699840B (zh) 2017-10-23 2018-10-22 形成扇出互連結構與互連結構的方法

Country Status (4)

Country Link
US (2) US11699651B2 (zh)
KR (1) KR102530568B1 (zh)
TW (1) TWI699840B (zh)
WO (1) WO2019083875A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12074106B2 (en) 2017-10-23 2024-08-27 Applied Materials, Inc. Fan-out interconnect integration processes and structures

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11824002B2 (en) * 2019-06-28 2023-11-21 Intel Corporation Variable pitch and stack height for high performance interconnects
KR20210075558A (ko) 2019-12-13 2021-06-23 삼성전자주식회사 반도체 패키지의 제조 방법
CN111937149B (zh) * 2020-07-16 2021-07-09 长江存储科技有限责任公司 用于键合半导体结构及其半导体器件的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060121690A1 (en) * 2002-12-20 2006-06-08 Pogge H B Three-dimensional device fabrication method
TW200733333A (en) * 2005-12-22 2007-09-01 Shinko Electric Ind Co Flip-chip mounting substrate and flip-chip mounting method
TW200802645A (en) * 2005-10-28 2008-01-01 Megica Corp Semiconductor chip with post-passivation scheme formed over passivation layer
TW201701406A (zh) * 2015-03-18 2017-01-01 艾馬克科技公司 半導體裝置和其製造方法
TW201725685A (zh) * 2016-01-11 2017-07-16 愛思開海力士有限公司 具有凸塊接合結構的半導體封裝

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514613A (en) * 1994-01-27 1996-05-07 Integrated Device Technology Parallel manufacturing of semiconductor devices and the resulting structure
US9368428B2 (en) * 2004-06-30 2016-06-14 Cree, Inc. Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US20080315407A1 (en) * 2007-06-20 2008-12-25 Vertical Circuits, Inc. Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
JP2011187473A (ja) 2010-03-04 2011-09-22 Nec Corp 半導体素子内蔵配線基板
US8680684B2 (en) * 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US10157823B2 (en) * 2014-10-31 2018-12-18 Qualcomm Incorporated High density fan out package structure
US10319701B2 (en) 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9520333B1 (en) 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
US10396269B2 (en) * 2015-11-05 2019-08-27 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits
KR101837511B1 (ko) 2016-04-04 2018-03-14 주식회사 네패스 반도체 패키지 및 그 제조방법
KR102530568B1 (ko) 2017-10-23 2023-05-08 어플라이드 머티어리얼스, 인코포레이티드 팬-아웃 상호연결부 통합 공정들 및 구조들

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060121690A1 (en) * 2002-12-20 2006-06-08 Pogge H B Three-dimensional device fabrication method
TW200802645A (en) * 2005-10-28 2008-01-01 Megica Corp Semiconductor chip with post-passivation scheme formed over passivation layer
TW200733333A (en) * 2005-12-22 2007-09-01 Shinko Electric Ind Co Flip-chip mounting substrate and flip-chip mounting method
TW201701406A (zh) * 2015-03-18 2017-01-01 艾馬克科技公司 半導體裝置和其製造方法
TW201725685A (zh) * 2016-01-11 2017-07-16 愛思開海力士有限公司 具有凸塊接合結構的半導體封裝

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12074106B2 (en) 2017-10-23 2024-08-27 Applied Materials, Inc. Fan-out interconnect integration processes and structures

Also Published As

Publication number Publication date
US11699651B2 (en) 2023-07-11
KR102530568B1 (ko) 2023-05-08
US20190122981A1 (en) 2019-04-25
TW201935581A (zh) 2019-09-01
WO2019083875A1 (en) 2019-05-02
KR20200060774A (ko) 2020-06-01
US12074106B2 (en) 2024-08-27
US20230352402A1 (en) 2023-11-02

Similar Documents

Publication Publication Date Title
TWI405321B (zh) 三維多層堆疊半導體結構及其製造方法
US9536785B2 (en) Method of manufacturing through silicon via stacked structure
JP5308145B2 (ja) 半導体装置
TWI699840B (zh) 形成扇出互連結構與互連結構的方法
KR100721353B1 (ko) 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조
TWI466258B (zh) 電性通透連接及其形成方法
JP5663607B2 (ja) 半導体装置
TWI596680B (zh) 具有打線接合互連的低熱膨脹係數部件
KR102415484B1 (ko) 패키지 구조체 및 그 제조 방법
JP2008182224A (ja) スタック・パッケージ及びスタック・パッケージの製造方法
US11694996B2 (en) Semiconductor package including a pad contacting a via
WO2016044389A1 (en) Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
WO2010097191A1 (en) A metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom
CN115763281B (zh) 一种扇出式芯片封装方法及扇出式芯片封装结构
US9263376B2 (en) Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
CN112397445B (zh) Tsv导电结构、半导体结构及制备方法
TWI604566B (zh) 半導體晶片與其多晶片封裝及其製造方法
TW202125732A (zh) 封裝結構及其形成方法
US20240063185A1 (en) Semiconductor bonding structure and method of forming the same
US8988893B2 (en) Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device
KR101013545B1 (ko) 스택 패키지 및 그의 제조방법
TWI757864B (zh) 封裝結構及其形成方法
US9368442B1 (en) Method for manufacturing an interposer, interposer and chip package structure
CN218918835U (zh) 半导体封装装置
CN219917166U (zh) 半导体封装装置