TWI689912B - Display system and display frame compensation method thererof - Google Patents

Abstract

A display system and a display frame compensation method thereof are provided. The display system includes a display panel, a display driving circuit, and a voltage drop estimation circuit. The display panel includes a plurality of power lines and a plurality of pixel units. A power terminal of each of the pixel units is coupled to a power voltage through each of the power lines. The display driving circuit is coupled to the display panel, and receives a plurality of data driving voltages to respectively drive the pixel units. The voltage drop estimation circuit is coupled to the display driving circuit and receives a grayscale image data. The voltage drop estimation circuit converts the grayscale image data into a plurality of current data and the data driving voltages, generates a plurality of voltage drop values according to a parasitic resistance value of a power line between an adjacent two pixel units and the current data, and adjusts at least part of the data driving voltages or compensates voltages of the power terminals of at least part of the pixel units according to the voltage drop values.

Description

Display system and display picture compensation method

The invention relates to a display technology, and in particular to a display picture compensation method and a display system adopting the display picture compensation method.

With the development of the semiconductor industry and the optoelectronic industry, Light Emission Diode (LED) is not only widely used in lighting applications, but also in the field of displays. Among them, Organic Light-Emitting Diode (Organic-LED, OLED) displays are considered to be one of the future mainstream displays due to their thin thickness, high efficiency, high contrast, no viewing angle limitation, and fast response speed.

Please refer to FIG. 1, which is a partial equivalent circuit diagram of an existing organic light-emitting diode display panel. The organic light-emitting diode display panel 920 includes a plurality of scan lines SL, a plurality of data lines DL, a plurality of power traces PL, and a pixel array, wherein the pixel array has a plurality of pixel units PX arranged in an array. However, for the sake of simplicity, FIG. 1 only shows one piece of information of the organic light-emitting diode display panel 920 Multiple pixel units PX on line DL. The power terminal PI of each pixel unit PX is sequentially coupled to the power trace PL for transmitting the power voltage ELVDD. Each pixel unit PX includes a pixel driving circuit PD and an organic light emitting diode LD. Each pixel driving circuit PD adopts a circuit structure of two transistors T1 and T2 and a capacitor C1 (that is, 2T1C). The first terminal of the transistor T1 is coupled to the power terminal PI. The second end of the transistor T1 is coupled to the anode end of the organic light emitting diode LD. The cathode terminal of the organic light emitting diode LD is coupled to the reference voltage VSS. The first end of the transistor T2 is coupled to the corresponding data line DL to receive the corresponding data driving voltage. The second terminal of the transistor T2 is coupled to the control terminal of the transistor T1. The control terminal of the transistor T2 is coupled to the corresponding scan line SL to receive the corresponding scan driving voltage. The first end of the capacitor C1 is coupled to the control end of the transistor T1 and the second end of the transistor T2. The second terminal of the capacitor C1 is coupled to the first terminal of the transistor T1 and the power terminal PI.

In an ideal situation, it is assumed that the power supply line PL has no impedance, that is, the power supply voltage ELVDD has no voltage drop (IR drop) during transmission, so the voltage of the power supply terminal PI of each pixel unit PX is the power supply Voltage ELVDD. In this case, when the display panel displays a solid color picture, the current Id flowing through each pixel driving circuit PD is the same, so that the brightness of each organic light emitting diode LD is the same, so that the display panel presents a uniform brightness . However, in an actual situation, there is inevitably an impedance in the power supply trace PL, such as the resistance R1 shown in FIG. 1. When a current flows through the power supply line PL, a voltage drop will be generated across each resistor R1 of the power supply line PL, so that the voltage of the power supply terminal PI of each pixel unit PX is different, which will affect the display screen Brightness uniformity and color accuracy.

In view of this, the present invention provides a display system and a display picture compensation method thereof, which can improve the brightness uniformity and color accuracy of a display picture.

The display system of the present invention includes a display panel, a display driving circuit, and a voltage drop estimation circuit. The display panel includes multiple power traces and multiple pixel units. The power supply terminal of each of the pixel units is coupled to the power supply voltage through one of the power supply traces. The display driving circuit is coupled to the display panel and is used to receive a plurality of data driving voltages to drive the pixel units respectively. The voltage drop estimation circuit is coupled to the display driving circuit, and receives gray-scale image data. The voltage drop estimation circuit converts the gray-scale picture data into a plurality of current data and the driving voltages of these data, and according to the parasitic resistance value of the power traces between the two adjacent pixel units in these pixel units and these Current data produces multiple voltage drop values. The voltage drop estimation circuit adjusts at least part of the data driving voltages or compensates at least part of the voltages of the power terminals of the pixel units according to the voltage drops.

In an embodiment of the invention, the above display system further includes a resistance setting interface. The resistance setting interface is coupled to the voltage drop estimation circuit. The resistance setting interface is used to provide a parasitic resistance value to the voltage drop estimation circuit.

The display picture compensation method of the present invention is applied to the display panel of the above display system, and includes the following steps. Set the parasitic resistance value of the power trace between two adjacent pixel units in these pixel units. Convert gray-scale image data into multiple current data and multiple data driving voltages. According to the parasitic resistance value and the current data Multiple voltage drop values. According to the voltage drop values, at least some of the data driving voltages are adjusted or at least some of the power supply voltages of the pixel units are compensated, and the pixel units are driven accordingly.

Based on the above, the display system and the display screen compensation method proposed by the present invention can calculate the difference between the power supply voltage and the power supply terminal of each pixel unit according to the impedance value of the power supply trace and the received gray scale screen data Voltage drop value, and adjust the data driving voltage of at least some pixel units or compensate the voltage of the power supply terminal of at least some pixel units according to the voltage drop value, so as to improve the brightness uniformity and color accuracy of the displayed image.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100: display system

120: display panel

140: Display drive circuit

160: Resistance setting interface

180: Voltage drop estimation circuit

190: Power circuit

920: Organic light-emitting diode display panel

C1: capacitance

CUR4: Curve

D1: First direction

D2: Second direction

DB ₁₁ , DB ₁₂ , DB _C1 , DB _C2 : data block

DL: data cable

IDATA: current data

Id: current

LD: organic light emitting diode

PA: pixel array

PD: pixel drive circuit

PDATA: Grayscale picture data

PI: Power terminal

PL: power wiring

PX: pixel unit

R1: resistance

RDB_1: the first block column

RDB_C: intermediate block column

RVAL: Parasitic resistance value

S800, S810, S820, S830, S840: steps

SL: Scan line

SUR1, SUR2, SUR3: curved surface

T1, T2: transistor

VDATA: data drive voltage

ELVDD: power supply voltage

VDRP: voltage drop value

VSCAN: Scan drive voltage

VSS: reference voltage

~

、

~

:係數

~

,

~

:coefficient

The following drawings are part of the description of the present invention, and illustrate exemplary embodiments of the present invention. The drawings together with the description of the description illustrate the principle of the present invention.

FIG. 1 is a partial equivalent circuit diagram of a conventional organic light-emitting diode display panel.

2 is a block diagram of a display system according to an embodiment of the invention.

FIG. 3 is a schematic diagram illustrating conversion of gray-scale image data into current data according to an embodiment of the invention.

FIG. 4 is a schematic diagram illustrating the relationship between the gray scale value and the estimated current value according to an embodiment of the invention.

5 is a schematic diagram of an equivalent two-dimensional circuit model of a display panel according to an embodiment of the invention.

6A is a schematic diagram of a grayscale screen for testing according to an embodiment of the invention.

FIG. 6B is a schematic diagram of the voltages of the power terminals of each pixel unit obtained by simulation analysis according to an embodiment of the invention.

6C is a schematic diagram of the voltages of the power terminals of each pixel unit obtained by calculation according to an embodiment of the invention.

FIG. 6D is a schematic diagram of the voltage of the power supply terminal of each pixel unit obtained by calculation according to another embodiment of the invention.

7A is a schematic diagram illustrating coefficients of two-dimensional filtering in a first direction according to an embodiment of the invention.

7B is a schematic diagram illustrating the coefficients of the two-dimensional filtering in the second direction according to an embodiment of the invention.

FIG. 8 is a flow chart of the steps of the display image compensation method according to an embodiment of the invention.

In order to make the content of the present invention easier to understand, the following specific examples are given as examples on which the present invention can indeed be implemented. In addition, wherever possible, at Elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar components.

2 is a block diagram of a display system according to an embodiment of the invention. Please refer to Figure 1 and Figure 2 together. The display system 100 includes a display panel 120, a display driving circuit 140, and a voltage drop estimation circuit 180, but the invention is not limited thereto. In other embodiments of the present invention, the display system 100 may further include a resistance setting interface 160 and a power circuit 190.

In an embodiment of the present invention, the display panel 120 may be, for example, an organic light emitting diode display panel, and the circuit architecture thereof may be as shown in the circuit structure of the organic light emitting diode display panel 920 of FIG. 1, but the present invention is not limited to Therefore, the invention does not limit the circuit structure of the display panel 120. The display panel 120 includes a plurality of scan lines SL, a plurality of data lines DL, a plurality of power traces PL, and a pixel array PA. The pixel array PA includes a plurality of pixel units PX arranged in an array. The power supply terminal PI of each pixel unit PX is coupled to the power supply voltage ELVDD through a power supply trace PL. The power supply trace PL itself has an impedance, such as the resistance R1 (parasitic resistance) shown in FIG. 1. Therefore, when a current flows through the power supply trace PL, a voltage drop is generated across each resistor R1 of the power supply trace PL. In addition, for the implementation details of the display panel 120, reference may be made to the related description of FIG. 1 described above, and details are not described herein again.

The display driving circuit 140 is coupled to the display panel 120. The display driving circuit 140 can generate a plurality of scan driving voltages VSCAN to the scan lines SL of the display panel 120. The display driving circuit 140 receives a plurality of data driving voltages VDATA and outputs the data driving voltages VDATA to the data lines DL to drive the pixel arrays respectively In the pixel units PX in the row PA, the data driving voltage VDATA may be an unadjusted data driving voltage or an adjusted data driving voltage, which will be described in detail later.

The voltage drop estimation circuit 180 is coupled to the display driving circuit 140, and receives gray-scale image data PDATA. The voltage drop estimation circuit 180 can convert the gray-scale picture data PDATA into a plurality of current data IDATA and the data driving voltage VDATA. The voltage drop estimation circuit 180 can generate a plurality of voltages according to the parasitic resistance value RVAL (that is, the resistance value of the resistor R1) of the power traces between two adjacent pixel units in the pixel units PX and the current data IDATA Decrease VDRP. The voltage drop estimation circuit 180 can adjust at least part of the data driving voltages in the data driving voltages VDATA according to the voltage drop values VDRP. Alternatively, the voltage drop estimation circuit 180 may compensate the voltage of the power terminal PI of at least some of the pixel units PX according to the voltage drop values VDRP, so that the data driving voltage VDATA may not need to be adjusted. Alternatively, the voltage drop estimation circuit 180 may also adjust at least part of the data drive voltages in the data drive voltages VDATA according to the voltage drop values VDRP and compensate the power supply of at least part of the pixel units in the pixel units PX The voltage at terminal PI.

Furthermore, when the transistor T2 in the pixel unit PX is turned on in response to the scan driving voltage VSCAN, the data driving voltage VDATA can be transmitted to the control terminal of the transistor T1 through the turned on transistor T2. According to the characteristics of the transistor, the current Id of the transistor T1 (that is, the current flowing into the organic light-emitting diode LD) is proportional to the formula (1), where ELVDD′ is the voltage of the first end of the transistor T1 (that is, the pixel The voltage of the power supply terminal PI of the cell PX), and VTH is the critical voltage of the transistor T1 (threshold voltage). In addition, the brightness of the organic light emitting diode LD is proportional to the current Id. Therefore, when the voltage drop of the power supply line PL due to its parasitic resistance causes the voltage of the power supply terminal PI of the pixel unit PX to decrease (that is, ELVDD' in equation (1) is less than the power supply voltage ELVDD), according to the obtained pixels The voltage drop value VDRP of the unit PX is used to adjust the data driving voltage VDATA of the pixel unit PX or the power supply voltage ELVDD to compensate the voltage ELVDD' of the power supply terminal PI of the pixel unit PX, so that the brightness of the organic light emitting diode LD Adjust to the correct brightness. In this way, the brightness uniformity and color accuracy of the overall display image can be improved.

(ELVDD '- VDATA - VTH) 2 formula (1)

In an embodiment of the present invention, the display driving circuit 140 may include a timing control circuit, a data line driving circuit, and a scanning line driving circuit, but the present invention is not limited thereto. The timing control circuit, data line drive circuit and scan line drive circuit can be implemented by using the existing timing control circuit, data line drive circuit and scan line drive circuit respectively, and the implementation details and related operations are well known to those skilled in the art, so I will not repeat them here. In an embodiment of the invention, the voltage drop estimation circuit 180 may be implemented by a processor or a microcontroller, but the invention is not limited to this.

The power circuit 190 is coupled to the voltage drop estimation circuit 180 and the display panel 120 to provide the power voltage ELVDD. In particular, the voltage drop estimation circuit 180 can adjust the power supply voltage ELVDD through the power supply circuit 190. In an embodiment of the present invention, the power circuit 190 can be implemented by using an existing power conversion circuit, such as a DC-DC conversion circuit or an AC-DC conversion circuit.

The resistance setting interface 160 is coupled to the voltage drop estimation circuit 180. Resistance setting The surface 160 can provide the parasitic resistance value RVAL (ie, the resistance value of the resistor R1) to the voltage drop estimation circuit 180. The voltage drop estimation circuit 180 may store the received parasitic resistance value RVAL in its internal register or memory element. In an embodiment of the invention, the resistance setting interface 160 can be implemented using an existing signal transmission interface.

In an embodiment of the present invention, the parasitic resistance value RVAL may also be pre-programmed in the memory element of the voltage drop estimation circuit 180, so that the display system 100 may omit the setting of the resistance setting interface 160.

In an embodiment of the invention, the parasitic resistance value RVAL can be obtained by testing the display panel 120 after it is manufactured. After obtaining the parasitic resistance value RVAL, the parasitic resistance value RVAL can be input into the register or memory element of the voltage drop estimation circuit 180 through the resistance setting interface 160 for the voltage drop estimation circuit 180 to perform various operations to generate this The use of these voltage drop values VDRP.

In an embodiment of the invention, the parasitic resistance RVAL can be obtained by testing the display panel 120 using a resistance estimation device, where the resistance estimation device can be, for example, an optical instrument. By measuring the brightness value of the display panel 120 by optical instruments, the parasitic resistance value RVAL between two adjacent pixel units in these pixel units PX can be estimated, but the invention is not limited thereto. For example, the optical instrument can measure the brightness difference of the display panel 120 of different display images. In an embodiment of the present invention, according to the brightness difference, a parasitic resistance value RVAL corresponding to the brightness difference can be found in a look-up table. In another embodiment of the present invention, the parasitic resistance value RVAL corresponding to the brightness difference can be converted according to the brightness difference. In an embodiment of the present invention, the above-mentioned look-up table may, for example, measure the display panel 120 after it is manufactured Try to get.

In another embodiment of the present invention, the parasitic resistance RVAL between two adjacent pixel units in the display panel 120 can also be provided by the panel trace provided by the display panel manufacturer (that is, the power trace PL of the display panel 120 ) Information (such as length, cross-sectional area or wire, etc.), estimated and obtained.

In yet another embodiment of the present invention, it is also possible to estimate the parasitic resistance between two adjacent pixel units by providing a test voltage to the power supply line PL and measuring the current of the power supply line PL Value RVAL.

In yet another embodiment of the present invention, it is also possible to estimate the parasitic resistance between two adjacent pixel units by providing a test current to the power supply line PL and measuring the voltage of the power supply line PL Value RVAL. FIG. 3 is a schematic diagram illustrating conversion of gray-scale image data into current data according to an embodiment of the invention. Please refer to Figure 2 and Figure 3 together. For ease of explanation, the following description uses the resolution of the display panel 120 as 2160 times 1080, and the grayscale image data PDATA includes (2160 times 1080) grayscale data as an example. As for other resolutions and other amounts of gray The grayscale picture data PDATA of the gradation data can be inferred according to the following description and so on.

First, in order to reduce the calculation amount of the voltage drop estimation circuit 180, the voltage drop estimation circuit 180 may divide the gray-scale picture data PDATA into a plurality of data blocks. For example, as shown in FIG. 3, the voltage drop estimation circuit 180 divides the gray-scale picture data PDATA into M block rows along the first direction D1, and divides the gray-scale picture data PDATA into the second direction D2 into N block rows to form (M times N) data blocks, where the first direction D1 is perpendicular to the second direction D2, and the display panel 120 These power traces PL extend along the first direction D1, and M and N are integers greater than one. In an embodiment of the present invention, the first direction D1 may be, for example, the arrangement direction of the scanning lines SL on the display panel 120, and the second direction D2 may be, for example, the arrangement direction of the data lines DL on the display panel 120. The invention is not limited to this.

Next, the voltage drop estimation circuit 180 converts each of the data blocks (ie, (M times N) data blocks) into one of the current data IDATA. Furthermore, each data block has multiple gray-scale data. The voltage drop estimation circuit 180 can convert the grayscale data in each data block into a plurality of estimated current values, and perform an average operation or other smoothing filter processing on the estimated current values to Get one of the current data. For example, as shown in FIG. 3, the data block DB ₁₁ has ((2160÷ M )×(1080÷ N )) gray-scale data, where the gray-scale values of such gray-scale data include 128 and 64, But it is not limited to this. The voltage drop estimation circuit 180 can convert the ((2160÷ M )×(1080÷ N )) grayscale data in the data block DB ₁₁ to ((2160÷ M )×(1080÷ N )) estimates a current value, and the averaging calculation ((2160 ÷ M) × ( 1080 ÷ N)) to afford a estimated current values corresponding to the current data block DB ₁₁ of the I data _11, such as of formula (2 ), where PDATA(k,s) in equation (2) represents each grayscale data in the data block DB ₁₁ , and the conversion function Gray2Curr will be described in detail later. By analogy, the current data I _{mn of} the remaining data blocks DB _mn is shown in equation (3), where PDATA(k,s) in equation (3) represents the grayscale data in the data block DB _mn , m is an integer less than or equal to M, and n is an integer less than or equal to N. In addition, these current data IDATA can be expressed in matrix, as shown in equation (4).

In an embodiment of the present invention, the display driving circuit 140 can be used to control the display panel 120 to display a screen with a specific gray level value, and the total current of the power traces PL of the display panel 120 can be measured. Then divide the total current by the number of pixel units PX to obtain an estimated current value corresponding to the specific gray level value. For example, the display panel 120 can display a screen with a gray scale value of 255, and then measure the total current of the power traces PL of the display panel 120, and divide the total current by the number of pixel units PX to obtain the corresponding An estimated current value at a gray scale value of 255. By analogy, the estimated current value corresponding to various gray levels can be obtained by the above-mentioned measurement method. Or, based on the estimated current value corresponding to the gray scale value of 255, the relationship between the brightness and the current is proportional to the relationship between the brightness and the gray scale value of the gamma (gamma) 2.2, to calculate the corresponding Estimated current values for various gray levels. In this way, the relationship between the gray scale value and the estimated current value can be obtained as shown in curve CUR4 of FIG. 4. It can be understood that the relationship represented by the curve CUR4 in FIG. 4 is the conversion function of the gray scale to current Count Gray2Curr.

、

、...、

為二維濾波於第一方向D1的係 數，而

、

、...、

為二維濾波於第二方向D2的係數。 After obtaining the current data of each data block, the voltage drop estimation circuit 180 may perform two-dimensional filtering on the current data IDATA to obtain multiple filtered data, and multiply the filtered data with the parasitic resistance value RVAL Operation to obtain the voltage drop values VDRP corresponding to the data blocks, as shown in equation (5), where the coefficient

,

,...,

Is a coefficient that is two-dimensionally filtered in the first direction D1, and

,

,...,

It is a coefficient that is two-dimensionally filtered in the second direction D2.

It is worth mentioning here that if two-dimensional filtering is not performed on these current data IDATA, the current data IDATA and the parasitic resistance value RVAL are multiplied directly to be used as the corresponding data blocks. For these voltage drop values VDRP, the errors of the obtained voltage drop values VDRP will be larger. For example, FIG. 5 is a schematic diagram of an equivalent two-dimensional circuit model of a display panel according to an embodiment of the invention, where V(x, y) represents the voltage of the power terminal PI of each pixel unit PX, I (x, y) represents the current flowing to each pixel unit PX, x is a positive integer less than or equal to 1080, and y is a positive integer less than or equal to 2160; and FIG. 6A is drawn according to an embodiment of the invention A schematic diagram of the grayscale screen used for the test. If the computer analysis software MatLab is used to simulate and analyze the equivalent two-dimensional circuit model of the display panel of FIG. 5 according to the gray scale data of the gray scale screen shown in FIG. 6A, each pixel can be obtained The voltage of the power supply terminal PI of the unit PX is shown in the curved surface SUR1 of FIG. 6B. In contrast, if the gray scale data of the gray scale screen shown in FIG. 6A is converted into the current data IDATA by Equations (2) to (4), then each pixel obtained by multiplying the parasitic resistance value RVAL The voltage of the power supply terminal PI of the unit PX is shown in the curved surface SUR2 of FIG. 6C. It can be seen that there is a great error between the curved surface SUR2 of FIG. 6C and the curved surface SUR1 of FIG. 6B.

、

、...、

以及於第二方向D2的 係數

、

、...、

。舉例來說，若M為8以及N為6，則二維濾波於第一方向D1的係數

~

如圖7A所示，而二維濾波於第二方向D2的係數

~

如圖7B所示。另外，圖6C的曲面SUR2在透過二維濾波之後所得到的曲面則如圖6D的曲面SUR3所示。圖6D的曲面SUR3相較於圖6C的曲面SUR2更加趨近於圖6B的曲面SUR1。 In order to make the curved surface SUR2 of FIG. 6C more similar to the curved surface SUR1 of FIG. 6B, in one embodiment of the present invention, the computer analysis software MatLab can be used to extract from the curved surface SUR1 of FIG. 6B through curve fitting Coefficient of two-dimensional filtering in the first direction D1

,

,...,

And the coefficient in the second direction D2

,

,...,

. For example, if M is 8 and N is 6, the coefficients of the two-dimensional filtering in the first direction D1

~

As shown in FIG. 7A, the coefficients that are two-dimensionally filtered in the second direction D2

~

As shown in Figure 7B. In addition, the curved surface SUR2 of FIG. 6C obtained through the two-dimensional filtering is as shown in the curved surface SUR3 of FIG. 6D. The curved surface SUR3 of FIG. 6D is closer to the curved surface SUR1 of FIG. 6B than the curved surface SUR2 of FIG. 6C.

Please refer to Figure 2 and Figure 3 again. After obtaining the voltage drop values VDRP corresponding to the data blocks through equation (5), the voltage drop estimation circuit 180 can select one of the M block lines as the correction block line, and Based on the voltage drop values corresponding to the correction block row, adjust the data driving voltage corresponding to each of the M block rows, or adjust the power supply voltage ELVDD to compensate for the M block The power supply terminals of the pixel units in each other block row in the row Pressure. In this way, the brightness of the adjusted other block rows can be made to be the same as the brightness of the corrected block row. The selection of the corrected block row can be determined according to actual application or design requirements.

For example, assuming that the voltage drop estimation circuit 180 selects the first block row RDB_1 of the M block rows as the correction block row, the voltage drop estimation circuit 180 corresponds to the first block row RDB_1. These voltage drop values are benchmarks, for example, adjusting the data driving voltage corresponding to the middle block row RDB_C in the M block rows or adjusting the power supply voltage ELVDD to compensate for the voltages of the power supply terminals of all the pixel units corresponding to the middle block row RDB_C . In this case, the voltage drop estimation circuit 180 can calculate the voltage drop value of the first data block DB _C1 of the middle block row RDB_C and the voltage drop of the first data block DB ₁₁ of the first block row RDB_1 The difference between the two, and adjust all data driving voltages corresponding to the data block DB _C1 according to the difference, or adjust the power supply voltage ELVDD according to the difference to compensate all the data blocks corresponding to the data block DB _C1 The voltage of the power supply terminal of the pixel unit. Similarly, the voltage drop estimation circuit 180 can calculate the voltage drop value of the second data block DB _C2 of the middle block row RDB_C and the voltage drop value of the second data block DB ₁₂ of the first block row RDB_1 The difference between the two, and adjust all data driving voltages corresponding to the data block DB _C2 according to the difference, or adjust the power supply voltage ELVDD according to the difference to compensate all pixels corresponding to the data block DB _C2 The voltage at the power supply end of the unit. The adjustment method of the remaining data blocks in the middle block row RDB_C can be deduced by analogy. In addition, the voltage drop estimation circuit 180 uses the voltage drop values corresponding to the first block row RDB_1 as a reference, and the method of adjusting the data driving voltage of the other block row or compensating the voltage of the power supply terminal can also be deduced by analogy.

Similarly, if the voltage drop estimation circuit 180 selects the middle block row RDB_C among the M block rows as the correction block row, the voltage drop estimation circuit 180 uses the voltage drop values corresponding to the middle block row RDB_C As a reference, for example, the data driving voltage corresponding to the first block row RDB_1 in the M block rows is adjusted or the power supply voltage ELVDD is adjusted to compensate the voltages of the power supply terminals of all the pixel units corresponding to the first block row RDB_1. In this case, the voltage drop estimation circuit 180 can calculate the voltage drop value of the first data block DB ₁₁ of the first block row RDB_1 and the voltage drop of the first data block DB _C1 of the middle block row RDB_C The difference between the two, and adjust all data driving voltages corresponding to the data block DB ₁₁ according to the difference, or adjust the power supply voltage ELVDD according to the difference to compensate for all data corresponding to the data block DB ₁₁ The voltage of the power supply terminal of the pixel unit. Similarly, the voltage drop estimation circuit 180 can calculate the voltage drop value of the second data block DB ₁₂ of the first block row RDB_1 and the voltage drop value of the second data block DB _C2 of the middle block row RDB_C The difference between the two, and adjust all data driving voltages corresponding to the data block DB ₁₂ according to the difference, or adjust the power supply voltage ELVDD according to the difference to compensate all pixels corresponding to the data block DB ₁₂ The voltage at the power supply end of the unit. The rest can be deduced by analogy.

Incidentally, the above embodiment uses the data block as a unit to improve the brightness uniformity and color accuracy of the display image, but the present invention is not limited to this. In other embodiments of the present invention, if the calculation capability of the voltage drop estimation circuit 180 is sufficient, the pixel unit PX can also be used as a unit to improve the brightness uniformity and color accuracy of the display screen, so as to greatly improve the brightness uniformity of the display screen Degree and color accuracy.

FIG. 8 is a flowchart of steps of a method for compensating a display screen according to an embodiment of the invention, which can be used in the display system 100 of FIG. Please refer to FIG. 2 and FIG. 8 at the same time. The display image compensation method in this exemplary embodiment includes the following steps. First, in step S800, the parasitic resistance value RVAL of the power traces between two adjacent pixel units in these pixel units PX is set. Next, in step S810, the gray-scale picture data PDATA is converted into a plurality of data driving voltages VDATA. Then, in step S820, the gray-scale picture data PDATA is converted into a plurality of current data IDATA. Next, in step S830, a plurality of voltage drop values VDRP are generated according to the parasitic resistance value RVAL and the current data IDATA. Afterwards, in step S840, at least part of the data driving voltage VDATA is adjusted or compensated for the voltage of the power terminal PI of at least part of the pixel units PX according to the voltage drop values VDRP, and the pixels are driven accordingly Unit PX.

In addition, the display picture compensation method of the embodiment of the present invention can obtain sufficient teaching, suggestions, and implementation descriptions from the description of the embodiments of FIG. 1 to FIG. 7B, and thus will not be repeated.

In summary, the display system and the display screen compensation method proposed in the embodiments of the present invention can calculate the power supply voltage and the power of each pixel unit according to the impedance value of the power supply trace and the gray scale screen data received The voltage drop value between the terminals, and adjust the data driving voltage of at least some pixel units or compensate the voltage of the power supply terminal of at least some pixel units according to the voltage drop value to improve the brightness uniformity and color accuracy of the displayed image.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art will not deviate from the present invention. Within the spirit and scope, some changes and modifications can be made, so the scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100: display system

120: display panel

140: Display drive circuit

160: Resistance setting interface

180: Voltage drop estimation circuit

190: Power circuit

D1: First direction

D2: Second direction

DL: data cable

ELVDD: power supply voltage

IDATA: current data

PA: pixel array

PDATA: Grayscale picture data

PL: power wiring

PX: pixel unit

RVAL: Parasitic resistance value

SL: Scan line

VDATA: data drive voltage

VDRP: voltage drop value

VSCAN: Scan drive voltage

Claims (13)

A display system includes: a display panel including a plurality of power traces and a plurality of pixel units, wherein a power terminal of each of the pixel units is coupled through one of the power traces A power supply voltage; a display drive circuit, coupled to the display panel, for receiving a plurality of data drive voltages to drive the pixel units; and a voltage drop estimation circuit, coupled to the display drive circuit, and receiving a Gray scale picture data, wherein the voltage drop estimation circuit converts the gray scale picture data into a plurality of current data and the data driving voltages, and according to the power supply between two adjacent pixel units in the pixel units A parasitic resistance value of the line and the current data generate a plurality of voltage drop values, wherein the voltage drop estimation circuit adjusts at least part of the data driving voltages or compensates at least part of the pixel units according to the voltage drop values The voltage of the power supply terminal, wherein the voltage drop estimation circuit divides the gray-scale picture data into a plurality of data blocks, and converts each of the data blocks into one of the current data. The display system as described in item 1 of the patent application further includes: a resistance setting interface coupled to the voltage drop estimation circuit, wherein the resistance setting interface is used to provide the parasitic resistance value to the voltage drop estimation circuit. The display system according to item 1 of the patent application scope, wherein each of the data blocks has a plurality of gray-scale data, and the voltage drop estimation circuit converts the gray-scale data into a plurality of estimated current values, respectively And performing an average operation or smoothing filtering on the estimated current values to obtain one of the current data. The display system as described in item 1 of the patent application scope, wherein the voltage drop estimation circuit performs two-dimensional filtering on the current data to obtain a plurality of filtered data, and multiplies the filtered data with the parasitic resistance value The operation is to obtain the voltage drop values corresponding to the data blocks, respectively. The display system as described in item 1 of the patent application scope, wherein: the voltage drop estimation circuit divides the gray-scale image data into a plurality of block rows along a first direction, and the gray The hierarchical picture data is divided into a plurality of block rows to form the data blocks, wherein the first direction is perpendicular to the second direction, and each of the power traces extends along the first direction, The voltage drop estimation circuit selects one of the block rows as a correction block row, and adjusts the area corresponding to the blocks based on the voltage drop values corresponding to the correction block row The data driving voltages of the other block rows in the block row, or the power supply voltage is adjusted to compensate for the voltages of the power supply terminals of the pixel units corresponding to the other block rows in the block rows. The display system as described in item 1 of the patent application scope, wherein the display driving circuit receives the adjusted data driving voltages, and drives the respective data driving voltages and the plurality of scanning driving voltages according to the adjusted data driving voltages Pixel unit. A display picture compensation method for a display panel of a display system, the display panel having a plurality of power traces and a plurality of pixel units, a power terminal of each of the pixel units passes through the power supplies One of the traces is coupled to a power supply voltage. The display image compensation method includes: setting a parasitic resistance value of the power trace between adjacent two pixel units of the pixel units; setting a gray scale screen Converting data into multiple current data and multiple data driving voltages; generating multiple voltage drop values based on the parasitic resistance value and the current data; and adjusting at least part of the data driving voltages or compensating at least part of the data according to the voltage drop values Part of the voltages of the power supply terminals of the pixel units, and driving the pixel units accordingly, wherein the step of converting the gray-scale picture data into the current data includes: dividing the gray-scale picture data into Multiple data blocks; and converting each of the data blocks into one of the current data. The display picture compensation method as described in item 7 of the patent application scope further includes: detecting a brightness difference value of the display panel; and estimating the parasitic resistance value according to the brightness difference value. The display picture compensation method as described in item 7 of the patent application scope further includes: estimating the parasitic resistance value according to the information of the power traces of the display panel. The display screen compensation method as described in item 7 of the patent application scope, wherein each of the data blocks has a plurality of gray-scale data, and the conversion of each of the data blocks into the currents The step of one of the data includes: converting the gray-scale data into a plurality of estimated current values; and performing an average operation or smoothing filtering on the estimated current values to obtain one of the current data By. The display picture compensation method as described in item 7 of the patent application scope, wherein the step of generating the voltage drop values based on the parasitic resistance value and the current data includes: performing two-dimensional filtering on the current data to obtain multiple Filtered data; and multiplying the filtered data and the parasitic resistance value to obtain the voltage drop values corresponding to the data blocks, respectively. The display picture compensation method as described in item 7 of the patent application scope, wherein the step of dividing the gray-scale picture data into the data blocks includes: dividing the gray-scale picture data into multiple along a first direction A row of blocks, and dividing the grayscale image data into a plurality of block rows along a second direction to form the data blocks, wherein the first direction is perpendicular to the second direction, and the power supplies Each of the traces extends along the first direction, wherein the step of adjusting at least part of the data driving voltages or compensating at least part of the voltages of the power terminals of the pixel units according to the voltage drops Including: selecting one of the block rows as a correction block row; And using the voltage drop values corresponding to the correction block row as a reference, adjust the data driving voltages corresponding to the other block rows in the block row, or adjust the power supply voltage to compensate for the corresponding The voltages of the power supply terminals of the pixel units of each other block row in the block rows. The display frame compensation method as described in item 7 of the patent application scope, wherein the step of driving the pixel units includes driving the pixels according to the adjusted data driving voltages and the scanning driving voltages, respectively unit.

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