TWI682396B - Method for operating memory array - Google Patents

Abstract

A method for operating a memory array is disclosed. The memory array comprises a first NAND memory string. The first NAND memory string comprises a i^th memory cell, a i-1^th memory cell, a i^th word line, and a i-1^th word line. The i^th memory cell and the i-1^th memory cell are arranged in a sequent order with a series electrical connection. The i^th word line is electrically connected to the i^th memory cell. The i-1^th word line is electrically connected to the i-1^th memory cell. The method for operating the memory array comprises in an operating time interval, performing a program inhibiting process to the i^th memory cell, and simultaneously performing a first process to the i-1^th memory cell. The program inhibiting process comprises providing a first pre-turn on voltage to the i^th word line. The first process comprises providing a second pre-turn on voltage to the i-1^th word line.

Description

Operation method of memory array

The present invention relates to a method of operating a memory array, and particularly to a method of operating a memory array that can improve the stability of the device.

As the critical dimensions of components in integrated circuits are gradually reduced to the limit of the process technology, designers have begun to look for technologies that can achieve greater memory density in order to achieve lower costs per bit. Technologies currently being focused on include three-dimensional NAND memory with a multi-layer memory cell structure on a single chip and its operation. However, current memory arrays still have the problem that their properties will vary with the time the data is stored.

The invention relates to a method of operating a memory array.

According to one aspect of the present invention, a method of operating a memory array is proposed. The memory array includes a first NAND memory string and a second NAND memory string. The first NAND memory string and the second NAND memory string each include an ith memory cell and an ith memory cell that are electrically connected in series in sequence. The first NAND memory series and the second NAND memory series include the i-th character line and the i-1th character line. First NAND memory string and second NAND memory string The ith memory cells in the row are all electrically connected to the ith character line. The i-1th memory cells of the first NAND memory string and the second NAND memory string are all electrically connected to the i-1th character line. The operation method of the memory array includes, during an operation period, providing a first pass voltage and then providing a programmed voltage to the i-th word line, and providing a second pass voltage to the i-th word line . The programmed voltage is used to program the ith memory cell of the second NAND memory string. The second pass voltage is greater than the first pass voltage. During the operation period, an inhibition programming process is performed on the i-th memory cell of the first NAND memory string.

According to another aspect of the present invention, a method of operating a memory array is proposed. The memory array includes a first NAND memory string. The first NAND memory series includes an ith memory cell, an ith memory cell, an ith character line and an ith character line. The ith memory cell and the ith memory cell are electrically connected in series. The ith word line is electrically connected to the ith memory cell. The i-1th word line is electrically connected to the i-1th memory cell. The operation method of the memory array includes performing an inhibition programming process on the i-th memory cell and performing a first process on the i-th memory cell at the same time during an operation period. The inhibiting programming process includes providing a first pre-on voltage to the i-th word line. The first procedure includes providing a second pre-on voltage to the i-1th word line.

In order to have a better understanding of the above and other aspects of the present invention, the preferred embodiments are described below in conjunction with the attached drawings, which are described in detail as follows:

102‧‧‧The first NAND memory serial

202‧‧‧Second NAND memory

56‧‧‧ baseline

CL‧‧‧channel line

CL(i), CL(i-1), CL(i-2) ‧‧‧ channels

T1, T2‧‧‧Series selector switch

108, 208‧‧‧ baseline

114, 116, 214, 216‧‧‧ selection line

330‧‧‧ memory layer

R12, R23

WL(0), WL(1), WL(i), WL(i-1), WL(i-2), WL(N-1) ‧‧‧ character line

MC, MC(i), MC(i-1), MC(i-2) ‧‧‧ memory cell

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 ‧‧‧

GSL-1, GSL-2‧‧‧Ground selection line

CSL‧‧‧Common Source Line

S1(i), S1(i-1), S1(i-2), S2(i), S2(i-1), S2(i-2), S(a), S(c), S( k)‧‧‧Pulse voltage

Vp(i)‧‧‧programmed voltage

Vo(i), Vo(i-1), Vo(i-2)‧‧‧‧Pre-open voltage

Vs(i), Vs(i-1), Vs(i-2), Vs(k)‧‧‧ Pass voltage

Va, Vb‧‧‧Voltage

Vc‧‧‧Voltage

SSL-1, SSL-2 ‧‧‧ serial selection line

BL-1, BL-2‧‧‧bit line

Figure 1 shows the memory array.

FIG. 2 is a voltage timing diagram of the operation method of the memory array in an embodiment.

FIG. 3 is a perspective view of a partial memory structure of a NAND string in a memory array according to an embodiment.

FIG. 4 is a cross-sectional view of the memory structure of FIG. 3 taken along line AA.

The disclosed embodiment provides a method for operating a memory array, which can improve the stability of the memory device.

It should be noted that this disclosure does not show all possible embodiments, and other implementations not proposed in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn according to the actual products. Therefore, the description and illustrations are only used to describe the embodiments, not to limit the scope of disclosure of the present disclosure. In addition, the descriptions in the embodiments, such as the detailed structure, process steps and material application, etc., are for illustrative purposes only, and do not limit the scope of the disclosure to be protected. The details of the steps and structure of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following description uses the same/similar symbols to indicate the same/similar components.

Please refer to Figure 1, which shows the memory array. The memory array includes a first NAND memory string 102 and a second NAND memory string 202. The first NAND memory string 102 and the second NAND memory string 202 may include N memory cells MC electrically connected in series, and correspondingly connect N character lines electrically connected to the N memory cells MC. The N word lines include those electrically connected to an end memory cell MC Word line WL(0), word line WL(N-1) electrically connected to an opposite end memory cell MC, and from word line WL(0) to word line WL(N-1) The other character lines WL(1) arranged in sequence and so on. The tandem selection switch T1 is electrically connected between the opposite end memory cell MC and the reference line 56.

The channel line CL of the first NAND memory string 102 is electrically connected to the reference line 56 (such as a common source line (CSL)) and the reference line 108 (such as a bit line (BL). Here, the symbol BL-1 may also be used Between the reference lines 108) of the first NAND memory string 102. The selection line 114 (for example, the ground selection line (GSL), in this text, the symbol GSL-1 may also be used to denote the selection line 114 of the first NAND memory string 102) is electrically connected to the string selection of the first NAND memory string 102 Switch T1. The series selection switch T2 of the first NAND memory series 102 is electrically connected between the opposite end memory cell MC and the reference line 108. The selection line 116 (for example, a serial selection line (SSL), in this text, the symbol SSL-1 may also be used to indicate the selection line 116 of the first NAND memory serial 102) is electrically connected to the serial of the first NAND memory serial 102 Select switch T2.

The channel line CL of the second NAND memory string 202 is electrically connected to the reference line 56 (e.g., common source line (CSL)) and the reference line 208 (e.g., bit line (BL). Here, the symbol BL-2 may also be used Between the reference lines 208) of the second NAND memory string 202. The selection line 214 (for example, the ground selection line (GSL), in this text, the symbol GSL-2 may also be used to denote the selection line 214 of the second NAND memory string 202) is electrically connected to the string selection of the second NAND memory string 202 Switch T1. The serial selection switch T2 of the second NAND memory serial 202 is electrically connected at the opposite end Between the end memory cell MC and the baseline 208. The selection line 216 (for example, a serial selection line (SSL), in this document, the symbol SSL-2 may also be used to indicate the selection line 216 of the second NAND memory serial 202) is electrically connected to the serial of the second NAND memory serial 202 Select switch T2.

The operation method of the memory array according to the concept of the present disclosure may be, for example, an i-th memory cell MC(i), an i-1th memory cell MC(i-1) electrically connected in series in N memory cells MC, The i-2th memory cell MC(i-2) is described as the i-th character line WL(i) and the i-1th character line WL(i- 1) and the i-2th character line WL(i-2) will be described. The ith memory cell MC(i) of the first NAND memory string 102 and the second NAND memory string 202 are electrically connected to the ith word line WL(i). The i-1 memory cell MC(i-1) of the first NAND memory string 102 and the second NAND memory string 202 are electrically connected to the i-1th word line WL(i-1) ). The i-2 memory cells MC(i-2) of the first NAND memory string 102 and the second NAND memory string 202 are electrically connected to the i-2th character line WL(i-2) ).

Please refer to Figure 1 and Figure 2 at the same time. FIG. 2 is a voltage (or bias) timing diagram of the operation method of the memory array in an embodiment. The vertical axis represents the common source line (CSL) (reference line 56), the ground selection line (GSL-1) (select line 114) of the first NAND memory string 102, and the second NAND memory string 202 Ground selection line (GSL-2) (selection line 214), i-th character line WL(i), i-1th character line WL(i-1), i-2th character line WL( i-2), other character lines, the serial select line (SSL-1) of the first NAND memory serial 102 (select line 116), the second NAND Serial select line (SSL-2) (select line 216) of the memory string 202, bit line (BL-1) (reference line 108) of the first NAND memory string 102, second NAND memory string The voltage (or bias) of the bit line (BL-2) (reference line 208) of the column 202. The horizontal axis represents time, which can include time point T1, time point T2... to time point T10 in sequence.

The operation method of the memory array includes performing a programming process on the i-th memory cell MC(i) of the second NAND memory series 202 during the operation period from time point T1 to time point T10, and simultaneously The i-th memory cell MC(i) of the NAND memory series 102 undergoes a suppression programming process. The i-th memory cell MC(i) of the second NAND memory string 202 is transferred from the erased state to the programmed state by a programming process. At the same time, the first procedure can be performed on the i-1th memory cell MC(i-1) of the first NAND memory series 102. The first procedure does not change the i-th of the first NAND memory series 102 The state of one memory cell MC(i-1). In addition, the second procedure can also be performed on the i-2th memory cell MC(i-2) of the first NAND memory string 102 at the same time. The second procedure does not change the number of the first NAND memory string 102. The state of i-2 memory cells MC (i-2).

Inhibition programming process for the i-th memory cell MC(i) of the first NAND memory string 102 and programming for the i-th memory cell MC(i) of the second NAND memory string 202 The procedure may include providing a pre-turn-on voltage Vo(i) (first pre-turn on voltage) to the i-th word line WL(i), and then providing a pass voltage Vs(i) (first pass Voltage), and then provide the programmed voltage Vp(i). The programming voltage Vp(i) depends on the i-th memory cell MC(i) used to program the second NAND memory string 202, but the first NAND memory string 102 The state of the i-th memory cell MC(i) will not be changed by the programming voltage Vp(i), that is, even if the i-th memory cell MC(i) of the first NAND memory series 102 is receiving a program After the voltage Vp(i) is still in the state of inhibiting programming. In one embodiment, the suppression programming process performed on the i-th memory cell MC(i) of the first NAND memory string 102 and the i-th memory cell MC(i) on the second NAND memory string 202 ) The programming process performed includes providing the pulse wave voltage S1(i) to the i-th character line WL(i) during the period from time point T2 to time point T5, and the pulse voltage S1(i) may include the pre-on voltage Vo(i). The pre-on voltage Vo(i) can be used to turn on the i-th word line WL(i). The pulse voltage S2(i) to the i-th word line WL(i) can be provided during the period from the time point T6 to the time point T10, and the pulse voltage S2(i) can include the maintenance from the time point T7 to the time point The pass voltage Vs(i) of T8 may also include the stylized voltage Vp(i) maintained at the time point T9 to the time point T10. The voltage supplied to the i-th word line WL(i) at other times may be 0V.

The first procedure performed on the i-1th memory cell MC(i-1) of the first NAND memory string 102 may include providing the pre-on voltage Vo for the i-1th word line WL(i-1) (i-1) (second pre-on voltage), and then provide the pass voltage Vs(i-1) (second pass voltage). As shown in FIG. 2, the pulse voltage S1(i-1) to the i-1th word line WL(i-1) may be supplied during the period from the time point T2 to the time point T5. The pulse voltage S1(i-1) may include the pre-on voltage Vo(i-1). The pre-on voltage Vo(i-1) can be used to turn on the i-1th word line WL(i-1). The pulse voltage S2(i-1) to the i-1th character line WL(i-1) may be provided during the period from time point T6 to time point T10, and the pulse voltage S2(i-1) may include maintenance The passing voltage Vs(i-1) from time point T7 to time point T10. At other times, the shutdown voltage (eg 0V) can be provided to the i-1th word line WL(i-1). In one embodiment, the first procedure may be performed on the i-1 memory cell MC(i-1) in the erased state. In another embodiment, the first procedure can be performed on the i-1th memory cell MC(i-1) that has been programmed to a predetermined memory state before the operation period (that is, before the time point (before T1)) get on.

The second procedure performed on the i-2th memory cell MC(i-2) of the first NAND memory string 102 may include providing a pre-on voltage Vo for the i-2th word line WL(i-2) (i-2) (Third pre-on voltage), and then pass voltage Vs(i-2) (third pass voltage). As shown in FIG. 2, the pulse voltage S1(i-2) to the i-2th word line WL(i-2) may be supplied during the period from the time point T2 to the time point T5. The pulse voltage S1(i-2) may include the pre-on voltage Vo(i-2). The pre-on voltage Vo(i-2) can be used to turn on the i-2th word line WL(i-2). The pulse voltage S2(i-2) to the i-2th character line WL(i-2) may be provided during the period from time point T6 to time point T10, and the pulse voltage S2(i-2) may include maintenance The passing voltage Vs(i-2) from time point T7 to time point T10. At other times, the shutdown voltage (eg 0V) can be provided to the i-2th word line WL(i-2). In one embodiment, the second procedure may be performed on the i-2th memory cell MC(i-2) in the erased state. In another embodiment, the second procedure may be performed on the i-2th memory cell MC(i-2) that has been programmed to a predetermined memory state before the operation period (that is, before the time point T1) .

For other memory cells MC, the pass voltage Vs(k) (fourth pass voltage) can be provided to the corresponding word line. As shown in FIG. 2, a turn-off voltage (for example, 0V) can be provided to the corresponding word line from time point T1 to time point T6. Then, you can The pulse voltage S(k) is provided to other character lines during the period from time point T6 to time point T10, and the pulse voltage S(k) may include the pass voltage Vs(k) maintained at time point T7 to time point T10 .

In an embodiment, the pass voltage Vs(i-1) may be greater than the pass voltage Vs(i). The pass voltage Vs(i-1) is also smaller than the stylized voltage Vp(i). The pass voltage Vs(i-1) may be greater than the pass voltage Vs(i-2). The pass voltage Vs(i-1) may be greater than the pass voltage Vs(k).

The pass voltages Vs(i), Vs(i-2), Vs(k) can be 4V to 10V. In an embodiment, the pass voltages Vs(i), Vs(i-2), Vs(k) may be the same, or may be the same as the pre-on voltages Vo(i), Vo(i-1), Vo(i-2 ). But this disclosure is not limited to this.

Before the pass voltages Vs(i), Vs(i-1), Vs(i-2), Vs(k) can be provided to the character line, for example, the first NAND memory can be The bit line (BL-1) of the serial 102 and the serial selection line (SSL-1) (select line 116) provide the pulse wave voltage S(a), which includes the voltage Va (eg 5V) . The voltage Va supplied to the bit line (BL-1) is the precharge voltage of the bit line (BL-1). The voltage Va supplied to the serial selection line (SSL-1) can be used to turn on the serial selection switch T2 of the first NAND memory serial 102. At other times, the voltage supplied to the bit line (BL-1) and the serial selection line (SSL-1) may be 0V, and the serial selection switch T2 may be in an off state.

The pulse voltage S(c) can be provided from the time point T6 to the time point T10 during the supply of the passing voltages Vs(i), Vs(i-1), Vs(i-2), Vs(k) to the character line The ground selection line (GSL-2) and the serial selection line (SSL-2) to the second NAND memory string 202. The pulse voltage S(c) includes the on-time maintained at time T7 to time T10. The starting voltage Vc is, for example, about 4V. At other times, the voltage supplied to the ground selection line (GSL-2) and the serial selection line (SSL-2) may be 0V.

The voltage Vb supplied to the common source line (CSL), the ground selection line (GSL-1) of the first NAND memory string 102, and the bit line (BL-2) of the second NAND memory string 202 may be Is 0V.

In an embodiment, during the inhibition programming of the i-th memory cell MC(i) of the first NAND memory string 102, by providing the i-th character line WL(i-1) The passing voltage Vs(i) of each memory cell MC(i) is higher than the passing voltage Vs(i-1), which can slow down the i-th memory cell MC(i) of the first NAND memory string 102 from being received by the second NAND The degree of critical voltage shift caused by the i-th memory cell MC(i) of the memory string 202 is programmed, that is, the i-th memory cell MC(i) of the first NAND memory string 102 will not Disturbed. Or/and, before passing the voltage, supplying a pre-on voltage (Vo(i), Vo(i-1), Vo(i-2)) to the word line can also slow down the first of the first NAND memory string 102 The degree of the critical voltage shift caused by the i-th memory cell MC(i) being programmed by the i-th memory cell MC(i) of the second NAND memory string 202. In particular, when the i-1 memory cell MC(i-1) of the first NAND memory string 102 has been programmed to a predetermined memory state before the operation period, the operation method according to the present disclosure The degree to which the critical voltage shift is alleviated by the i-th memory cell MC(i) to be inhibited during the operation period is more obvious.

In a comparative example, during the operation period, the precharge voltage (Va) is not provided to the bit line of the first NAND memory string 102, nor is the pre-opening provided Voltage to the word line, and the pass voltage supplied to all word lines is the same voltage, even if the pass voltage is as high as 10V, the critical voltage of the i-th memory cell MC(i) of the first NAND memory string 102 is The i-th memory cell MC(i) of the second NAND memory string 202 is shifted by about 0.4V due to the programming effect. In another comparative example, during the operation period, the bit line of the first NAND memory string 102 is provided with a precharge voltage (Va), but the pre-on voltage is not provided to the word line, and is provided to all words The pass voltage of the element line is the same voltage. At this time, the pass voltage must be at least as high as 8V or even as high as 10V in order to offset the critical voltage of the i-th memory cell MC(i) of the first NAND memory string 102 The degree of shift drops to about 0V.

In contrast, in some embodiments, during the operation period, the bit line of the first NAND memory string 102 is provided with a pre-charge voltage (Va), and a pre-on voltage (Vo(i), Vo(i -1), Vo(i-2)) to the word line, and the pass voltage Vs(i-1) provided to the i-1th word line WL(i-1) is higher than that of other word lines Passing voltage (Vs(i), Vs(i-2), Vs(k)), at this time, a passing voltage (for example, 4V) lower than that of the comparative example (for other word lines) can be used, so that the i The critical voltage shift of each memory cell MC(i) is about 0V. In some embodiments, when the i-1 memory cell MC(i-1) of the adjacent first NAND memory string 102 has been programmed to a programmed state before the operation period, the i The critical voltage shift of the memory cell MC(i) is also about 0V.

Accordingly, the operation method according to the concept of the embodiment can make the memory cell have stable properties, thereby maintaining the electrical properties of the memory array and the stability of data storage.

In one embodiment, the NAND memory string includes a wrap-around gate Gate-all-around (GAA) memory structure. For example, refer to FIG. 3 and FIG. 4, wherein FIG. 3 is a perspective view of the memory structure, and FIG. 4 is a cross-sectional view of the memory structure of FIG. 3 along line AA. The NAND memory string includes a channel line CL, a character line (such as the i-th character line WL(i), the i-1th character line WL(i-1), and the i-2th character line WL (i-2)) and the memory layer 330. The memory layer 330 is located between the channel line CL and the word line. The channel line CL is a column-shaped channel line. The memory layer 330 is a columnar memory layer, which can also be regarded as a ring-shaped memory layer or a hollow columnar memory layer surrounding the channel line CL. The character line surrounds the memory layer 330. Memory cells (i-th memory cell MC(i), i-1th memory cell MC(i-1), i-2th memory cell MC(i-2)) are defined on the channel line CL and characters The intersection of the lines. The channel line CL may include the channel CL(i) of the ith memory cell MC(i), the channel CL(i-1) of the i-1 memory cell MC(i-1), and the i-2 memory cell Channel CL(i-2) of MC(i-2). The character lines can be separated by an insulating layer (not shown) corresponding to the regions R12 and R23.

The channel line CL may include semiconductor materials such as polysilicon materials, silicon dioxide, and the like. The memory layer 330 may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure. For example, the charge trapping film may use nitride such as silicon nitride, or other polysilicon materials. High dielectric constant materials include metal oxides, such as aluminum oxide (Al2O3), zirconium oxide (HfO2), etc., with a thickness of 10-50 Angstroms (Angstrom), which can be configured on the memory layer 330 and the gate electrode Including metal).

The concept according to the present disclosure can also be extended to other changes.

The NAND memory series is not limited to vertical channels, and a single gate vertical channel structure or a vertical gate structure can also be used. The memory cell may be a floating gate memory cell or a nitride-captured memory cell and so on. The memory cell may be a single-order memory cell, a multi-order memory cell, a third-order memory cell, or the like.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

WL(i), WL(i-1), WL(i-2) ‧‧‧ character line

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 ‧‧‧

GSL-1, GSL-2‧‧‧Ground selection line

CSL‧‧‧Common Source Line

S1(i), S1(i-1), S1(i-2), S2(i), S2(i-1), S2(i-2), S(a), S(c), S( k)‧‧‧Pulse voltage

Vp(i)‧‧‧programmed voltage

Vo(i), Vo(i-1), Vo(i-2)‧‧‧‧Pre-open voltage

Vs(i), Vs(i-1), Vs(i-2), Vs(k)‧‧‧ Pass voltage

Va, Vb, Vc ‧‧‧ voltage

SSL-1, SSL-2 ‧‧‧ serial selection line

BL-1, BL-2‧‧‧bit line

Claims (10)

A method of operating a memory array, wherein the memory array includes a first NAND memory string, a second NAND memory string, an i-th character line and an i-1th character line, the first NAND The memory string and the second NAND memory string each include an i-th memory cell and an i-1th memory cell that are electrically serially connected in series, the first NAND memory string and the second NAND memory The i-th memory cells of the series are all electrically connected to the i-th word line, the i-1 memory cells of the first NAND memory series and the second NAND memory series Are electrically connected to the i-1th word line, the operation method of the memory array includes providing a first pass voltage during an operation period and then providing a programmed voltage to the ith word line And provide a second pass voltage to the i-1th word line while providing the first pass voltage, wherein the programmed voltage is used to program the i th of the second NAND memory string For a memory cell, the second pass voltage is greater than the first pass voltage, and during the operation period, a suppression programming process is performed on the i-th memory cell of the first NAND memory string. The method for operating a memory array as described in item 1 of the patent application, wherein the first NAND memory string includes a channel line and a reference line electrically connected, the channel line includes the first NAND memory string The channel of the i-th memory cell and the i-1th memory cell, the operation method of the memory array includes providing the first pass voltage to the i-th word line and providing the second Before passing the voltage to the i-1th word line, a precharge voltage is provided to the reference line. The method for operating a memory array as described in item 1 of the patent application range, wherein the suppression programming process includes providing a pre-open voltage to the i-th character before the first pass voltage and the programmed voltage And/or during the operation period, a first procedure is performed on the i-1th memory cell of the first NAND memory string, the first procedure includes providing the Pre-turn on the voltage to the i-1th word line. The method for operating a memory array as described in item 1 of the patent application range, wherein the second pass voltage is maintained during the supply period of the first pass voltage and the programmed voltage. The method of operating a memory array as described in item 1 of the patent application, wherein the second pass voltage is less than the programmed voltage. The method for operating a memory array as described in item 1 of the patent application, wherein the first NAND memory series further includes the i-2th memory cell and the i-2th character line, the i-2 The word line is electrically connected to the i-2th memory cell, the i-1th memory cell is electrically connected in series between the ith memory cell and the i-2th memory cell, the memory The operation method of the array further includes performing a first procedure on the i-1th memory cell while performing a second procedure on the i-2th memory cell, wherein the first procedure includes providing the first Two pass voltages to the i-1th word line, the second procedure includes providing a third pass voltage to the i-2th word line, the second pass voltage is greater than the third pass voltage. A method for operating a memory array, wherein the memory array includes a first NAND memory string, the first NAND memory string includes: an ith memory cell and an ith number electrically connected in series Memory cell; i-th word line, electrically connected to the i-th memory cell; and i-1 word line, electrically connected to the i-th memory cell, wherein the memory array The operation method includes performing an inhibition programming process on the i-th memory cell during an operation period, and simultaneously performing a first procedure on the i-1 memory cell, wherein the inhibition programming process includes providing a first A pre-on voltage, then a turn-off voltage, and then a pass voltage to the i-th word line, the first procedure includes providing a second pre-on voltage to the i-th word line. The method of operating a memory array as described in item 7 of the patent application range, wherein the inhibiting programming process includes providing a programmed voltage to the i-th word line after the first pre-turn-on voltage, the first The procedure includes providing another pass voltage to the i-1th word line after the second pre-on voltage. The method for operating a memory array as described in item 7 of the patent application range, wherein the first NAND memory string includes a channel line and a reference line electrically connected, the channel line includes the i-th memory cell and The channel of the i-1th memory cell, the method of operating the memory array includes providing the first pre-on voltage to the i-th word line and providing the second pre-on voltage to the i-1 Within the period of the word line, a precharge voltage is provided to the reference line. The method for operating a memory array as described in item 7 of the patent application range, wherein the first NAND memory string further includes the i-2th memory cell and the i-2th character line, the i-2 The word line is electrically connected to the i-2 memory cell, the i-1 memory cell is electrically connected in series between the i th memory cell and the i-2 memory cell, the memory The operation method of the array further includes performing the second procedure on the i-2th memory cell while performing the first procedure on the i-1th memory cell, wherein the second procedure includes providing a third pre-opening Voltage to the i-2th word line.

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