TWI665860B - System controller and method for regulating power converter - Google Patents

Abstract

A system controller and method for regulating a power converter are disclosed. For example, the system controller includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect the power converter The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration.

Description

   System controller and method for regulating power converter   

The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

FIG. 1 is a simplified diagram showing a conventional flyback power conversion system. The power conversion system 100 includes a primary winding 110, a secondary winding 112, a power switch 120, a current sensing resistor 122, a rectifying diode 124, a capacitor 126, an isolation feedback component 128, and a controller 102. The controller 102 includes: an undervoltage lockout element 104, a pulse width modulation generator 106, a gate driver 108, a leading edge blanking (LEB) element 116, and an over current protection (OCP) element 114 . For example, the power switch 120 is a bipolar transistor. In another example, the power switch 120 is a field effect transistor.

The power conversion system 100 implements a transformer including a primary winding 110 and a secondary winding 112 to isolate the AC input voltage 190 on the primary side and the output voltage 192 on the secondary side. The isolated feedback element 128 processes the information about the output voltage 192 and generates a feedback signal 136. The controller 102 receives the feedback signal 136 and generates a gate driving signal (Gate) 130 to turn on and off the switch 120 to adjust the output voltage 192. For example, the isolated feedback element 128 includes an error amplifier, a compensation network, and an optocoupler.

Although the flyback power conversion system 100 can be used for output voltage regulation, the power conversion system 100 often cannot obtain good output current control without high-cost additional circuits. In addition, the output current sensing resistor required in the secondary side generally reduces the efficiency of the power conversion system 100.

FIG. 2A is a simplified diagram showing another conventional flyback power conversion system. The power conversion system 200 includes a system controller 202, a primary winding 210, a secondary winding 212, an auxiliary winding 214, a power switch 220, a current sensing resistor 230, two rectifying diodes 260 and 262, and two capacitors 264. And 266, and two resistors 268 and 270. For example, the power switch 220 is a bipolar transistor. In another example, the power switch 220 is a MOS transistor.

Information about the output voltage 250 can be extracted through the auxiliary winding 214 to adjust the output voltage 250. When the power switch 220 is closed (eg, turned on), energy is stored in a transformer including a primary winding 210 and a secondary winding 212. Then, when the power switch 220 is turned off (eg, turned off), the stored energy is released to the secondary side, and the voltage of the auxiliary winding 214 maps the output voltage on the secondary side. The system controller 202 receives a current sensing signal 272 indicating a primary current 276 flowing through the primary winding 210 and a feedback signal 274 regarding a demagnetization process on the secondary side. For example, the switching period of the switch 220 includes an on period during which the switch 220 is closed (eg, on) and an off period during which the switch 220 is off (eg, off).

FIG. 2B is a simplified conventional timing diagram of the flyback power conversion system 200 operating in a discontinuous conduction mode (DCM). A waveform 292 represents the voltage 254 of the auxiliary winding 214 as a function of time, and a waveform 294 represents a second current 278 flowing through the secondary winding 212 as a function of time.

For example, as shown in FIG. 2B, the switching period T _{s of the} switch 220 starts at time t ₀ and ends at time t ₃ ; the on time period T _on starts at time t ₀ and ends at time t ₁ ; the demagnetization period T _demag It starts at time t ₁ and ends at time t ₂ ; the off-time period T _off starts at time t ₁ and ends at time t ₃ . In another example, t ₀ t ₁ t ₂ t ₃ . In DCM, the off-time period T _{off is} much longer than the demagnetization period T _demag .

During the demagnetization period T _demag , the switch 220 remains open, and the primary current 276 remains at a low value (eg, near zero). The secondary current 278 decreases from the value 296 (for example, at t ₁ ), as shown by the waveform 294. The demagnetization process ends at time t ₂ when the secondary current 278 has a low value of 298 (eg, near zero). The secondary current 278 remains at the value 298 for the remainder of the switching cycle. The next switching cycle does not begin until some time after the demagnetization process is complete (for example, at t ₃ ).

As shown in FIGS. 1 and 2A, each of the power conversion system 100 and the power conversion system 200 uses a rectifying diode on the secondary side (for example, the diode 124 and the figure in FIG. 1). 2 diode 260) to rectify. The forward voltage of the rectified diode is usually in the range of 0.3V-0.8V. This forward voltage often results in significant power loss during operation, resulting in inefficient power conversion systems. For example, when the power conversion system has an output level of 5V / 1A, a rectified diode with a forward voltage of 0.3V-0.4V causes a power loss of about 0.3W-0.4W at full load (eg, 1A). The reduction in system efficiency is approximately 4% -6%.

In addition, in order to obtain a lower standby power loss for the power conversion system 200, the switching frequency is often kept low to reduce the switching loss under no-load or light-load conditions. However, when the power conversion system 200 changes from a no-load / light-load condition to a full-load condition, the output voltage 250 may drop suddenly, and the voltage drop may not be immediately sensed by the system controller 202, because the system controller 202 usually The output voltage can only be sensed during the demagnetization of each switching cycle. Therefore, the dynamic performance of the power conversion system 200 is often unsatisfactory at low switching frequencies under no-load / light-load conditions. For example, the power conversion system 200 has an output level of 5V / 1A, and the output capacitor 264 has a capacitance of 1000 μF. Under no-load / light-load conditions, the switching frequency is 1kHz, which corresponds to a switching period of 1ms. If the output load changes from no-load / light-load condition (for example, 0A) to full-load condition (for example, 1A), the output voltage 250 drops by 1V (for example, from 5V to 4V), which is generally unacceptable in some applications of.

FIG. 3 is a simplified diagram showing a conventional power conversion system having a secondary synchronous rectifier (SR). The power conversion system 2300 (eg, a flyback power converter) includes a primary-side pulse width modulation (PWM) controller 2302, a primary winding 2304, a secondary winding 2306, and a secondary-side synchronous rectifier (SR ) Controller 2308, transistor 2310 (for example, Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), output capacitive load 2312 Outputs a resistive load 2314, and a power switch 2330 (eg, a transistor). The secondary-side synchronous rectifier (SR) controller 2308 includes terminals 2390, 2392, 2394, and 2396.

As shown in FIG. 3, the terminal 2390 receives a voltage signal 2362 indicating the voltage at the terminal 2364 (for example, the drain terminal of the transistor 2310) of the transistor 2310, and the terminal 2392 outputs to the transistor 2310 (for example, a MOSFET) Driving signal 2366. In addition, the terminal 2394 receives a voltage signal 2316 indicating an output voltage, wherein the output voltage is received by the output capacitive load 2312 and the output resistive load 2314. In addition, the terminal 2396 is biased to the secondary ground.

The primary-side pulse width modulation (PWM) controller 2302 generates a driving signal 2332 (for example, V _g1 ) and outputs the driving signal 2332 to a power switch 2330 (for example, a transistor), and a secondary-side synchronous rectifier (SR) controller 2308 A driving signal 2366 (for example, V _g ) is generated and output to the transistor 2310 (for example, a MOSFET).

In a secondary-side synchronous rectifier (SR) control system, the turn-on delay of the transistor 2310 generally needs to be minimized to avoid any significant demagnetizing current flowing through the body diode of the transistor 2310. Minimization of the on-delay of transistor 2310 is often very important for efficient and / or high power density systems. On the other hand, in order to prevent the transistor 2310 from being unintentionally turned on by noise or disturbance, it is usually very important for the secondary controller 2308 to filter out noise or disturbance by adding a debounce time before turning on the transistor 2310.

The secondary-side synchronous rectifier (SR) controller 2308 includes a voltage sensor 2320, a logic controller 2322, and a driver 2324. The secondary-side synchronous rectifier (SR) controller 2308 senses a voltage signal 2362 (eg, V _d ) indicating a voltage at the terminal 2364 (eg, the drain terminal of the transistor 2310) of the transistor 2310, and provides a decision transistor Drive signal 2366 (eg, V _g ) of 2310 on or off. Initially, the transistor 2310 is turned off because the driving signal 2366 (for example, the voltage V _g ) is equal to zero or the voltage signal 2362 (for example, V _d ) is greater than zero. Under normal operation, when the primary-side pulse width modulation (PWM) controller 2302 turns off (eg, turns off) the power switch 2330 (eg, a transistor), the voltage signal 2362 (eg, V _d ) decreases rapidly. After the voltage signal 2362 (for example, V _d ) becomes smaller than the threshold voltage, the secondary-side synchronous rectifier (SR) controller 2308 turns on the transistor 2310 by pulling the driving voltage 2366 (for example, V _d ) high. Generally, noise or disturbance is coupled from the AC line to the voltage signal 2362 through a transformer.

Therefore, it is highly desirable to improve the technology of rectification and output sensing for power conversion systems.

The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

However, it should be recognized that the present invention has a wider scope of application.

According to one embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal and generate a gate drive signal at a second controller terminal based on information associated with at least the input signal to turn the transistor on or off This affects the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a gate driving signal at a first logic level to turn off the transistor if the input signal is greater than a first threshold, and change the input signal from a first value greater than a second threshold to change the input signal. If the second value is smaller than the second threshold, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, the input signal being proportional to an output voltage associated with a secondary winding of the power conversion system, and based on at least information associated with the input signal, at the first The two controller terminals generate a gate drive signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a pulse of the gate drive signal only when the input signal changes from a first value greater than a first threshold value to a second value less than the first threshold value to a pulse associated with the pulse. The transistor is turned on during the period.

According to another embodiment, a system controller for adjusting a power conversion system includes a first comparator, a signal sensor, and a driving element. The first comparator is configured to receive an input signal and output a first comparison signal based on information associated with at least the input signal. The signal sensor is configured to receive an input signal and output a first sensing signal based on at least information associated with the input signal. The driving element is configured to output the gate driving signal to turn on or off the transistor based on the information associated with at least the first comparison signal and the first sensing signal to affect the current associated with the secondary winding of the power conversion system. The comparator is further configured to determine whether the input signal is greater than a first threshold. The signal sensor is further configured to determine whether the input signal changes from a first value greater than a second threshold value to a second value less than the second threshold value. The driving element is further configured to: if the first comparison signal indicates that the input signal is greater than a first threshold value, generate a gate driving signal at a first logic level to turn off the transistor, and if the first sensing signal indicates that the input signal is from If the first value larger than the second threshold becomes the second value smaller than the second threshold, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

In one embodiment, a system controller for regulating a power conversion system includes a comparator, a pulse signal generator, and a driving element. The comparator is configured to receive an input signal and output a comparison signal based on information associated with at least the input signal. The pulse signal generator is configured to receive at least a comparison signal and generate a pulse signal based on at least information associated with the comparison signal. The driving element is configured to receive a pulse signal and generate a gate driving signal based on at least information associated with the pulse signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The comparator is also configured to determine whether the input signal is greater than or less than a threshold. The pulse signal generator is further configured to generate a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The driving element is further configured to generate a second pulse of the gate driving signal in response to the first pulse of the pulse signal to turn on the transistor in a pulse period associated with the second pulse.

In another embodiment, a method for adjusting a power conversion system includes receiving at least an input signal, processing information associated with the input signal, and generating a gate driving signal based on the information associated with at least the input signal, to Turn the transistor on or off to affect the Current associated with the secondary winding of the power conversion system. The process of generating a gate driving signal based on at least information associated with the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: if the input signal is greater than a first threshold, A gate drive signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold to a second value less than a second threshold, the gate drive signal is changed from The first logic level becomes the second logic level to turn on the transistor.

In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal that is proportional to an output voltage associated with a secondary winding of the power conversion system, and processing information associated with the input signal And generate a gate drive signal based on at least information associated with the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal based on information associated with at least the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: only when the input signal changes from greater than the first When the first value of the threshold value becomes a second value less than the first threshold value, a pulse of the gate drive signal is generated to turn on the transistor during the pulse period associated with the pulse.

In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than a first threshold. The method further includes generating a comparison signal based on at least information associated with the input signal, determining whether the input signal has changed from a first value greater than a second threshold value to a second value less than a second threshold value, and based on at least being associated with the input signal. Information generated by the sensor. In addition, the method includes outputting a gate drive signal based on information associated with at least the comparison signal and the sensing signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The process of outputting the gate drive signal based on the information associated with at least the comparison signal and the sensing signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: if the comparison signal indicates an input If the signal is greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the sensing signal indicates that the input signal is greater than a second When the first value of the threshold value becomes a second value smaller than the second threshold value, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than or less than a threshold. The method further includes generating a comparison signal based on information associated with at least the first input signal, receiving the comparison signal, and processing the information associated with the comparison signal. In addition, the method includes generating a pulse signal based on at least information associated with the comparison signal, receiving the pulse signal, processing the information associated with the pulse signal, and generating a gate driving signal based on at least information associated with the pulse signal, The transistor is turned on or off to affect the current associated with the secondary winding of the power conversion system. The process of generating a pulse signal based on at least information associated with the comparison signal includes generating a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The process of generating a gate drive signal based on information associated with at least the pulse signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: a first pulse in response to the pulse signal A second pulse of the gate drive signal is generated to turn on the transistor during a pulse period associated with the second pulse.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at a first controller terminal, and generate a drive signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion The current associated with the secondary winding of the system. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold at a first moment; in response to the input signal being determined to be greater than a first threshold at a first moment, determine that the input signal is at a second moment Whether it is less than the second threshold; and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal at the second controller terminal is changed from the first logic level to the second logic level. In addition, the second time is after the first time.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn the transistor on or off, thereby affecting the power supply Transform the current associated with the secondary winding of the system. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a period of time longer than the predetermined duration, and in response to the input signal is determined to be longer than the predetermined duration It remains larger than the first threshold during the time period, and determines whether the input signal is less than the second threshold at a certain time after the time period. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a second threshold at this time, change the driving signal at the terminal of the second controller from the first logic level to the second logic level .

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to determine whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration, And in response to the time interval being determined to be longer than a predetermined duration, it is determined whether the input signal is less than a third threshold at a certain time after the time interval. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a third threshold at this time, change the driving signal at the second controller terminal from the first logic level to the second logic level .

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is configured to determine the input signal Whether it is greater than the first threshold; determining whether the input signal remains greater than the second threshold for a period of time longer than the first predetermined duration; and determining from the first moment when the input signal becomes greater than the third threshold to the input signal Whether the time interval of the second moment which becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, the system controller is further configured to: in response to the input signal being determined to be greater than the first threshold value, the input signal being determined to remain greater than the second threshold value for a time period longer than the first predetermined duration, or The time interval is determined to be longer than the second predetermined duration, it is determined whether the input signal is less than a fifth threshold, and in response to the input signal being determined to be less than a fifth threshold, the driving signal at the second controller terminal is removed from the first One logic level becomes the second logic level.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal is greater than a first threshold at a first moment. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than the A threshold to determine whether the input signal is less than the second threshold at the second moment, and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal is changed from the first logic level to the second logic bit quasi. In addition, the second time is after the first time.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal remains greater than a first threshold for a period of time longer than a predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be more than a predetermined duration Stays greater than the first threshold for a long period of time, determines the input message Whether the number is less than the second threshold at a certain time after the time period, and in response to the input signal being determined to be less than the second threshold at the time, the driving signal is changed from the first logic level to the second logic level.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration long. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the time interval being determined to be longer than a predetermined duration, Determine whether the input signal is less than the third threshold at a certain time after the time interval, and in response to the input signal being determined to be less than the third threshold at the time, change the driving signal from the first logic level to the second logic bit quasi.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes: determining whether the input signal is greater than a first threshold; determining whether the input signal remains greater than a second threshold for a period of time longer than a first predetermined duration; and determining from Whether the time interval from the first moment when the input signal becomes larger than the third threshold to the second moment when the input signal becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than a first threshold, the The input signal is determined to remain greater than the second threshold for a time period longer than the first predetermined duration, or the time interval is determined to be longer than the second predetermined duration, determining whether the input signal is less than a fifth threshold, and And in response to the input signal being determined to be smaller than the fifth threshold, the driving signal is changed from the first logic level to the second logic level.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a drive signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration; and in response to the input signal not being determined to be equal to or longer than the first The first period of a predetermined duration remains greater than the first threshold, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; in response to the input signal being determined to be at The driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a second period equal to or longer than the second predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains less than or equal to the first threshold and greater than the second threshold during a first period equal to or longer than the first predetermined duration, and the second threshold is smaller than the first threshold; And in response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a second period equal to or longer than the second predetermined duration; in response to the input signal being determined to be at Keeping the second controller terminal for a second period equal to or longer than the second predetermined duration to be less than the third threshold The driving signal at is changed from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period of time equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration for a second Whether it remains greater than the second threshold during the period. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. In addition, the system controller is further configured to: in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than The second predetermined duration is kept greater than the second threshold within the second period, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to: determine whether the input signal remains less than a third threshold in a third period equal to or longer than a third predetermined duration; and in response to the input signal being determined as The driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a third period equal to or longer than the third duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration. Whether it remains greater than the second threshold in the two periods. In addition, the system controller is configured to: in response to the input signal not being determined to be equal to Or remains greater than the first threshold for a first period longer than the first predetermined duration, and the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, using the first scheme operating. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold value changes with the input signal in amplitude, and the second threshold value changes with the input signal in amplitude.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration. Whether it remains greater than the second threshold in the two periods. In addition, the system controller is further configured to: in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than The second predetermined duration is kept greater than the second threshold within the second period, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in amplitude with the input signal, and the second predetermined duration changes in amplitude with the input signal.

According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than the first predetermined duration; and in response to the input signal not being determined to be equal to or longer than the first predetermined The first period of the duration remains greater than the first threshold, and the first scheme is used for operation. Generate drive signals based at least in part on input signals To switch on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining that the input signal is at a second equal to or longer than a second predetermined duration Whether it remains less than the second threshold during the period; and in response to the input signal being determined to remain less than the second threshold for a second period equal to or longer than the second predetermined duration, the driving signal is changed from the first logic level to the second Logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains less than or equal to a first threshold value and greater than a second threshold value, and the second threshold value is less than the first threshold value within a first period equal to or longer than the first predetermined duration; and In response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than the first Whether the driving signal remains less than the third threshold in the second period of the second predetermined duration; and in response to the input signal being determined to remain less than the third threshold in the second period equal to or longer than the second predetermined duration, the driving signal is changed from the first The logic level becomes the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Whether it remains greater than the second threshold, the second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration; and In response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not being determined to remain for a second period equal to or longer than the second predetermined duration If it is larger than the second threshold, the first solution is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining that the input signal is equal to or longer than Whether the driving signal is kept smaller than the third threshold within a third period of the third predetermined duration; and in response to the input signal being determined to remain smaller than the third threshold within a third period equal to or longer than the third predetermined duration, the driving signal is driven Change from a first logic level to a second logic level. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero.

According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Whether or not remains greater than the second threshold; and in response to the input signal not being determined to remain greater than the first threshold for a first period of time equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than the second threshold The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold value changes with the input signal in amplitude, and the second threshold value changes with the input signal in amplitude.

According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining the input signal Whether the number remains greater than the second threshold for a second period equal to or longer than the second predetermined duration; and in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration And the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in amplitude with the input signal, and the second predetermined duration changes in amplitude with the input signal.

Depending on the embodiment, one or more of these benefits may be realized. These benefits and various additional objects, features, and advantages of the present invention will be fully understood with reference to the following drawings and detailed description.

100, 200, 2300, 300, 400, 3300‧‧‧ Power Conversion System

102, 302, 402‧‧‧ controller

104‧‧‧Undervoltage lockout element

106‧‧‧Pulse width modulation generator

108‧‧‧Gate driver

110, 210, 2304, 304, 404, 3304‧‧‧ primary winding

112, 212, 2306, 306, 406, 3306‧‧‧ secondary winding

114. OCP‧‧‧Overcurrent protection element

116. LEB‧‧‧ leading edge blanking element

120, 220, 2330, 330, 430, 3330‧‧‧ power switches

122, 230, 328, 428‧‧‧ current sensing resistors

124, 260, 262‧‧‧ rectified diodes

126, 264, 266, 312, 380, 412, 476, 478‧‧‧ capacitors

128‧‧‧Isolated feedback components

130.Gate‧‧‧Gate driving signal

136, 274, 360, 460‧‧‧ feedback signals

190‧‧‧AC input voltage

192, 250, 350, 450‧‧‧ output voltage

202‧‧‧System Controller

214, 324‧‧‧Auxiliary winding

424‧‧‧The first auxiliary winding

425‧‧‧second auxiliary winding

Voltage of 254‧‧‧214

272‧‧‧Current sensing signal

276‧‧‧ primary current

278, 352, 452, I _sec ‧‧‧ secondary current

Ts‧‧‧ scheduled time

T _ON ‧‧‧ On time period

T _off ‧‧‧ off time period

T _Demag ‧‧‧ Demagnetization Period

2302, 3302‧‧‧ primary side pulse width modulation controller

2308, 3308‧‧‧‧ Secondary-side synchronous rectifier controller

2310, MOSFET, 310, 410, 3310‧‧‧ transistor

2312,3312, C _O ‧‧‧ output capacitive load

2314, 3314, R _O ‧‧‧ output resistive load

2320‧‧‧Voltage Sensor

2322‧‧‧Logic Controller

2324, 3850‧‧‧Drive

2332, 2366, 3332, 3366, V _g , V _g1 ‧‧‧ drive signal

301, 401‧‧‧ rectifier circuit

308, 408‧‧‧ secondary controller

320, 420, 474‧‧‧ diodes

368‧‧‧channel current

370‧‧‧body diode current

372‧‧‧ground voltage

528, 828, 928, 1028, 1109, V _th1 ‧‧‧ first threshold voltage

530, 830, 930, 1030, 1113, V _th2 ‧‧‧ second threshold voltage

T _d ‧‧‧ Delay

602, 1102‧‧‧clamp element

604, 1104‧‧‧Compensation element

606, 1106‧‧‧ rising edge sensing element

610, 1110‧‧‧falling edge sensing element

612, 1112‧‧‧ timing controller

614, 1114‧‧‧Logic control element

616, 1116‧‧‧Gate driver

618, 1118‧‧‧‧light load sensor

620, 1120‧‧‧Signal generator

622, 1122‧‧‧oscillator

626, 1126‧‧‧ reference signal generator

628, 1128‧‧‧undervoltage lockout element

652, 1180‧‧‧ reference signal

722, V _th3 ‧‧‧ third threshold voltage

724, V _th4 ‧‧‧ fourth threshold voltage

730‧‧‧pulse

829, 1218, 3490, V _ref1 ‧‧‧ first reference voltage

929, 1228, 3590, V _ref2 ‧‧‧ second reference voltage

1029,1238, V _ref3 ‧‧‧ third reference voltage

1031,1248, V _ref4 ‧‧‧ the fourth reference voltage

1250‧‧‧Gate

1174‧‧‧clock signal

1224, 3820, 3826‧‧‧ Debounce components

1234‧‧‧Timer element

3480‧‧‧Threshold voltage

T _A , T _J , T _K ‧‧‧ Duration

1300, 3600‧‧‧Method

3812, 3818‧‧‧Comparison signal

T _th1 ‧‧‧ first threshold time period

T _th2 ‧‧‧threshold duration

3830‧‧‧ Connected to the solution controller

3836‧‧‧ On Signal Controller

3840‧‧‧ Shutdown Signal Controller

3860‧‧‧Clamp Device

3876‧‧‧Threshold Duration Generator

3842‧‧‧ Shutdown control signal

532‧‧‧ secondary demagnetization completed

R‧‧‧Primary Pulse Width Modulation Controller Startup Resistance

M‧‧‧Power Switch

C‧‧‧ Primary side pulse width modulation controller power supply capacitor

D‧‧‧ Drain terminal of synchronous rectifier switch

V _AC ‧‧‧AC input voltage

R _s ‧‧‧Transformer primary current sense resistor

R2‧‧‧ System output voltage divider resistor

L _p ‧‧‧Transformer primary winding inductance

V _th _ _oc ‧‧‧ overcurrent protection threshold

CS‧‧‧Transformer primary current detection signal

VCC‧‧‧ Primary side pulse width modulation controller power supply

VDD‧‧‧ secondary side synchronous rectifier controller power supply

POR, UVLO‧‧‧ Undervoltage protection enable signal

FB‧‧‧Isolated feedback control signal

GND, GND2‧‧‧ ground pin

D1‧‧‧Output voltage rectified diode

D2‧‧‧ secondary side synchronous rectifier controller power supply rectifier diode

D3‧‧‧ primary side pulse width modulation controller power supply rectifier diode

T1‧‧‧Transformer

N _aux ‧‧‧ number of transformer auxiliary winding turns

N _p ‧‧‧ number of turns of transformer primary winding

V _aux ‧‧‧Transformer auxiliary winding voltage

N _sec ‧‧‧Transformer secondary winding turns

I _pri ‧‧‧ peak current of secondary side of transformer

R1‧‧‧ system output resistor

Np‧‧‧Transformer primary winding turns

N _S ‧‧‧Transformer secondary winding turns

U1‧‧‧Primary Pulse Width Modulation Controller

U2‧‧‧ secondary-side synchronous rectifier controller

Vbulk‧‧‧Bulk capacitor voltage

M1‧‧‧Synchronous Rectifier Switch

M2‧‧‧Power Switch

1021‧‧‧Resonant third valley bottom after secondary side demagnetization

CLK‧‧‧Pulse Width Modulation Controller Clock Signal

V_D‧‧‧Synchronous Rectifier Switch Drain Signal

V_FB‧‧‧PSR Pulse Width Modulation Controller Feedback Signal

V _in , 2316, 2362, V _d , 362, 388, 658, V _s , 462, 3316, 3362‧‧‧ voltage signals

268, 270, 314, 316, 318, 322, 326, 414, 416, 418, 470, 472‧‧‧ resistors

608, 624, 1124, 1210, 1220, 1230, 1240, 3810, 3816‧‧‧ comparator

t0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t24, t25, t30, t34, t35, t36, t37, t4o, t44, t45, t46, t47, t48, t50, t51, t101, t102, t111, t112, t113, t114, t115, t116

292, 294, 502, 504, 506, 508, 510, 512, 514, 702, 704, 706, 708, 710, 712, 802, 808, 810, 902, 908, 910, 1002, 1008, 1010, 3432, 3462, 3466, 3532‧‧‧ waveform

296, 268, 516, 518, 520, 522, 524, 525, 526, 529, 534, 714, 716, 718, 720, 726, 728, 818, 819, 826, 827, 918, 919, 926, 927, 1018, 1019, 1026, 1027‧‧‧ values

366, 466, 650, 660, 670, 672, 676, 678, 682, 684, 1107, 1111, 1115, 1252, 1172, 1176, 1178, 1182, 1184, 1158, 1216, 1222, 1226, 1232, 1236, 1242, 3822, 3828, 3874, 3878, 3832, 3838‧‧‧ signals

2364, 2390, 2392, 2394, 2396, 390, 392, 394, 396, 398, 364, G2, 464, 3364, 3390, 3392, 3394, 3396, DR‧‧‧ terminals

1310, 1320, 1322, 1324, 1340, 3610, 3620, 3622, 3630, 3640, 3710, 3720, 3721, 3722, 3723, 3740‧‧‧ process

FIG. 1 is a simplified diagram showing a conventional flyback power conversion system.

FIG. 2A is a simplified diagram showing another conventional flyback power conversion system.

FIG. 2B is a simplified conventional timing diagram of the flyback power conversion system shown in FIG. 2A operated in discontinuous conduction mode (DCM).

FIG. 3 is a simplified diagram showing a conventional power conversion system having a secondary-side synchronous rectifier (SR).

FIG. 4A is a simplified diagram showing a power conversion system having a rectifier circuit according to an embodiment of the present invention.

FIG. 4B is a simplified diagram showing a power conversion system having a rectifier circuit according to another embodiment of the present invention.

FIG. 5 is a simplified timing diagram of the power conversion system shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention.

Fig. 6 is a simplified diagram showing certain elements of the secondary controller as part of the power conversion system as shown in Fig. 4A according to an embodiment of the present invention.

FIG. 7 is an embodiment according to the present invention, including a secondary controller as shown in FIG. 6 and A simplified timing diagram of a power conversion system operating in discontinuous conduction mode (DCM) as shown in FIG. 4A.

FIG. 8 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

FIG. 9 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

FIG. 10 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

FIG. 11 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to another embodiment of the present invention.

FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 308 as part of the power conversion system 300 according to one embodiment of the present invention.

FIG. 13 is a simplified diagram showing a power conversion system having a secondary-side synchronous rectifier (SR) according to an embodiment of the present invention.

FIG. 14 is a diagram illustrating a switching scheme for a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 from a slow-on scheme to a fast-on scheme according to an embodiment of the present invention A simplified diagram of one or more predetermined conditions.

FIG. 15 is a diagram illustrating a switching scheme of a secondary-side synchronous rectifier (SR) controller from a slow-switching scheme to a fast-switching scheme according to another embodiment of the present invention. Simplified graph of one or more predetermined conditions.

FIG. 16 is a simplified diagram illustrating a method of determining a switching scheme of a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 according to some embodiments of the present invention.

FIG. 17 is a simplified diagram illustrating a method of determining a switching scheme of a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 according to some embodiments of the present invention.

FIG. 18 is a simplified diagram showing certain components of a secondary-side synchronous rectifier (SR) controller of the power conversion system as shown in FIG. 13 according to an embodiment of the present invention.

The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

FIG. 4A is a simplified diagram showing a power conversion system having a rectifier circuit according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 300 includes: a controller 302, a primary winding 304, a secondary winding 306, an auxiliary winding 324, a rectifier circuit 301, a diode 320, a current sensing resistor 328, capacitors 312 and 380, resistors 314, 316, 322 and 326, and power switch 330. The rectifier circuit 301 includes a secondary controller 308, a resistor 318 and a transistor 310. The secondary controller 308 includes terminals 390, 392, 394, 396, and 398. For example, the transistor 310 is a MOSFET. In another example, the power switch 330 is a transistor.

According to one embodiment, when the power switch 330 is closed (eg, on), energy is stored in a transformer including a primary winding 304 and a secondary winding 306. For example, when the power switch 330 is turned off (eg, turned off), the stored energy is transferred to the secondary side, and the voltage of the auxiliary winding 324 is mapped to the output voltage 350 on the secondary side. In another example, the controller 302 receives a feedback signal 360 for output voltage adjustment from a voltage divider including resistors 322 and 326. In another example, during a process of energy transfer (eg, a demagnetization process), the transistor 310 is turned on, and at least a portion of the secondary current 352 flows through the transistor 310. In another example, the on-resistance of the transistor 310 is very small (for example, in the range of tens of milliohms). In another example, when turned on, the voltage drop across transistor 310 is much less than the voltage drop across the rectifier diode (eg, diode 124 or diode 260), so the power loss of the power conversion system 300 Compared to system 100 or system 200, it is greatly reduced.

According to another embodiment, at the end of the energy transfer process (eg, demagnetization process), the secondary current 352 has a low value (eg, almost zero). For example, the transistor 310 is turned off to prevent residual current from flowing from the output terminal 351 to the ground through the transistor 310. In another example, when the transistor 310 is on, the power switch 330 remains off (eg, off). In another example, the secondary controller 308 receives a voltage signal 362 (eg, V _DR ) indicating a voltage at the terminal 364 (eg, the drain terminal of the transistor 310) of the transistor 310, and (eg, at the terminal G2 Where) a signal 366 is provided to drive the transistor 310.

As discussed above and further emphasized here, Figure 4A is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the controller 302 and the secondary controller 308 are on different wafers. In another example, the secondary controller 308 and the transistor 310 are on different wafers that are part of a multi-chip package. In another example, the secondary controller 308 and the transistor 310 are integrated on the same wafer.

FIG. 4B is a simplified diagram showing a power conversion system having a rectifier circuit according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 400 includes a controller 402, a primary winding 404, a secondary winding 406, a first auxiliary winding 424, a second auxiliary winding 425, a rectifier circuit 401, diodes 420 and 474, capacitors 412, 476, and 478, and a current Sense resistor 428, resistors 414, 416, 470, and 472, and power switch 430. The rectifying circuit 401 includes a secondary controller 408, a resistor 418, and a transistor 410. For example, the transistor 410 is a MOSFET. In another example, the power switch 430 is a transistor. In another example, the rectifying circuit 401 is the same as the rectifying circuit 301.

According to one embodiment, when the power switch 430 is closed (eg, on), energy is stored in a transformer including a primary winding 404 and a secondary winding 406. For example, when the power switch 430 is turned off (eg, turned off), the stored energy is transferred to the secondary side, and the voltage of the second auxiliary winding 425 is mapped to the output voltage 450 on the secondary side. In another example, the controller 402 receives a feedback signal 460 for output voltage adjustment from a voltage divider including resistors 470 and 472. In another example, during an energy transfer process (eg, a demagnetization process), the transistor 410 is turned on, and at least a portion of the secondary current 452 flows through the transistor 410. In another example, the on-resistance of the transistor 410 is very small (for example, in the range of tens of milliohms).

According to another embodiment, at the end of the energy transfer process (eg, demagnetization process), the secondary current 452 has a low value (eg, almost zero). For example, the transistor 410 is turned off to prevent reverse current from flowing from the output terminal to the ground through the transistor 410. In another example, when the transistor 410 is on, the power switch 430 remains off (eg, off). In another example, the secondary controller 408 (e.g., at the terminal DR) receives a voltage signal 462 indicating a voltage at a terminal 464 (e.g., the drain terminal of the transistor 410) of the transistor 410, and (e.g., at A signal 466 is provided at terminal G2) to drive transistor 410.

As discussed above and further emphasized here, Figure 4B is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the controller 402 and the secondary controller 408 are on different wafers. In another example, the secondary controller 408 and the transistor 410 are on different wafers that are part of a multi-chip package. In another example, the secondary controller 408 and the transistor 410 are integrated on the same wafer.

FIG. 5 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 502 represents the power switch 330 on or off as a function of time, waveform 504 represents the secondary current 352 as a function of time, and waveform 506 represents the feedback signal 360 as a function of time. In addition, waveform 508 represents the voltage signal 362 (for example, at terminal DR) as a function of time, waveform 510 represents the voltage signal 366 (for example, at terminal G2) as a function of time, and waveform 512 will flow through the trench of transistor 310 The track current 368 is represented as a function of time, and the waveform 514 represents the body diode current 370 flowing through a body diode (eg, a parasitic diode) of the transistor 310 as a function of time.

For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 5, the on-time period of the switch 330 (eg, T _on ) starts at time t ₄ and ends at time t ₅ ; the off-time period of the switch 330 (eg, T _off ) Starts at time t ₅ and ends at time t ₉ . A demagnetization period (eg, T _demag ) associated with including the primary winding 304 and the secondary winding 306 starts at time t ₅ and ends at time t ₈ . In another example, t ₄ t ₅ t ₆ t ₇ t ₈ t ₉ .

According to one embodiment, during the on-time period (eg, T _on ), the switch 330 is closed (eg, on), as shown by the waveform 502, and energy is stored in a transformer including the primary winding 304 and the secondary winding 306 . For example, the secondary current 352 has a low value 516 (eg, almost zero), as shown by the waveform 504. In another example, the voltage signal 362 (eg, V _DR ) received by the secondary controller 308 has a value 518 (eg, as shown by the waveform 508) above zero. In another example, signal 366 is at a logic low level (eg, as shown by waveform 510) and transistor 310 is turned off. In another example, during the on-time period (eg, T _on ), the channel current 368 has a low value of 520 (eg, almost zero, as shown by waveform 512), and the body diode current 370 has a low Value 522 (for example, almost zero, as shown by waveform 514).

According to another embodiment, at the end of the on time period (e.g., at t _5), the switch 330 turned off (e.g., turned off), as shown in the waveform 502, and the energy is transferred to the secondary side. For example, the secondary current 352 increases from a value 516 to a value 524 (eg, at t ₅ ), as shown by the waveform 504. In another example, the voltage signal 362 (eg, V _DR ) is reduced from a value 518 to a value 526 (eg, as shown by the waveform 508). In another example, the value 526 is lower than both the first threshold voltage 528 (eg, V _th1 ) and the second threshold voltage 530 (eg, V _th2 ). In another example, both the first threshold voltage 528 (eg, V _th1 ) and the second threshold voltage 530 (eg, V _th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the body diode of the transistor 310 begins to conduct, and the body diode current 370 increases from a value of 522 to a value of 529 (for example, as shown by waveform 514). Thereafter, the signal 366 changes from a logic low level to a logic high level (for example, at t ₆ as shown by the waveform 510), and in some embodiments, the transistor 310 is turned on. For example, the channel current 368 increases from a value of 520 to a value of 525 (eg, at t ₆ as shown by waveform 512). In another example, there is a delay (e.g., T _d ) between the time when the voltage signal 362 (eg, V _DR ) decreases from a value 518 to a value 526 and the time when the signal 366 changes from a logic low level to a logic high level . In another example, this (eg, T _d ) is zero.

According to another embodiment, during a demagnetization period (eg, T _demag ), the switch 330 remains off (eg, off), as shown by the waveform 502. For example, the secondary current 352 drops from the value 524 as shown by the waveform 504. In another example, if the voltage signal 362 (eg, V _DR ) is greater than the first threshold voltage 528 (eg, at t ₇ , as shown by waveform 508), the signal 366 changes from a logic high level to a logic low level ( (For example, as shown by waveform 510). In another example, the voltage signal 362 (eg, V _DR ) drops again to become lower than the first threshold signal 528 (eg, at t ₈ , as shown by waveform 508). In another example, the transistor 310 is turned off, and the channel current 368 is reduced to a low value 534 (eg, almost zero, as shown by the waveform 512). In another example, a body diode current 370 flows through the body diode of the transistor 310 and decreases to a low value (for example, almost zero at t ₉ as shown by the waveform 514). In another example, the demagnetization period ends at time t ₉ . In another example, immediately after time t ₉ , the voltage signal 362 increases, as shown by the rising edge of the waveform 508, and even if the rising edge is sensed, it will not be used to determine the switching frequency of the power conversion system 300 ( (Eg load conditions). In another example, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370. Thus, in some embodiments, waveform 512 (e.g., between t ₅ and t ₉₎ and a portion of a waveform 514 (e.g., between t ₅ and t ₉₎ bound a portion of the waveform is equal to 504 (e.g., Between t ₅ and t ₉ ).

According to another embodiment of the present invention, FIG. 5 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operated in a discontinuous conduction mode (DCM). For example, waveform 502 represents the power switch 430 on or off as a function of time, waveform 504 represents the secondary current 452 as a function of time, and waveform 506 represents the feedback signal 460 as a function of time. In addition, waveform 508 represents the voltage signal 462 (eg, at terminal DR) as a function of time, waveform 510 represents the voltage signal 466 (eg, at terminal G2) as a function of time, and waveform 512 will flow through the trench of transistor 410 Track current 468 is expressed as a function of time, while waveform 514 The body diode current 480 flowing through a body diode (eg, a parasitic diode) of the transistor 410 is represented as a function of time.

As discussed above and further emphasized here, Figures 4A and 4B are merely examples, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the power conversion system 300 shown in FIG. 4A or the power conversion system 400 shown in FIG. 4B that operates in other modes (for example, a quasi-resonant mode) can also implement the solutions shown in FIGS. 4A and 4B. .

In some embodiments, the scheme shown in Figure 5 is implemented in a continuous conduction mode. For example, if the secondary controller 308 senses a falling edge of the signal 362 (eg, V _DR ), the secondary controller 308 changes the signal 366 to turn on the transistor 310. In another example, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the secondary current 352 is greater than zero), and in response, the signal 362 (eg, V _DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

FIG. 6 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The secondary controller 308 includes: a clamp element 602, an offset component 604, a rising edge sensing element 606, comparators 608 and 624, a falling edge sensing element 610, a timing controller 612, and a logic control element 614 , A gate driver 616, a light load sensor 618, a signal generator 620, an oscillator 622, an undervoltage lockout element 628, and a reference signal generator 626. For example, some elements of the secondary controller 308 are used for synchronous rectification, including: clamp element 602, compensation element 604, rising edge sensing element 606, comparator 608, falling edge sensing element 610, and timing controller 612 , A logic control element 614, and a gate driver 616. In another example, certain elements of the secondary controller 308 are used for output voltage sensing and control, including: light load sensor 618, signal generator 620, oscillator 622, reference signal generator 626, logic The control element 614 and the gate driver 616. in In another example, the elements in the secondary controller 308 for output voltage sensing and control and the elements in the secondary controller 308 for synchronous rectification are integrated on the same chip.

FIG. 7 is a simplified timing diagram of a power conversion system 300 including a secondary controller 308 as shown in FIG. 6 and operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 702 represents the power switch 330 on or off as a function of time, waveform 704 represents the feedback signal 360 as a function of time, and waveform 706 represents a voltage signal 362 (eg, at terminal 390) as a function of time. In addition, waveform 708 represents signal 366 (eg, at terminal 392) as a function of time, waveform 710 represents channel current 368 flowing through transistor 310 as a function of time, and waveform 712 will indicate voltage signal 388 of output voltage 350 (For example, at terminal 398) is represented as a function of time.

According to one embodiment, the clamp element 602 receives a voltage signal 362 (eg, V _DR ) from a terminal 390 (eg, terminal _DR ). For example, the rising edge sensing element 606, the comparator 608, and the falling edge sensing element 610 receive a signal 658 that is equal to the voltage signal 362 modified by the compensation element 604. In another example, rising-edge sensing element 606, comparator 608, and falling-edge sensing element 610 output signals 670, 660, and 650, respectively, based on information associated with at least signal 658. In another example, the timing controller 612 receives signals 670, 660, and 650 and outputs a signal 672 to the logic controller 614 to drive the transistor 310. In some embodiments, the compensation component 604 is omitted.

According to another embodiment, before time t ₁₆ , the power conversion system 300 is under no-load / light-load conditions, and the switching frequency of the system 300 remains low (eg, below a threshold). For example, during the on-time period (for example, between time t ₁₁ and time t ₁₂ ), the switch 330 is closed (for example, on) as shown by the waveform 702 and the energy is stored including the primary windings 304 and two Secondary transformer 306. In another example, the voltage signal 362 (eg, at the terminal DR) has a value 714 (eg, as shown by the waveform 706) and is clamped by the clamp element 602. In another example, the signal 366 (eg, at the terminal G2) is at a logic low level (eg, as shown by the waveform 708), and the transistor 310 is turned off. In another example, during the on-time period (eg, T _on ), the channel current 368 has a low value of 716 (eg, almost zero, as shown by waveform 710). In another example, the voltage signal 388 (eg, V _s ) has a value of 718 (eg, as shown by waveform 712).

According to another embodiment, at the end of the on-time period (eg, at t ₁₂ ), the switch 330 is turned off (eg, off), as shown by the waveform 702, and energy is transferred to the secondary side. For example, the voltage signal 362 decreases from a value 714 to a value 720 (eg, as shown by the waveform 706). In another example, the value 720 is lower than both the third threshold voltage 722 (eg, V _th3 ) and the fourth threshold voltage 724 (eg, V _th4 ). In another example, both the third threshold voltage 722 (eg, V _th3 ) and the fourth threshold voltage 724 (eg, V _th4 ) are lower than the ground voltage 372. In another example, the body diode of the transistor 310 starts to conduct, and the body diode current 370 increases in size. Thereafter, the signal 366 changes from a logic low level to a logic high level (eg, at t ₁₃ as shown by the waveform 708), and in some embodiments, the transistor 310 is turned on. For example, the third threshold voltage 722 (for example, V _th3 ) and the fourth threshold voltage 724 (for example, V _th4 ) are the same as the first threshold voltage 528 and the second threshold voltage 530, respectively.

According to another embodiment, when the voltage signal 362 decreases from a value 714 to a value 720 (for example, as shown by the waveform 706), the falling edge sensing element 610 senses a drop in the voltage signal 362 and changes the signal 650 to connect Electricity crystal 310. For example, in response, the channel current 368 increases from a value of 716 to a value of 726 (eg, at t ₁₃ as shown by waveform 710). In another example, the voltage between the drain terminal and the source terminal of transistor 310 drops is determined based on the _{formula: V DS_M 2 = - I sec} × R ds_on ( Equation 1)

Among them, V _{DS_M2} indicates the voltage drop between the drain terminal and the source terminal of the transistor 310, I _sec indicates the secondary current 352, and R _{ds_on} indicates the on-resistance of the transistor 310.

According to some embodiments, because the on-resistance of transistor 310 is very small, the magnitude of the voltage drop between the drain and source terminals of transistor 310 is much smaller than that of a rectifying diode (e.g., diode 124 or diode) Body 260). For example, when the secondary current 352 becomes small (for example, near zero), the voltage drop between the drain terminal and the source terminal of the transistor 310 becomes very small in size, and the voltage signal 362 is very small in size . In another example, if the signal 658 is larger in size than the reference signal 652, the comparator 608 changes the signal 660 to turn off the transistor 310. In another example, the signal 366 changes from a logic high level to a logic low level (eg, at t ₁₄ as shown by the waveform 708) and the transistor 310 is turned off. In another example, the body diode of the transistor 310 begins to conduct again, and the body diode current 370 decreases in size (eg, eventually reaches almost zero at t ₁₅ ). Therefore, in some embodiments, energy is fully transferred to the output.

In one embodiment, the secondary controller 308 continuously monitors the output voltage 350 through a signal 388 (eg, V _s ). For example, the comparator 624 receives a reference signal 680 and a signal 388 (eg, V _s ), and outputs a signal 682. In another example, the light load sensor 618 receives a clock signal from the oscillator 622 and a signal 676 from the timing controller 612. In another example, the signal 676 indicates certain switching events (eg, rising or falling edges) in the signal 362. In another example, the light load sensor 618 outputs a signal 678 indicating the switching frequency of the power conversion system 300. In another example, the signal generator 620 receives the signals 678 and 682 and outputs a signal 684 to the logic control element 614 to affect the state of the transistor 310.

In another embodiment, if the output voltage 350 drops to low under any condition (for example, when the output load condition changes from no-load / light-load condition to full-load condition (for example, between t ₁₆ and t ₁₇ )) At the threshold level, the output voltage 350 decreases (eg, below the threshold level). For example, if the signal 388 (eg, V _s ) changes from a first value that is larger in size than the reference signal 680 to a second value that is lower in size than the reference signal 680 (eg, at t ₁₆ , as shown by waveform 712 ), The comparator 624 generates a pulse in the signal 682 to turn on the transistor 310 in a short period of time. In some embodiments, if signal 678 indicates that power conversion system 300 is under no-load / light-load conditions, signal generator 620 outputs a pulse in signal 684, and in response, gate driver 616 generates pulse 730 in signal 366 (For example, as shown by waveform 708). For example, the signal 362 (eg, at the terminal DR) is reduced to a value 728 (eg, between t ₁₆ and t ₁₇ as shown by the waveform 706). In another example, during the pulse period associated with pulse 730 in signal 366, transistor 310 is turned on and channel current 368 is in a different direction (e.g., from output capacitor 312 through transistor 310 to ground) Flow, as shown by waveform 710. In another example, the feedback signal 360 increases in size and forms a pulse (eg, between t ₁₆ and t ₁₇ as shown by waveform 704). According to some embodiments, the controller 302 senses the pulse of the feedback signal 360 and, in response, increases the peak current and switching frequency of the primary winding 304 in order to transfer more energy to the secondary side. For example, the output voltage 350 and the voltage signal 388 on the final size increases (e.g., at t _18, the waveform as shown in 712).

As discussed above and further emphasized here, Figures 6 and 7 are merely examples, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the secondary controller 408 is the same as the secondary controller 308 shown in FIG. 6.

In some embodiments, FIG. 7 is a simplified timing diagram of a power conversion system 400 including a secondary controller 408 and operating in a discontinuous conduction mode (DCM). For example, waveform 702 represents the power switch 430 on or off as a function of time, waveform 704 represents the feedback signal 460 as a function of time, and waveform 706 represents a voltage signal 462 as a function of time. In addition, waveform 708 represents the signal 466 as a function of time, waveform 710 represents the channel current 468 flowing through the transistor 410 as a function of time, and waveform 712 represents a voltage signal 488 indicating the output voltage 450 as a function of time.

In some embodiments, the secondary controller 308 as part of the power conversion system 300 or as part of the power conversion system 400 operates in other modes (eg, continuous conduction mode and critical conduction mode (eg, quasi-resonant mode)). The secondary controller 408 can also implement the solutions shown in FIG. 6 and FIG. 7.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, and based on information associated with at least the input signal, generate a gate drive signal at a second controller terminal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. The system controller is also configured to: If the signal is greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold to a second value less than the second threshold, then The gate driving signal is changed from the first logic level to the second logic level to turn on the transistor. For example, the system is implemented according to Figs. 4A, 4B, 5, 5, 6, and / or 7.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, the input signal being proportional to an output voltage associated with a secondary winding of the power conversion system, and based on at least information associated with the input signal, at the first The two controller terminals generate a gate drive signal to turn on or off the transistor, thereby affecting the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a pulse of the gate drive signal only when the input signal changes from a first value greater than a first threshold value to a second value less than the first threshold value to a pulse associated with the pulse. The transistor is turned on during the period. For example, the system is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

According to another embodiment, a system controller for adjusting a power conversion system includes a first comparator, a signal sensor, and a driving element. The first comparator is configured to receive an input signal and output a first comparison signal based on information associated with at least the input signal. The signal sensor is configured to receive an input signal and output a first sensing signal based on at least information associated with the input signal. The driving element is configured to output the gate driving signal to turn on or off the transistor based on the information associated with at least the first comparison signal and the first sensing signal to affect the current associated with the secondary winding of the power conversion system. The comparator is further configured to determine whether the input signal is greater than a first threshold. The signal sensor is further configured to determine whether the input signal changes from a first value greater than a second threshold value to a second value less than the second threshold value. The driving element is further configured to: if the first comparison signal indicates that the input signal is greater than a first threshold value, generate a gate driving signal at a first logic level to turn off the transistor, and if the first sensing signal indicates that the input signal is from If the first value greater than the second threshold becomes the second value smaller than the second threshold, the gate driving signal is changed from the first logic level to the second Logic level to turn on the transistor. For example, the system is implemented according to Figs. 4A, 4B, 5, 5, 6, and / or 7.

In one embodiment, a system controller for regulating a power conversion system includes a comparator, a pulse signal generator, and a driving element. The comparator is configured to receive an input signal and output a comparison signal based on information associated with at least the input signal. The pulse signal generator is configured to receive at least a comparison signal and generate a pulse signal based on at least information associated with the comparison signal. The driving element is configured to receive a pulse signal and generate a gate driving signal to turn on or off the transistor based on information associated with at least the pulse signal to affect the current associated with the secondary winding of the power conversion system. The comparator is also configured to determine whether the input signal is greater than or less than a threshold. The pulse signal generator is further configured to generate a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The driving element is further configured to generate a second pulse of the gate driving signal in response to the first pulse of the pulse signal to turn on the transistor in a pulse period associated with the second pulse. For example, the system is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal, processing information associated with the input signal, and generating a gate driving signal for receiving based on the information associated with at least the input signal. Turning the transistor on or off affects the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal to turn on or off a transistor based on information associated with at least the input signal to affect the current associated with the secondary winding of the power conversion system includes: if the input signal is greater than a first threshold, A gate drive signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold value to a second value less than a second threshold value, the gate drive signal is changed from the first value A logic level becomes a second logic level to turn on the transistor. For example, the method is implemented according to FIG. 4A, FIG. 4B, FIG. 5, FIG. 6, and / or FIG.

In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal that is proportional to an output voltage associated with a secondary winding of the power conversion system, and processing information associated with the input signal And based on at least the input signal The associated information generates a gate drive signal to turn the transistor on or off to affect the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal to turn on or off a transistor based on information associated with at least the input signal to affect the current associated with the secondary winding of the power conversion system includes: only when the input signal changes from greater than a first threshold A pulse of the gate drive signal is generated only when the first value of is changed to a second value that is less than the first threshold to turn on the transistor during the pulse period associated with the pulse. For example, the method is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than a first threshold. The method further includes generating a comparison signal based on at least information associated with the input signal, determining whether the input signal has changed from a first value greater than a second threshold value to a second value less than a second threshold value, and based on at least being associated with the input signal. Information generated by the sensor. In addition, the method includes outputting a gate driving signal to turn on or off the transistor based on information associated with at least the comparison signal and the sensing signal to affect the current associated with the secondary winding of the power conversion system. The process of outputting the gate drive signal to turn on or off the transistor based on the information associated with at least the comparison signal and the sensing signal to affect the current associated with the secondary winding of the power conversion system includes: if the comparison signal indicates an input signal Greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the sensing signal indicates that the input signal changes from a first value greater than a second threshold to a second less than the second threshold Value, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor. For example, the method is implemented according to FIG. 4A, FIG. 4B, FIG. 5, FIG. 6, and / or FIG.

In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than or less than a threshold. The method further includes generating a comparison signal based on information associated with at least the first input signal, receiving the comparison signal, and processing the information associated with the comparison signal. In addition, the method includes generating a pulse signal based on at least information associated with the comparison signal, receiving the pulse signal, processing the information associated with the pulse signal, and based on at least the pulse signal associated with the pulse signal. The information generates a gate drive signal to turn the transistor on or off, thereby affecting the current associated with the secondary winding of the power conversion system. The process of generating a pulse signal based on at least information associated with the comparison signal includes generating a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The process of generating a gate drive signal to turn on or off the transistor based on information associated with at least the pulse signal to affect the current associated with the secondary winding of the power conversion system includes: a first pulse in response to the pulse signal, A second pulse of the gate drive signal is generated to turn on the transistor during a pulse period associated with the second pulse. For example, the method is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

FIG. 8 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 802 represents power switch 330 on or off as a function of time, waveform 808 represents voltage signal 362 (e.g., V _DR at terminal _DR ) as a function of time, and waveform 810 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

As shown in FIG. 8, according to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V _ref1 ) . For example, the first reference voltage 829 (for example, V _ref1 ) is higher than the first threshold voltage 828 (for example, V _th1 ), and the first threshold voltage 828 (for example, V _th1 ) is higher than the second threshold voltage 830 (for example, V V _th2 ). In another example, the first reference voltage 829 (eg, V _ref1 ) is higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (eg, V _th1 ) V _th2 ) Both are below ground voltage 372 (eg, zero volts). In another example, the first reference voltage 829 (eg, V _ref1 ) is approximately equal to 15V.

In one embodiment, if the voltage signal 362 is determined by the secondary controller 308 to exceed the first reference voltage 829, the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) from above the first reference voltage 829 Decreases to a value below both the first threshold voltage 828 (for example, V _th1 ) and the second threshold voltage 830 (for example, V _th2 ), changing the signal 366 from a logic low level to a logic high level for turning on Transistor 310. In another embodiment, if the voltage signal 362 is not determined by the secondary controller 308 to exceed the first reference voltage 829, then even if the voltage signal 362 (eg, V _DR ) decreases below the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (for example, V _th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 8, the on-time period (for example, T _on ) of the switch 330 starts at time t ₂₄ and ends at time t ₂₅ ; the off-time period (for example, T _off ) of the switch 330 ) Starts at time t ₂₅ and ends at time t ₃₀ . In another example, a demagnetization period (eg, T _demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t ₂₅ and ends at time t ₃₀ or before time t ₃₀ . In another example, t ₂₄ t ₂₅ t ₃₀ .

In one embodiment, during the on-time period (eg, T _on ), the switch 330 is closed (eg, on), as shown by the waveform 802, and the energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V _DR ) received by the secondary controller 308 has a value 818 (eg, as shown by the waveform 808) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 810) and the transistor 310 is turned off. In another example, during the on-time period (eg, T _on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

In another embodiment, at the end of the on-time period (for example, at time t ₂₅ ), the switch 330 is turned off (for example, turned off), as shown by the waveform 802, and energy is transferred to the secondary side . For example, the secondary current 352 increases (for example, at time t ₂₅ ). In another example, the voltage signal 362 (eg, V _DR ) is reduced from a value 818 to a value 826 (eg, as shown by the waveform 808). In another example, the value 826 is lower than both the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (eg, V _th2 ). In another example, both the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (eg, V _th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 828 (eg, V _th1 ) is approximately equal to 300 mV, and the second threshold voltage 830 (eg, V _th2 ) is approximately equal to 10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V _ref1 ). In one embodiment, the first reference voltage 829 (eg, V _ref1 ) is higher than the first threshold voltage 828 (eg, V _th1 ), and the first threshold voltage 828 (eg, V _th1 ) is higher than the second threshold voltage 830 (For example, V _th2 ). For example, the first reference voltage 829 (eg, V _ref1 ) is approximately equal to 15V. In another embodiment, if the voltage signal 362 (eg, value 818) has been determined to exceed the first reference voltage 829 (eg, between time t ₂₄ and time t ₂₅ , as shown by waveform 808), then two The secondary controller 308 decreases in response to the voltage signal 362 (eg, V _DR ) from a value (eg, value 818) above the first reference voltage 829 to below a first threshold voltage 828 (eg, V _th1 ) and a second The value of both the threshold voltage 830 (for example, V _th2 ) (for example, the value 826) changes the signal 366 from a logic low level to a logic high level (for example, at time t ₂₅ , as shown in waveform 810, or at time t ₂₅ ), so that the transistor 310 is turned on. In another embodiment, if the voltage signal 362 (eg, value 818) has been determined to exceed the first reference voltage 829 (eg, between time t ₂₄ and time t ₂₅ , as shown by waveform 808), then two The secondary controller 308 reduces the voltage signal 362 (eg, V _DR ) from a value (eg, value 818) above the first reference voltage 829 to a value (eg, V _th2 ) below the second threshold voltage 830 (eg, V _th2 ). For example, the value 826) changes the signal 366 from a logic low level to a logic high level (eg, at time t ₂₅ , as shown by waveform 810, or at a time after time t ₂₅ ) to turn on transistor 310.

For example, there is a delay (eg, T _d ) between the time when the voltage signal 362 (eg, V _DR ) decreases from the value 818 to the value 826 and the time when the signal 366 changes from a logic low level to a logic high level. In another example, the delay (eg, T _d ) is zero. In another example, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another example, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

In another embodiment, if the voltage signal 362 is not determined to exceed the first reference voltage 829, it does not matter whether the voltage signal 362 (for example, V _DR ) is reduced below the first threshold voltage 828 (for example, V _th1 ) And the value of both the second threshold voltage 830 (eg, V _th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to keep the transistor 310 off. In another embodiment, if the voltage signal 362 is not determined to exceed the first reference voltage 829, it does not matter whether the voltage signal 362 (eg, V _DR ) is reduced below the second threshold voltage 830 (eg, V _th2 ) The secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 802. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (e.g., V _DR ) becomes greater than the first threshold voltage 828 (e.g., as shown by waveform 808), the signal 366 changes from a logic high level to a logic low level (e.g., as Waveform 810). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period ends before time t ₃₀ . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value of 819, as shown by the rising edge of the waveform 808.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V _ref1 ). In one embodiment, the first reference voltage 829 (eg, V _ref1 ) is higher than the first threshold voltage 828 (eg, V _th1 ), and the first threshold voltage 828 (eg, V _th1 ) is higher than the second threshold voltage 830 (For example, V _th2 ). For example, the first reference voltage 829 (eg, V _ref1 ) is approximately equal to 15V. In another embodiment, if the voltage signal 362 (eg, value 819) is not determined to exceed the first reference voltage 829 (eg, after time t ₂₅ but before time t ₃₀ , as shown by waveform 808), Even if the voltage signal 362 (for example, V _DR ) decreases to a value (for example, 82827) lower than both the first threshold voltage 828 (for example, V _th1 ) and the second threshold voltage 830 (for example, V _th2 ), two times The controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

According to another embodiment of the present invention, FIG. 8 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 802 represents power switch 430 on or off as a function of time, waveform 808 represents voltage signal 462 (eg, at terminal DR) as a function of time, and waveform 810 represents signal 466 (eg, at terminal G2) ) Is expressed as a function of time.

As previously discussed, in one embodiment, if the voltage signal 362 (eg, V _DR ) becomes greater than the first threshold voltage 828 (eg, as shown by waveform 808), the signal 366 changes from a logic high level to a logic level Low level (eg, as shown by waveform 810) to turn off transistor 310. For example, a hard turn-off such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 passes through the transistor The parasitic body diode 374 of 310 emits and resonates with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., t as shown in the waveform 808 at a time before the ringing ₃₀₎ reach lower than the first threshold voltage 828 (e.g., V _ThI) and a second threshold voltage 830 (e.g., V _th2 ) value of both (e.g., value 827).

Also as previously discussed, in another embodiment, the secondary controller 308 determines whether the voltage signal 362 (eg, V _DR ) exceeds the first reference voltage 829 (eg, V _ref1 ), and based on the result of the determination, It is also determined whether to turn off the power in response to the voltage signal 362 (eg, V _DR ) decreasing to a value below both the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (eg, V _th2 ) Crystal 310. For example, if the AC input voltage on the primary side has a large amplitude, the value 818 of the voltage signal 362 is higher than the value 819 of the voltage signal 362 as shown by the waveform 808; therefore, the first reference voltage 829 (eg, V _ref1 ) It may be selected to be less than the value 818 but greater than the value 819 in order to avoid false triggering of the secondary controller 308 by resonant ringing (eg, ringing before time t ₃₀ as shown by waveform 808). In another example, this false triggering may cause an out-of-synchronization of the secondary-side rectifier and an instability of the output voltage 350.

As discussed above and further emphasized here, Figure 8 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 8 can be implemented.

According to some embodiments, the scheme shown in Figure 8 is implemented in continuous conduction mode. In one embodiment, if the voltage signal 362 is determined by the secondary controller 308 to exceed the first reference voltage 829, the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) from above the first reference voltage 829 Decreases to a value below both the first threshold voltage 828 (for example, V _th1 ) and the second threshold voltage 830 (for example, V _th2 ), changing the signal 366 from a logic low level to a logic high level for turning on Transistor 310. In another embodiment, if the voltage signal 362 is not determined by the secondary controller 308 to exceed the first reference voltage 829, then even if the voltage signal 362 (eg, V _DR ) decreases below the first threshold voltage 828 (eg, V _th1 ) and the second threshold voltage 830 (for example, V _th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (eg V _DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

FIG. 9 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 902 represents power switch 330 on or off as a function of time, waveform 908 represents a voltage signal 362 (e.g., V _DR at terminal _DR ) as a function of time, and waveform 910 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

As shown in FIG. 9, according to some embodiments, the secondary controller 308 receives the voltage signal 362 (for example, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (for example, V _ref2 ) . In one embodiment, if the voltage signal 362 is determined to exceed the second reference voltage 929 (eg, V _ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains above the second reference voltage 929 (eg, V _ref2 ) And determine whether the duration is longer than a first threshold time period (eg, T _th1 ). For example, the second reference voltage 929 (for example, V _ref2 ) is lower than the first reference voltage 829 (for example, V _ref1 ) shown in FIG. 8. In another example, the second reference voltage 929 (eg, V _ref2 ) is higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th1 ) V _th2 ) Both are below ground voltage 372 (eg, zero volts).

In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V _ref2 ) is determined to be longer than the first threshold time period (eg, T _th1 ), the secondary controller 308 In response to the voltage signal 362 (eg, V _DR ) decreasing from a value above the second reference voltage 929 to a value below the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th2 ) This value changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V _ref2 ) is not determined to be longer than the first threshold time period (eg, T _th1 ), then even if the voltage signal 362 is (For example, V _DR ) is reduced to a value lower than both the first threshold voltage 928 (for example, V _th1 ) and the second threshold voltage 930 (for example, V _th2 ). From logic low to logic high, transistor 310 remains off.

For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 9, the on-time period of the switch 330 (for example, T _on ) starts at time t ₃₄ and ends at the time t ₃₅ ; the off-time period of the switch 330 (for example, T _off ) Starts at time t ₃₅ and ends at time t ₄₀ . In another example, a demagnetization period (eg, T _demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t ₃₅ and ends at time t ₄₀ or before time t ₄₀ . In another example, t ₃₄ t ₃₅ t ₄₀ .

In one embodiment, during the on time period (eg, T _on ), the switch 330 is closed (eg, on) as shown by the waveform 902 and the energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V _DR ) received by the secondary controller 308 has a value 918 (eg, as shown by the waveform 908) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 910) and the transistor 310 is turned off. In another example, during the on-time period (eg, T _on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

In another embodiment, at the end of the on-time period (for example, at time t ₃₅ ), the switch 330 is turned off (for example, turned off), as shown by the waveform 902, and energy is transferred to the secondary side . For example, the secondary current 352 increases (for example, at time t ₃₅ ). In another example, the voltage signal 362 (eg, V _DR ) is reduced from a value 918 to a value 926 (eg, as shown by the waveform 908). In another example, the value 926 is lower than both the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th2 ). In another example, both the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 928 (eg, V _th1 ) is approximately equal to -300 mV, and the second threshold voltage 930 (eg, V _th2 ) is approximately equal to -10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (eg, V _ref2 ). In one embodiment, if the voltage signal 362 is determined to exceed (eg, at time t ₃₄ ) the second reference voltage 929 (eg, V _ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains beyond the second Reference the duration of the voltage 929 (eg, V _ref2 ) (eg, duration T _A from time t ₃₄ to time t ₃₅ ) and determine if the duration (eg, duration T _A ) is greater than the first threshold time The segment (for example, T _th1 ) is long. For example, the second reference voltage 929 (for example, V _ref2 ) is lower than the first reference voltage 829 (for example, V _ref1 ) shown in FIG. 8. In another embodiment, if the duration (eg, duration T _A ) is determined to be longer than the first threshold time period (eg, T _th1 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) decreases from a value higher than the second reference voltage 929 (for example, the value 918) to a value lower than both the first threshold voltage 928 (for example, V _th1 ) and the second threshold voltage 930 (for example, V _th2 ). Value (e.g., value 926) to change signal 366 from a logic low level to a logic high level (e.g., at time t ₃₅ , as shown by waveform 910, or some time after t ₃₅ ) to turn on the transistor 310. In another embodiment, if the duration (eg, duration T _A ) is determined to be longer than the first threshold time period (eg, T _th1 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) decreases from a value higher than the second reference voltage 929 (for example, value 918) to a value lower than the second threshold voltage 930 (for example, V _th2 ) (for example, value 926), and moves the signal 366 from a logic low The quasi-level becomes a logic high level (for example, at time t ₃₅ , as shown by the waveform 910, or some time after t ₃₅ ) in order to turn on the transistor 310.

For example, the duration T _{A is} longer than the first threshold period T _th1 . In another example, the first threshold voltage 928 (for example, V _th1 ) is the same as the first threshold voltage 828 (for example, V _th1 ) shown in FIG. 8, and the second threshold voltage 930 (for example, V _th2 ) is the same as The second threshold voltage 830 (for example, V _th2 ) shown in FIG. 8 is the same. In another example, there is a delay between the time when the voltage signal 362 (eg, V _DR ) decreases from the value 918 to the value 926 and the time when the signal 366 changes from a logic low level to a logic high level (eg, T _d ) . In another example, the delay (eg, T _d ) is zero.

In another example, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another embodiment, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

In another embodiment, if the duration (eg, duration T _A ) is not determined to be longer than the first threshold time period (eg, T _th1 ), regardless of whether the voltage signal 362 (eg, V _DR ) decreases To values below both the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to maintain the transistor 310 Shut down. In another embodiment, if the duration (eg, duration T _A ) is not determined to be longer than the first threshold time period (eg, T _th1 ), regardless of whether the voltage signal 362 (eg, V _DR ) decreases To a value below the second threshold voltage 930 (eg, V _th2 ), the secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 902. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (eg, V _DR ) becomes greater than the first threshold voltage 928 (eg, as shown by waveform 908), the signal 366 changes from a logic high level to a logic low level (eg, as Waveform 910). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period ends before time t ₄₀ . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value 919, as shown by the rising edge of the waveform 908.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (eg, V _ref2 ). In one embodiment, if the voltage signal 362 is determined to exceed (eg, at time t ₃₆ ) the second reference voltage 929 (eg, V _ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains beyond the second Reference the duration (eg, duration T _B from time t ₃₆ to time t ₃₇ ) during the voltage 929 (eg, V _ref2 ) and determine whether the duration (eg, duration T _B ) is greater than the first threshold time The segment (for example, T _th1 ) is long. In another embodiment, if the duration (eg, duration T _B ) is not determined to be longer than the first threshold time period (eg, T _th1 ), then even if the voltage signal 362 (eg, V _DR ) decreases to Below the value of both the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 (eg, V _th2 ) (eg, the value 927), the secondary controller 308 also does not move the signal 366 from a logic low The quasi becomes a logic high level, so that the transistor 310 remains off. For example, the duration T _{B is} shorter than the first threshold time period T _th1 .

According to another embodiment of the present invention, FIG. 9 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 902 represents power switch 430 on or off as a function of time, waveform 908 represents voltage signal 462 (eg, at terminal DR) as a function of time, and waveform 910 represents signal 466 (eg, at terminal G2) ) Is expressed as a function of time.

As previously discussed, in one embodiment, if the voltage signal 362 (eg, V _DR ) becomes greater than the first threshold voltage 928 (eg, as shown by waveform 908), the signal 366 changes from a logic high level to a logic level Low level (eg, as shown by waveform 910) to turn off transistor 310. For example, a hard shutdown such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 is dissipated through parasitic diode 374 of transistor 310 And generate resonance with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., as shown by the waveform 908 in the time t before the ringing ₄₀₎ reach lower than the first threshold voltage 928 (e.g., V _ThI) and a second threshold voltage 930 (e.g., V _th2 ) value of both (e.g., value 927).

Also as previously discussed, in another embodiment, the secondary controller 308 determines whether the duration during which the voltage signal 362 remains beyond the second reference voltage 929 (eg, V _ref2 ) is greater than the first threshold time period (eg, T _th1 ) is long. For example, based on the result of this determination, the secondary controller 308 also decides whether to respond to the voltage signal 362 (eg, V _DR ) to decrease below the first threshold voltage 928 (eg, V _th1 ) and the second threshold voltage 930 ( For example, V _th2 ) and the transistor 310 is turned off.

In another example, if the AC input voltage on the primary side has a small amplitude, the value 918 of the voltage signal 362 and the value 919 of the voltage signal 362 are approximately equal, as shown by the waveform 908; therefore, a value less than the value 918 but greater than The value of the first reference voltage 829 (for example, V _ref1 ) having a value of 919 is difficult, but the value of the second reference voltage 929 (for example, V _ref2 ) may be selected such that the voltage signal 362 remains beyond the second reference voltage 929 ( For example, the duration of V _ref2 ) may be used to prevent the secondary controller 308 from being triggered by resonance ringing (eg, ringing before time t ₄₀ as shown in waveform 908) by mistake. In another example, this false triggering may cause an out-of-synchronization of the secondary-side rectifier and an instability of the output voltage 350.

As discussed above and further emphasized here, Figure 9 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 9 can be implemented.

According to some embodiments, the scheme shown in Figure 9 is implemented in continuous conduction mode. In one embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V _ref2 ) is determined to be longer than the first threshold time period (eg, T _th1 ), the secondary controller 308 responds The voltage signal 362 (for example, V _DR ) decreases from a value higher than the second reference voltage 929 to both lower than the first threshold voltage 928 (for example, V _th1 ) and the second threshold voltage 930 (for example, V _th2 ) Value to change the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V _ref2 ) is not determined to be longer than the first threshold time period (eg, T _th1 ), then even if the voltage signal 362 is (For example, V _DR ) is reduced to a value lower than both the first threshold voltage 928 (for example, V _th1 ) and the second threshold voltage 930 (for example, V _th2 ). From logic low to logic high, transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (eg, V _DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

According to some embodiments, as shown in FIG. 9, the secondary controller 308 receives the voltage signal 362 (for example, V _DR ) at the terminal 390 and determines whether the voltage signal 362 is lower than the first reference voltage 829 (for example, V _ref1 ) But exceeds the second reference voltage 929 (eg, V _ref2 ). In one embodiment, if the voltage signal 362 is determined to be lower than the first reference voltage 829 (eg, V _ref1 ) but exceeds the second reference voltage 929 (eg, V _ref2 ), the secondary controller 308 further determines the voltage signal 362 remains below the first reference voltage 829 (eg, V _ref1 ) but exceeds the duration of the second reference voltage 929 (eg, V _ref2 ) and determines whether the duration is longer than the first threshold time period (eg, T _th1 ) long. In another embodiment, if the voltage signal 362 remains below the first reference voltage 829 (eg, V _ref1 ) but exceeds the second reference voltage 929 (eg, V _ref2 ), the duration is determined to be greater than the first threshold time period (For example, T _th1 ) is long, the secondary controller 308 reduces the value of the secondary controller 308 (for example, V _DR ) from a value higher than the second reference voltage 929 to a value lower than the first threshold voltage 928 (for example, V _th1 ) And a second threshold voltage 930 (eg, V _th2 ), changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the voltage signal 362 remains below the first reference voltage 829 (eg, V _ref1 ) but exceeds a second reference voltage 929 (eg, V _ref2 ), the duration is not determined to be longer than the first threshold time The segment (for example, T _th1 ) is long, even if the voltage signal 362 (for example, V _DR ) decreases below both the first threshold voltage 928 (for example, V _th1 ) and the second threshold voltage 930 (for example, V _th2 ) Value, the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

FIG. 10 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 1002 represents the power switch 330 on or off as a function of time, waveform 1008 represents a voltage signal 362 (e.g., V _DR at terminal _DR ) as a function of time, and waveform 1010 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

As shown in FIG. 10, the secondary controller 308 receives the voltage signal 362 (for example, V _DR ) at the terminal 390, and determines from the time when the voltage signal 362 exceeds the third reference voltage 1029 (for example, V _ref3 ) to the voltage signal 362 drops to a duration that is lower than a fourth reference voltage 1031 (eg, V _ref4 ), and further determines whether the duration is longer than a second threshold time period (eg, T _th2 ). In one embodiment, if the duration is determined to be longer than a second threshold time period (eg, T _th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) from above a third reference The value of voltage 1029 is reduced to a value below both the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ), changing the signal 366 from a logic low level to a logic high level so that The transistor 310 is turned on. In another embodiment, if the duration is not determined to be longer than the second threshold time period (eg, T _th2 ), then even if the voltage signal 362 (eg, V _DR ) decreases below the first threshold voltage 1028 (For example, V _th1 ) and the second threshold voltage 1030 (for example, V _th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off Off.

For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 10, the on-time period (eg, T _on ) of the switch 330 starts at time t ₄₄ , ends at time t ₄₅ , or starts at time t ₅₀ , and ends at time t ₅₁ . In another example, as shown in FIG. 10, the off period (eg, T _off ) of the switch 330 starts at time t ₄₅ and ends at time t ₅₀ . In another example, a demagnetization period (eg, T _demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t ₄₅ and ends at time t ₅₀ or before time t ₅₀ . In another example, t ₄₄ t ₄₅ t ₅₀ t ₅₁ .

In one embodiment, during the on time period (eg, T _on ), the switch 330 is closed (eg, on), as shown by the waveform 1002, and energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V _DR ) received by the secondary controller 308 has a value 1018 (eg, as shown by waveform 1008) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 1010), and the transistor 310 is turned off. In another example, during the on-time period (eg, T _on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

In another embodiment, at the end of the on-time period (eg, at time t ₄₅ or at time t ₅₁ ), the switch 330 is turned off (eg, turned off), as shown in waveform 1002, and the energy It is transferred to the secondary side. For example, the secondary current 352 increases (for example, at time t ₄₅ or at time t ₅₁ ). In another example, the voltage signal 362 (eg, V _DR ) is reduced from a value of 1018 to a value of 1026 (eg, as shown by waveform 1008). In another example, the value 1026 is lower than both the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ). In another example, both the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 1028 (eg, V _th1 ) is approximately equal to -300 mV, and the second threshold voltage 1030 (eg, V _th2 ) is approximately equal to -10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines a time (eg, time t) from the voltage signal 362 to exceed the third reference voltage 1029 (eg, V _ref3 ). ₄₆ ) to the duration (e.g., duration T _C ) of the time (e.g., time t ₄₇ ) until the voltage signal 362 drops below the fourth reference voltage 1031 (e.g., V _ref4 ), and further determine the duration (e.g., time T _C ) , Whether the duration T _C ) is longer than the second threshold time period (for example, T _th2 ). For example, the fourth reference voltage 1031 (for example, V _ref4 ) is lower than the third reference voltage 1029 (for example, V _ref3 ), and the third reference voltage 1029 (for example, V _ref3 ) is lower than the first reference voltage shown in FIG. 8 829 (for example, V _ref1 ) is also lower than the second reference voltage 929 (for example, V _ref2 ) shown in FIG. 9. In another example, the third reference voltage 1029 (eg, V _ref3 ) is higher than the fourth reference voltage 1031 (eg, V _ref4 ), and the fourth reference voltage 1031 (eg, V _ref4 ) is higher than the first threshold voltage 1028 ( For example, V _th1 ), and the first threshold voltage 1028 (for example, V _th1 ) is higher than the second threshold voltage 1030 (for example, V _th2 ). In another example, the third reference voltage 1029 (eg, V _ref3 ) and the fourth reference voltage 1031 (eg, V _ref4 ) are both higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 1028 (Eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ) are both lower than the ground voltage 372 (eg, zero volts). In another example, the duration T _{C is} shorter than the second threshold time period T _th2 .

In one embodiment, if the duration (eg, duration T _C ) is not determined to be longer than the second threshold time period (eg, T _th2 ), then even if the voltage signal 362 (eg, V _DR ) decreases to low Based on the value of the first threshold voltage 1028 (for example, V _th1 ) and the second threshold voltage 1030 (for example, V _th2 ) (for example, the value 1027), the secondary controller 308 also does not bring the signal 366 from a logic low level. Goes logic high, so transistor 310 remains off. For example, the first threshold voltage 1028 (for example, V _th1 ) is the same as the first threshold voltage 928 (for example, V _th1 ) already shown in FIG. 9, and is also the same as the first threshold voltage 828 (for example, V _th1 ) shown in FIG. 7. For example, V _th1 ) is the same. In another example, the second threshold voltage 1030 (for example, V _th2 ) is the same as the second threshold voltage 930 (for example, V _th2 ) shown in FIG. 9, and also the second threshold voltage 830 as shown in FIG. 8. (For example, V _th2 ) is the same.

According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines a time (eg, time) when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V _ref3 ) t ₄₈₎ to the voltage signal 362 drops below the fourth reference voltage to time 1031 (e.g., V _ref4) (e.g., time t ₅₁₎ duration (e.g., the duration T _D), and further determines the time duration ( For example, is the duration T _D ) longer than a second threshold time period (for example, T _th2 ). In one embodiment, if the duration (eg, duration T _D ) is determined to be longer than the second threshold time period (eg, T _th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) Decreases from a value higher than the third reference voltage 1029 (for example, the value 1018) to a value lower than both the first threshold voltage 1028 (for example, V _th1 ) and the second threshold voltage 1030 (for example, V _th2 ) ( For example, the value 1026) changes the signal 366 from a logic low level to a logic high level (for example, at time t ₅₁ , as shown in waveform 1010, or some time after t ₅₁ ) to turn on transistor 310. In another embodiment, if the duration (eg, duration T _D ) is determined to be longer than the second threshold time period (eg, T _th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) decreases from a value higher than the third reference voltage 1029 (e.g., value 1018) to a value lower than the second threshold voltage 1030 (e.g., _Vth2 ) (e.g., the value 1026), and moves the signal 366 from a logic low level Go to a logic high level (for example, at time t ₅₁ , as shown by waveform 1010, or some time after t ₅₁ ) to turn on transistor 310.

For example, the duration T _{D is} longer than the second threshold time period T _th2 . In another example, there is a delay between the time when the voltage signal 362 (eg, V _DR ) decreases from the value 1018 to the value 1026 and the time when the signal 366 changes from a logic low level to a logic high level (eg, T _d ) . In another example, the delay (eg, T _d ) is zero. In another embodiment, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another embodiment, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

In another embodiment, if the duration (eg, duration T _D ) is not determined to be longer than the second threshold time period (eg, T _th2 ), then whether or not the voltage signal 362 (eg, V _DR ) decreases To values below both the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to maintain the transistor 310 Shut down. In another embodiment, if the duration (eg, duration T _D ) is not determined to be longer than the second threshold time period (eg, T _th2 ), then whether or not the voltage signal 362 (eg, V _DR ) decreases To a value below the second threshold voltage 1030 (eg, V _th2 ), the secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 1002. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (e.g., V _DR ) becomes greater than the first threshold voltage 1028 (e.g., as shown by waveform 1008), the signal 366 changes from a logic high level to a logic low level (e.g., as Waveform 1010). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period starts at time t ₄₅ and ends before time t ₅₀ or starts at time t ₅₁ . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value of 1019, as shown by the rising edge of the waveform 1008.

According to another embodiment of the present invention, FIG. 10 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 1002 represents the power switch 430 on or off as a function of time, waveform 1008 represents the voltage signal 462 (for example, at terminal DR) as a function of time, and waveform 1010 represents signal 466 (for example, at terminal G2) ) Is expressed as a function of time.

As previously discussed, in one embodiment, if the voltage signal 362 (eg, V _DR ) becomes greater than the first threshold voltage 1028 (eg, as shown by waveform 1008), the signal 366 changes from a logic high level to a logic level A low level (eg, as shown by waveform 1010) to turn off transistor 310. For example, a hard shutdown such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 is dissipated through parasitic diode 374 of transistor 310 And generate resonance with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., t as before ringing waveform ₅₀ at time 1008 shown) could be achieved at 1028 a first threshold voltage (e.g., V _ThI) 1030 and a second threshold voltage (e.g., V _th2 ) the value of both (for example, the value 1027).

Also as previously discussed, in another embodiment, the secondary controller 308 determines from the moment the voltage signal 362 exceeds the third reference voltage 1029 (eg, V _ref3 ) until the voltage signal 362 drops below the fourth reference voltage Whether the duration of the time of 1031 (for example, V _ref4 ) is longer than the second threshold time period (for example, T _th2 ). For example, based on the result of this determination, the secondary controller 308 further decides whether to respond to the voltage signal 362 (eg, V _DR ) to decrease below the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 ( For example, V _th2 ) and the transistor 310 is turned off. In another example, if the power conversion system 300 is under a light load or no load condition, the duration T _A (eg, T _on ) may become shorter than the first threshold time period (eg, T _th1 ), resulting in Missing pulse firing and / or out of sync, but such a resonant ringing pattern can be sensed, as shown in FIG. 10.

As discussed above and further emphasized here, Figure 10 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 10 can be implemented.

According to some embodiments, the scheme shown in Figure 10 is implemented in continuous conduction mode. In one embodiment, if the duration from the moment when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V _ref3 ) to the moment when the voltage signal 362 falls below the fourth reference voltage 1031 (eg, V _ref4 ) is Determined to be longer than the second threshold time period (for example, T _th2 ), the secondary controller 308 reduces the value of the second reference voltage 1029 from a value higher than the third reference voltage 1029 to a value lower than the first in response to the voltage signal 362 (for example, V _DR ) The values of both the threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ) change the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration from the moment when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V _ref3 ) to the moment when the voltage signal 362 falls below the fourth reference voltage 1031 (eg, V _ref4 ) Not determined to be longer than the second threshold time period (eg, T _th2 ), even if the voltage signal 362 (eg, V _DR ) decreases below the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (for example, V _th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (for example, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (for example V _DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

According to some embodiments, as shown in FIG. 10, the secondary controller 308 receives the voltage signal 362 (eg, V _DR ) at the terminal 390 and determines that the slave voltage signal 362 is lower than the first reference voltage 829 (eg, V _ref1 ) And the second reference voltage 929 (for example, V _ref1 ) but exceeding the third reference voltage 1029 (for example, V _ref3 ) until the voltage signal 362 drops below the fourth reference voltage 1031 (for example, V _ref4 ) The duration of the time, and further determine whether the duration is longer than a second threshold time period (eg, T _th2 ). For example, V _ref1 > V _ref2 > V _ref3 > V _ref4 . In one embodiment, if the duration is determined to be longer than a second threshold time period (eg, T _th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V _DR ) from above a third reference The value of voltage 1029 is reduced to a value below both the first threshold voltage 1028 (eg, V _th1 ) and the second threshold voltage 1030 (eg, V _th2 ), changing the signal 366 from a logic low level to a logic high level so that The transistor 310 is turned on. In another embodiment, if the duration is not determined to be longer than the second threshold time period (eg, T _th2 ), then even if the voltage signal 362 (eg, V _DR ) decreases below the first threshold voltage 1028 (For example, V _th1 ) and the second threshold voltage 1030 (for example, V _th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off Off.

FIG. 11 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. Secondary controller 308 includes: clamp element 1102, compensation element 1104, rising edge sensing element 1106, comparators 1124, 1210, 1220, 1230, and 1240, falling edge sensing element 1110, timing controller 1112, logic control Element 1114, gate driver 1116, light load sensor 1118, signal generator 1120, oscillator 1122, undervoltage lockout element 1128, reference signal generator 1126, or gate 1250, debounce element 1224, and timer element 1234 . For example, some elements of the secondary controller 308 are used for synchronous rectification, including: clamp element 1102, compensation element 1104, rising edge sensing element 1106, comparator 1124, 1210, 1220, 1230, and 1240, falling edge sensing element 1110, timing controller 1112, logic control element 1114, gate driver 1116, or gate 1250, debounce element 1224, and timer element 1234. In another example, certain elements of the secondary controller 308 are used for output voltage sensing and control, including: light load sensor 1118, signal generator 1120, oscillator 1122, reference signal generator 1126, logic The control element 1114 and the gate driver 1116. In another example, the elements for synchronous rectification in the secondary controller 308 and the elements for output voltage sensing and control in the secondary controller 308 are integrated on the same wafer.

In one embodiment, the clamp element 1102 receives a voltage signal 362 (eg, V _DR ) from a terminal 390 (eg, terminal _DR ). For example, the voltage signal 362 (eg, V _DR ) is clamped by the clamp element 1102. In another example, the clamp element 1102 is removed from the secondary controller 308. In another embodiment, the rising edge sensing element 1106, the comparators 1210, 1220, 1230, and 1240, and the falling edge sensing element 1110 receive a signal 1158 that is equal to the voltage signal 362 modified by the compensation element 1104. For example, the compensation element 604 is omitted, and the signal 1158 is the same as the signal 362. In another example, the rising edge sensing element 1106 includes a comparator, and the falling edge sensing element 1110 includes a comparator.

In another embodiment, the comparator 1210 receives the signal 1158 and a first reference voltage 1218 (eg, the first reference voltage 829), and outputs a signal 1216 to the OR gate. For example, if the signal 1158 is greater than the first reference voltage 1218 (eg, the first reference voltage 829), the signal 1216 is at a logic high level. In another example, if the signal 1158 is less than the first reference voltage 1218 (eg, the first reference voltage 829), the signal 1216 is at a logic low level. In another embodiment, the comparator 1220 receives the signal 1158 and the second reference voltage 1228 (eg, the second reference voltage 929), and outputs a signal 1222 to the debouncer 1224. For example, if the signal 1158 is greater than the second reference voltage 1228 (eg, the second reference voltage 929), the signal 1222 is at a logic high level. In another example, if the signal 1158 is less than the second reference voltage 1228 (eg, the second reference voltage 929), the signal 1222 is at a logic low level.

In another embodiment, the comparator 1230 receives the signal 1158 and the third reference voltage 1238 (eg, the third reference voltage 1029), and outputs a signal 1232 to the timer element 1234. For example, if the signal 1158 is greater than the third reference voltage 1238 (eg, the third reference voltage 1029), the signal 1232 is at a logic high level. In another example, if the signal 1158 is less than the third reference voltage 1238 (eg, the third reference voltage 1029), the signal 1232 is at a logic low level. In another embodiment, the comparator 1240 receives the signal 1158 and a fourth reference voltage 1248 (eg, the fourth reference voltage 1031), and outputs a signal 1242 to the timer element 1234. For example, if the signal 1158 is greater than the fourth reference voltage 1248 (eg, the fourth reference voltage 1031), the signal 1242 is at a logic high level. In another example, if the signal 1158 is less than the fourth reference voltage 1248 (eg, the fourth reference voltage 1031), the signal 1242 is at a logic low level.

According to one embodiment, the debounce element 1224 receives the signal 1222 from the comparator 1220, and determines whether the signal 1222 indicates that the signal 1158 remains greater than the second reference voltage 1228 for a longer duration than the first threshold time period (e.g., T _th1 ). (For example, the second reference voltage 929), and outputs a signal 1226 to the OR gate 1250. For example, if the anti-shake element 1224 determines that the signal 1222 indicates that the signal 1158 remains greater than the second reference voltage 1228 (eg, the second reference voltage 929) for a longer duration than the first threshold time period (eg, T _th1 ), then The debounce element 1224 generates a signal 1226 at a logic high level. In another example, if the anti-shake element 1224 determines that the signal 1222 does not indicate that the signal 1158 remains greater than the second reference voltage 1228 (for example, the second reference) for a longer duration than the first threshold time period (for example, T _th1 ) Voltage 929), the debounce element 1224 generates a signal 1226 at a logic low level.

According to another embodiment, the timer element 1234 receives a signal 1232 from the comparator 1230, and a signal 1242 from the comparator 1240, and outputs a signal 1236 to the OR gate 1250. For example, the timer element 1234 determines from the time when the voltage signal 1158 exceeds the third reference voltage 1238 (eg, the third reference voltage 1029) until the voltage signal 1158 drops below the fourth reference voltage 1248 (eg, the fourth reference voltage 1031) The duration of the moment. In another example, if the determined duration is longer than a second threshold time period (eg, T _th2 ), the timer element 1234 generates a signal 1236 at a logic high level. In another example, if the determined duration is not longer than a second threshold time period (eg, T _th2 ), the timer element 1234 generates a signal 1236 at a logic low level.

According to another embodiment, OR gate 1250 receives signals 1216, 1226, and 1236 from comparator 1210, debounce element 1224, and timer element 1234, respectively, and outputs signal 1252 to falling edge sensing element 1110 (eg, a comparator). For example, if any of the signals 1216, 1226, and 1236 are at a logic high level, the OR gate generates a signal 1252 at a logic high level. In another example, if none of the signals 1216, 1226, and 1236 are at a logic high level, the OR gate generates a signal 1252 at a logic low level.

In one embodiment, the falling edge sensing element 1110 (eg, a comparator) receives a signal 1252 from the OR gate 1250 and outputs a signal 1111 to the timing controller 1112. For example, if the signal 1252 is at a logic high level, the falling edge sensing element 1110 (eg, a comparator) is enabled for falling edge sensing; and if the signal 1252 is at a logic low level, the falling edge sensing element 1110 ( For example, the comparator) is not enabled (e.g., in standby) for falling edge sensing. In another example, if the falling edge sensing element 1110 (eg, a comparator) is enabled, if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, And / or the second threshold voltage 1030), then the falling edge sensing element 1110 changes the signal 1111 from a logic high level to a logic low level. In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold The voltage is 1113.

In another embodiment, the rising edge sensing element 1106 (eg, a comparator) outputs a signal 1107 to the timing controller 1112. For example, if the signal 1158 becomes greater than the first threshold voltage 1109 (eg, the first threshold voltage 828, the first threshold voltage 928, and / or the first threshold voltage 1028), the rising edge sensing element 1106 pulls the signal 1107 from the logic The high level becomes a logic low level. In another example, the first threshold voltage 1109 is larger in magnitude than the second threshold voltage 1113.

In another embodiment, the timing controller 1112 receives the signals 1107 and 1111 and outputs a signal 1172 to the logic controller 1114. For example, the logic controller 1114 outputs a signal 1115 to the gate driver 1116. In another example, the gate driver 1116 provides a signal 366 (eg, at the terminal G2) to drive the transistor 310. For example, in response to the signal 1107 changing from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic high level to a logic low level to turn off the transistor 310. In another example, if the signal 1111 changes from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310.

According to one embodiment, the secondary controller 308 continuously monitors the output voltage 350 through a signal 388 (eg, V _s ). For example, the comparator 1124 receives a reference signal 1180 and a signal 388 (eg, V _s ), and outputs a signal 1182. In another example, the light load sensor 1118 receives a clock signal 1174 from the oscillator 1122 and a signal 1176 from the timing controller 1112. In another example, the signal 1176 indicates certain switching events (eg, rising or falling edges) in the signal 362. In another example, the light load sensor 1118 outputs a signal 1178 indicating a switching frequency of the power conversion system 300. In another example, the signal generator 1120 receives the signal 1178 and the signal 1182, and outputs a signal 1184 to the logic control element 1114 to affect the state of the transistor 310.

In another embodiment, if the output voltage 350 drops below a certain threshold level under any condition (for example, when the output load condition changes from no-load / light-load condition to full-load condition), the output voltage 350 decreases (For example, below a certain threshold level). For example, if the signal 388 (eg, V _s ) changes from a first value that is greater than the reference signal 1180 in size to a second value that is lower than the reference signal 1180 in size, the signal generator 1120 generates a pulse in the signal 1184 so that The transistor 310 is turned on in a short period of time.

According to some embodiments, if the signal 1178 indicates that the power conversion system 300 is under no-load / light-load conditions, the signal generator 620 responds to the signal 388 (eg, V _s ) from a first value that is larger in size than the reference signal 1180 To be lower in magnitude than the second value of the reference signal 1180, a pulse is output in a signal 1184. For example, in response to a pulse in the signal 1184, the gate driver 1116 generates a pulse 730 in the signal 366. In another example, during a pulse period associated with pulse 730 in signal 366, transistor 310 is turned on and channel current 368 is in a different direction (e.g., from output capacitor 312 through transistor 310 to ground) flow. In another example, the feedback signal 360 increases in size and forms a pulse. According to some embodiments, the controller 302 senses the pulse of the feedback signal 360 and, in response, increases the peak current and switching frequency of the primary winding 304 in order to transfer more energy to the secondary side. For example, the output voltage 350 and the voltage signal 388 eventually increase in size.

As discussed above and further emphasized here, Figure 11 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, comparators 1230 and 1240 and timer element 1234 are removed from secondary controller 308, and OR gate 1250 receives signals 1216 and 1226 and outputs signal 1252 to falling edge sensing element 1110 (eg, a comparator). In another example, the comparator 1220 and the debounce element 1224 are removed from the secondary controller 308, and the OR gate 1250 receives the signals 1216 and 1236 and outputs a signal 1252 to the falling edge sensing element 1110 (e.g., a comparator). . In another example, the comparator 1210 is removed from the secondary controller 308, and the OR gate 1250 receives signals 1226 and 1236 and outputs a signal 1252 to a falling edge sensing element 1110 (eg, a comparator).

In another example, the comparators 1220, 1230, and 1240, the debounce element 1224, the timer element 1234, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1216 is used as the signal 1252 and the falling edge A sensing element 1110 (eg, a comparator) receives. In another example, the comparators 1210, 1230, and 1240, the timer element 1234, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1226 is used as the signal 1252 and is detected by the falling edge sensing element 1110 ( For example, a comparator) receives. In another example, the comparators 1210 and 1220, the debounce element 1224, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1236 is used as the signal 1252 and the falling edge sensing element 1110 (for example, Comparator) receive.

FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 308 as part of the power conversion system 300 according to one embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 1300 includes a process 1310 for keeping the falling edge sensing element 1110 disabled, a process 1320 for determining whether the condition A is satisfied, a process 1322 for determining whether the condition B is satisfied, and a method 1322 for determining whether the condition C is satisfied. Process 1324, a process 1330 for determining whether at least one of the conditions A, B, or C is satisfied, and a process 1340 for enabling the falling edge sensing element 1110.

At process 1310, the falling edge sensing element 1110 remains disabled (eg, remains on standby). For example, if the signal 1252 is at a logic low level, the falling edge sensing element 1110 (eg, a comparator) is not enabled (eg, in standby) for falling edge sensing. In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold The voltage is 1113.

At process 1320, it is determined whether condition A is satisfied, where condition A requires signal 1158 to be greater than a first reference voltage 1218 (eg, first reference voltage 829). For example, if the signal 1158 is greater than the first reference voltage 1218 (eg, the first reference voltage 829), the condition A is determined to be satisfied. In another example, the process 1320 is performed by a comparator 1210.

In process 1322, it is determined whether condition B is satisfied, where condition B requires signal 1158 to remain greater than the second reference voltage 1228 (eg, first reference voltage 929) for a longer duration than the first threshold time period ( _Tth1 ). For example, if the signal 1158 remains greater than the second reference voltage 1228 (eg, the second reference voltage 929) for a longer duration than the first threshold time period ( _Tth1 ), then the condition B is determined to be satisfied. In another example, the process 1322 is performed by a comparator 1220 and a debounce element 1224.

In process 1324, it is determined whether the condition C is satisfied, where the condition C requires that the voltage signal 1158 exceed the third reference voltage 1238 (for example, the third reference voltage 1029) until the voltage signal 1158 drops below the fourth reference voltage 1248 (for example The duration of the time of the fourth reference voltage 1031) is longer than the second threshold time period (T _th2 ). For example, if the duration from the moment when the voltage signal 1158 exceeds the third reference voltage 1238 (eg, the third reference voltage 1029) to the moment when the voltage signal 1158 falls below the fourth reference voltage 1248 (eg, the fourth reference voltage 1031) If the time is longer than the second threshold time period (T _th2 ), the condition C is determined to be satisfied. In another example, process 1324 is performed by comparators 1230 and 1240 and a timer element 1234.

According to some embodiments, the second reference voltage 1228 (eg, the second reference voltage 929) is less than the first reference voltage 1218 (eg, the first reference voltage 829) and the third reference voltage 1238 (eg, the third reference voltage 1029) Is smaller than the second reference voltage 1228 (for example, the second reference voltage 929), the fourth reference voltage 1248 (for example, the fourth reference voltage 1031) is smaller than the third reference voltage 1238 (for example, the third reference voltage 1029), and the second threshold value The voltage 1113 (for example, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030) is smaller than the fourth reference voltage 1248 (for example, the fourth reference voltage 1031). According to some embodiments, the first reference voltage 1218 (eg, the first reference voltage 829), the second reference voltage 1228 (eg, the second reference voltage 929), the third reference voltage 1238 (eg, the third reference voltage 1029), The fourth reference voltages 1248 (eg, the fourth reference voltage 1031) are each greater than zero, and the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030) Less than zero.

At process 1330, it is determined whether at least one of condition A, condition B, or condition C is satisfied. For example, if condition A is satisfied, at least one of condition A, condition B, or condition C is satisfied. In another example, if condition A and condition B are satisfied, at least one of condition A, condition B, or condition C is satisfied. In another example, process 1330 is performed by OR gate 1250.

According to one embodiment, if condition A, condition B, or condition C is not satisfied, process 1310 is performed, so that the falling edge sensing element 1110 remains unenabled (for example, (Standby). According to another embodiment, if at least one of condition A, condition B, or condition C is satisfied, process 1340 is performed.

For example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold voltage 1113 (eg (The second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030). In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the gate driver 1116 maintains the signal 366 at a logic low level to keep the transistor 310 off regardless of whether the signal 1158 is changed Is less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030).

At step 1340, the falling edge sensing element 1110 is enabled. For example, if the falling edge sensing element 1110 (eg, a comparator) is enabled, if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the first Two threshold voltages 1030), then the falling edge sensing element 1110 changes the signal 1111 from a logic high level to a logic low level. In another example, if the signal 1111 changes from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another example, if the falling edge sensing element 1110 (eg, a comparator) is enabled and if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and (Or the second threshold voltage 1030), the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310.

As discussed above and further emphasized here, Figure 12 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, if the falling edge sensing element 1110 is enabled in the process 1340, after the falling edge sensing element 1110 senses that the signal 1158 becomes smaller than the second threshold voltage 1113, the falling edge sensing element 1110 becomes inactive again. If so, process 1310 is repeated. In another example, the signal 1158 is the same as the signal 362.

In one embodiment, the secondary controller 408 is the same as the secondary controller 308 shown in FIG. 11. In another embodiment, FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 408 as part of the power conversion system 400.

According to some embodiments, the secondary controller 308 that is part of the power conversion system 300 or that is part of the power conversion system 400 that operates in other modes (eg, continuous conduction mode and critical conduction mode (eg, quasi-resonant mode)) The secondary controller 408 can also implement the solutions shown in FIG. 11 and FIG. 12.

Certain embodiments of the present invention provide a rectifier circuit that can avoid false triggering of switching pulses due to resonance oscillations caused by parasitic capacitors and transformer inductance. For example, a false triggering of a switching pulse may cause a non-synchronization between the secondary-side switching control and the primary-side switching control. In another example, this out of sync can cause reliability issues that can cause damage to the power conversion system. Some embodiments of the present invention provide systems and methods that improve the synchronization between the secondary-side switch and the primary-side switch and also improve the reliability of the power conversion system. For example, the secondary controller of the present invention can identify whether a negative pulse is really a turn-on signal or only a resonant ringing or glitch.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold at a first moment; in response to the input signal being determined to be greater than a first threshold at a first moment, determine that the input signal is at a second moment Whether it is less than the second threshold; and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal at the second controller terminal is changed from the first logic level to the second logic level. In addition, the second time is after the first time. For example, the system controller is implemented according to at least FIG. 8 and / or FIG. 11.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to The first controller terminal receives an input signal, and based at least in part on the input signal, generates a drive signal at the second controller terminal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a period of time longer than the predetermined duration, and in response to the input signal is determined to be longer than the predetermined duration It remains larger than the first threshold during the time period, and determines whether the input signal is less than the second threshold at a certain time after the time period. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a second threshold at this time, change the driving signal at the terminal of the second controller from the first logic level to the second logic level . For example, the system controller is implemented according to at least FIG. 9 and / or FIG. 11.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to determine whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration, And in response to the time interval being determined to be longer than a predetermined duration, it is determined whether the input signal is less than a third threshold at a certain time after the time interval. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a third threshold at this time, change the driving signal at the second controller terminal from the first logic level to the second logic level . For example, the system controller is implemented according to at least FIG. 10 and / or FIG. 11.

According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold; determine whether the input signal is longer than a first predetermined duration Remain within the interval greater than the second threshold; and determine whether the time interval from the first moment when the input signal becomes greater than the third threshold to the second moment when the input signal becomes less than the fourth threshold is longer than the second predetermined duration . In addition, the system controller is further configured to: in response to the input signal being determined to be greater than the first threshold value, the input signal being determined to remain greater than the second threshold value for a time period longer than the first predetermined duration, or The time interval is determined to be longer than the second predetermined duration, it is determined whether the input signal is less than a fifth threshold, and in response to the input signal being determined to be less than a fifth threshold, the driving signal at the second controller terminal is removed from the first One logic level becomes the second logic level. For example, the system controller is implemented according to at least FIG. 11 and / or FIG. 12.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal is greater than a first threshold at a first moment. In addition, generating a driving signal based on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than the first at a first moment Threshold, determining whether the input signal is less than the second threshold at the second moment, and in response to the input signal being determined to be less than the second threshold at the second moment, changing the driving signal from the first logic level to the second logic level . In addition, the second time is after the first time. For example, the method is implemented according to at least FIG. 8 and / or FIG. 11.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal remains greater than a first threshold for a period of time longer than a predetermined duration. In addition, generating a drive signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be longer than a predetermined duration Remains greater than the first threshold for a period of time, determines that the input signal is within the Whether a certain time after the time period is less than the second threshold, and in response to the input signal being determined to be less than the second threshold at that time, the driving signal is changed from the first logic level to the second logic level. For example, the method is implemented according to at least FIG. 9 and / or FIG. 11.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration long. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the time interval being determined to be longer than a predetermined duration, determining Whether the input signal is less than the third threshold at a time after the time interval, and in response to the input signal being determined to be less than the third threshold at the time, changing the driving signal from the first logic level to the second logic level . For example, the method is implemented according to at least FIG. 10 and / or FIG. 11.

According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes: determining whether the input signal is greater than a first threshold; determining whether the input signal remains greater than a second threshold for a period of time longer than a first predetermined duration; and determining from Whether the time interval from the first moment when the input signal becomes larger than the third threshold to the second moment when the input signal becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than a first threshold, the input The signal is determined to remain greater than the second threshold for a time period longer than the first predetermined duration, or the time interval is determined to be longer than the second predetermined duration, determines whether the input signal is less than a fifth threshold, and returns When the input signal is determined to be smaller than the fifth threshold, the driving signal is changed from the first logic level to the second logic level. For example, the method is implemented according to at least FIG. 11 and / or FIG. 12.

FIG. 13 is a simplified diagram showing a power conversion system having a secondary-side synchronous rectifier (SR) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 3300 (eg, a flyback power converter) includes a primary-side pulse width modulation (PWM) controller 3302, a primary winding 3304, a secondary winding 3306, a secondary-side synchronous rectifier (SR) controller 3308, A crystal 3310 (eg, a MOSFET), an output capacitive load 3312, an output resistive load 3314, and a power switch 3330 (eg, a transistor). The secondary-side synchronous rectifier (SR) controller 3308 includes terminals 3390, 3392, 3394, and 3396.

In one embodiment, the terminal 3390 receives a voltage signal 3362 indicating the voltage at the terminal 3364 (eg, the drain terminal of the transistor 3310) of the transistor 3310, and the terminal 3392 outputs a drive signal 3366 to the transistor 3310 (eg, a MOSFET) . In another embodiment, the terminal 3394 receives a voltage signal 3316 indicating the output voltage received by the output capacitive load 3312 and the output capacitive load 3314. In yet another embodiment, the terminal 3396 is biased to the secondary ground.

According to some embodiments, the primary-side pulse width modulation (PWM) controller 3302 generates a drive signal 3332 and outputs the drive signal 3332 to a power switch 3330 (eg, a transistor), and the secondary-side synchronous rectifier (SR) controller 3308 generates a drive The signal 3366 also outputs a driving signal 3366 to the transistor 3310 (for example, a MOSFET).

In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses a voltage signal 3362 indicating a voltage at a terminal 3364 of the transistor 3310 (eg, a building terminal of the transistor 3310), and provides a decision transistor 3310 The driving signal 3366 is turned on or off. In another embodiment, the secondary-side synchronous rectifier (SR) controller 3308 determines whether to use a slow-on scheme or a fast-on scheme.

According to one embodiment, if the secondary-side synchronous rectifier (SR) controller 3308 determines to use a fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses whether the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ). For example, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 immediately changes the driving signal 3366 from a logic low level to a logic high level; if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 does not become less than a threshold voltage (for example, V _th ), the secondary The side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level. In another example, if the driving signal 3366 does not change from a logic low level to a logic high level in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains fast turn-on Solution until the response signal 3366 changes from a logic low level to a logic high level in the fast turn-on scheme, and the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from the fast turn-on scheme to the slow turn-on Link scheme. In yet another example, if the driving signal 3366 changes from a logic low level to a logic high level in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from the fast turn-on scheme Return to the slow-on scheme until one or more predetermined conditions are met (for example, as shown in Figure 14, Figure 15, and / or Figure 16) for a secondary-side synchronous rectifier (SR) The connection scheme of the controller 3308 is changed from a slow connection scheme to a fast connection scheme.

According to another embodiment, if the secondary-side synchronous rectifier (SR) controller 3308 determines to use a slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses whether the voltage signal 3362 becomes less than a threshold voltage (e.g., , V _th ). For example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 does not immediately change the driving signal 3366 from a logic low level to a logic high level. In another example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier ( (SR) The controller 3308 senses whether the voltage signal 3362 remains less than a threshold voltage (for example, V _th ) for a duration equal to or greater than a predetermined period of time, and if the voltage signal 3362 remains for a duration equal to or greater than a predetermined period of time If it is less than a predetermined voltage (for example, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level. In another example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has not remained below a threshold voltage for a duration equal to or greater than a predetermined time period (for example, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level. In yet another example, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default switching scheme regardless of whether the driving signal 3366 changes from a logic low level to a logic high level in the slow switching scheme. Slow-on scheme until responding to one or more predetermined conditions are met (eg, as shown in Figure 14, Figure 15, and / or Figure 16) for secondary-side synchronous rectifier (SR) control The connection scheme of the switch 3308 is changed from a slow-connection scheme to a fast-connection scheme.

According to some embodiments, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR The controller 3308 immediately changes the driving signal 3366 from a logic low level to a logic high level. For example, after the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 from a logic low level to a logic high level in the fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 Keep at the logic high level, and then change the driving signal 3366 from the logic high level to the logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

According to some embodiments, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR The controller 3308 senses whether the voltage signal 3362 remains less than a threshold voltage (eg, V _th ) for a duration equal to or longer than a predetermined period of time, and if the voltage signal 3362 remains less than a duration equal to or longer than a predetermined period of time The threshold voltage (for example, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level. For example, after the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 from a logic low level to a logic high level in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 Keep at the logic high level, and then change the drive signal 3366 from the logic high level to the logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time at which the drive signal 3366 will change from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

According to some embodiments, the default on scheme for the secondary-side synchronous rectifier (SR) controller 3308 is a slow on scheme. In one embodiment, if one or more predetermined conditions are met (e.g., as shown in Figure 14, Figure 15, and / or Figure 16), it is used for a secondary-side synchronous rectifier (SR) controller The 3308 connection scheme changed from a slow connection scheme to a fast connection scheme. For example, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR) controller 3308 generates a drive signal 3366 for turning on the transistor 3310 without delay. In another example, if the driving signal 3366 for turning on the transistor 3310 is generated in the fast-on scheme, the turning-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 becomes slower from the fast-on scheme Turn-on scheme, and maintain the slow-on scheme as the default turn-on scheme until one or more predetermined conditions are met (for example, as shown in FIG. 14, FIG. 15, and / or FIG. 16), The switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme.

In another embodiment, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR) The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns), and if the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns) Then, the secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 for turning on the transistor 3310. For example, if the voltage signal 3362 does not remain less than a threshold voltage (for example, V _th ) for at least the debounce duration (for example, 400 ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate Driving signal 3366. In another example, regardless of whether the driving signal 3366 for turning on the transistor 3310 is generated in the slow-on scheme, the switching-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains slow as the default switching scheme. The scheme is switched on in response to one or more predetermined conditions being met (for example, as shown in FIG. 14, FIG. 15, and / or FIG. 16) for a secondary-side synchronous rectifier (SR) controller 3308 The connection scheme changed from a slow connection scheme to a fast connection scheme. In yet another example, a slow-on scheme is used to filter out noise interference from the voltage signal 3362.

According to some embodiments, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is set at the beginning of the power-up process as a slow-on scheme as its default turn-on scheme. In one embodiment, if one or more predetermined conditions as shown in FIG. 14 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme. After the switching-on scheme, and then generating the driving signal 3366 for turning on the transistor 3310 in the quick-switching scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the quick-switching scheme back to its default The scheme's slow-on scheme. In another embodiment, if one or more predetermined conditions shown in FIG. 15 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme. After the switching-on scheme, and then generating the driving signal 3366 for turning on the transistor 3310 in the quick-switching scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the quick-switching scheme back to its default The scheme's slow-on scheme. In yet another embodiment, if one or more predetermined conditions as shown in FIG. 16 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to Quick-on scheme, and then turn on the transistor in the quick-on scheme After the driving signal 3366 of 3310, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast switching scheme to the slow switching scheme as its default scheme.

FIG. 14 is a diagram illustrating a switching scheme of the secondary-side synchronous rectifier (SR) controller 3308 shown in FIG. 13 from a slow-on scheme to a fast-on scheme according to an embodiment of the present invention. A simplified diagram of one or more predetermined conditions. This figure is only an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Waveform 3432 represents the driving signal 3332 as a function of time, waveform 3462 voltage signal 3362 represents a function of time, and waveform 3466 represents the driving signal 3366 as function of time.

In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal at a 3362 t ₁₀₁ 3490 becomes greater than the reference voltage (e.g., V _ref1) at time t at time ₁₀₂ remains greater than the reference voltage before 3490 and becomes less than the reference voltage 3490 (for example, V _ref1 ) at time t ₁₀₂ . For example, if the duration (for example, T _A ) from time t ₁₀₁ to time t ₁₀₂ is equal to or greater than the threshold duration T _th1 , the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 is connected slowly The communication scheme is changed to the quick connection scheme. In another example, the threshold duration T _th1 represents the leading edge debounce time (eg, 300 ns) of the primary control system.

In another embodiment, in the fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has become less than the threshold voltage 3480 (for example, V _th ) at time t ₁₀₂ , two The secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t ₁₀₂ . For example, the threshold voltage 3480 (eg, V _th ) is less than the reference voltage 3490 (eg, V _ref1 ). In another example, after the driving signal 3366 is changed from a logic low level to a logic high level at time t ₁₀₂ in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 starts from The fast-on scheme changes back to the slow-on scheme as its default scheme.

In yet another embodiment, after the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t ₁₀₂ , the secondary-side synchronous rectifier (SR) controller 3308 The driving signal 3366 is maintained at a logic high level, and then the driving signal 3366 is changed from a logic high level to a logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

FIG. 15 is one or more of the switching scheme of the secondary-side synchronous rectifier (SR) controller 3308 shown in FIG. 13 from the slow-switching scheme to the fast-switching scheme according to another embodiment of the present invention. Simplified graph of multiple predetermined conditions. This figure is only an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Waveform 3532 represents the drive signal 3332 as a function of time, waveform 3562 represents the voltage signal 3362 as a function of time, and waveform 3566 represents the drive signal 3366 as a function of time.

In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal 3362 at time t ₁₁₁ 3590 becomes greater than the reference voltage (e.g., V _ref2), before the time t ₁₁₂ 3590 remains greater than the reference voltage (For example, V _ref2 ), and becomes smaller than the reference voltage 3590 (for example, V _ref2 ) at time t ₁₁₂ . For example, the reference voltage 3590 (eg, V _ref2 ) is less than the reference voltage 3490 (eg, V _ref1 ). In another example, if the duration (eg, T _J ) from time t ₁₁₁ to time t ₁₁₂ is equal to or greater than the threshold duration Tth2, a turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 From a slow-on scheme to a fast-on scheme. In yet another example, the threshold duration _Tth2 is longer than the threshold duration Tth1.

In another embodiment, in the fast turn-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than the threshold voltage 3480 (eg, V _th ) at time t ₁₁₂ , two The secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t ₁₁₂ . For example, the threshold voltage 3480 (eg, Vth) is less than the reference voltage 3490 (eg, V _ref1 ) and the reference voltage 3590 (eg, V _ref2 ). In another example, after the driving signal 3366 changes from a logic low level to a logic high level at time t ₁₁₂ in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 starts from The fast-on scheme changes back to the slow-on scheme as its default scheme.

In yet another embodiment, after the secondary-side synchronous rectifier (SR) controller 3308 drives the driving signal 3366 from a logic low level to a logic high level at time t ₁₁₂ , the secondary-side synchronous rectifier (SR) controls The driver 3308 maintains the driving signal 3366 at a logic high level, and then changes the driving signal 3366 from a logic high level to a logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

According to one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal becomes at a time t ₁₁₃ 3362 3590 than the reference voltage (e.g., V _ref2), the time t is greater than the reference voltage ₁₁₄ remains before 3590 (For example, V _ref2 ), and becomes smaller than the reference voltage 3590 (for example, V _ref2 ) at time t ₁₁₄ . For example, if the duration (for example, T _K ) from time t ₁₁₃ to time t ₁₁₄ is less than the threshold duration T _th2 , the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 maintains a slow turn-on scheme .

According to another embodiment, in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than the threshold voltage 3480 (eg, V _th ) at time t ₁₁₅ , and the secondary The side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level at time 115. For example, in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 determines whether the voltage signal 3362 remains less than a threshold voltage 3480 (for example, for a duration equal to or greater than a predetermined time period (for example, T _s ) V _th ). In another example, the predetermined time period (eg, T _s ) is greater than zero, the threshold duration T _{th1 is} greater than zero, and the threshold duration T _{th2 is} greater than zero. In yet another example, as shown in FIG. 15, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has become greater than the threshold voltage 3480 (for example, V _th ) at time t ₁₁₆ , and It is determined that the duration from time t ₁₁₅ to t ₁₁₆ is shorter than a predetermined time period (for example, T _s ), and the secondary-side synchronous rectifier (SR) controller 3308 maintains the driving signal 3366 at a logic low level.

As mentioned earlier and further emphasized here, Figure 15 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes smaller than the reference voltage 3490 (for example, V _ref1 ) but greater than the reference voltage 3590 (for example, V _ref2 ) at time t ₁₁₁ at time t Before t _112, it remains less than the reference voltage 3490 (eg, V _ref1 ) but is greater than the reference voltage 3590 (eg, V _ref2 ), and becomes less than the reference voltage 3590 (eg, V _ref2 ) at time t ₁₁₂ . In another example, if the duration (for example, T _J ) from time t ₁₁₁ to time t ₁₁₂ is equal to or greater than the threshold duration T _th2 , for the turn-on of the secondary-side synchronous rectifier (SR) controller 3308 The scheme changed from a slow-on scheme to a fast-on scheme.

FIG. 16 is a simplified diagram illustrating a method of determining a turn-on scheme by a secondary-side synchronous rectifier (SR) controller 3308 as shown in FIG. 13 according to some embodiments of the present invention. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 3600 includes a process 3610 for determining that the connection scheme is a slow connection scheme, a process 3620 for determining whether the condition P is satisfied, a process 3622 for determining whether the condition Q is satisfied, and a method for determining the condition P or the condition Q. At least one of the processes 3630 is satisfied, and the process 3640 for determining that the connection scheme is a fast connection scheme.

At process 3610, the secondary-side synchronous rectifier (SR) controller 3308 determines the turn-on scheme as a slow-on scheme as a default turn-on scheme. For example, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is a slow turn-on scheme as its default turn-on scheme at the beginning of the power-up process.

In process 3620, it is determined whether the condition P is satisfied. For example, the condition P is that the voltage signal 3362 becomes greater than the reference voltage 3490 (for example, V _ref1 ), and remains greater than the reference voltage 3490 (for example, V for a duration equal to or greater than the threshold duration T _th1 (for example, T _A )). _ref1 ). In another example, if the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V _ref1 ) and remains greater than the reference voltage 3490 (eg, T _A ) for a duration equal to or greater than the threshold duration T _th1 (eg, T _A ) V _ref1 ), it is determined that the condition P is satisfied.

In process 3622, it is determined whether the condition Q is satisfied. For example, the condition Q is that the voltage signal 3362 becomes greater than the reference voltage 3590 (for example, V _ref2 ) and remains greater than the reference voltage 3590 (for example, V for a duration equal to or greater than the threshold duration T _th2 (for example, T _J ) _ref2 ). In another example, if the voltage signal 3362 becomes greater than the reference voltage 3590 (e.g.,) and equal to or greater than the duration threshold duration T _th2 (e.g., T _J) 3590 remains greater than the reference voltage (e.g., V _ref2 ), It is determined that the condition Q is satisfied. In yet another example, the reference voltage 3590 (eg, V _ref2 ) is less than the reference voltage 3490 (eg, V _ref1 ), and the threshold duration T _{th2 is} longer than the threshold duration T _th1 .

At process 3630, it is determined that at least one of condition P or condition Q is satisfied. For example, if the condition P is satisfied, at least one of the condition P or the condition Q is satisfied. In another example, if the condition Q is satisfied, at least one of the condition P or the condition Q is satisfied. In yet another example, if the condition P and the condition Q are satisfied, at least one of the condition P or the condition Q is satisfied.

According to one embodiment, if neither the condition P nor the condition Q is satisfied, the process 3610 is executed so that the turn-on scheme of the secondary-side synchronous rectifier (SR) controller 3308 remains as the slow-on scheme of the default turn-on scheme. According to another embodiment, if at least one of the condition P or the condition Q is satisfied, the process 3640 is performed.

At process 3640, the secondary-side synchronous rectifier (SR) controller 3308 determines that the turn-on scheme is a fast turn-on scheme. For example, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from a slow-on scheme to a fast-on scheme.

In one embodiment, under the turn-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier (SR The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (eg, 400ns), and if the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (eg, 400ns), then The secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 that turns on the transistor 3310. For example, if the voltage signal 3362 does not remain less than a threshold voltage (for example, Vth) for at least the duration of the debounce duration (for example, 400ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate a drive to turn on the transistor 3310 Signal 3366. In another example, regardless of whether the driving signal 3366 for turning on the transistor 3310 is generated under the slow-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default switching scheme A slow-on scheme, as shown in process 3610.

In another embodiment, under the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, Vth), the secondary-side synchronous rectifier ( (SR) The controller 3308 generates a drive signal 3366 for turning on the transistor 3310 without delay. In another example, after the driving signal 3366 for turning on the transistor 3310 is generated under the fast-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast-on scheme to the slow-on scheme. Communication scheme, as shown in process 3610.

As discussed above and further emphasized here, Figure 16 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, the condition P is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3490 (for example, V _ref1 ) and remains equal to or greater than the reference voltage 3490 (for example, T _A ) for a duration equal to or greater than the threshold duration T _th1 (for example, T _A ) For example, V _ref1 ), the condition Q is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3590 (eg, V _ref2 ) and remains equal to or greater than a duration equal to or greater than the threshold duration T _th2 (eg, T _J ) Reference voltage 3590 (for example, V _ref2 ). In another example, the condition P is that the reference voltage 3362 becomes equal to or greater than the reference voltage 3490 (for example, V _ref1 ), and remains equal to or greater than the reference for a duration (for example, T _A ) that is greater than the threshold duration T _th1 . Voltage 3490 (eg, V _ref1 ), condition Q is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3590 (eg, V _ref2 ), and remains equal to a duration (eg, T _J ) that is greater than a threshold duration T _th2 Or greater than the reference voltage 3590 (for example, V _ref2 ). In yet another example, the condition P is that the reference voltage 3362 becomes greater than the reference voltage 3490 (eg, V _ref1 ) and remains greater than the reference voltage 3490 (eg, T _A ) for a duration (eg, T _A ) that is greater than the threshold duration T _th1 . , V _ref1 ), condition Q is that the voltage signal 3362 becomes greater than the reference voltage 3590 (for example, V _ref2 ), and remains greater than the reference voltage 3590 (for example, T _J ) for a duration greater than the threshold duration T _th2 (for example, T _J ) V _ref2 ).

FIG. 17 is a simplified diagram illustrating a method of determining a turn-on scheme by a secondary-side synchronous rectifier (SR) controller 3308 as shown in FIG. 13 according to some embodiments of the present invention. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 3600 includes a process 3710 for determining that the turn-on scheme is a slow-on scheme, a process 3720 for determining whether the voltage signal 3362 becomes greater than a reference voltage 3490 (eg, V _ref1 ), and a process for determining whether the voltage signal 3362 is Or a process 3721 that remains greater than a reference voltage 3490 (for example, V _ref1 ) for a duration that is greater than a threshold duration T _th1 , a process 3722 for determining whether the voltage signal 3362 becomes greater than a reference voltage 3590 (for example, V _ref2 ), with A process 3723 for determining whether the voltage signal 3362 remains greater than a reference voltage 3590 (eg, V _ref2 ) for a duration equal to or greater than the threshold duration T _th2 , and a process 3740 for determining that the turn-on scheme is a quick-on scheme.

At process 3710, the secondary-side synchronous rectifier (SR) controller 3308 determines the turn-on scheme as a slow-on scheme as a default turn-on scheme. For example, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is a slow turn-on scheme as its default turn-on scheme at the beginning of the power-up process.

At process 3720, it is determined whether the voltage signal 3362 becomes greater than a reference voltage 3490 (eg, V _ref1 ). For example, if it is determined at process 3720 that the voltage signal 3362 has not become greater than the reference voltage 3490 (eg, V _ref1 ), then the process 3722 is performed. In another example, if it is determined in process 3720 that the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V _ref1 ), then the process 3721 is performed.

In process 3721, it is determined whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V _ref1 ) for a duration equal to or greater than the threshold duration T _th1 . For example, if it is determined in process 3721 that the voltage signal 3362 has not remained greater than the reference voltage 3490 (eg, V _ref1 ) for a duration equal to or greater than the threshold duration T _th1 , then process 3722 is performed. In another example, if it is determined in process 3721 that the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V _ref1 ) for a duration equal to or greater than the threshold duration T _th1 , the process 3740 is performed.

At process 3722, it is determined whether the voltage signal 3362 has become greater than a reference voltage 3590 (eg, V _ref2 ). For example, the reference voltage 3590 (eg, V _ref2 ) is less than the reference voltage 3490 (eg, V _ref1 ). In another example, if it is determined in process 3722 that the voltage signal 3362 has not become greater than the reference voltage 3590 (eg, V _ref2 ), then Process 3710 is performed. In another example, if it is determined in process 3722 that the voltage signal 3362 becomes greater than a reference voltage 3590 (eg, V _ref2 ), then process 3723 is performed.

In process 3723, it is determined whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or greater than the threshold duration T _th2 . For example, if it is determined in process 3723 that the voltage signal 3362 has not remained greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or greater than the threshold duration T _th2 , then process 3710 is performed. In another example, if it is determined in process 3723 that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or greater than the threshold duration T _th2 , the process 3740 is performed.

At process 3740, the secondary-side synchronous rectifier (SR) controller 3308 determines that the turn-on scheme is a fast turn-on scheme. For example, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from a slow-on scheme to a fast-on scheme.

In one embodiment, under the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier ( (SR) The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), and if the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns), Then, the secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 for turning on the transistor 3310. In addition, if the voltage signal 3362 does not remain less than a threshold voltage (for example, V _th ) at least during the debounce duration (for example, 400 ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate Driving signal 3366. In another example, regardless of whether a drive signal 3366 for turning on the transistor 3310 is generated under the slow turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default turn-on scheme The slow-on scheme is shown in process 3610.

In another embodiment, under the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the secondary-side synchronous rectifier The (SR) controller 3308 generates the drive signal 3366 that turns on the transistor 3310 without delay, regardless of whether the voltage signal 3362 remains less than a threshold voltage (for example, V _th ) at least during the debounce duration (for example, 400 ns). In another example, after the driving signal 3366 for turning on the transistor 3310 is generated under the fast-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast-on scheme to the slow-on scheme. Communication scheme, as shown in process 3610.

As discussed above and further emphasized here, Figure 17 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, in process 3722, it is determined whether the voltage signal 3362 becomes less than the reference voltage 3490 (for example, V _ref1 ) but is greater than the reference voltage 3590 (for example, V _ref2 ). If it is determined in process 3722 that the voltage signal 3362 becomes less than the reference voltage 3490 ( For example, V _ref1 ) but greater than the reference voltage 3590 (eg, V _ref2 ), the process 3723 is performed. In another example, in process 3723, it is determined whether the voltage signal 3362 remains less than the reference voltage 3490 (e.g., V _ref1 ) but greater than the reference voltage 3590 (e.g., V _ref2 ) for a duration equal to or greater than the threshold duration Tth2, If it is determined in process 3723 that the voltage signal 3362 remains less than the reference voltage 3490 (eg, V _ref1 ) but greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or greater than the threshold duration T _th2 , then the process 3740 is performed.

FIG. 18 is a simplified diagram showing certain components of the secondary-side synchronous rectifier (SR) controller 3308 of the power conversion system 3300 as shown in FIG. 13 according to an embodiment of the present invention. This figure is only an example, which should not unduly limit the scope of patent application. this Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. The secondary-side synchronous rectifier (SR) controller 3308 includes terminals 3390, 3392, 3394, and 3396. In addition, the secondary-side synchronous rectifier (SR) controller 3308 includes comparators 3810 and 3816, debouncing elements 3820 and 3826, a solution controller 3830, a signal controller 3836, a signal controller 3840, and a driver 3850. , Clamp unit 3860, reference voltage generator 3870, and threshold duration generator 3876.

In one embodiment, the reference voltage generator 3870 receives the voltage signal 3316 and generates a reference voltage 3490 (eg, V _ref1 ) and a reference voltage 3590 (eg, V _ref2 ) based at least in part on the voltage signal 3316. For example, the reference voltage 3490 (for example, V _ref1 ) and the reference voltage 3590 (for example, V _ref2 ) are determined according to the following equations: V _{ref 1} = V _{ref_ini} + α × V _in (Equation 2)

V _{ref 2} = V _{ref_ini} + β × V _in (Equation 3)

Among them, V _ref1 represents the reference voltage 3490, and V _ref2 represents the reference voltage 3590. In addition, V _in represents a voltage signal 3316. V _{ref_ini} represents a predetermined voltage magnitude. In addition, α represents a predetermined constant, and β represents another predetermined constant.

In another example, the reference voltage 3490 (eg, V _ref1 ) is greater than the reference voltage 3590 (eg, V _ref2 ). In another example, the predetermined constant α in Equation 2 is greater than zero, the predetermined constant β in Equation 3 is greater than zero, and the predetermined constant α in Equation 2 is greater than the predetermined constant β in Equation 3. In yet another example, the reference voltage 3490 (eg, V _ref1 ) increases linearly with the voltage signal 3316 (eg, V _in ), and the reference voltage 3590 (eg, V _ref2 ) increases with the voltage signal 3316 (eg, V _in ) Increases linearly.

In another embodiment, the duration of the threshold voltage generator 3876 receives signal 3316, and 3316 at least in part generated based on the voltage signal representing a threshold time period T _th1 and the signal 3874 represents the threshold time period T _th2 signal 3878. For example, the threshold duration Tth1 and the threshold duration T _th2 are respectively determined according to the following equations: T _{th 1} = T _{th_ini} + γ × V _in (Equation 4)

T _{th 2} = T _{th_ini} + δ × V _in (Equation 5)

T _th1 represents the threshold duration Tth1, and Tth2 represents the threshold duration T _th2 . In addition, V _in represents a voltage signal 3316. T _{th_ini} represents a predetermined voltage magnitude. In addition, γ represents a predetermined constant, and δ represents another predetermined constant. In another example, Tth2 threshold duration longer than the duration threshold value T _th1. In yet another example, the reference voltage 3590 (eg, V _ref2 ) is less than the reference voltage 3490 (eg, V _ref1 ), and the threshold duration T _{th2 is} longer than the threshold duration T _th1 .

In yet another example, the predetermined constant γ in Equation 4 is greater than zero, the predetermined constant δ in Equation 5 is greater than zero, and the predetermined constant γ in Equation 4 is less than the predetermined constant δ in Equation 5. In yet another example, the threshold duration T _th1 increases linearly with the voltage signal 3316 (eg, V _in ), and the threshold duration T _th2 increases linearly with the voltage signal 3316 (eg, V _in ).

According to one embodiment, the comparator 3810 receives a voltage signal 3362 and a reference voltage 3590 (eg, V _ref2 ), and generates a comparison signal 3812. For example, if the voltage signal 3362 becomes greater than the reference voltage 3590 (eg, V _ref2 ), the comparison signal 3812 changes from a logic low level to a logic high level. In another example, the comparison signal 3812 is received by a debouncer element 3820. According to another embodiment, the debouncer element 3820 receives a comparison signal 3812 and a signal 3878 representing a threshold time period _Tth2 . For example, the debounce element 3820 determines whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _th2 ) for a duration equal to or longer than the threshold duration T _th2 (eg, whether the comparison signal 3812 remains at a logic high level). In another example, the debounce element 3820 generates a signal 3822 that indicates whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or longer than the threshold duration T _th2 (eg, a comparison signal 3812 remains at a logic high level).

According to another embodiment, the comparator 3816 receives the voltage signal 3362 and a reference voltage 3490 (eg, V _ref1 ), and generates a comparison signal 3818. For example, if the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V _ref1 ), the comparison signal 3818 changes from a logic low level to a logic high level. In another example, the comparison signal 3818 is received by a debounce element 3826. According to another embodiment, the debouncer element 3826 receives the comparison signal 3818 and a signal 3874 representing a threshold time period T _th1 . For example, the debounce element 3826 determines whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V _ref1 ) for a duration equal to or longer than the threshold duration T _th1 (eg, whether the comparison signal 3818 remains at a logic high level). In another example, the debounce element 3826 generates a signal 3828 that indicates whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V _ref1 ) (eg, a comparison signal) for a duration equal to or longer than the threshold duration T _th1 . 3818 remains at a logic high level).

In another embodiment, the connection plan controller 3830 receives the signals 3822 and 3828 and, in response, generates a signal 3832 indicating whether the connection plan is a fast connection plan or a slow connection plan. For example, if the signal 3822 indicates that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or longer than the threshold duration T _th2 , and / or the signal 3828 indicates that the voltage signal 3362 is equal to or longer than the threshold duration The duration of Tth1 remains greater than the reference voltage 3490 (for example, V _ref1 ), then the connection plan controller 3830 determines that the connection plan is a fast-on plan and generates a signal 3832 indicating that the connection plan is a fast-on plan. In another example, if the signal 3822 does not indicate that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V _ref2 ) for a duration equal to or longer than the threshold duration T _th2 , and the signal 3828 does not indicate that the voltage signal 3362 is equal to or The duration longer than the threshold duration Tth1 remains greater than the reference voltage 3490 (for example, V _ref1 ), then the connection scheme controller 3830 determines that the connection scheme is a slow connection scheme and generates a signal indicating that the connection scheme is a slow connection scheme 3832.

In another example, as shown in FIG. 16, if at least one of the condition P or the condition Q is satisfied, the connection plan controller 3830 determines that the connection plan is a quick connection plan, and generates an indication that the connection is on. The scheme is the signal 3832 of the quick-connect scheme. In another example, as shown in FIG. 16, if neither the condition P nor the condition Q is satisfied, the connection plan controller 3830 determines that the connection plan is a slow connection plan, and generates an indication that the connection plan is a slow connection.通 programme signal 3832.

According to some embodiments, the on-signal controller receives a signal 3832 and a voltage signal 3362 and generates a signal 3838. In one embodiment, if the signal 3832 indicates that the turn-on scheme is a fast turn-on scheme, the turn-on signal controller is turned on when the turn-on signal controller senses that the voltage signal 3362 has become less than a threshold voltage (eg, V _th ). The signal 3838 is output without delay. If the signal 3838 is received by the driver 3850, the driver 3850 instructs the driver 3850 to generate a driving signal 3366 that turns on the transistor 3310 (for example, a MOSFET). For example, the driver 3850 receives the signal 3838 and, in response, generates a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830. For example, if the signal 3838 is received by the driver 3850, the driver 3850 instructs the driver 3850 to generate a driving signal 3366 for turning on the transistor 3310 (for example, a MOSFET), and in response, the switching scheme controller 3830 switches the switching scheme from the quick switching on. The scheme becomes a slow-on scheme, and a signal 3832 indicating that the on-scheme is a slow-on scheme is generated.

In yet another embodiment, if the signal 3832 indicates that the turn-on scheme is a fast turn-on scheme, when the turn-on signal controller does not sense that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ), the turn-on signal The controller does not output a signal 3838. If the signal 3838 is received by the driver 3850, it will instruct the driver 3850 to generate a driving signal 3366 that turns on the lens sense 3310 (for example, a MOSFET). For example, the driver 3850 receives the signal 3838 and, in response, does not generate a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830. For example, when the signal 3838 is received by the driver 3850, the driver 3850 does not instruct the driver 3850 to generate a driving signal 3366 for turning on the transistor 3310 (for example, a MOSFET), and in response, the switching scheme controller 3830 keeps the switching scheme as a fast connection. And the signal 3832 is generated to indicate that the connection scheme is a fast connection scheme.

In yet another embodiment, if the signal 3832 indicates that the on scheme is a slow on scheme, when the on signal controller senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ) and senses the voltage signal If 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), the on-signal controller outputs a signal 3838, and the signal 3838 instructs the driver 3850 to generate an on-transistor 3310 (for example, MOSFET) driving signal 3366. For example, the driver 3850 receives the signal 3838 and, in response, generates a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830, and in response, the keep-on scheme is a slow-on scheme and a signal 3832 is generated indicating that the on-scheme is a slow-on scheme.

In yet another embodiment, if the signal 3832 indicates that the turn-on scheme is a slow-on scheme, when the on-signal controller does not sense that the voltage signal 3362 becomes less than a threshold voltage (eg, V _th ) or does not sense it The voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), then the on-signal controller does not output a signal 3838, and the signal 3838 instructs the driver 3850 to generate a switching transistor 3310 when it is received by the driver 3850 (Eg, MOSFET) drive signal 3366. For example, the driver 3850 receives the signal 3838 and, in response, does not generate a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another example, the signal 3838 is received by the connection plan controller 3830. In response, the connection plan controller 3830 maintains the connection plan as a slow connection plan and generates a signal 3832 that the connection plan is a slow connection plan.

In yet another embodiment, the clamper 3860 receives the voltage signal 3362. For example, the voltage signal 3362 includes one or more high-voltage glitches. In another example, a clamp is used to clamp the element voltage signal 3362 to protect one or more internal circuits of the secondary-side synchronous rectifier (SR) controller 3308.

Certain embodiments of the present invention provide such a secondary-side synchronous rectifier (SR) controller that selects a fast-on scheme or a slow-on scheme in order to provide a desired compromise between efficiency and reliability.

According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration, and is responsive to the input The incoming signal is not determined to be greater than a first threshold within a first period of time equal to or longer than a first predetermined duration, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine that the input signal remains less than the second threshold for a second period equal to or longer than the second predetermined duration, and in response to the input signal is equal to or longer than the second threshold The second duration of the predetermined duration is kept smaller than the second threshold, and the driving signal at the second controller terminal is changed from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the system controller is implemented according to at least FIG. 13 and / or FIG. 14.

According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains less than or equal to a first threshold value and greater than a second threshold value within a first period of time equal to or longer than the first predetermined duration, the second threshold value is less than the first threshold value, and responds When the input signal is not determined to remain equal to or smaller than the first threshold and greater than the second threshold within a first period equal to or longer than the first predetermined duration, the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a second period equal to or longer than the second predetermined duration, and in response to the input signal being determined to be equal to Alternatively, the driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a second period longer than the second predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the system controller is implemented according to at least FIG. 13 and / or FIG. 15.

According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second Secondary winding related Associated current. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is equal to or longer than a second predetermined duration It remains greater than the second threshold during the period. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a third period equal to or longer than a third predetermined duration, and in response to the input signal being determined to be equal to Alternatively, the driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a third period longer than the third predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero. For example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is equal to or longer than a second predetermined duration It remains greater than the second threshold during the period. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold changes in size with the input signal, and the second threshold is large Xiao Shang changes with the input signal, for example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is for a second period equal to or longer than the second duration Is kept greater than the second threshold. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in size with the input signal, and the second predetermined duration changes in size with the input signal. For example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than the first predetermined duration; in response to the input signal not being determined to be equal to or longer than the first predetermined duration The first period of time remains greater than the first threshold, and the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than Remain less than a second threshold for a second period of a second predetermined duration; and in response to an input signal It is determined to remain less than a second threshold for a second period of time equal to or longer than the second predetermined duration to change the driving signal from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the method is implemented according to at least FIG. 13 and / or FIG. 14.

According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains less than or equal to a first threshold and greater than a second threshold for a first period of time equal to or longer than a first predetermined duration, and the second threshold is less than the first threshold; and In response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than The driving signal is kept from the first threshold in the second period of the second predetermined duration to be less than the third threshold; and in response to the input signal being determined to remain less than the third threshold in the second period equal to or longer than the second predetermined duration The logic level becomes the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the method is implemented according to at least FIG. 13 and / or FIG. 15.

According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Is maintained greater than the second threshold, the second threshold is smaller than the first threshold, the second predetermined duration is longer than the first predetermined duration; and in response to the input signal not being determined to be in a first period equal to or longer than the first predetermined duration The internal retention is greater than the first threshold and the input signal is not determined to remain greater than the second threshold for a second period that is equal to or longer than the second predetermined duration, and is operated using the first scheme. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than The driving signal is kept from the first threshold in the third period of the third predetermined duration to be less than the third threshold; and in response to the input signal being determined to remain less than the third threshold in the third period of time equal to or longer than the third predetermined duration The logic level becomes the second logic level. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Within the first threshold; in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second predetermined duration The second period of time remains greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold changes in size with the input signal, and the second threshold changes in size with the input signal. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing information associated with the input signal includes: determining if the input signal is waiting Remains greater than the first threshold for a first period of time that is longer than or longer than the first predetermined duration; determines that the input signal remains greater than the second threshold for a second period that is equal to or longer than the second predetermined duration; in response to the input signal not being determined as The first scheme is used to keep greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, using the first scheme Do it. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first predetermined duration changes in size with the input signal, and the second predetermined duration changes in size with the input signal. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

For example, some or all of the elements of the various embodiments of the present invention are each individually and individually using one or more software elements, one or more hardware elements, and / or one or more combinations of software and hardware elements. And / or implemented in combination with at least one other component. In another example, some or all of the elements of the various embodiments of the present invention are each implemented individually and / or in combination with at least one other element in one or more circuits, such as One or more analog circuits and / or one or more digital circuits. In yet another example, various embodiments and / or examples of the invention can be combined.

Although specific embodiments of the invention have been described, those skilled in the art will understand that there are other embodiments equivalent to the described embodiments. Therefore, it should be understood that the present invention is not limited by the specifically illustrated embodiments, but is limited only by the scope of the appended patent applications.

Claims (79)

A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and in response to the input signal being not It is determined to remain greater than the first threshold within the first period of time equal to or longer than the first predetermined duration, and the operation is performed using a first scheme; wherein the operation is performed using the first scheme, and the system controls The controller is further configured to determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; in response to The input signal is determined to remain less than the second threshold for the second period equal to or longer than the second predetermined duration, and the drive signal at the second controller terminal is removed from the first logic The level becomes a second logical level; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. The system controller according to item 1 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration For a period of time that remains greater than the first threshold and operates using the second scheme; and operating with the second scheme, the system controller is further configured to determine whether the input signal becomes less than the first scheme Two thresholds; and in response to the input signal being determined to become smaller than the second threshold, changing the drive signal at the second controller terminal from the first logic level to the second A logic level regardless of whether the input signal remains less than the second threshold during the second period equal to or longer than the second predetermined duration. The system controller according to item 2 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the second threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the second threshold in the second period equal to or longer than the second predetermined duration After that, the first scheme is used for operation. The system controller according to item 2 of the patent application scope, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The system controller according to item 1 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. The system controller according to item 1 of the patent application scope, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. The system controller according to item 1 of the scope of patent application, wherein the second threshold value is smaller than the first threshold value. A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to determine whether the input signal remains less than or equal to a first threshold and greater than a second threshold within a first period of time equal to or longer than a first predetermined duration, the A second threshold value is less than the first threshold value; and in response to the input signal not being determined to remain less than or equal to the first threshold value and greater than the first time period equal to or longer than the first predetermined duration The second threshold is operated using the first scheme; wherein, the system controller is further configured to determine the output using the first scheme to operate. Whether an incoming signal remains less than a third threshold for a second period equal to or longer than a second predetermined duration; in response to the input signal being determined to be within the second period equal to or longer than the second predetermined duration Keeping it less than the third threshold, changing the driving signal at the second controller terminal from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; and all The second predetermined duration is greater than zero. The system controller according to item 8 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration For a period of time remaining less than or equal to the first threshold value and greater than the second threshold value, and operating with a second scheme; and operating with the second scheme, the system controller is further configured to determine the Whether the input signal becomes smaller than the third threshold; and in response to the input signal being determined to become smaller than the third threshold, the driving signal at the second controller terminal is removed from the first The logic level becomes the second logic level regardless of whether the input signal remains less than the third threshold for the second period of time equal to or longer than the second predetermined duration. The system controller according to item 9 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the third threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the third threshold in the second period equal to or longer than the second predetermined duration After that, the first scheme is used for operation. The system controller according to item 9 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The system controller according to item 8 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. The system controller according to item 8 of the scope of patent application, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. The system controller according to item 8 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold within a second period longer than a second predetermined duration, the second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration; wherein, the The system controller is further configured in response to the input signal not being determined to be within the first period of time equal to or longer than the first predetermined duration. Remain greater than the first threshold, and the input signal is not determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and operate using the first scheme; Wherein, using the first scheme for operation, the system controller is further configured to: determine whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration; and responding to The input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, and the drive signal at the second controller terminal is removed from the first logic The level becomes a second logical level; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; and the third predetermined duration is greater than zero. The system controller according to item 15 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform And operating with the second scheme, the system controller is further configured to: determine whether the input signal becomes less than the third threshold; and determine that the input signal becomes less than in response to the input signal The third threshold value changes the driving signal at the second controller terminal from the first logic level to the second logic level, regardless of whether the input signal is equal to or longer than the input signal Whether the third predetermined period of time remains smaller than the third threshold. The system controller according to item 16 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. The system controller according to item 16 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the third threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the third threshold in the third period equal to or longer than the third predetermined duration After that, the first scheme is used for operation. The system controller according to item 16 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The system controller according to item 15 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. The system controller according to item 15 of the scope of patent application, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. The system controller according to item 15 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold for a second period longer than a second predetermined duration; wherein the system controller is further configured to: in response to the input signal not being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period of time, and the input signal is not determined to be equal to or longer than the second predetermined duration Within the second period of time remaining greater than the second threshold, using the first scheme to operate; wherein: the second threshold is smaller than the first threshold; and the second predetermined duration is longer than the first A predetermined duration; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero; wherein: the first threshold value changes in amplitude with the input signal; the second threshold value Changes in amplitude with the input signal. The system controller according to item 23 of the patent application scope, wherein: the first threshold value increases with the input signal in amplitude; and the second threshold value increases with the input signal in amplitude . The system controller according to claim 24, wherein: the first threshold increases linearly with the input signal in amplitude; and the second threshold linearly increases with the input signal in amplitude Increase. The system controller according to item 23 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform Operation; and the second scheme is different from the first scheme. The system controller according to item 26 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. The system controller as described in claim 26, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The system controller according to item 23 of the scope of patent application, wherein: using the first scheme for operation, the system controller is further configured to determine that the input signal is equal to or longer than a third predetermined duration Whether it remains less than a third threshold within a third period, the third predetermined duration is greater than zero; and in response to the input signal being determined to remain less than the third period equal to or longer than the third duration The third threshold changes the driving signal at the second controller terminal from a first logic level to a second logic level. The system controller according to item 29 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. The system controller of claim 29, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. The system controller according to item 23 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold for a second period longer than a second predetermined duration; wherein the system controller is further configured to: in response to the input signal not being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period of time, and the input signal is not determined to be equal to or longer than the second predetermined duration The second period of time remains larger than the second threshold, and the first scheme is used for operation; wherein: the second threshold is smaller than the first threshold; and the second predetermined duration is longer than the first A predetermined duration; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; the first predetermined duration changes in amplitude with the input signal; and the second predetermined duration The duration varies in magnitude with the input signal. The system controller according to item 33 of the scope of patent application, wherein: the first predetermined duration increases in amplitude with the input signal; and the second predetermined duration increases in amplitude with the input signal The input signal increases. The system controller according to item 34 of the patent application scope, wherein: the first predetermined duration increases linearly with the input signal in amplitude; and the second predetermined duration increases in amplitude with the The input signal increases linearly. The system controller according to item 33 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform Operation; and the second scheme is different from the first scheme. The system controller of claim 36, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. The system controller according to claim 36, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The system controller according to item 33 of the scope of patent application, wherein: using the first scheme for operation, the system controller is further configured to determine that the input signal is equal to or longer than a third predetermined duration Whether it remains less than a third threshold within a third period, the third predetermined duration is greater than zero; and in response to the input signal being determined to remain less than the third period equal to or longer than the third duration The third threshold changes the driving signal at the second controller terminal from a first logic level to a second logic level. The system controller according to item 39 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. The system controller according to claim 39, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. The system controller according to item 33 of the patent application scope, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; and in response to the input signal not being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, operate using a first scheme Generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes: responding to operation using the first scheme To determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; And in response to the input signal being determined to remain less than the second threshold for the second period equal to or longer than the second predetermined duration, the driving signal is changed from a first logic level to a Two logic levels; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. The method of claim 43, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to be equal to or greater than the first predetermined duration Remain greater than the first threshold for the first period of time, and operate using the second scheme; generating a drive signal based at least in part on the input signal to turn on or off the transistor to affect the secondary connection with the power converter The winding-associated current further includes: determining whether the input signal becomes smaller than the second threshold in response to operating with the second scheme; and in response to the input signal being determined to become smaller than the first threshold Two thresholds to change the driving signal from the first logic level to the second logic level, regardless of whether the input signal is within the second period equal to or longer than the second predetermined duration Whether to keep it smaller than the second threshold. The method of claim 44, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to become less than the second threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the second within the second period equal to or longer than the second predetermined duration After the threshold, the first scheme is used for operation. The method according to item 44 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The method of claim 43, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. The method of claim 43, wherein the second threshold is smaller than the first threshold. A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain less than or equal to a first threshold value and greater than a second threshold value, the second threshold value being less than the first threshold value; and in response to the input signal not being determined to be equal to or longer than the first predetermined duration The first period of time remains less than or equal to the first threshold value and is greater than the second threshold value, and is operated using the first scheme; wherein a driving signal is generated based at least in part on the input signal to turn on or off the transistor Thus affecting the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining Whether the input signal remains less than a third threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal being determined to be at the second equal to or longer than the second predetermined duration Staying less than the third threshold for a period of time, changing the driving signal from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. The method of claim 49, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remain within the first period less than or equal to the first threshold and greater than the second threshold, and operate using a second scheme; wherein a driving signal is generated based at least in part on the input signal to turn the transistor on or off Thus affecting the current associated with the secondary winding of the power converter further includes: determining whether the input signal becomes less than the third threshold in response to operating with the second scheme; and responding to the The input signal is determined to become smaller than the third threshold, and the driving signal is changed from the first logic level to the second logic level, regardless of whether the input signal is equal to or longer than the first logic level. Whether the second predetermined period of time remains smaller than the third threshold. The method of claim 50, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to become less than the third threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the third within the second period equal to or longer than the second predetermined duration After the threshold, the first scheme is used for operation. The method of claim 50, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The method of claim 49, further comprising: in response to changing the driving signal from the first logic level to the second logic level, turning on the transistor. The method of claim 49, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration, the second threshold being less than the first threshold, and the second predetermined The duration is longer than the first predetermined duration; and in response to the input signal not being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, and The input signal is not determined to remain greater than the second threshold for the second period that is equal to or longer than the second predetermined duration Use the first scheme to operate; wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect the current associated with the secondary winding of the power converter includes: The first solution is operated to determine whether the input signal remains less than a third threshold for a third period equal to or longer than a third predetermined duration; and in response to the input signal being determined to be equal to or longer than the first threshold The third period of three predetermined durations is kept smaller than the third threshold, and the driving signal is changed from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; The second predetermined duration is greater than zero; and the third predetermined duration is greater than zero. The method of claim 55, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or greater than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution Performing an operation; generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter further includes: responding to using the second scheme Performing an operation to determine whether the input signal becomes less than the third threshold; and in response to the input signal being determined to become less than the third threshold, driving the drive signal from the first logic level Becomes the second logic level regardless of whether the input signal remains smaller than the third period in the third period equal to or longer than the third predetermined duration Value. The method of claim 56, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or greater than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using a second solution. The method of claim 56, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to become less than the third threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the third period in the third period equal to or longer than the third predetermined duration After the threshold, the first scheme is used for operation. The method according to item 56 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The method of claim 55, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. The method of claim 55, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal not being determined to be equal to or longer than the The first predetermined duration is maintained greater than the first threshold for the first time period, and the input signal is not determined to remain greater than the first time period for the second time period that is equal to or longer than the second predetermined time duration. The second threshold is operated by using the first scheme; wherein: the second threshold is smaller than the first threshold; and the second predetermined The duration is longer than the first predetermined duration; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero; wherein: the first threshold value follows the input signal in amplitude And the second threshold changes in amplitude with the input signal. The method of claim 62, wherein: the first threshold value increases with the input signal in amplitude; and the second threshold value increases with the input signal in amplitude. The method of claim 63, wherein: the first threshold increases linearly with the input signal in amplitude; and the second threshold increases linearly with the input signal in amplitude . The method of claim 62, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution And the second scheme is different from the first scheme. The method of claim 65, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using the second scheme. The method of claim 65, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The method of claim 62, wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes : In response to operating with the first scheme, determining whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration, the third predetermined duration being greater than zero; and responding After the input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, the driving signal is changed from a first logic level to a second logic bit quasi. The method of claim 68, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. The method of claim 68, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal not being determined to be equal to or longer than the The first predetermined duration is maintained greater than the first threshold for the first time period, and the input signal is not determined to remain greater than the first time period for the second time period that is equal to or longer than the second predetermined time duration. The second threshold is operated by using the first scheme; wherein: the second threshold is smaller than the first threshold; and the second predetermined The duration is longer than the first predetermined duration; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; the first predetermined duration changes in amplitude with the input signal ; And the second predetermined duration changes in amplitude with the input signal. The method of claim 71, wherein: the first predetermined duration increases with the input signal in amplitude; and the second predetermined duration increases with the input signal in amplitude Increase. The method of claim 72, wherein: the first predetermined duration increases linearly with the input signal in amplitude; and the second predetermined duration increases in amplitude with the input The signal increases linearly. The method of claim 71, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution And the second scheme is different from the first scheme. The method of claim 74, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using the second scheme. The method of claim 74, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. The method of claim 71, wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes : In response to operating with the first scheme, determining whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration, the third predetermined duration being greater than zero; and responding After the input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, the driving signal is changed from a first logic level to a second logic bit quasi. The method of claim 77, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. The method of claim 77, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold.