TWI642119B - Semiconductor device and method of forming the same - Google Patents

Abstract

A method and apparatus for attaching a first substrate to a second substrate are provided. In some embodiments, the first substrate has a protective layer, such as a solder mask, surrounding a die attach area to which the second substrate is attached. A keep-out region (eg, a region between the second substrate and the protective layer) is a region surrounding the second substrate on which the protective layer is not formed or removed. The size of the exclusion region is such that there is sufficient spacing between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or avoiding voids, and at the same time allowing the wires in the exclusion region to be excluded Covered by bottom filling.

Description

Semiconductor device and method of forming same

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of forming the same, and more particularly to a bump-on-line wafer package device and a method of forming the same.

Integrated circuits or wafers consist of a large number of active and passive components such as transistors and capacitors. These components are initially isolated from each other and then interconnected to form an integrated circuit. The connector structure is further formed for use in an integrated circuit that may include bond pads or metal bumps formed on the surface of the circuit. Electrical connections are made via bond pads or metal bumps that connect the wafer to the package substrate or other die. In general, wafer bonding can be assembled into a package such as a pin grid array (PGA) or a ball grid using wire bonding (WB) or flip chip (FC) packaging techniques. Ball grid array (BGA).

A flip-chip (FC) package technology utilizes a bump-on-trace (BOT) structure to connect a wafer to a package substrate, wherein the connection to the package substrate or crystal is via a metal bump connection Metal traces of particles. The low cost provided by the BOT structure can replace the microelectronic packaging industry. However, as the substrate structure becomes thinner, the reliability problem of the BOT structure rises.

When the BOT structure is utilized, the bumps for the wafer are soldered to the wires on the package substrate by a reflow process. When the bump is bonded to the substrate and cooled to the chamber from the reflow state At warmer temperatures, the thermal force caused by the coefficient of thermal expansion (CTE) mismatch causes the substrate to shrinkage and cause relative torsion on each bump. Once the stress level rises above the adhesion standard between the substrate and the wire, a trace peeling failure occurs.

In an embodiment, a semiconductor device is provided. The device includes a first substrate having a wire formed thereon. The first substrate has a die attaching region, the exclusion region surrounds the periphery of the die attach region, and a surrounding region surrounds the periphery of the exclusion region. The first substrate has a wire overlying the surrounding area of the protective layer. The second substrate is electrically coupled to the first substrate in the die attach region; and the bottom filler is sandwiched between the first substrate and the second substrate, and the bottom filler extends over the wires in the exclusion region; The area of the exclusion zone accounts for about 5% to about 18% of the area of the second substrate.

In another embodiment, a semiconductor device is provided. The device includes a first substrate having a die attach region, a surrounding region and a exclusion region interposed between the die attach region and the surrounding region, wherein the protective layer covers the wires in the surrounding region, and wherein the protective layer does not extend into the crystal Grain attachment area and exclusion area. The second substrate is electrically coupled to the first substrate such that the second substrate is located above the die attach region of the first substrate. The die attach region corresponds to a region where the first substrate is directly under the second substrate, and the exclusion region extends from the boundary of the protective layer to the boundary of the die attach region. The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.

In still another embodiment, a method of forming a semiconductor device is provided, the method comprising providing a first substrate having a wire formed thereon and forming a protective layer over a portion of the first substrate. The second substrate is attached to the first substrate. exclude The region extends between the boundary of the protective layer and the periphery of the second substrate, wherein the area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.

201‧‧‧ wafer

202‧‧‧Cullar bump or post, copper pillar, pillar

203‧‧‧ solder balls, solder bumps

204‧‧‧Wire (trace)

205‧‧‧Encapsulation body

206‧‧‧Substrate

207‧‧‧ ball

210‧‧‧welding groove

211‧‧‧welding cover, welding cover

220‧‧‧Steps

221‧‧‧Steps

223‧‧ steps

227‧‧‧Steps

231‧‧‧Steps

233‧‧ steps

235‧‧ steps

301‧‧‧Area

311‧‧‧welding groove

2021‧‧‧ Pillars or interconnections

2022‧‧‧ pillars or interconnections

402‧‧‧First substrate

404‧‧‧Wire

404a‧‧‧End of wire

406‧‧‧Protective layer

408‧‧‧ die attach area

520‧‧‧second substrate

522‧‧‧Electrical connector

522a‧‧‧conductive column

522b‧‧‧Welding materials

524‧‧‧Keep-out-region (KOR)

650‧‧‧Bottom filling

702‧‧‧Steps

704‧‧‧Steps

706‧‧‧Steps

708‧‧ steps

B-B‧‧‧ cut line

L ₁ ‧‧‧ length

W ₁ ‧‧‧Width

D1‧‧‧Keep-out distance (KOD)

The embodiments of the present invention can be best understood from the following detailed description and appended claims. It is emphasized that, in accordance with standard practice practices in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion.

Figure 1 illustrates one embodiment of a wafer on a bump-on-trace (BOT) structure to form a flip-chip (FC) package.

2a-c illustrate one embodiment of a method and apparatus for a solder mask trench for use in a BOT structure to form an FC package.

Figure 3 illustrates a top view of a plurality of bumps connected to the wires in a plurality of solder mask trenches used in the BOT structure.

4a-6b illustrate various planes and cross-sectional views of an intermediate process step in accordance with some embodiments.

Figure 7 is a flow diagram of a method of fabrication in accordance with some embodiments.

It should be understood that the following disclosure provides various embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are just examples and are not intended to be limiting. For example, a description in which one of the following first features is formed on a second feature may include an embodiment The first and second features are formed in direct contact, and other features may be included between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may use repeated reference symbols and/or words in the various examples. These repeated symbols or words are not intended to limit the relationship between the various embodiments and/or the structures.

In addition, spatial relative terms, such as "lower", "lower", "upper", etc., are used to describe the relative relationship of an element or feature to other elements or features in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device can be otherwise positioned (e.g., rotated 90 degrees or other orientation), and the spatially relative descriptions used herein can also be interpreted accordingly.

The following description will disclose a method and apparatus for a solder mask trench for use in a BOT structure to form a semiconductor package. A solder mask layer is formed on the wires and on the substrate. An opening is formed into the solder mask layer called the solder mask trench to expose the wires on the substrate. The wafer is connected to the exposed conductors in the solder mask trench. As the shroud trench is formed, the wires exposed in the trench can have better grip, which can reduce semiconductor package wire peeling failure.

1 is a schematic diagram showing a wafer 201 on a bump-on-trace (BOT) structure to form a flip-chip (FC) package, according to an embodiment. Substrate 206 can have a plurality of sub-layers. The two sub-layers of substrate 206 shown in Figure 1 are for illustrative purposes only and are not limiting. A plurality of balls 207 located below the substrate 206 may form a ball grid array (BGA). The wafer 201 is connected to the substrate 206 by a plurality of interconnects, each of which includes a copper pillar bump or post 202 and solder balls 203. Solder balls 203 are placed on wires 204, and wires 204 are formed on the base On board 206. The solder mask 211 is formed on the surface of the substrate 206 to cover the wires. An opening of a solder mask called a solder mask trench is formed to expose the wire 204. The space between the wafer 201 and the substrate 206 can be filled with a compound to form an encapsulation body 205.

2a is a single solder mask trench 210 on substrate 206, which may be one of the trenches exposed in FIG. 1 and connected to wafer 201, in accordance with an embodiment. A wire 204 is formed on the surface of the substrate 206. The solder mask layer 211 may be formed on the wire to cover the surface of the wire and the substrate 206. The trench may form an opening in the solder mask layer 211 to form the solder mask trench 210 exposing the wire 204. The trench has a sufficiently large opening such that the interconnect, such as solder ball 203, can land directly on the wire in the opening. For example, the shroud trench has a size that is approximately the diameter of the solder bump. Wires 204 can be connected to wafer 201 by interconnection. The interconnect may include solder bumps 203 and posts such as copper pillars 202, wherein solder balls 203 are placed directly on conductors 204 and surrounded by solder mask trenches. The structure shown in Figure 2a is for illustrative purposes only and is not limiting. Additional embodiments are contemplated.

Figure 2b depicts a top view of post 202 on wire 204, which is surrounded by solder mask 211. The wafer 201 and the substrate 206 are not shown in FIG. 2b.

Figure 2c depicts an exemplary manufacturing process of the embodiment shown in Figure 2a. The details of the process shown in Figure 2c are set forth below.

The process begins in step 220 by providing a substrate such as substrate 206 in Figure 2a. The substrate 206 can provide a mechanical support for the package and an interface that allows external components to enter the device within the package. The substrate 206 may comprise a bulk silicon substrate, a doped or undoped substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Other substrates may include a multilayer substrate, a gradient substrate, or a hybrid orientation substrate. The substrate 206 may further be a laminate substrate formed by stacking a plurality of thin layers of a polymer material. And a polymer material such as bismaleimide triazine, or the like.

Wires 204 can be located on the surface of substrate 206. Wire 204 can be used to expand the footprint of the die. The width or diameter of the wire may be approximately the same as the diameter of the ball (or bump), or may be as narrow as two to four times the diameter of the ball (or bump). For example, wire 204 can have a line width between about 10 micrometers (μm) and 40 micrometers (μm), and a wire spacing P between about 30 micrometers (μm) and 70 micrometers (μm). The wires can be narrow, wide or tapered. The ends of the wires may be of different shapes than the bodies of the wires. The wire body can be of substantially constant thickness. The end of the wire is formed integrally with the body of the wire, which is different from placing the pad on the wire. The wire may have a length that is longer than the diameter of the ball (or bump). Alternatively, the attachment pad can have a length or width that is similar to the diameter of the ball or bump.

There may be multiple wires on the substrate, each wire being electrically insulated from the other wire, and the space between the two wires may be between 10 microns and 40 microns.

For example, the wire 204 can comprise a conductive material such as aluminum (Al), copper (Cu), gold (Au), alloys thereof, other materials, or combinations thereof, and/or multilayers thereof. Alternatively, wire 204 can comprise other materials. In some embodiments, the dielectric layer can cover portions of the wire 204. The wire 204 may be covered by a metal finish coated on the wire 204, such as an organic film layer or a mixed material layer such as nickel (Ni) / palladium (Pd) / gold (Au).

The wire 204 and the substrate are attached by only the interface therebetween, which may not have sufficient grip force, and thus a strong bond cannot be formed between the wire 204 and the substrate 206.

In step 221, the solder mask layer is as shown in FIG. 2a, which can be formed on the surface of the substrate 206 to cover the surface of the wire 204 and the substrate. The solder mask layer 211 can perform several functions, including providing electrical insulation resistance between the wires on the substrate (electrical insulation) Resistance), chemical and corrosion resistance or protection, mechanical (scraping, grinding) protection, boundary on the solder surface, additional grip on the wire, and improved dielectric reliability. The shroud layer provides additional grip between the wire 204 and the substrate 206 because the shroud, wire, and substrate form a sandwich structure in which the shroud and the substrate "snap" the wire.

The solder mask layer 211 can be formed in a single step by screening a wet film on the surface of the substrate and then curing the wet film by oven baking. The thickness of the solder mask layer 211 can be from about 30 to 40 microns (typically about 35 microns). The solder mask layer may comprise a polymer material.

At step 223, the trench may form an opening in the solder mask layer 211 to form the solder mask trench 210 exposing the trace 204, as shown in FIG. 2a. The trench has a sufficiently large opening such that the interconnect, such as solder ball 203, can land directly on the wire in the opening. The wider opening of the solder ball can increase the strength of the connection between the solder ball and the wire. Thus the size of the opening is resilient and can vary with the size of the solder balls used to connect to the wires. The solder mask layer 211 formed by the wet film can be screen printed according to a pattern to form the solder mask trench 210. For example, a solder mask layer having a solder mask trench can be placed on the roller to be printed on the substrate. Alternatively, a photosensitive material can be used to pattern the solder mask trench to cure the film. The shroud trench 210 can be formed to expose the wire 204 to further form an appropriate electrical connection with the die that will later be mounted on the substrate.

A solder flux (not shown) can be applied to the wire. Flux is primarily used to aid in the flow of solder, allowing solder balls 203 to have good contact with the wires on the substrate. This can be applied to any changing method, including brushing or spraying. Fluxes typically have an acidic component that removes the oxidative barrier from the solder surface and adhesion quality that helps prevent wafer movement on the substrate during the assembly process.

In step 227, as shown in FIG. 2a, by way of interconnecting the wafers, Wafer 201 can be connected to wire 204. As shown in FIG. 2a, the interconnects can include solder bumps 203 and pillars such as copper pillars 202. The trench has a sufficiently large opening so that the solder ball 203 can land directly on the wire in the opening.

The solder bumps 203 of the wafer 201 can be placed on the wires 204 exposed by the solder mask trenches. Solder bumps 203 may comprise materials such as tin, or other suitable materials such as silver, lead-free tin, copper, combinations thereof, or the like. In one embodiment, the solder bumps 203 are tin solder bumps, and the solder bumps 203 are formed by, for example, evaporation, electroplating, printing, solder transfer. The original tin layer formed by ball transfer or ball placement is to a thickness of about 15 microns and then reflowed to shape the material into the desired bump shape. Any suitable method of making the solder bumps 203 can be used instead.

The wafer 201 as shown in FIG. 2a can be connected to the wire 204 by solder bumps 203 and pillars 202. The pillars 202 may be formed on the wafer 201. The struts 202 can be copper posts or other metals having a melting point above 300 °C. The wafer 201 can be aligned such that the posts 202 are placed onto the solder bumps 203. The wafer can be a memory chip or any other functional wafer.

The pillars 202 and the solder bumps 203 together form an interconnection of the wafers. The pillars 202 and the solder bumps 203 may be formed in a plurality of suitable shapes to avoid nearby components, control the connection area between the wafer 201 and the wires 204, or other suitable Reasons. The shape of the interconnect may be circular, octagonal, rectangular, elongated hexagonal, elliptical, diamond shaped, wherein the elongated hexagon has two trapezoids at opposite ends thereof.

At step 231, a reflow process is performed. As shown in FIG. 2a, after the wafer 201 is bonded to the wire, heat can be applied to the wafer 201 and the substrate 206, causing the solder balls 203 to be reflowed and forming an electrical connection between the wafer 201 and the substrate 206. For an embodiment, the thermal temperature can be up to about 220 °C.

At step 233, the underfill material, typically a thermo-set epoxy, can be dispensed into the space between wafer 201 and substrate 206. A bead of a thermosetting epoxy resin may be applied along one edge of the wafer, wherein the epoxy resin is stretched under the wafer by a capillary action until it is completely filled between the wafer and the substrate The interval. It is important that the underlying filler material is evenly dispersed throughout the space.

A separate bead of epoxy resin may also be dispersed and bonded around the periphery of the wafer 201. Thereafter, the underfill and the peripherally bonded epoxy are cured by heating the substrate and the wafer to a suitable curing temperature to form a package such as the package 205 shown in FIG. The package 205 has been filled with a gap between the wafer 201 and the substrate 206. In this manner, the process produces a mechanical and electrical combination of semiconductor wafer assembly when the process is complete.

FIG. 3 is a plan view showing a substrate of a semiconductor package formed by a BOT structure. The surface of the substrate can be covered by a solder mask in addition to the region 301. The solder mask can also cover the surface of other shaped substrates. A plurality of solder mask trenches 311 may be formed on the solder mask layer. The shroud trench surrounds a central region of the substrate and forms a plurality of shroud trench rings. The shape of the shroud trench is based on the contour of the wire on the substrate, and other shapes may be substituted for the formed shroud ring. Three of the described shroud groove rings are formed in Figure 3, and other numbers of shroud groove rings may be formed. A plurality of struts or interconnects such as 2021 and 2022 can be placed over the wires exposed in the shroud trenches. The distance between the two pillars or the two interconnects can be less than about 140 microns.

In other embodiments, the solder mask is removed from a die-attach area, such as a region where the die or other substrate can be attached, and a keep-out region (eg, closely surrounding the die attach) Area of the area). As described in more detail below, the shroud material will be removed such that the area directly under the die and the tight surrounding area are removed. Welding cover material The size of the removed area is larger than the size of the die. Determining the size of the area in which the shroud material is removed, such that the side regions between the edge of the die and the edge of the shroud allow the underfill material to be applied by completely filling the area between the die and the underlying substrate, leaving no exposure wire.

For example, in some cases, the side area between the edge of the die and the edge of the shroud is too small, and the underfill material may not completely fill the area between the die and the underlying substrate, allowing one or more voids to be formed in the die. Between the substrate and the lower substrate. In other cases, the side areas between the edge of the die and the edge of the weld bead are too large and the wire may still be exposed. It has been found that by controlling the distance between the edge of the die and the edge of the bead, and/or controlling the ratio of the area of the die to the area of the die and the area of the die, the underfill can completely fill the die and the underlying substrate. The area covers the wires, thereby providing protection for the electrical connection between the die and the underlying substrate, as well as for the wires on the underlying substrate.

It is noted that the discussion herein regarding the attachment of the die to the substrate is for illustrative purposes to explain the features of various embodiments. In other embodiments, the die may be another substrate, such as a package, a packaging substrate, an interposer, a die, a printed circuit board, or the like. Things.

4a-6b illustrate various intermediate stages of forming a process in accordance with some embodiments, wherein the "A" diagram is a plan view and the "B" diagram is a cross-sectional view along line B-B of the corresponding "A" diagram. Referring first to Figures 4a and 4b, a plan view of the first substrate 402 and a cross-sectional view taken along line B-B of Figure 4a are shown. The first substrate 402 can be, for example, an integrated circuit die, a package substrate, a wafer, a printed circuit board, an interposer, or the like. In some embodiments, a BOT configuration is used. For example, the wires 404 are depicted in Figures 4a, 4b. In general, wire 404 sends an electrical signal to a desired location and/or an area used to expand the die. The width or diameter of the wire 404 can be approximately the same as the diameter of the ball (or bump), or Up to two to three times narrower than the diameter of the ball (or bump). For example, wire 404 can have a line width between about 10 microns and 40 microns, and a wire pitch P between 30 microns and 70 microns. The wires can be narrow, wide or tapered. In some embodiments, the ends 404a of the wires can be of different shapes than the body of the wires, or the body of the wires can be of substantially constant thickness. The end 404a of the wire is formed integrally with the body of the wire, which is different from placing the pad on the wire. The wire can have a length that is substantially longer than the diameter of the ball (or bump). Alternatively, the attachment pad can have a length or width that is similar to the diameter of the ball or bump.

In some embodiments, for example, wire 404 can comprise a conductive material such as aluminum (Al), copper (Cu), gold (Au), alloys thereof, other materials, or combinations thereof, and/or multilayers thereof. Alternatively, wire 404 can comprise other materials. The wire 404 can be covered by a metal polishing layer coated on the wire 404, such as an organic film layer or a mixed material layer such as nickel (Ni) / palladium (Pd) / gold (Au). In some embodiments, the distance between adjacent wires can be between about 10 microns and 40 microns.

The protective layer 406 is further illustrated in Figures 4a, 4b. In general, the protective layer 406 provides protection from environmental contaminants, electrical insulation resistance between circuit leads on the substrate, chemical and corrosion resistance or protection, mechanical (scraping, grinding) protection, on the solder surface. Additional grip on the boundaries, wires and/or substrate and improved dielectric reliability. In some embodiments, for example, the protective layer 406 is a polymeric or other dielectric material. In some embodiments, for example, the protective layer 406 is a polymer that is formed by screen printing or spin coating, patterning, and subsequent curing.

The protective layer 406 covers portions of the wires 404, such as portions of the wires in the surrounding area of the first substrate 402. For example, Figure 4a depicts an embodiment in which the protective layer 406 is formed around and separated from the die attach region 408 (as shown by the dashed outline shown in Figure 4a). As described in more detail below, the die attach region 408 represents another substrate to be placed One of the areas above. The protective layer 406 protects the protective conductor 404 from external environmental contaminants and is sized to allow the underfill to completely fill the area between the die and the first substrate 402 while also covering the exposed wires 404. The protective layer 406 can have a thickness of from about 30 microns to about 40 microns, such as about 35 microns.

Referring now to Figures 5a, 5b, there are shown some embodiments of the first substrate 402 of Figures 4a, 4b after the second substrate 520 has been attached to the first substrate 402. For example, the second substrate 520 can be a die, a substrate, a wafer, a package substrate, a printed circuit board, or the like. The second substrate 520 is electrically coupled to the first substrate by an electrical connector 522. In some embodiments, the electrical connector 522 includes conductive posts 522a (eg, copper posts) and solder material 552b coupled to each other, although other electrical connectors may be used.

In some embodiments, the first substrate 402 is an integrated circuit die, and the second substrate 520 is a wafer, wherein the bonding substrate is in a flip-chip chip-scale package (FCCSP). The wafers are then singulated to form a separate package. However, other configurations are also possible.

As shown in FIGS. 5a and 5b, a keep-out-region (KOR) 524 is located between the second substrate 520 and the protective layer 406 and extends around the second substrate 520. In some embodiments, the exclusion region 524 includes a region that separates the inner edge of the protective layer 406 from the edge of the second substrate 520 by a keep-out distance (KOD) D ₁ . In some embodiments, the area of the exclusion zone 524 is from about 5% to about 18% of the area of the second substrate 520. For example, the area of the second substrate 520 is multiplied by the width W ₁ of length L _1, the area ratio of the area of the second region 524 of the substrate 520 (e.g., length multiplied by width W ₁ of L ₁₎ between about 1 negative line : 20 to about 9:50. Further, in some embodiments, the exclusion distance D _{1 is} greater than or equal to 420 microns.

It has been found that the use of these indicators (excluding the area of the area 524 and the second substrate The ratio of the area of 520 and the minimum dimension of the exclusion distance), the sufficient distance provided between the edge of the protective layer 406 and the second substrate allows the underfill material to be applied afterwards so that the underfill material will be substantially void free (void -free) and covering the exposed wires in the exclusion area 524. As noted above, a smaller distance may result in a poorer fill capability between the first substrate 402 and the second substrate 520, thereby creating voids, while larger distances may result in exposure of the wires in the exclusion region 524. Maintaining the exclusion distance and exclusion region 524 described above solves these problems, avoids or reduces the occurrence of voids between the first substrate 402 and the second substrate 520, and provides better coverage of the exposed wires in the exclusion region 524.

6a, 6b illustrate a first substrate 402 and a second substrate 520 having a bottom fill 650 interposed therebetween, in accordance with some embodiments. In some embodiments, the underfill 650 comprises a polymer, a thermoset epoxy or the like that is dispensed into the space between the second substrate 520 and the protective layer 406, such as the exclusion region 524. For example, in some embodiments, the underfill material is a high molecular compound having a ceria filler material. The beads of the underfill 650 can be applied along one edge of the wafer, wherein the underfill 650 is stretched under the wafer by capillary action until it is completely filled between the first substrate 402 and the second substrate 520. .

Figure 7 is a flow chart illustrating a manufacturing process in accordance with some embodiments. The process begins in step 702, in which a first substrate is provided such that the first substrate includes a die attach region, a exclusion region, and a surrounding region, wherein the protective layer protects the wires in the surrounding region, as described with reference to Figures 4a, 4b above. In step 704, a second substrate is provided, and in step 706 the second substrate is attached to the first substrate, as described with reference to Figures 5a, 5b above. The manner in which the first substrate is attached to the second substrate is to provide an exclusion region and an exclusion distance between the first substrate and the protective layer closest to an edge. At step 708, the underfill is placed between the first substrate and the second substrate. Maintaining the above exclusion and exclusion distances when providing protection to the wires in the exclusion zone This allows the underfill to be placed with little or no voids.

In an embodiment, a semiconductor device is provided. The device includes a first substrate having a wire formed thereon. The first substrate has a die attaching region, the exclusion region surrounds the periphery of the die attach region, and a surrounding region surrounds the periphery of the exclusion region. The first substrate has a wire overlying the surrounding area of the protective layer. The second substrate is electrically coupled to the first substrate in the die attach region; and the bottom filler is sandwiched between the first substrate and the second substrate, and the bottom filler extends over the wires in the exclusion region; The area of the exclusion zone accounts for about 5% to about 18% of the area of the second substrate.

In another embodiment, a semiconductor device is provided. The device includes a first substrate having a die attach region, a surrounding region and a exclusion region interposed between the die attach region and the surrounding region, wherein the protective layer covers the wires in the surrounding region, and wherein the protective layer does not extend into the crystal Grain attachment area and exclusion area. The second substrate is electrically coupled to the first substrate such that the second substrate is located above the die attach region of the first substrate. The die attach region corresponds to a region where the first substrate is directly under the second substrate, and the exclusion region extends from the boundary of the protective layer to the boundary of the die attach region. The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.

In still another embodiment, a method of forming a semiconductor device is provided, the method comprising providing a first substrate having a wire formed thereon and forming a protective layer over a portion of the first substrate. The second substrate is attached to the first substrate. The exclusion region extends between the boundary of the protective layer and the periphery of the second substrate, wherein the area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.

The features of several embodiments have been outlined above. It should be understood by those of ordinary skill in the art that the present invention can be used to implement the same objectives and/or achieve the same advantages in the embodiments described herein. The basis of the process and structure. It is also to be understood by those skilled in the art that such equivalents are not to be Spirit and scope.

Claims (10)

A semiconductor device comprising: a first substrate having a wire formed thereon, the first substrate having a die attach region, a exclusion region surrounding the die attachment region, and a surrounding region surrounding the exclusion The first substrate has a protective layer overlying the wire in the surrounding region, and wherein the protective layer does not extend into the die attach region; a second substrate is electrically coupled to the first substrate In the die attach region; and a bottom filler is interposed between the first substrate and the second substrate, the underfill extends over the wire in the exclusion region; wherein the semiconductor device is viewed from above The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate. A device according to claim 1, wherein an exclusion distance is between an edge of one of the second substrates and an edge of one of the protective layers, and the exclusion distance is equal to or greater than about 420 microns. The device of claim 1, wherein the underfill completely covers the exclusion zone and the wire in the die attachment region. The device of claim 1, wherein the second substrate is attached to the first substrate by a bump-on-trace connection. The device of claim 1, wherein the second substrate comprises a copper pillar directly coupled to the first conductor on the first substrate by a solder material. A semiconductor device includes: a first substrate having a die attach region, a surrounding region, and a reject region interposed between the die attach region and the peripheral region, wherein a protective layer covers the peripheral region a wire, wherein the protective layer does not extend into the die attach region and the exclusion region; and a second substrate is electrically coupled to the first substrate, the second substrate is located on the first substrate a region above the region; wherein the die attach region corresponds to a region of the first substrate directly below the second substrate; wherein the exclusion region extends from a boundary of the protective layer to a boundary of the die attach region; Looking down the semiconductor device, the area of the exclusion region is from about 5% to about 18% of the area of the second substrate. The device of claim 6, further comprising an underfill interposed between the first substrate and the second substrate. The device of claim 6, wherein an exclusion distance is between an edge of one of the second substrates and an edge of one of the protective layers, and the exclusion distance is equal to or greater than about 420 microns. A method of forming a semiconductor device, the method comprising: providing a first substrate, the first substrate having a wire formed thereon, the first substrate having a die attach region; forming a protective layer on the first substrate Part of the top, where the protective layer will not Extending into the die attach region; and attaching a second substrate to the first substrate; wherein a exclusion region extends between a boundary of the protective layer and a periphery of the second substrate, and the semiconductor device is viewed from above, The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate. The method of claim 9, further comprising placing an underfill between the first substrate and the second substrate.