TWI529920B - Semiconductor device - Google Patents

Description

Semiconductor device

The disclosed invention relates to a semiconductor device using a semiconductor element and a method of fabricating the same.

A storage device using a semiconductor element can be roughly classified into a volatile storage device that disappears without power supply storage contents and a nonvolatile storage device that retains stored contents even without power supply.

As a typical example of a volatile storage device, there is a DRAM (Dynamic Random Access Memory). The DRAM is selected to form a transistor of the storage element and stores the charge in the capacitor to store information.

According to the above principle, since the charge of the capacitor disappears when the information is read from the DRAM, the write operation needs to be performed again each time the data is read. In addition, since there is a leakage current in the transistor constituting the storage element, even if the transistor is not selected, the charge flows out or flows, so the data retention period is short. For this reason, it is necessary to perform the write operation (refresh operation) again in a predetermined cycle, and it is difficult to sufficiently reduce the power consumption. In addition, since there is no power supply to store the contents, it is necessary to have a magnetic material. Another storage device of material or optical material to achieve storage retention for a longer period of time.

As another example of the volatile storage device, there is an SRAM (Static Random Access Memory). SRAM uses a circuit such as a flip-flop to keep the contents stored without the need for a refresh operation, at which point SRAM is superior to DRAM. However, since a circuit such as a flip-flop is used, there is a problem that the unit price of the storage capacity becomes high. In addition, the SRAM is the same as the DRAM in that it disappears without the supply of power.

As a typical example of a nonvolatile storage device, there is a flash memory. The flash memory has a floating gate between the gate electrode of the transistor and the channel forming region, and the floating gate holds the charge for storage. Therefore, the flash memory has an extremely long period of data retention (semi-permanent) There is no need to perform the refresh operation required for the volatile storage device (for example, refer to Patent Document 1).

However, since the gate insulating layer constituting the memory element is degraded by the tunneling current generated at the time of writing, there is a problem that the function of the memory element cannot be exhibited due to writing for a predetermined number of times. In order to alleviate the influence of the above problem, for example, a method of equalizing the number of writes of each storage element is used, but in order to use this method, it is necessary to have a complicated peripheral circuit. In addition, even if the above method is used, the fundamental problem of the service life cannot be solved. That is to say, the flash memory is not suitable for the purpose of high rewriting frequency of information.

In addition, in order to keep the floating gate charged or to remove the charge, a high voltage is required. Furthermore, it takes a long time to maintain or remove the charge. It is difficult to achieve the problem of high speed of writing and erasing.

Patent Document 1: Japanese Patent Application Laid-Open No. 57-105889

In view of the above problems, it is an object of one embodiment of the disclosed invention to provide a semiconductor device of a new configuration capable of holding stored contents and having no limitation on the number of writes even without power supply.

One embodiment of the present invention is a semiconductor device in accordance with a laminated structure of a transistor formed using an oxide semiconductor and a transistor formed using a material other than the above. For example, the following structure can be employed.

An embodiment of the present invention is a semiconductor device including: a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein a plurality of parallel connections are made between the first wiring and the second wiring a storage element, one of the plurality of storage elements comprising: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; having a second gate electrode and a second source electrode And a second transistor of the second drain electrode; and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode, wherein the first transistor system is disposed on the semiconductor-containing material In the substrate, the second transistor includes an oxide semiconductor layer, and the first gate electrode is electrically connected to one of the second source electrode and the second drain electrode, and the first wiring is electrically connected to the first source electrode The first drain electrode is electrically connected to the third source electrode, the second wiring is electrically connected to the third drain electrode, and the third wiring and the other of the second source electrode and the second drain electrode are Electrical connection, fourth wiring and Two electrode system is electrically connected to the gate, and the first The fifth wiring is electrically connected to the third gate electrode.

In addition, an embodiment of the present invention is a semiconductor device including: a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein the first wiring and the second wiring are connected in parallel Having a plurality of storage elements, one of the plurality of storage elements comprising: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; having a second gate electrode, a second source a second electrode of the pole electrode and the second drain electrode; and a capacitor, wherein the first transistor system is disposed in the substrate including the semiconductor material, the second transistor includes the oxide semiconductor layer, the first gate electrode, One of the two source electrodes and the second drain electrode and one of the electrodes of the capacitor are electrically connected, the first wiring is electrically connected to the first source electrode, and the second wiring and the first drain electrode system are Electrically connected, the third wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fourth wiring is electrically connected to the second gate electrode, and the fifth wiring is in the electrode of the capacitor another By the Department of electrical connection.

In the above structure, the first transistor includes: a channel formation region provided in the substrate including the semiconductor material; an impurity region provided to sandwich the channel formation region; and a first gate insulation over the channel formation region a layer; a first gate electrode over the first gate insulating layer; and a first source electrode and a first drain electrode electrically connected to the impurity region.

Further, in the above structure, the second transistor includes: a second gate electrode included over the substrate of the semiconductor material; a second gate insulating layer over the second gate electrode; and a second gate insulation An oxide semiconductor layer over the layer; and a second source electrode electrically connected to the oxide semiconductor layer and Two-pole electrode.

Further, in the above structure, the third transistor includes: a channel formation region provided in the substrate including the semiconductor material; an impurity region provided in such a manner as to sandwich the channel formation region; and a third gate above the channel formation region a pole insulating layer; a third gate electrode over the third gate insulating layer; and a third source electrode and a third drain electrode electrically connected to the impurity region.

Further, in the above configuration, a single crystal semiconductor substrate or an SOI substrate is preferably used as the substrate including the semiconductor material. In particular, the semiconductor material is preferably germanium.

Further, in the above structure, the oxide semiconductor layer preferably contains an In-Ga-Zn-O-based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains crystals of In ₂ Ga ₂ ZnO ₇ . Further, the hydrogen concentration of the oxide semiconductor layer is preferably 5 × 10 ¹⁹ /cm ³ or less. Further, the off-state current of the second transistor is preferably 1 × 10 ^-13 A or less.

Further, in the above structure, the second transistor may be disposed in a region overlapping the first transistor.

Further, in the description of the present invention and the like, "upper" or "lower" is not limited to the positional relationship of the constituent elements being "upper" or "below". For example, the "first gate electrode on the gate insulating layer" includes a case where another constituent element is included between the gate insulating layer and the gate electrode. In addition, "upper" or "lower" is used for convenience of explanation, and "upper" or "lower" also includes the case where it is reversed upside down unless otherwise specified.

Further, in the description of the present invention and the like, "electrode" or "wiring" does not functionally limit its constituent elements. For example, sometimes "electrodes" are used as Part of "wiring" and vice versa. Furthermore, the "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are integrally formed.

Further, in the case of using a transistor having a different polarity or a case where a current direction of a circuit operation is changed, the functions of "source" and "drain" are sometimes interchanged. Therefore, in the description of the present invention and the like, the "source" and the "drain" can be interchanged.

Further, in the description of the present invention and the like, "electrical connection" includes a case where it is connected via "an element having a certain electrical action". Here, the "element having a certain electrical action" is not particularly limited as long as it can transfer and receive an electrical signal between the connected objects.

For example, "an element having a certain electrical action" includes not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In general, the "SOI substrate" refers to a substrate in which a germanium semiconductor layer is provided on an insulating surface, but in the description of the present invention, a substrate including a semiconductor layer including a material other than germanium on the insulating surface is further included. . In other words, the semiconductor layer of the "SOI substrate" is not limited to the germanium semiconductor layer. Further, the substrate in the "SOI substrate" is not limited to a semiconductor substrate such as a wafer, and may be a non-semiconductor substrate such as a glass substrate, a quartz substrate, a sapphire substrate, or a metal substrate. That is, the "SOI substrate" further includes a conductor substrate or an insulator substrate having a layer including a semiconductor material thereon. In the description of the present invention, the term "semiconductor substrate" refers not only to a substrate including only a semiconductor material but also to a semiconductor material. All the substrates of the material. That is, in the description of the present invention and the like, the "semiconductor substrate" includes the "SOI substrate".

As an embodiment of the present invention, there is provided a semiconductor device having a transistor using a material other than an oxide semiconductor in its lower portion and having a transistor using an oxide semiconductor in an upper portion thereof.

Since the off-state current of the transistor using the oxide semiconductor is extremely small, it is possible to maintain the stored content for an extremely long period of time by using the transistor. That is to say, since the refresh operation is not required, or the frequency of the refresh operation can be reduced to an extremely low level, the power consumption can be sufficiently reduced. In addition, even if there is no power supply, the content can be stored for a long period of time.

In addition, the writing of information does not require a high voltage, and there is no problem of component degradation. Further, information writing is performed in accordance with the on state or the off state of the transistor, and high speed operation can be easily realized. In addition, there are advantages to operations that do not require information to be erased.

Further, since a transistor using a material other than an oxide semiconductor can be sufficiently operated at a high speed, high-speed storage of the content can be read by using a transistor of a material other than the oxide semiconductor.

As described above, a semiconductor device having a new feature can be realized by integrally forming a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor.

100‧‧‧Substrate

102‧‧‧Protective layer

104‧‧‧Semiconductor area

106‧‧‧ Component separation insulation

108a‧‧‧ gate insulation

110a‧‧‧gate electrode

112‧‧‧Insulation

114‧‧‧ impurity area

116‧‧‧Channel formation area

118‧‧‧Sidewall insulation

120‧‧‧High concentration impurity area

122‧‧‧metal layer

124‧‧‧Metal compound area

126‧‧‧Interlayer insulation

128‧‧‧Interlayer insulation

130a‧‧‧Source electrode or drain electrode

130b‧‧‧Source electrode or drain electrode

130c‧‧‧electrode

130d‧‧‧electrode

132‧‧‧Insulation

134‧‧‧ Conductive layer

136a‧‧‧electrode

136b‧‧‧electrode

136c‧‧‧electrode

136d‧‧‧gate electrode

138‧‧‧ gate insulation

140‧‧‧Oxide semiconductor layer

142a‧‧‧Source electrode or drain electrode

142b‧‧‧Source electrode or drain electrode

144‧‧‧Protective insulation

146‧‧‧Interlayer insulation

148‧‧‧ Conductive layer

150a‧‧‧electrode

150b‧‧‧electrode

150c‧‧‧electrode

150d‧‧‧electrode

150e‧‧‧electrode

152‧‧‧Insulation

154a‧‧‧electrode

154b‧‧‧electrode

154c‧‧‧electrode

154d‧‧‧electrode

154e‧‧‧electrode

160‧‧‧Optoelectronics

162‧‧‧Optoelectronics

200‧‧‧ memory unit

201‧‧‧Optoelectronics

202‧‧‧Optoelectronics

203‧‧‧Optoelectronics

204‧‧‧ capacitor

205‧‧‧ capacitor

206‧‧‧Optoelectronics

210‧‧‧Memory Cell Array

211‧‧‧ drive circuit for second wiring and third wiring

212‧‧‧Readout circuit

213‧‧‧Drive circuit for fourth wiring and fifth wiring

220‧‧‧ memory unit

230‧‧‧Memory Cell Array

231‧‧‧ drive circuit for second wiring and fourth wiring

232‧‧‧Readout circuit

233‧‧‧Drive circuit for the third wiring and the fifth wiring

240‧‧‧ memory unit

250‧‧‧Memory Cell Array

260‧‧‧ memory unit

270‧‧‧ memory cell array

280a‧‧‧ memory unit

280b‧‧‧ memory unit

290‧‧‧ memory unit

301‧‧‧ Subject

302‧‧‧Shell

303‧‧‧Display Department

304‧‧‧ keyboard

311‧‧‧ Subject

312‧‧‧ stylus

313‧‧‧Display Department

314‧‧‧ operation button

315‧‧‧ external interface

320‧‧‧ e-book reader

321‧‧‧Shell

323‧‧‧shell

325‧‧‧Display Department

327‧‧‧Display Department

331‧‧‧Power supply

333‧‧‧ operation keys

335‧‧‧Speaker

337‧‧‧Axis

340‧‧‧shell

341‧‧‧Shell

342‧‧‧ display panel

343‧‧‧Speaker

344‧‧‧Microphone

345‧‧‧ operation keys

346‧‧‧ indicating device

347‧‧‧Photographic lens

348‧‧‧External connection terminal

349‧‧‧Solar battery unit

350‧‧‧ external storage slot

361‧‧‧ Subject

363‧‧‧Viewfinder

364‧‧‧Operation switch

365‧‧‧Display Department B

366‧‧‧Battery

367‧‧‧Display A

370‧‧‧TV installation

371‧‧‧Shell

373‧‧‧Display Department

375‧‧‧ bracket

377‧‧‧Display Department

379‧‧‧ operation keys

380‧‧‧Remote control

1 is a circuit diagram for explaining a semiconductor device; FIGS. 2A and 2B are cross-sectional views and plan views for explaining a semiconductor device; FIGS. 3A to 3H are cross-sectional views for explaining a process of the semiconductor device; FIGS. 4A to 4G are used for BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A to FIG. 5D are cross-sectional views for explaining a process of a semiconductor device; FIG. 6 is a cross-sectional view for explaining a semiconductor device; and FIGS. 7A and 7B are cross-sectional views for explaining a semiconductor device. 8A and 8B are cross-sectional views for explaining a semiconductor device; Figs. 9A and 9B are cross-sectional views for explaining a semiconductor device; Fig. 10 is a circuit diagram for explaining a memory element; and Fig. 11 is a view for explaining operation of a memory element Figure 12 is a circuit diagram for explaining a semiconductor device; Figure 13 is a circuit diagram for explaining a memory device; Figure 14 is a circuit diagram for explaining a semiconductor device; Figure 15 is a circuit diagram for explaining a memory element; Is a diagram showing the relationship between the node A and the fifth wiring potential; FIG. 17 is a circuit diagram for explaining the semiconductor device; FIG. 18 is a circuit diagram for explaining the storage element; FIG. 20A and FIG. 20B are circuit diagrams for explaining a storage element; FIG. 21 is a circuit diagram for explaining a storage element; FIG. 22 is a circuit diagram for explaining a readout circuit; and FIGS. 23A to 23F are for explaining an electronic circuit. Figure 24 is a longitudinal sectional view of an inverted staggered transistor using an oxide semiconductor; Figs. 25A and 25B are energy band diagrams (schematic diagrams) taken along line AA ^{' of} Fig. 24; Fig. 26A is a view showing positive A graph in which the potential (+V _G ) is applied to the state of the gate (G1), and FIG. 26B is a graph showing a state in which a negative potential (-V _G ) is applied to the gate (G1); FIG. 27 is a view A graph of the relationship between the vacuum level, the work function of the metal (Φ _M ), and the electron affinity (χ) of the oxide semiconductor.

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. However, the invention is not limited to the following description. One of ordinary skill in the art can readily appreciate the fact that the modes and details can be varied in various forms without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

Note that, for convenience of explanation, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like sometimes do not indicate actual positions, sizes, ranges, and the like. Therefore, the present invention is not limited to the positions, sizes, ranges, and the like shown in the drawings and the like.

In addition, the "first", "second", and "first" used in the description of the present invention and the like Ordinal numbers are used to avoid the merging of structural elements, and not to limit them in terms of numbers.

(Example 1)

In the present embodiment, a structure of a semiconductor device and a method of fabricating the same according to an embodiment of the disclosed invention are explained with reference to FIGS. 1 through 9A and 9B.

<Circuit Structure of Semiconductor Device>

FIG. 1 shows an example of a circuit configuration of a semiconductor device. This semiconductor device is composed of a transistor 160 using a material other than an oxide semiconductor and a transistor 162 using an oxide semiconductor.

Here, the gate electrode of the transistor 160 is electrically connected to one of the source electrode and the drain electrode of the transistor 162. In addition, the first wiring (1st Line: also referred to as a source line) and the source electrode of the transistor 160 are electrically connected, the second wiring (2nd Line: also referred to as a bit line), and the drain electrode of the transistor 160 Electrical connection. Further, the third wiring (3rd Line: also referred to as a first signal line) is electrically connected to the other of the source electrode and the drain electrode of the transistor 162, and the fourth wiring (4th Line: also referred to as the second The signal line) is electrically connected to the gate electrode of the transistor 162.

The transistor 160 using a material other than the oxide semiconductor can perform sufficient high-speed operation. Therefore, high-speed storage of the content can be read by using the transistor 160 using a material other than the oxide semiconductor. In addition, the transistor 162 using an oxide semiconductor has a cutoff state Very small flow characteristics. Therefore, by bringing the transistor 162 into an off state, the potential of the gate electrode of the transistor 160 can be maintained for a very long time.

By exhibiting the feature that the potential of the gate electrode can be maintained, information writing, holding, and reading can be performed as described below.

First, explain the writing and holding of information. First, the transistor 162 is turned on by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode (writing) of the transistor 160. Then, by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned off, the transistor 162 is turned off, and the potential of the gate electrode of the transistor 160 is maintained (hold).

Since the off-state current of the transistor 162 is extremely small, the potential of the gate electrode of the transistor 160 is maintained for a long time. For example, in the case where the potential of the gate electrode of the transistor 160 is a potential at which the transistor 160 is in an on state, the on state of the transistor 160 is maintained for a long period of time. Further, in the case where the potential of the gate electrode of the transistor 160 is a potential at which the transistor 160 is in an off state, the off state of the transistor 160 is maintained for a long period of time.

Next, the reading of the information will be explained. As described above, when a predetermined potential (low potential) is applied to the first wiring while maintaining the on state or the off state of the transistor 160, the potential of the second wiring is depending on the on state or the off state of the transistor 160. different. For example, when the transistor 160 is in an on state, the potential of the second wiring is lowered with respect to the potential of the first wiring. In contrast, the transistor 160 is in an off state. In this case, the potential of the second wiring does not change.

As described above, the information can be read by comparing the potential of the second wiring with the predetermined potential while maintaining the information.

The following describes the rewriting of information. The information is rewritten in the same manner as the writing and holding of the above information. That is, the transistor 162 is turned on by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned on. Thereby, the potential of the third wiring (the potential according to the new information) is applied to the gate electrode of the transistor 160. Then, by setting the potential of the fourth wiring to a potential at which the transistor 162 is in the off state, the transistor 162 is turned off, and is in a state of holding new information.

As described above, the semiconductor device according to the disclosed invention can directly rewrite information by writing information again. Thereby, the erasing operation required for the flash memory or the like is not required, and the reduction in the operation speed due to the erasing operation can be suppressed. That is to say, high-speed operation of the semiconductor device can be achieved.

Further, although the above description has been made regarding the use of an n-type transistor (n-channel transistor) in which electrons are majority carriers, it is of course possible to use a p-type transistor in which a hole is a majority carrier instead of an n-type transistor.

<Planar structure and sectional structure of semiconductor device>

2A and 2B are diagrams showing an example of the structure of the above semiconductor device. 2A and 2B show a cross section of a semiconductor device and a plane of a semiconductor device, respectively. Here, FIG. 2A corresponds to the line A1-A2 along FIG. 2B and Section of line B1-B2. The semiconductor device shown in FIGS. 2A and 2B has a transistor 160 using a material other than an oxide semiconductor in its lower portion and a transistor 162 using an oxide semiconductor in its upper portion. Here, in the case where the transistor 160 and the transistor 162 are both n-type transistors, a p-type transistor may be employed. In particular, the transistor 160 is easily used as a p-type transistor.

The transistor 160 has a channel formation region 116 provided in the substrate 100 including a semiconductor material, an impurity region 114 provided to sandwich the channel formation region 116, and a high-concentration impurity region 120 (also referred to as an impurity region collectively) a gate insulating layer 108a disposed over the channel forming region 116, a gate electrode 110a disposed over the gate insulating layer 108a, a source electrode or a drain electrode 130a electrically connected to the impurity region 114, and a source electrode Or the drain electrode 130b.

Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, the high-concentration impurity region 120 is not overlapped in the region of the sidewall insulating layer 118 in the cross-sectional view of the substrate 100, and the metal compound region 124 exists above the high-concentration impurity region 120. In addition, an element isolation insulating layer 106 is disposed on the substrate 100 around the transistor 160, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are disposed to cover the transistor 160. The source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the metal compound region 124 by openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the high concentration impurity via the metal compound region 124. Region 120 and impurity region 114. Further, the gate electrode 110a is electrically connected to the electrode 130c provided in the same manner as the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b.

The transistor 162 has a gate electrode 136d disposed over the interlayer insulating layer 128, a gate insulating layer 138 disposed over the gate electrode 136d, an oxide semiconductor layer 140 disposed over the gate insulating layer 138, and a setting Above the oxide semiconductor layer 140 and electrically connected to the source electrode or the drain electrode 142a of the oxide semiconductor layer 140 and the source electrode or the drain electrode 142b.

Here, the gate electrode 136d is disposed to be buried in the insulating layer 132 formed over the interlayer insulating layer 128. Further, similarly to the gate electrode 136d, an electrode 136a that is in contact with the source electrode or the drain electrode 130a, an electrode 136b that is in contact with the source electrode or the gate electrode 130b, and an electrode 136c that is in contact with the electrode 130c are formed.

In addition, a protective insulating layer 144 is provided on a portion of the oxide semiconductor layer 140 in contact with a portion of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is disposed over the protective insulating layer 144. Here, an opening reaching the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b is formed in the protective insulating layer 144 and the interlayer insulating layer 146, and the electrode 150d and the electrode 150e are formed by the opening Contact with the source or drain electrode 142a and the source or drain electrode 142b. Further, similarly to the electrode 150d and the electrode 150e, the electrode 150a, the electrode 150b, and the electrode 150c are formed to be in contact with the electrode 136a by an opening provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, electrode 136b and electrode 136c.

Here, the oxide semiconductor layer 140 is preferably an oxide semiconductor layer which is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10 ¹⁹ /cm ³ or less, preferably 5 × 10 ¹⁸ /cm ³ or less, more preferably 5 × 10 ¹⁷ /cm ³ or less. In addition, the carrier concentration of the oxide semiconductor layer 140 which is sufficiently purified and which is sufficiently reduced in hydrogen concentration is 5 × 10 ¹⁴ /cm ³ or less, preferably 5 × 10 ¹² /cm ³ or less. As described above, the transistor 162 having extremely excellent off-state current characteristics can be obtained by using an i-type or substantially i-type oxide semiconductor which is sufficiently purified by reducing the hydrogen concentration. For example, in the case where the drain voltage Vd is +1 V or +10 V and the gate voltage Vg is -5 V to -20 V, the off-state current is 1 × 10 ^-13 A or less. As described above, the semiconductor device having a new structure can be realized by reducing the off-state current of the transistor 162 by using the oxide semiconductor layer 140 whose hydrogen concentration is sufficiently lowered to be highly purified. In addition, the concentration of hydrogen in the above oxide semiconductor layer 140 was measured using secondary ion mass spectrometry (SIMS).

Further, an insulating layer 152 is provided over the interlayer insulating layer 146, and the electrode 154a, the electrode 154b, the electrode 154c, and the electrode 154d are disposed so as to be buried in the insulating layer 152. Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150b, the electrode 154c is in contact with the electrode 150c and the electrode 150d, and the electrode 154d is in contact with the electrode 150e.

That is, in the semiconductor device shown in FIGS. 2A and 2B, the gate electrode 110a of the transistor 160 is interposed between the electrode 130c, the electrode 136c, and the electric The pole 150c, the electrode 154c, and the electrode 150d are electrically connected to the source electrode or the drain electrode 142a of the transistor 162.

<Method of Manufacturing Semiconductor Device>

Hereinafter, an example of the method of manufacturing the above semiconductor device will be described. Hereinafter, first, a method of manufacturing the lower transistor 160 will be described with reference to FIGS. 3A to 3H, and then a method of manufacturing the upper transistor 162 will be described with reference to FIGS. 4A to 4G and FIGS. 5A to 5D.

<Method of Manufacturing Lower Transistor>

First, a substrate 100 including a semiconductor material is prepared (see FIG. 3A). As the substrate 100 including a semiconductor material, a single crystal semiconductor substrate such as tantalum or tantalum carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as tantalum, or an SOI substrate can be used. Here, as an example of the substrate 100 including a semiconductor material, a single crystal germanium substrate is used. In general, the "SOI substrate" refers to a substrate in which a germanium semiconductor layer is provided on an insulating surface, but in the description of the invention, etc., a semiconductor layer including a material other than germanium is provided on the insulating surface. The substrate. In other words, the semiconductor layer of the "SOI substrate" is not limited to the germanium semiconductor layer. Further, the SOI substrate includes a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer.

A protective layer 102 (see FIG. 3A) serving as a mask for forming an element isolation insulating layer is formed over the substrate 100. As the protective layer 102, for example, insulation of a material such as yttrium oxide, tantalum nitride, or yttrium oxynitride can be used. Floor. Further, before and after this step, an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity may be added to the substrate 100 to control the threshold voltage of the transistor. When the semiconductor is germanium, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic or the like can be used. Further, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium or the like can be used.

Next, etching is performed using the above-described protective layer 102 as a mask to remove a portion of the substrate 100 that is not covered by the protective layer 102 (exposed region). Thereby, the semiconductor region 104 to be separated is formed (see FIG. 3B). The etching is preferably performed by dry etching, but wet etching may also be used. The etching gas and the etching liquid can be appropriately selected depending on the material to be etched.

Next, an insulating layer is formed by covering the semiconductor region 104, and the insulating layer overlapping the region of the semiconductor region 104 is selectively removed to form the element isolation insulating layer 106 (refer to FIG. 3B). The insulating layer is formed using hafnium oxide, tantalum nitride, hafnium oxynitride or the like. As a method of removing the insulating layer, there are a polishing treatment such as CMP or an etching treatment, and any method can be used. In addition, after the semiconductor region 104 is formed, or after the element isolation insulating layer 106 is formed, the above protective layer 102 is removed.

Next, an insulating layer is formed over the semiconductor region 104, and a layer containing a conductive material is formed over the insulating layer.

The insulating layer is a layer which is later used as a gate insulating layer, and the insulating layer is preferably obtained by a CVD method, a sputtering method, or the like, comprising cerium oxide, cerium oxynitride, cerium nitride, cerium oxide, aluminum oxide. A single layer structure or a multilayer structure of a film such as ruthenium oxide may be used. In addition, it can also be processed by high-density plasma The surface of the semiconductor region 104 is oxidized or nitrided by thermal oxidation treatment to form the above insulating layer. For example, a high-density plasma treatment can be performed using a mixed gas of a rare gas such as He, Ar, Kr, or Xe, oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In addition, the thickness of the insulating layer is not particularly limited, and for example, the thickness thereof may be set to 1 nm to 100 nm.

The layer containing the conductive material may be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Alternatively, a layer containing a conductive material may be formed by using a semiconductor material such as a polysilicon containing a conductive material. The formation method is not particularly limited, and various deposition methods such as a vapor deposition method, a CVD method, a sputtering method, and a spin coating method can be used. Further, in the present embodiment, an example in which a metal material is used to form a layer containing a conductive material will be described.

Then, the gate insulating layer 108a and the gate electrode 110a are formed by selectively etching the insulating layer and the layer containing the conductive material. (Refer to Figure 3C).

Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 3C). Then, phosphorus (P) or arsenic (As) or the like is added to the semiconductor region 104 to form an impurity region 114 having a shallow junction depth (see FIG. 3C). Here, although phosphorus or arsenic is added to form an n-type transistor, an impurity element such as boron (B) or aluminum (Al) may be added at the time of forming a p-type transistor. Further, by forming the impurity region 114, the channel formation region 116 is formed in the lower portion of the gate insulating layer 108a of the semiconductor region 104 (refer to FIG. 3C). Here, although the concentration of the added impurity can be appropriately set, it is preferably increased in accordance with the miniaturization of the height of the semiconductor element. Its concentration. Here, although the step of forming the impurity region 114 after the formation of the insulating layer 112 is employed, the step of forming the insulating layer 112 after the impurity region 114 is formed may also be employed.

Next, a sidewall insulating layer 118 is formed (refer to FIG. 3D). After the insulating layer is formed over the insulating layer 112, the sidewall insulating layer 118 is formed in a self-aligned manner by anisotropically etching the insulating layer. Further, at this time, it is preferable to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114 by etching a part of the insulating layer 112.

Next, an insulating layer is formed covering the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, and the like. Then, phosphorus (P) or arsenic (As) or the like is added to the region contacting the impurity region 114 to form the high concentration impurity region 120 (refer to FIG. 3E). Then, the metal layer 122 is formed by covering the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, and the like by removing the insulating layer (see FIG. 3E). The metal layer 122 can be formed by various deposition methods such as a vacuum deposition method, a sputtering method, or a spin coating method. The metal layer 122 is preferably formed using a metal material that reacts with a semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Examples of the metal material include titanium, tantalum, tungsten, nickel, cobalt, platinum, and the like.

Next, heat treatment is performed to cause the metal layer 122 to react with the semiconductor material. Thereby, the metal compound region 124 contacting the high-concentration impurity region 120 is formed (see FIG. 3F). Further, in the case where polysilicon or the like is used as the gate electrode 110a, a metal compound region is also formed in a portion where the gate electrode 110a is in contact with the metal layer 122.

As the above heat treatment, for example, heat treatment using a flash lamp can be used. Of course, other heat treatment methods can also be used, but a method of performing heat treatment in a very short time is preferably used to improve the controllability of the chemical reaction formed according to the metal compound. Further, the metal compound region is formed by a reaction between the metal material and the semiconductor material, and the conductivity of the metal compound region is sufficiently improved. By forming the metal compound region, the electric resistance can be sufficiently lowered, and the element characteristics can be improved. In addition, after the metal compound region 124 is formed, the metal layer 122 is removed.

Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed to cover the respective structures formed by the above steps (see FIG. 3G). The interlayer insulating layer 126 and the interlayer insulating layer 128 may be formed using an inorganic insulating material such as cerium oxide, cerium oxynitride, cerium nitride, cerium oxide, aluminum oxide or cerium oxide. Further, the interlayer insulating layer 126 and the interlayer insulating layer 128 may be formed using an organic insulating material such as polyimide or acrylic resin. Here, although the two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is shown, the structure of the interlayer insulating layer is not limited thereto. After the interlayer insulating layer 128 is formed, it is preferably planarized by subjecting its surface to CMP or etching treatment or the like.

Then, a source electrode or a drain electrode 130a and a source electrode or a drain electrode 130b are formed in the opening by forming an opening reaching the metal compound region 124 in the interlayer insulating layer (see FIG. 3H). For example, a PVD method or a CVD method or the like may be used in a region including an opening to form a conductive layer, and then a portion of the above-described conductive layer may be removed using a etching treatment or CMP or the like to form a source electrode or a drain electrode 130a and a source. A pole electrode or a drain electrode 130b.

Further, when the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b are formed by removing a part of the above-mentioned conductive layer, the surface thereof is preferably processed to be flat. For example, when a thin titanium film or a titanium nitride film is formed in a region including an opening, and then a tungsten film is formed into the embedded opening, excess tungsten, titanium or titanium nitride can be removed by performing subsequent CMP. At the same time, the flatness of the surface is improved. As described above, by planarizing the surface including the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b, it is possible to form an excellent electrode, wiring, insulating layer, semiconductor layer or the like in the subsequent step.

Here, although only the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b of the contact metal compound region 124 are shown, the electrode contacting the gate electrode 110a may be formed in this step (for example, FIG. 2A) And the electrode 130c) in 2B and the like. A material which can be used as the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b is not particularly limited, and various conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, ruthenium or iridium may be used.

Through the above steps, the transistor 160 using the substrate 100 containing the semiconductor material is formed. Further, after performing the above steps, an electrode, a wiring, an insulating layer, or the like may be formed. By using a multilayer wiring structure composed of a laminated structure of an interlayer insulating layer and a conductive layer as a wiring structure, a highly integrated semiconductor device can be provided.

<Method of Manufacturing Upper Transistor>

Next, a step of manufacturing the transistor 162 over the interlayer insulating layer 128 will be described with reference to FIGS. 4A to 4G and FIGS. 5A to 5D. In addition, FIGS. 4A to 4G and FIGS. 5A to 5D illustrate processes of various electrodes or transistors 162 and the like on the interlayer insulating layer 128, and the transistor 160 and the like existing in the lower portion of the transistor 162 are omitted.

First, an insulating layer 132 is formed over the interlayer insulating layer 128, the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b, and the electrode 130c (see FIG. 4A). The insulating layer 132 can be formed using a PVD method, a CVD method, or the like. Further, the insulating layer 132 may be formed using an inorganic insulating material such as cerium oxide, cerium oxynitride, cerium nitride, cerium oxide, aluminum oxide or cerium oxide.

Next, an opening reaching the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b, and the electrode 130c is formed in the insulating layer 132. At this time, an opening is also formed in a region where the gate electrode 136d is formed later. Then, the conductive layer 134 is formed to be embedded in the above opening (refer to FIG. 4B). The opening may be formed by a method such as etching using a mask. The mask is formed by a method such as exposure using a photomask. As the etching, any of wet etching and dry etching is used, but from the viewpoint of microfabrication, dry etching is preferably used. The conductive layer 134 can be formed using a deposition method such as a PVD method or a CVD method. As a material which can be used to form the conductive layer 134, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, ruthenium or iridium, an alloy or a compound (for example, a nitride) of the material, or the like can be given.

More specifically, the following methods can be used: for example, including an opening A thin titanium film is formed using the PVD method in the region, and a thin titanium nitride film is formed using a CVD method, and then the tungsten film is formed into the embedded opening. Here, the titanium film formed by the PVD method has a reduction in the oxide film of the interface to reduce contact with the lower electrode (here, the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b, the electrode 130c, etc.). The function of the resistor. In addition, the titanium nitride film formed later has a barrier function of suppressing diffusion of the conductive material. Further, after forming a barrier film made of titanium or titanium nitride or the like, a copper film may be formed by an electroplating method.

After the conductive layer 134 is formed, a portion of the conductive layer 134 is removed by a method such as etching treatment or CMP, and the insulating layer 132 is exposed to form the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d (refer to Figure 4C). Further, when a part of the above-mentioned conductive layer 134 is removed to form the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d, the surface thereof is preferably processed to be flat. Therefore, by processing the surfaces of the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d to be flat, excellent electrodes, wirings, insulating layers, semiconductor layers, and the like can be formed in the subsequent steps.

Next, a gate insulating layer 138 is formed over the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d (see FIG. 4D). The gate insulating layer 138 can be formed by a CVD method, a sputtering method, or the like. Further, the gate insulating layer 138 preferably contains hafnium oxide, tantalum nitride, hafnium oxynitride, hafnium oxynitride, aluminum oxide, cerium oxide or cerium oxide. In addition, the gate insulating layer 138 may have a single layer structure or a stacked structure. For example, a plasma CVD method using decane (SiH ₄ ), oxygen, and nitrogen as a source gas is used to form a gate insulating layer 138 including hafnium oxynitride. The thickness of the gate insulating layer 138 is not particularly limited, and for example, the thickness thereof may be set to 10 nm to 500 nm. When a laminated structure is used, for example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a second gate insulating layer having a thickness of 5 nm to 300 nm over the first gate insulating layer are preferably used. Lamination.

In addition, since i-type is removed by removing impurities or an oxide semiconductor (highly purified oxide semiconductor) which is substantially i-type is extremely sensitive to interface level or interface charge, it is used as an oxide semiconductor layer. In the case of using the oxide semiconductor, it is important to interface with the gate insulating layer. That is, the gate insulating layer 138 that contacts the highly purified oxide semiconductor layer is required to be of high quality.

For example, since a high-quality gate insulating layer 138 having a dense and high withstand voltage can be formed by a high-density plasma CVD method using microwave (2.45 GHz), the method is preferable. This is because the highly purified oxide semiconductor layer is bonded to the high-quality gate insulating layer, so that the interface level is lowered and excellent interface characteristics can be obtained.

Of course, as long as it is a method of forming a high-quality insulating layer as a gate insulating layer, other methods such as a sputtering method or a plasma CVD method may be used in the case of using a highly purified oxide semiconductor layer. Further, an insulating layer which is improved in film quality or interface characteristics by heat treatment after formation may also be used. In either case, it is sufficient to form a gate insulating layer which is excellent in film quality as the gate insulating layer 138 and which can reduce the interfacial density of the oxide semiconductor layer to form an excellent interface.

Furthermore, in the gate bias-thermal stress test (referred to as BT test) at 85 ° C, 2 × 10 ⁶ V/cm and time of 12 hours, if impurities, impurities and oxides are added to the oxide semiconductor The bond between the main components of the semiconductor is cut by a strong electric field (B: bias) and a high temperature (T: temperature), and the resulting dangling bond causes a shift in the threshold voltage (Vth).

On the contrary, by removing the impurities of the oxide semiconductor as much as possible, especially hydrogen or water, as described above, and having excellent interface characteristics with the gate insulating layer, a transistor which is stable to the BT test can be obtained. .

Next, an oxide semiconductor layer is formed over the gate insulating layer 138, and the oxide semiconductor layer is processed by etching using a mask or the like to form an island-shaped oxide semiconductor layer 140 (see FIG. 4E).

As the oxide semiconductor layer, In-Ga-Zn-O type, In-Sn-Zn-O type, In-Al-Zn-O type, Sn-Ga-Zn-O type, Al-Ga-Zn are preferably used. Oxidation of -O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O A semiconductor layer, especially an amorphous oxide semiconductor layer. In the present embodiment, as the oxide semiconductor layer, an amorphous oxide semiconductor layer is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor deposition target. In addition, since ruthenium can be suppressed by adding it to the amorphous oxide semiconductor layer, for example, a target containing 2 wt.% to 10 wt.% of SiO ₂ can also be used to form an oxide semiconductor. Floor.

As a target for producing an oxide semiconductor layer by a sputtering method, for example, a target of a metal oxide containing zinc oxide as a main component can be used. Further, a target for oxide semiconductor deposition containing In, Ga, and Zn (composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:1 [mol%], In:Ga:Zn) may also be used. =1:1:0.5[atom%]) and so on. Further, as a target for depositing an oxide semiconductor containing In, Ga, and Zn, a composition ratio of In:Ga:Zn=1:1:1 [atom%] or In:Ga:Zn=1:1 can also be used. : 2 [atom%] target, etc. The filling ratio of the target for oxide semiconductor deposition is 90% to 100%, preferably 95% or more (for example, 99.9%). The target for oxide semiconductor deposition having a high filling ratio is used to form a dense oxide semiconductor layer.

The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, for example, it is preferred to use impurities such as hydrogen, water, a hydroxyl group or a hydride to be removed to a high purity gas having a concentration in the range of about ppm (preferably in a range of about ppb).

When the oxide semiconductor layer is formed, the substrate is fixed in a processing chamber maintained in a reduced pressure state, and the substrate temperature is set to 100 ° C to 600 ° C, preferably 200 ° C to 400 ° C. By forming the oxide semiconductor layer while heating the substrate, the concentration of impurities contained in the oxide semiconductor layer can be lowered. In addition, damage due to sputtering can be alleviated. Then, a sputtering gas which is removed by introducing hydrogen and water while removing residual moisture in the processing chamber, and a metal oxide is used as a target to form an oxide semiconductor layer. An adsorption type vacuum pump is preferably used to remove residual moisture in the treatment chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Further, as the exhaust unit, a turbo pump provided with a cold trap may be used. In a deposition chamber that is evacuated using a cryopump, for example, a compound containing a hydrogen atom such as a hydrogen atom or water (H ₂ O) (more preferably, a compound containing a carbon atom) is exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the deposition chamber can be lowered.

As the formation conditions, for example, a condition in which the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is oxygen (oxygen flow rate ratio is 100%) can be employed. Note that when a pulsed direct current (DC) power source is used, powdery substances (also referred to as fine particles or dust) which occur at the time of deposition can be reduced, and the film thickness distribution becomes uniform, so that it is preferable. The thickness of the oxide semiconductor layer is set to 2 nm of only 200 nm, preferably 5 nm to 30 nm. In addition, since the appropriate thickness of the oxide semiconductor layer differs depending on the oxide semiconductor material to be used, the thickness thereof can be appropriately selected depending on the material to be used.

Further, it is preferable to perform reverse sputtering of introducing plasma by introducing an argon gas before forming the oxide semiconductor layer by a sputtering method to remove dust adhering to the surface of the gate insulating layer 138. Here, the usual sputtering refers to collision of ions to a sputtering target, and reverse sputtering refers to a property of colliding ions to a treatment surface to change the surface thereof. As a method of colliding ions to the treatment surface, there is a method of applying a high-frequency voltage to the treatment surface side in an argon atmosphere to generate plasma in the vicinity of the substrate. Further, an atmosphere such as nitrogen, helium or oxygen may be used instead of the argon atmosphere.

As the etching of the above oxide semiconductor layer, any of dry etching and wet etching can be used. Of course, dry etching and wet etching can also be used in combination. The etching conditions are appropriately set according to the material (etching gas) Body, etchant, etching time, temperature, etc.) to etch it into the desired shape.

Examples of the etching gas used for the dry etching include a chlorine-containing gas (chlorine-based gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), cesium chloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ). )and many more. Further, a fluorine-containing gas (fluorine-based gas such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), trifluoromethane (CHF ₃ ), or the like can also be used. Hydrogen bromide (HBr), oxygen (O ₂ ), or a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to the above gas.

As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, and the like) are appropriately set to be etched into a desired shape.

As the etching liquid for wet etching, a solution of phosphoric acid, acetic acid, and nitric acid mixed, ammonia hydrogen peroxide (31 wt.% hydrogen peroxide water: 28 wt.% ammonia water: water = 5:2:2), or the like can be used. . Further, an etching solution of ITO07N (manufactured by Kanto Chemical Co., Inc.) or the like can also be used.

Next, it is preferred to perform the first heat treatment on the oxide semiconductor layer. Dehydration or dehydrogenation of the oxide semiconductor layer can be performed by performing the first heat treatment. The temperature of the first heat treatment is set to be higher than or equal to 300 ° C and lower than or equal to 750 ° C, preferably higher than or equal to 400 ° C and lower than the strain point of the substrate. For example, introducing a substrate into an electric furnace using a resistance heater or the like The oxide semiconductor layer 140 was heat-treated in a nitrogen atmosphere at a temperature of 450 ° C for 1 hour. During this period, the oxide semiconductor layer 140 is not exposed to the air to avoid re-mixing of water or hydrogen.

Further, the heat treatment apparatus is not limited to the electric furnace, and may be a device that heats the object to be treated by heat transfer or heat radiation from a medium such as a heated gas. For example, an RTA (Rapid Thermal Annealing) device such as a GRTA (Gas Rapid Thermal Annealing) device or an LRTA (Light Rapid Thermal Annealing) device can be used. The LRTA device is a device that heats an object to be treated by radiation (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high temperature gas. As the gas, an inert gas such as a rare gas such as argon or nitrogen or the like which does not react with the object to be treated by heat treatment is used.

Further, as the first heat treatment, the following GRTA treatment may be performed, that is, the substrate is introduced into an inert gas heated to a high temperature of 650 ° C to 700 ° C, heated for several minutes, and then the substrate is taken out from the inert gas. High temperature heat treatment can be performed in a short time by using GRTA treatment. In addition, since the GRTA treatment is a heat treatment performed in a short time, the GRTA treatment can be used even under temperature conditions exceeding the strain point of the substrate.

Further, it is preferred to carry out the first heat treatment in an atmosphere containing nitrogen or a rare gas (such as helium, neon or argon) as a main component and not containing water or hydrogen. For example, it is preferred to set the purity of the rare gas such as nitrogen or helium, neon, argon or the like introduced into the heat treatment device to be higher than or equal to 6N (99.9999%), preferably. It is set to be higher than or equal to 7N (99.99999%) (that is, the impurity concentration is lower than or equal to 1 ppm, preferably lower than or equal to 0.1 ppm).

The oxide semiconductor layer may be crystallized to become crystallites or polycrystals depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. For example, a microcrystalline oxide semiconductor layer having a crystallization ratio of 90% or more or 80% or more may be used. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer not containing a crystal component may be used.

In addition, an oxide semiconductor layer in which an amorphous oxide semiconductor (for example, a surface of an oxide semiconductor layer) and microcrystals (having a particle diameter of 1 nm to 20 nm (typically 2 nm to 4 nm)) are mixed together are sometimes used.

Further, the electrical characteristics of the oxide semiconductor layer can also be changed by arranging the crystallites in the amorphous state. For example, when an In-Ga-Zn-O-based oxide semiconductor deposition target is used to form an oxide semiconductor layer, crystal grain-aligned crystallites of In ₂ Ga ₂ ZnO ₇ having electrical anisotropy are formed. The electrical characteristics of the oxide semiconductor layer can be changed.

More specifically, for example, by aligning the crystal grains of In ₂ Ga ₂ ZnO ₇ such that the c-axis thereof is perpendicular to the surface of the oxide semiconductor layer, conductivity in a direction parallel to the surface of the oxide semiconductor layer can be improved, And the insulation in the direction perpendicular to the surface of the oxide semiconductor layer is improved. Further, the crystallite portion has a function of suppressing entry of impurities such as water or hydrogen into the oxide semiconductor layer.

Further, the oxide semiconductor layer having the above-described crystallite portion can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Further, more preferably, the oxide semiconductor layer can be formed by using a sputtering target having a Zn content smaller than the In or Ga content.

The first heat treatment of the oxide semiconductor layer 140 may be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 140. In this case, the substrate is taken out from the heating device after the first heat treatment, and the lithography step is performed.

Further, since the heat treatment has an effect of dehydrating or dehydrogenating the oxide semiconductor layer 140, it may be referred to as a dehydration treatment or a dehydrogenation treatment. After the oxide semiconductor layer is formed, after the source electrode or the drain electrode is laminated on the oxide semiconductor layer 140, or after the protective insulating layer is formed over the source electrode or the gate electrode, etc., Dehydration treatment or dehydrogenation treatment. Further, the dehydration treatment or the dehydrogenation treatment may be carried out one or more times.

Next, a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b are formed in contact with the oxide semiconductor layer 140 (see FIG. 4F). The source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b may be formed by selectively etching the conductive layer after forming the conductive layer covering the oxide semiconductor layer 140.

The conductive layer can be formed by a CVD method such as a PVD method or a plasma CVD method which is typically performed by a sputtering method. Further, as the material of the conductive layer, an element selected from aluminum, chromium, copper, ruthenium, titanium, molybdenum, and tungsten, an alloy containing the above element as a component, or the like can be used. Any one or more materials selected from the group consisting of manganese, magnesium, zirconium, hafnium and tantalum may also be used. Further, a material in which aluminum is combined with one element or a plurality of elements selected from the group consisting of titanium, tantalum, tungsten, molybdenum, chromium, niobium and tantalum may also be used. The conductive layer may be a single layer structure or a laminated structure of two or more layers. For example, a single layer junction of an aluminum film containing germanium can be cited. A two-layer structure in which a titanium film is laminated on an aluminum film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated.

Here, when exposure is performed to form a mask for etching, ultraviolet rays, KrF lasers or ArF lasers are preferably used.

The channel length (L) of the transistor is determined according to the interval between the lower edge portion of the source electrode or the drain electrode 142a and the lower edge portion of the source electrode or the drain electrode 142b. Further, when exposure is performed under the condition that the channel length (L) is shorter than 25 nm, exposure for forming a mask is performed using Ultra Ultraviolet which has a very short wavelength, that is, several nm to several tens of nm. The exposure using ultra-ultraviolet light has a high resolution and a large depth of focus. Therefore, the channel length (L) of the transistor to be formed later can be set to 10 nm to 1000 nm, and the operation speed of the circuit can be increased. Furthermore, since the off-state current value is extremely small, it is possible to suppress an increase in power consumption.

In addition, when the conductive layer is etched, its material and etching conditions are appropriately adjusted to prevent the oxide semiconductor layer 140 from being removed. Further, depending on the material and the etching conditions, a part of the oxide semiconductor layer 140 may be etched in this step to form an oxide semiconductor layer having a groove portion (concave portion).

Further, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a or between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142b. The oxide conductive layer and the metal layer for forming the source or drain electrode 142a and the source or drain electrode 142b may be continuously formed (continuously deposited). Oxide guide The electrical layer can be used as a source region or a drain region. By providing the oxide conductive layer, low resistance of the source region or the drain region can be achieved, and high-speed operation of the transistor can be achieved.

Alternatively, an exposure mask having a plurality of intensities of light transmission, that is, a multi-tone mask can be used to form a resist mask, and the resist mask is used to perform an etching step to reduce the mask. The number of uses and the number of steps. The resist mask formed using the multi-tone mask becomes a shape having a plurality of thicknesses (stepped shape), and is ashed to further change the shape, so that a plurality of etching steps that can be processed into different patterns can be used . That is, with a multi-tone mask, a resist mask corresponding to at least two different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the number of corresponding lithography steps can be reduced, so that the steps can be simplified.

Further, after the above steps, plasma treatment using a gas such as N ₂ O, N ₂ or Ar is preferably carried out. This plasma treatment is performed to remove water or the like adhering to the surface of the exposed oxide semiconductor layer. Alternatively, the plasma treatment may be carried out using a mixed gas of oxygen and argon.

Next, a protective insulating layer 144 that contacts a portion of the oxide semiconductor layer 140 is formed without contact with air (see FIG. 4G).

The protective insulating layer 144 can be formed by a method in which impurities such as water or hydrogen are not mixed into the protective insulating layer 144 by a sputtering method or the like as appropriate. In addition, it has a thickness of at least 1 nm. As a material which can be used for the protective insulating layer 144, there are cerium oxide, cerium nitride, cerium oxynitride or cerium oxynitride. Further, the structure may be a single layer structure or a laminate structure. Better will form a guarantee The substrate temperature at the time of protecting the insulating layer 144 is set to be higher than or equal to room temperature and lower than or equal to 300 ° C, preferably using a rare gas (typically argon) atmosphere, an oxygen atmosphere or a rare gas (typically argon) and oxygen. Mixed atmosphere.

When the protective insulating layer 144 contains hydrogen, hydrogen may intrude into the oxide semiconductor layer or oxygen may be extracted from the oxide semiconductor layer by hydrogen, which may cause formation of a low resistance on the back channel side of the oxide semiconductor layer. Parasitic channel. Therefore, it is important that hydrogen is not used in the method of forming the protective insulating layer 144 to minimize the protective insulating layer 144 from containing hydrogen.

Further, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent the oxide semiconductor layer 140 and the protective insulating layer 144 from containing hydrogen, a hydroxyl group or water.

An adsorption type vacuum pump is preferably used to remove residual moisture in the treatment chamber. For example, a cryopump, an ion pump or a titanium sublimation pump is preferably used. Further, as the exhaust unit, a turbo pump provided with a cold trap may be used. In a deposition chamber that is evacuated using a cryopump, for example, a compound containing hydrogen atoms such as hydrogen atoms, water (H ₂ O), or the like is removed, so that the protective insulating layer 144 formed in the deposition chamber can be reduced. The concentration of impurities.

As the deposition gas when forming the protective insulating layer 144, it is preferable to use a high-purity gas which removes impurities such as hydrogen, water, a hydroxyl group or a hydride to a concentration of about ppm (preferably, a concentration of about ppb).

Next, a second heat treatment (preferably 200 ° C to 400 ° C, for example, 250 ° C to 350 ° C) is preferably carried out in an inert gas atmosphere or in an oxygen gas atmosphere. For example, under a nitrogen atmosphere and at a temperature of 250 ° C, a small The second heat treatment. By performing the second heat treatment, fluctuations in the electrical characteristics of the transistor can be reduced.

Further, the heat treatment may be carried out in the air at a temperature of 100 ° C to 200 ° C for 1 hour or longer and 30 hours or shorter. The heat treatment can be carried out while maintaining a certain heating temperature, and the temperature rise from room temperature to 100 ° C to 200 ° C and the temperature drop from the heating temperature to room temperature can be repeated a plurality of times. Alternatively, the heat treatment may be performed under reduced pressure before forming the protective insulating layer. The heating time can be shortened by performing heat treatment under reduced pressure. Further, the heat treatment may be performed instead of the second heat treatment, or the heat treatment may be performed before and after the second heat treatment.

Next, an interlayer insulating layer 146 is formed over the protective insulating layer 144 (refer to FIG. 5A). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Further, the interlayer insulating layer 146 may be formed using an inorganic insulating material such as cerium oxide, cerium oxynitride, cerium nitride, cerium oxide, aluminum oxide or cerium oxide. After the interlayer insulating layer 146 is formed, it is preferably planarized by subjecting its surface to CMP or etching treatment or the like.

Next, an opening reaching the electrode 136a, the electrode 136b, the electrode 136c, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b is formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138, A conductive layer 148 is formed to be embedded in the opening (refer to FIG. 5B). The above opening may be formed by a method such as etching using a mask. The mask is formed by a method such as exposure using a photomask. As the etching, any one of wet etching and dry etching is used. However, from the viewpoint of microfabrication, dry etching is preferably used. The conductive layer 148 can be formed using a deposition method such as a PVD method or a CVD method. As a material which can be used to form the conductive layer 148, a conductive material such as molybdenum, titanium, chromium, ruthenium, tungsten, aluminum, copper, ruthenium or iridium, an alloy or a compound (for example, a nitride) of the material, or the like can be given.

Specifically, a method can be used: for example, a thin titanium film is formed using a PVD method in a region including an opening, and a thin titanium nitride film is formed using a CVD method, and then the tungsten film is formed into the embedded opening. Here, the titanium film formed by the PVD method has a lowering of the oxide film of the interface and lowering the lower electrode (here, the electrode 136a, the electrode 136b, the electrode 136c, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode) The function of the contact resistance of the electrode 142b). In addition, the titanium nitride film formed later has a barrier function of suppressing diffusion of the conductive material. Further, after forming a barrier film made of titanium or titanium nitride or the like, a copper film may be formed by an electroplating method.

After the conductive layer 148 is formed, a portion of the conductive layer 148 is removed by a method such as etching treatment or CMP, and the interlayer insulating layer 146 is exposed to form the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e ( Refer to Figure 5C). Further, when a part of the above-mentioned conductive layer 148 is removed to form the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e, the surface thereof is preferably processed to be flat. Therefore, by processing the surfaces of the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e to be flat, excellent electrodes, wiring, and insulation can be formed in the subsequent steps. Layers, semiconductor layers, and the like.

Further, an insulating layer 152 is formed, and openings reaching the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e are formed in the insulating layer 152, and a conductive layer is formed to be embedded in the opening, and then etching or CMP or the like is used. The method removes a portion of the conductive layer to expose the insulating layer 152 to form the electrode 154a, the electrode 154b, the electrode 154c, and the electrode 154d (refer to FIG. 5D). This step is the same as the case of forming the electrode 150a and the like, and a detailed description thereof will be omitted.

When the transistor 162 is manufactured by the above method, the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10 ¹⁹ /cm ³ or less, and the off-state current of the transistor 162 is 1 × 10 ^-13 A or less. As described above, the transistor 162 having excellent characteristics can be obtained by using the oxide semiconductor layer 140 which is sufficiently reduced in hydrogen concentration and high in purity. In addition, a semiconductor device having a transistor 160 using a material other than an oxide semiconductor in the lower portion and a transistor 162 using an oxide semiconductor in the upper portion and having excellent characteristics can be manufactured.

Further, as a semiconductor material to be compared for an oxide semiconductor, there is niobium carbide (for example, 4H-SiC). Oxide semiconductors have several things in common with 4H-SiC. Carrier density is an example of this. When the Fermi-Dirac distribution is used at normal temperature, the minority carrier of the oxide semiconductor is estimated to be about 1 × 10 ^-7 /cm ³ , which is the same as 6.7 × 10 ^-11 /cm ^{3 of} 4H-SiC. Very low value. By comparing its intrinsic carrier density with 矽 (about 1.4 × 10 ¹⁰ /cm ³ ), it can be clearly understood that the carrier density is extremely low.

In addition, since the band gap of the oxide semiconductor is 3.0 eV to 3.5 eV and the band gap of 4H-SiC is 3.26 eV, the oxide semiconductor and the tantalum carbide have in common from the viewpoint of the wide-gap semiconductor.

On the other hand, there is a great difference between the oxide semiconductor and the tantalum carbide, that is, the processing temperature. Since the semiconductor step using tantalum carbide generally requires a start-up heat treatment of 1500 ° C to 2000 ° C, it is difficult to realize its laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate or the semiconductor element or the like is damaged at the above high temperature. On the other hand, an oxide semiconductor can be produced by performing heat treatment at a temperature of 300 ° C to 500 ° C (below the glass transition temperature, up to about 700 ° C), and can be formed after forming an integrated circuit using other semiconductor materials. A semiconductor element composed of an oxide semiconductor.

Further, unlike the tantalum carbide, the oxide semiconductor has an advantage that a low heat resistant substrate such as a glass substrate can be used. Further, from the viewpoint of not requiring heat treatment at a high temperature, the oxide semiconductor has an advantage that energy consumption can be sufficiently reduced as compared with ruthenium carbide.

In addition, although various studies have been conducted on physical properties such as DOS (state density) in an oxide semiconductor, these studies do not include a technical idea of sufficiently reducing DOS itself. In one embodiment of the disclosed invention, a highly purified oxide semiconductor is produced by removing water or hydrogen which is a cause of DOS from an oxide semiconductor. This is based on the technical idea of fully reducing DOS itself. Thereby, an extremely excellent industrial product can be manufactured.

Furthermore, by supplying oxygen to the suspension of the metal produced by oxygen deficiency The key is used to reduce DOS caused by oxygen defects, and a higher purity (i type) oxide semiconductor can be obtained. For example, by forming an oxygen-excess oxide film by the contact channel formation region and supplying oxygen from the oxide film, DOS due to oxygen deficiency can be reduced.

The defects of the oxide semiconductor are considered to be caused by a shallower energy level of 0.1 eV to 0.2 eV and a deeper energy level caused by oxygen deficiency under a conduction band caused by hydrogen excess. The technical idea of removing hydrogen as much as possible and supplying oxygen sufficiently to eliminate the above defects is correct.

Further, in general, the oxide semiconductor is n-type, but in one embodiment of the disclosed invention, i-type is achieved by removing impurities, especially water or hydrogen. In this regard, it is not the case that the impurity is added as in the case of ruthenium or the like to realize the i-type, so it can be said that it includes a technical idea that has never been.

Further, in the present embodiment, although the bottom gate type structure is shown as the structure of the transistor 162, an embodiment of the present invention is not limited thereto. For example, a top gate type structure can be employed as the structure of the transistor 162. Further, as the structure of the transistor 162, a double gate type structure in which two gate electrode layers are disposed above and below the gate insulating region via the gate insulating layer can be employed.

<Electrical mechanism of a transistor including an oxide semiconductor>

Here, a conductive mechanism of a transistor including an oxide semiconductor will be described with reference to FIGS. 24 to 27. Note that the following description is only an investigation, and the validity of the invention will not be denied according to the description.

Fig. 24 is a cross-sectional view showing a double gate type transistor (thin film transistor) including an oxide semiconductor. An oxide semiconductor layer (OS) is provided over the gate electrode layer (GE1) via a gate insulating layer (GI1), and a source electrode (S) and a drain electrode (D) are disposed thereon. . Further, a gate insulating layer (GI2) is provided over the oxide semiconductor layer (OS), the source electrode (S), and the drain electrode (D), and a gate is interposed on the oxide semiconductor layer (OS). A gate electrode (GE2) is provided in the insulating layer (GI2).

25A and 25B show an energy band diagram (schematic diagram) taken along line AA ^{' of} Fig. 24. 25A shows a case where the potential difference between the source and the drain is 0 (equal potential, V _D =0 V), and FIG. 25B shows a case where the potential of the drain is raised with respect to the source (V _D >0 V).

26A and 26B show an energy band diagram (schematic diagram) of a section along BB ^' of Fig. 24. Fig. 26A shows a state in which a positive potential (+V _G ) is applied to the gate (G1), and shows a conduction state in which an overload (electron) flows between the source and the drain. In addition, FIG. 26B shows a state in which a negative potential (-V _G ) is applied to the gate (G1), and an off state (a state in which a minority carrier does not flow) is shown.

Fig. 27 shows the relationship between the vacuum level, the work function (Φ _M ) of the metal, and the electron affinity (χ) of the oxide semiconductor.

The existing oxide semiconductor is n-type, and its Fermi level (E _f ) is far from the intrinsic Fermi level (E _i ) at the center of the band gap, and is located on the side close to the conduction band. Further, a part of hydrogen in the oxide semiconductor is a donor, which is considered to be one of the causes of n-type formation.

In contrast, the oxide semiconductor according to one embodiment of the disclosed invention is obtained by removing hydrogen which is an n-type from an oxide semiconductor and purifying it so as not to contain an oxide semiconductor as much as possible. An element other than the main component (impurity element) is an intrinsic (i-type) oxide semiconductor or an oxide semiconductor as close as possible to the intrinsic. In other words, it is characterized in that a highly purified intrinsic (i-type) oxide semiconductor or an intrinsic oxide semiconductor is obtained by removing impurities such as hydrogen or water as much as possible, instead of adding an impurity element to realize i. Modeling. Thus, the Fermi level (E _f ) can be set to be substantially the same as the intrinsic Fermi level (E _i ).

In the case where the band gap (E _g ) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is considered to be 4.3 eV. The work function of titanium (Ti) constituting the source electrode or the drain electrode is substantially the same as the electron affinity (χ) of the oxide semiconductor. In this case, a Schottky barrier to electrons is not formed in the metal-oxide semiconductor interface.

That is, in the case where the work function (Φ _M ) of the metal and the electron affinity (χ) of the oxide semiconductor are the same, an energy band diagram (schematic diagram) as shown in FIG. 25A is displayed when the two are in contact.

In Fig. 25B, black dots (̇) indicate electrons. When a positive potential is applied to the drain, electrons are injected into the oxide semiconductor beyond the barrier (h) and then flow toward the drain. The height of the barrier (h) varies with the gate voltage and the drain voltage, but when a positive drain voltage is applied, the height of the barrier (h) is lower than the height of the barrier of FIG. 25A when no voltage is applied. That is, 1/2 of the band gap (E _g ).

At this time, as shown in FIG. 26A, electrons are in the gate insulating layer and high purity. The vicinity of the interface of the oxide semiconductor (the lowest part of the energy stable of the oxide semiconductor) migrates.

Further, as shown in FIG. 26B, when a negative potential is applied to the gate electrode (G1), since there is actually no hole of a minority carrier, the current becomes a value extremely close to zero.

As described above, the intrinsic (i-type) or actually intrinsic oxide semiconductor is obtained by carrying out the high purity of the oxide semiconductor so as not to include an element (impurity element) other than the main component of the oxide semiconductor. Thereby, the interface characteristics with the gate insulating layer are conspicuous. Therefore, as the gate insulating layer, a gate insulating layer which can form an excellent interface with an oxide semiconductor is required. Specifically, for example, an insulating layer produced by a CVD method using a high-density plasma generated by using a VHF band to a power source frequency of a microwave band, an insulating layer produced by a sputtering method, or the like is preferably used.

The interface between the oxide semiconductor and the gate insulating layer is improved while the oxide semiconductor is highly purified, for example, in the case where the channel width W of the transistor is 1 × 10 ⁴ μm and the channel length L is 3 μm. The off-state current of 1 × 10 ^-13 A and the subcritical swing value (S value) of 0.1 V/dec. (thickness of the gate insulating layer: 100 nm) can be achieved at normal temperature.

In this way, by performing high purity of the oxide semiconductor so as not to include an element (impurity element) other than the main component of the oxide semiconductor as much as possible, excellent operation of the thin film transistor can be achieved.

<Modification>

6 to 9A and 9B show a modification of the structure of the semiconductor device child. In the following, as a modification, a transistor 162 having a structure different from the above will be described. That is, the structure of the transistor 160 is the same as described above.

6 shows an example of a semiconductor device having a transistor 162 having a gate electrode 136d under the oxide semiconductor layer 140, and a source or drain electrode 142a and a source or drain electrode 142b. The oxide semiconductor layer 140 is contacted on the bottom surface of the oxide semiconductor layer 140. Further, the planar structure may be appropriately changed depending on the cross section, and therefore, only the cross section is shown here.

The structure shown in FIG. 6 differs most from the structure shown in FIGS. 2A and 2B in the connection position of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b with the oxide semiconductor layer 140. That is, in the structure shown in FIGS. 2A and 2B, the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b contact the oxide semiconductor layer 140 on the top surface of the oxide semiconductor layer 140, in the figure. In the structure shown in FIG. 6, the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b contact the oxide semiconductor layer 140 at the bottom surface of the oxide semiconductor layer 140. The arrangement of the other electrodes, the insulating layer, and the like is different from that of FIGS. 2A and 2B due to the difference in the above contact. The details of each component are the same as those of Figs. 2A and 2B.

Specifically, the semiconductor device shown in FIG. 6 includes: a gate electrode 136d disposed over the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; and a gate insulating layer 138 disposed thereon a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b; and a contact source electrode or a drain electrode 142a and a source electrode or a drain electrode The oxide semiconductor layer 140 of the top surface of 142b.

Here, the gate electrode 136d is provided as an insulating layer 132 which is buried to be formed over the interlayer insulating layer 128. Further, similarly to the gate electrode 136d, an electrode 136a that is in contact with the source electrode or the drain electrode 130a, an electrode 136b that is in contact with the source electrode or the gate electrode 130b, and an electrode 136c that is in contact with the electrode 130c are formed.

In addition, a protective insulating layer 144 is provided on a portion of the oxide semiconductor layer 140 in contact with a portion of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is disposed over the protective insulating layer 144. Here, an opening reaching the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b is formed in the protective insulating layer 144 and the interlayer insulating layer 146, and the electrode 150d and the electrode 150e are formed to be in contact by the opening. The source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b. Further, similarly to the electrode 150d and the electrode 150e, the electrode 150a, the electrode 150b, and the electrode 150c are formed to be in contact with the electrode 136a and the electrode by openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. 136b and electrode 136c.

Further, an insulating layer 152 is provided over the interlayer insulating layer 146, and the electrode 154a, the electrode 154b, the electrode 154c, and the electrode 154d are provided so as to be buried in the insulating layer 152. Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150b, the electrode 154c is in contact with the electrode 150c and the electrode 150d, and the electrode 154d is in contact with the electrode 150e.

7A and 7B show an example of a semiconductor device having a gate electrode 136d over the oxide semiconductor layer 140. Here, FIG. 7A shows the source The electrode or drain electrode 142a and the source or drain electrode 142b are in contact with the oxide semiconductor layer 140 at the bottom surface of the oxide semiconductor layer 140, and FIG. 7B shows the source or drain electrode 142a and the source electrode. Or the example in which the drain electrode 142b contacts the oxide semiconductor layer 140 on the top surface of the oxide semiconductor layer 140.

The structure shown in FIGS. 2A and 2B and FIG. 6 is largely different from the structure shown in FIGS. 7A and 7B in that a gate electrode 136d is provided on the oxide semiconductor layer 140. In addition, the structure shown in FIG. 7A differs greatly from the structure shown in FIG. 7B in that the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are in contact with the bottom surface of the oxide semiconductor layer 140. The material semiconductor layer 140 also contacts the oxide semiconductor layer 140 at the top surface of the oxide semiconductor layer 140. The arrangement of the other electrodes, the insulating layer, and the like is different from those of FIGS. 2A and 2B and the like due to these differences. The details of each component are the same as those of Figs. 2A and 2B and the like.

Specifically, the semiconductor device shown in FIG. 7A includes a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b disposed over the interlayer insulating layer 128; a contact source electrode or a drain electrode 142a and An oxide semiconductor layer 140 on a top surface of the source electrode or the drain electrode 142b; a gate insulating layer 138 disposed over the oxide semiconductor layer 140; and an overlying oxide semiconductor layer over the gate insulating layer 138 Gate electrode 136d of 140.

In addition, the semiconductor device illustrated in FIG. 7B includes: an oxide semiconductor layer 140 disposed over the interlayer insulating layer 128; a source electrode or a drain electrode 142a disposed to contact a top surface of the oxide semiconductor layer 140; a source electrode or a drain electrode 142b; a gate insulating layer 138 disposed over the oxide semiconductor layer 140, the source or drain electrode 142a, and the source or drain electrode 142b; and the gate insulating layer 138 Overlying the gate electrode 136d of the oxide semiconductor layer 140.

Further, in comparison with the structure shown in FIGS. 2A and 2B, constituent elements (for example, the electrode 150a and the electrode 154a, etc.) may be omitted in the structure shown in FIGS. 7A and 7B. In this case, a simplified indirect effect of the process can be obtained. Of course, constituent elements that are not necessarily required may be omitted in the configuration shown in FIGS. 2A and 2B and the like.

8A and 8B show an example in which the gate electrode 136d is provided under the oxide semiconductor layer 140 in the case where the size of the element is relatively large. In this case, since the flatness or coverage of the surface is not so high, it is not necessary to form a wiring, an electrode, or the like to be buried in the insulating layer. For example, the gate electrode 136d or the like can be formed by patterning after forming the conductive layer. Further, although not shown here, the transistor 160 can be manufactured in the same manner.

In addition, the structure shown in FIG. 8A and the structure shown in FIG. 8B are largely different in that the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are in contact with the bottom surface of the oxide semiconductor layer 140. The material semiconductor layer 140 also contacts the oxide semiconductor layer 140 at the top surface of the oxide semiconductor layer 140. The arrangement of the other electrodes, the insulating layer, and the like is different from those of FIGS. 2A and 2B and the like due to these differences. The details of each component are the same as those of Figs. 2A and 2B and the like.

Specifically, the semiconductor device shown in FIG. 8A includes: disposed in a layer a gate electrode 136d over the insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; a source electrode or a drain electrode 142a and a source electrode disposed over the gate insulating layer 138 or The drain electrode 142b; and the oxide semiconductor layer 140 contacting the source electrode or the drain electrode 142a and the top surface of the source electrode or the drain electrode 142b.

In addition, the semiconductor device shown in FIG. 8B includes: a gate electrode 136d disposed over the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; and a gate insulating layer 138 disposed over the gate insulating layer 138 An oxide semiconductor layer 140 overlapping in a region of the gate electrode 136d; and a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b disposed to contact the top surface of the oxide semiconductor layer 140.

Further, in comparison with the structure shown in FIGS. 2A and 2B, the constituent elements may be omitted in the configurations shown in FIGS. 8A and 8B. In this case, a simplified effect to the process can also be obtained.

9A and 9B show an example in which the gate electrode 136d is provided on the oxide semiconductor layer 140 in the case where the size of the element is relatively large. In this case, since the flatness of the surface or the coverage is not so high, it is not necessary to form a wiring, an electrode, or the like to be buried in the insulating layer. For example, the gate electrode 136d or the like can be formed by patterning after forming the conductive layer. Further, although not shown here, the transistor 160 can be manufactured in the same manner.

The structure shown in FIG. 9A differs greatly from the structure shown in FIG. 9B in that the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are in contact with the oxide half at the bottom surface of the oxide semiconductor layer 140. The conductor layer 140 also contacts the oxide semiconductor layer 140 at the top surface of the oxide semiconductor layer 140. The arrangement of the other electrodes, the insulating layer, and the like is different from those of FIGS. 2A and 2B and the like due to these differences. The details of each component are the same as those of Figs. 2A and 2B and the like.

Specifically, the semiconductor device shown in FIG. 9A includes a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b disposed on the interlayer insulating layer 128; a contact source electrode or a drain electrode 142a and a source An oxide semiconductor layer 140 on a top surface of the electrode or drain electrode 142b; a gate insulating layer 138 disposed on the source or drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 140 And a gate electrode 136d disposed in a region overlapping the oxide semiconductor layer 140 over the gate insulating layer 138.

In addition, the semiconductor device illustrated in FIG. 9B includes: an oxide semiconductor layer 140 disposed over the interlayer insulating layer 128; a source electrode or a drain electrode 142a and a source electrode disposed to contact a top surface of the oxide semiconductor layer 140 Or a drain electrode 142b; a gate insulating layer 138 disposed on the source or drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 140; and disposed over the gate insulating layer 138 The gate electrode 136d overlaps in the region of the oxide semiconductor layer 140.

Further, the constituent elements may be omitted in the configuration shown in FIGS. 9A and 9B as compared with the configuration shown in FIGS. 2A and 2B. In this case, a simplified effect to the process can also be obtained.

As described above, in accordance with an embodiment of the disclosed invention, to achieve A semiconductor device having a new structure. In the present embodiment, although an example in which the transistor 160 and the transistor 162 are laminated is described, the structure of the semiconductor device is not limited thereto. Further, in the present embodiment, although an example in which the channel length directions of the transistor 160 and the transistor 162 are perpendicular to each other has been described, the positional relationship and the like of the transistor 160 and the transistor 162 are not limited thereto. Further, the transistor 160 and the transistor 162 may be disposed to overlap each other.

Further, in the present embodiment, the semiconductor device of the minimum memory unit (1 bit) has been described for the sake of easy understanding, but the configuration of the semiconductor device is not limited thereto. It is also possible to constitute a higher-order semiconductor device by appropriately connecting a plurality of semiconductor devices. For example, a plurality of the above semiconductor devices can be used to constitute a NAND type or a NOR type semiconductor device. The structure of the wiring is not limited to FIG. 1, and the structure of the wiring can be appropriately changed.

The semiconductor device according to the present embodiment can hold information for a very long time due to the low off-state current characteristic of the transistor 162. That is to say, it is not necessary to perform a refresh operation required for a DRAM or the like, and power consumption can be suppressed. In addition, it can be practically used as a nonvolatile semiconductor device.

Further, since information writing or the like is performed in accordance with the switching operation of the transistor 162, a high voltage is not required, and there is no problem that the element is degraded. Furthermore, information writing or erasing is performed depending on whether the transistor is turned on or off, and high-speed operation can be easily realized. In addition, there is an advantage that an operation for erasing information required for flash memory or the like is not required.

Further, a transistor using a material other than an oxide semiconductor can perform a sufficiently high-speed operation, and therefore, by using the oxide semiconductor The material of the transistor allows for high-speed reading of stored content.

The structure, method, and the like shown in the present embodiment can be used in combination with any of the structures, methods, and the like shown in the other embodiments.

(Example 2)

In the present embodiment, as a semiconductor device according to an embodiment of the present invention, a circuit configuration of a storage element and an operation thereof will be described.

FIG. 10 shows an example of a circuit diagram of a storage element (hereinafter also referred to as a storage unit) included in a semiconductor device. The memory unit 200 shown in FIG. 10 includes a first wiring SL (source line), a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line). a fifth wiring WL (word line), a transistor 201 (first transistor), a transistor 202 (second transistor), and a transistor 203 (third transistor). The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

Here, the gate electrode of the transistor 201 is electrically connected to one of the source electrode and the drain electrode of the transistor 202. Further, the first wiring is electrically connected to the source electrode of the transistor 201, and the drain electrode of the transistor 201 is electrically connected to the source electrode of the transistor 203. In addition, the second wiring is electrically connected to the drain electrode of the transistor 203, the third wiring is electrically connected to the other of the source electrode and the drain electrode of the transistor 202, and the gate of the fourth wiring and the transistor 202 is connected. The electrode electrodes are electrically connected, and the fifth wiring is electrically connected to the gate electrode of the transistor 203.

Hereinafter, the operation of the circuit will be specifically described.

When data is written to the memory unit 200, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When the data "1" is written, the third wiring is set to 2V, and when the data "0" is written, the third wiring is set to 0V. At this time, the transistor 203 is in an off state, and the transistor 202 is in an on state. Further, when the data is written, the fourth wiring is set to 0 V and the transistor 202 is turned off before the potential of the third wiring changes.

As a result, after writing the material "1", the potential of the node connected to the gate electrode of the transistor 201 (hereinafter, referred to as node A) becomes about 2 V, and after writing the material "0", the potential of the node A Becomes about 0V. The charge according to the potential of the third wiring is stored at the node A, but since the off-state current of the transistor 202 is extremely small or is actually zero, the potential of the gate electrode of the transistor 201 can be maintained for a long time. FIG. 11 shows an example of a timing chart of a write operation.

Next, when reading data from the memory cell, the first wiring is set to 0V, the fifth wiring is set to 2V, the fourth wiring is set to 0V, and the third wiring is set to 0V, so that connection is made to the second wiring. The readout circuit is in an operational state. At this time, the transistor 203 is in an on state, and the transistor 202 is in an off state.

When the data is "0", that is, the node A is at about 0 V, the transistor 201 is in an off state, and therefore the resistance between the second wiring and the first wiring is in a high resistance state. On the other hand, the information is "1", that is, node A is at about 2V, transistor 201 It is in an on state, so the resistance between the second wiring and the first wiring is in a low resistance state. In the readout circuit, the material "0" or "1" can be read out depending on the resistance state of the memory cell. Further, although the second wiring is set to 0 V at the time of writing, the second wiring may be placed in a floating state or charged to a potential higher than 0 V. Although the third wiring is set to 0 V at the time of reading, the third wiring may be made to be in a floating state or charged to a potential higher than 0V.

Note that the material "1" and the data "0" are defined for convenience and may be exchanged with each other. In addition, the above operating voltage is just an example. As long as the transistor 201 is in an off state when the data is "0" and the transistor 201 is in an on state when the data is "1", the transistor 202 is turned on at the time of writing and at the time of writing. The operation voltage may be selected such that the transistor 202 is in an off state and the transistor 203 is in an on state at the time of reading. In particular, it is also possible to use the power supply potential VDD of the peripheral logic circuit instead of 2V.

Figure 12 shows a block circuit diagram of a semiconductor device in accordance with one embodiment of the present invention having a storage capacity of m x n bits.

A semiconductor device according to an embodiment of the present invention includes: m fifth wirings and fourth wirings; n second wirings and third wirings; and a plurality of memory cells 200 (1, 1) to 200 (m, n) a memory cell array 210 of a matrix shape arranged in a vertical m (column) × horizontal n (row) (m, n is a natural number); and peripheral circuits such as a second wiring and a third wiring driving circuit 211, fourth Wiring circuit and drive circuit 213 of fifth wiring and readout Road 212. As other peripheral circuits, a refresh circuit or the like may be provided.

As each memory unit, the memory unit 200 (i, j) is taken as a typical example. Here, the memory unit 200 (i, j) (i is an integer of 1 to m, and j is an integer of 1 to n) is connected to the second wiring BL(j), the third wiring S1(j), and the fifth wiring, respectively. WL(i), fourth wiring S2(i), and first wiring. The first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are connected to the driving circuit 211 and the reading circuit 212 of the second wiring and the third wiring, and the fifth The wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the driving circuits 213 of the fourth wiring and the fifth wiring.

Hereinafter, the operation of the semiconductor device shown in FIG. 12 will be described. In this configuration, writing and reading are performed for each column.

When the memory cells 200 (i, 1) to 200 (i, n) of the i-th column are written, the first wiring potential Vs is set to 0 V, and the fifth wiring WL (i) is set to 0 V. The two wirings BL(1) to BL(n) are set to 0V, and the fourth wiring S2(i) is set to 2V. At this time, the transistor 202 is in an on state. The third wirings S1(1) to S1(n) are set to 2V in the row in which the material "1" is written, and the third wirings S1(1) to S1(n) are written in the row in which the material "0" is written. ) is set to 0V. Further, when the data is written, the fourth wiring S2(i) is set to 0 V before the potential of the third wiring S1(1) to S1(n) changes, and the transistor 202 is turned off. In addition, the fifth wiring that has not been selected is set to 0V, and the fourth wiring that has not been selected is set to 0V.

As a result, in the memory cell in which the data "1" is written, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 becomes about 2 V, and the memory having the data "0" is written. In the cell, the potential of the node A becomes about 0V. In addition, the potential of the node A of the unselected memory cell does not change.

When the memory cells 200 (i, 1) to 200 (i, n) of the i-th column are read, the first wiring potential Vs is set to 0 V, and the fifth wiring WL (i) is set to 2 V. The fourth wiring S2(i) is set to 0V, the third wirings S1(1) to S1(n) are set to 0V, and the readout circuits connected to the second wirings BL(1) to BL(n) are operated. . For example, in the readout circuit, the material "0" or "1" can be read depending on the resistance state of the memory cell. In addition, the fifth wiring that has not been selected is set to 0V, and the fourth wiring that has not been selected is set to 0V. Further, although the second wiring is set to 0 V at the time of writing, the second wiring may be in a floating state or charged to a potential of 0 V or more. Although the third wiring is set to 0 V at the time of reading, the third wiring may be in a floating state or charged to a potential of 0 V or more.

Note that the material "1" and the data "0" are defined for convenience and may be exchanged with each other. In addition, the above operating voltage is just an example. As long as the transistor 201 is in the off state when the data is "0" and the transistor 201 is in the on state when the data is "1", the transistor 202 is turned on and written during writing. The operation voltage may be selected such that the transistor 202 is in an off state and the transistor 203 is in an on state at the time of reading. especially, It is also possible to use the power supply potential VDD of the peripheral logic circuit instead of 2V.

Hereinafter, another example of the circuit configuration of the storage element and its operation according to an embodiment of the present invention will be described.

FIG. 13 shows an example of a memory cell circuit included in a semiconductor device. The memory unit 220 shown in FIG. 13 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 201 (first transistor), and a transistor 202 (second A transistor) and a transistor 203 (third transistor). The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

The direction of the third wiring and the fourth wiring is different in the circuit of the memory unit 220 shown in FIG. 13 as compared with the circuit of the memory unit 200 shown in FIG. That is, in the circuit of the memory unit 220 shown in FIG. 13, the third wiring is disposed in the direction (column direction) of the fifth wiring, and the fourth wiring is disposed in the direction (row direction) of the second wiring.

Here, the gate electrode of the transistor 201 is electrically connected to one of the source electrode and the drain electrode of the transistor 202. Further, the first wiring is electrically connected to the source electrode of the transistor 201, and the drain electrode of the transistor 201 is electrically connected to the source electrode of the transistor 203. In addition, the second wiring is electrically connected to the drain electrode of the transistor 203, the third wiring is electrically connected to the other of the source electrode and the drain electrode of the transistor 202, and the gate of the fourth wiring and the transistor 202 is connected. The electrode electrodes are electrically connected, and the fifth wiring is electrically connected to the gate electrode of the transistor 203.

Because the operation of the circuit of the memory unit 220 shown in FIG. 13 is compared with FIG. The operation of the circuit of the memory unit 200 shown is the same, and a detailed description is omitted.

Figure 14 shows a block circuit diagram of a semiconductor device in accordance with one embodiment of the present invention having a storage capacity of m x n bits.

A semiconductor device according to an embodiment of the present invention includes: m third wirings and fifth wirings; n second wirings and fourth wirings; and a plurality of memory cells 220 (1, 1) to 220 (m, n) a memory cell array 230 arranged in a matrix of a vertical m (column) × a horizontal n (row) (m, n is a natural number); and a peripheral circuit such as a second wiring and a fourth wiring driving circuit 231, a third The wiring circuit and the fifth wiring drive circuit 233 and the read circuit 232. As other peripheral circuits, a refresh circuit or the like may be provided.

Compared with the semiconductor device shown in FIG. 12, in the semiconductor device shown in FIG. 14, the directions of the third wiring and the fourth wiring are different. That is, in the semiconductor device shown in FIG. 14, the third wiring is disposed in the direction (column direction) of the fifth wiring, and the fourth wiring is disposed in the direction (row direction) of the second wiring.

As each memory unit, the memory unit 220 (i, j) is taken as a typical example. Here, the memory unit 220 (i, j) (i is an integer of 1 to m, and j is an integer of 1 to n) is connected to the second wiring BL (j), the fourth wiring S2 (j), and the fifth wiring, respectively. WL(i), third wiring S1(i), and first wiring. The first wiring potential Vs is applied to the first wiring. Further, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2(n) are connected to the driving circuit 231 and the reading circuit 232 of the second wiring and the fourth wiring, and the fifth Wiring WL(1) to WL The (m) and third wirings S1(1) to S1(m) are driving circuits 233 connected to the third wiring and the fifth wiring.

Hereinafter, the operation of the semiconductor device shown in FIG. 14 will be described. In the present structure, writing is performed for each row, and reading is performed for each column.

When writing the memory cells 220 (1, j) to 220 (m, j) of the jth row, the first wiring potential Vs is set to 0 V, and the fifth wirings WL(1) to WL(m) are set. At 0 V, the second wiring BL(j) is set to 0 V, and the fourth wiring S2(j) is set to 2V. The third wirings S1(1) to S1(m) are set to 2V in the column in which the material "1" is written, and the third wirings S1(1) to S1(m) are written in the column in which the material "0" is written. ) is set to 0V. Further, when the data is written, the fourth wiring S2(j) is set to 0 V before the potential of the third wiring S1(1) to S1(m) is changed, and the transistor 202 is turned off. In addition, the second wiring that has not been selected is set to 0V, and the fourth wiring that has not been selected is set to 0V.

As a result, in the memory cell in which the data "1" is written, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 becomes about 2 V, and the memory having the data "0" is written. In the cell, the potential of the node A becomes about 0V. In addition, the potential of the node A of the unselected memory cell does not change.

When the memory cells 220 (i, 1) to 220 (i, n) of the i-th column are read, the first wiring is set to 0 V, the fifth wiring WL (i) is set to 2 V, and the fourth wiring is set. S2(1) to S2(n) are set to 0V, the third wiring S1(i) is set to 0V, and is connected to the second wiring BL (1) The readout circuit to BL(n) is in an operating state. For example, reading The data "0" or "1" can be read out in the output circuit depending on the resistance state of the memory cell. In addition, the fifth wiring that has not been selected is set to 0V, and the third wiring that has not been selected is set to 0V. Further, although the second wiring is set to 0 V at the time of writing, the second wiring may be in a floating state or charged to a potential of 0 V or more. Although the third wiring is set to 0 V at the time of reading, the third wiring may be in a floating state or charged to a potential of 0 V or more.

Note that the material "1" and the data "0" are defined for convenience and may be exchanged with each other. In addition, the above operating voltage is just an example. As long as the transistor 201 is in an off state when the data is "0" and the transistor 201 is in an on state when the data is "1", the transistor 202 is turned on at the time of writing and at the time of writing. The operation voltage may be selected such that the transistor 202 is in an off state and the transistor 203 is in an on state at the time of reading. In particular, it is also possible to use the power supply potential VDD of the peripheral logic circuit instead of 2V.

Since the off-state current of the transistor using the oxide semiconductor is extremely small, it is possible to maintain the stored content for an extremely long period of time by using the transistor. That is to say, since the refresh operation is not required, or the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced. In addition, even if there is no power supply, the content can be stored for a long period of time.

In addition, the writing of information does not require a high voltage, and there is no problem of component degradation. Furthermore, depending on the conduction state or the off state of the transistor Line information is written so that high-speed operation can be easily achieved. In addition, there is an advantage that an operation for erasing information required for flash memory or the like is not required.

Further, a transistor using a material other than an oxide semiconductor can achieve a sufficiently fast operation speed, and therefore, by using the transistor, high-speed reading of the stored content can be performed.

(Example 3)

In the present embodiment, an example of the circuit configuration of the storage element different from the second embodiment and an operation thereof will be described.

FIG. 15 shows an example of a circuit diagram of a memory cell included in a semiconductor device. The memory unit 240 shown in FIG. 15 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 201 (first transistor), and a transistor 202 (second A transistor) and a capacitor 204. The transistor 201 is formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

Here, one of the gate electrode of the transistor 201, one of the source electrode and the drain electrode of the transistor 202, and the electrode of the capacitor 204 is electrically connected. In addition, the first wiring and the source electrode of the transistor 201 are electrically connected, the second wiring is electrically connected to the drain electrode of the transistor 201, and the third wiring is connected to the source electrode and the drain electrode of the transistor 202. One is electrically connected, the fourth wiring is electrically connected to the gate electrode of the transistor 202, and the fifth wiring is electrically connected to the other of the electrodes of the capacitor 204.

Hereinafter, the operation of the circuit will be specifically described.

When data is written to the memory unit 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When the data "1" is written, the third wiring is set to 2V, and when the data "0" is written, the third wiring is set to 0V. At this time, the transistor 202 is in an on state. Further, when the data is written, the fourth wiring is set to 0 V and the transistor 202 is turned off before the potential of the third wiring changes.

As a result, after writing the material "1", the potential of the node connected to the gate electrode of the transistor 201 (hereinafter, referred to as node A) becomes about 2 V, and after writing the material "0", the potential of the node A Becomes about 0V.

When reading data from the memory unit 240, the first wiring is set to 0V, the fifth wiring is set to 2V, the fourth wiring is set to 0V, and the third wiring is set to 0V, so that the second wiring is connected to the second wiring. The readout circuitry is in an operational state. At this time, the transistor 202 is in an off state.

Hereinafter, the state of the transistor 201 when the fifth wiring is set to 2 V will be described. The potential of the node A for determining the state of the transistor 201 depends on the capacitance C1 between the fifth wiring-node A and the gate-source and the capacitance C2 between the drains of the transistor 201.

Fig. 16 shows the relationship between the potential of the fifth wiring and the potential of the node A. Here, as an example, C1/C2>>1 in a state where the transistor 201 is turned off, and C1/C2=1 in a state where the transistor 201 is turned on. In addition, the critical value of the transistor 201 is 2.5V. According to FIG. 16, it can be seen that under the condition that the potential of the fifth wiring is 2 V, in the state of the data "0", Node A becomes approximately 2V, but transistor 201 is in an off state. On the other hand, in the state of the data "1", the node A becomes about 3.25 V, so the transistor 201 is in an on state. When the transistor 201 is in the on state, the memory cell is in a low resistance state, and in the case where the transistor 201 is in an off state, the memory cell is in a high resistance state. Therefore, the material "0" or "1" can be read out in the readout circuit depending on the resistance state of the memory cell. Further, when the readout is not performed, that is, when the potential of the fifth wiring is 0 V, the node A becomes approximately 0 V in the state of the material "0", and the node A becomes approximately 2 V in the state of the data "1". In either of the above states, the transistor 201 is in an off state.

Further, although the third wiring is set to 0 V at the time of reading, the third wiring may be placed in a floating state or charged to a potential higher than 0V. The data "1" and the data "0" are defined for convenience and may be exchanged with each other.

In addition, the above operating voltage is just an example. Regarding the potential of the third wiring at the time of writing, the data "1" or the data is selected in the range in which the transistor 201 is in the off state when the transistor 202 is in the off state after writing and the potential of the fifth wiring is 0V. The potential of "0" can be. The potential of the fifth wiring at the time of reading may be selected such that the transistor 201 is in an off state when the data is "0" and the transistor 201 is in an on state when the data is "1". In addition, the threshold voltage of the transistor 201 is just an example. Any threshold value can be employed as long as the range of the state of the above-described transistor 201 is not changed.

A semiconductor device according to an embodiment of the present invention shown in FIG. 17 includes: m fifth wirings and fourth wirings; n second wirings and third wirings; and a plurality of memory cells 240 (1, 1) to 240 (m, n) is a memory cell array 250 of a matrix shape in which m (columns) × n (rows) (m, n are natural numbers); and driving of peripheral circuits such as second wiring and third wiring The circuit 211, the fourth wiring and the fifth wiring drive circuit 213, and the readout circuit 212. As other peripheral circuits, a refresh circuit or the like may be provided.

As each memory unit, the memory unit 240 (i, j) is taken as a typical example. Here, the memory unit 240 (i, j) (i is an integer of 1 to m, and j is an integer of 1 or more and n or less) is connected to the second wiring BL(i), the third wiring S1(j), and the Five wirings WL(i), fourth wirings S2(i), and first wirings. The first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are connected to the driving circuit 211 and the reading circuit 212 of the second wiring and the third wiring, and the fifth The wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the driving circuits 213 of the fourth wiring and the fifth wiring.

Hereinafter, the operation of the semiconductor device shown in FIG. 17 will be described. In this configuration, writing and reading are performed for each column.

When writing the memory cells 240 (i, 1) to 240 (i, n) of the i-th column, the first wiring potential Vs is set to 0 V, and the fifth wiring WL (i) is set to 0 V. The two wirings BL(1) to BL(n) are set to 0V, and the fourth wiring S2(i) is set to 2V. At this time, electricity The crystal 202 is in an on state. The third wirings S1(1) to S1(n) are set to 2V in the row in which the material "1" is written, and the third wirings S1(1) to S1(n) are written in the row in which the material "0" is written. ) is set to 0V. Further, when the data is written, the fourth wiring S2(i) is set to 0 V before the potential of the third wiring S1(1) to S1(n) changes, and the transistor 202 is turned off. In addition, the fifth wiring that has not been selected is set to 0V, and the fourth wiring that has not been selected is set to 0V.

As a result, in the memory cell in which the data "1" is written, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 becomes about 2 V, and the memory having the data "0" is written. In the cell, the potential of the node A becomes about 0V. In addition, the potential of the node A of the unselected memory cell does not change.

When the memory cells 240 (i, 1) to 240 (i, n) of the i-th column are read, the first wiring potential Vs is set to 0 V, and the fifth wiring WL (i) is set to 2 V. The four wirings S2(i) are set to 0V, and the third wirings S1(1) to S1(n) are set to 0V, and the readout circuits connected to the second wirings BL(1) to BL(n) are placed at Operating status. At this time, the transistor 202 is in an off state. In addition, the fifth wiring that has not been selected is set to 0V, and the fourth wiring that has not been selected is set to 0V.

Hereinafter, the state of the transistor 201 at the time of reading will be described. As described above, if C1/C2>>1 in the state where the transistor 201 is turned off and C1/C2=1 in the state where the transistor 201 is turned on, the relationship between the potential of the fifth wiring and the potential of the node A It is shown in Figure 16. In addition, the transistor The threshold voltage of 201 is 2.5V. In the memory cell that has not been selected, since the fifth wiring potential becomes 0V, the node A of the memory cell having the material "0" becomes about 0V, and the node A of the memory cell having the data "1" becomes about 2V, In either of the above states, the transistor 201 is in an off state. In the memory cell of the i-th column, since the fifth wiring potential becomes 2V, the node A of the memory cell having the material "0" becomes about 2V, and the transistor 201 is turned off, but the memory of the data "1" is present. The node A of the cell becomes approximately 3.25V, leaving the transistor 201 in an on state. When the transistor 201 is in the on state, the memory cell is in a low resistance state, and in the case where the transistor 201 is in an off state, the memory cell is in a high resistance state. As a result, in the memory cell of the i-th column, only the memory cell having the data "0" is in a low resistance state. The readout circuit can read the material "0" or "1" depending on the load resistance connected to the second wiring.

Further, although the third wiring is set to 0 V at the time of reading, the third wiring may be placed in a floating state or charged to a potential higher than 0V. The data "1" and the data "0" are defined for convenience and may be exchanged with each other.

In addition, the above operating voltage is just an example. Regarding the potential of the third wiring at the time of writing, the data "1" or the data "" is selected as long as the transistor 202 is in the off state after writing and the transistor 201 is in the off state when the potential of the fifth wiring is 0V. 0" potential, you can. Regarding the potential of the fifth wiring at the time of reading, the transistor 201 is turned on when the data "1" is at the time when the transistor 201 is in the off state at the material "0". The state of the way to select the potential, you can. In addition, the threshold voltage of the transistor 201 is just an example. Any threshold value can be employed as long as the range of the state of the above-described transistor 201 is not changed.

Since the off-state current of the transistor using the oxide semiconductor is extremely small, it is possible to maintain the stored content for an extremely long period of time by using the transistor. That is to say, since the refresh operation is not required, or the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced. In addition, even if there is no power supply, the content can be stored for a long period of time.

In addition, the writing of information does not require a high voltage, and there is no problem of component degradation. Furthermore, information writing is performed according to the on state or the off state of the transistor, so that high speed operation can be easily realized. In addition, there is an advantage that an operation for erasing information required for flash memory or the like is not required.

Further, a transistor using a material other than an oxide semiconductor can achieve a sufficiently fast operation speed, and therefore, by using the transistor, high-speed reading of the stored content can be performed.

Next, another example of the circuit configuration of the storage element and its operation according to an embodiment of the present invention will be described.

FIG. 18 shows an example of a memory cell circuit included in a semiconductor device. The memory unit 260 shown in FIG. 18 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 201, a transistor 202, and a capacitor 204. The transistor 201 is formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

In the circuit of the memory unit 260 shown in FIG. 18, the directions of the third wiring and the fourth wiring are different from those of the memory unit 240 shown in FIG. That is, in the memory cell 260 circuit shown in FIG. 18, the third wiring is disposed in the direction (column direction) of the fifth wiring, and the fourth wiring is disposed in the direction (row direction) of the second wiring.

Here, one of the gate electrode of the transistor 201, one of the source electrode and the drain electrode of the transistor 202, and the electrode of the capacitor 204 is electrically connected. Further, the first wiring is electrically connected to the source electrode of the transistor 201, the second wiring is electrically connected to the drain electrode of the transistor 201, and the third wiring is connected to the source electrode and the drain electrode of the transistor 202. One is electrically connected, the fourth wiring is electrically connected to the gate electrode of the transistor 202, and the fifth wiring is electrically connected to the other of the electrodes of the capacitor 204.

Since the operation of the circuit of the memory unit 260 shown in FIG. 18 is the same as the operation of the circuit of the memory unit 240 shown in FIG. 15, the detailed description is omitted.

Figure 19 shows a block circuit diagram of a semiconductor device in accordance with one embodiment of the present invention having a storage capacity of m x n bits.

A semiconductor device according to an embodiment of the present invention includes: m third wirings and fifth wirings; n second wirings and fourth wirings; and a plurality of memory cells 260 (1, 1) to 260 (m, n) a memory cell array 270 of a matrix shape arranged in a vertical m (column) × horizontal n (row) (m, n is a natural number); and a peripheral circuit such as a second wiring and a fourth wiring driving circuit 231, a third The wiring circuit and the fifth wiring drive circuit 233 and the read circuit 232. As other peripheral circuits, a refresh circuit or the like may be provided.

In the semiconductor device shown in FIG. 19, the direction of the third wiring and the fourth wiring is different from that of the semiconductor device shown in FIG. That is, in the semiconductor device shown in FIG. 19, the third wiring is disposed in the direction (column direction) of the fifth wiring, and the fourth wiring is disposed in the direction (row direction) of the second wiring.

As each memory unit, the memory unit 260 (i, j) is taken as a typical example. Here, the memory unit 260(i, j) (i is an integer of 1 to m, and j is an integer of 1 to n) is connected to the second wiring BL(j), the fourth wiring S2(j), and the fifth wiring, respectively. WL(i), third wiring S1(i), and first wiring. The first wiring potential Vs is applied to the first wiring. Further, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2(n) are connected to the driving circuit 231 and the reading circuit 232 of the second wiring and the fourth wiring, and the fifth The wirings WL(1) to WL(m) and the third wirings S1(1) to S1(m) are connected to the driving circuits 233 of the third wiring and the fifth wiring.

The operation of the semiconductor device shown in FIG. 19 is the same as the operation of the semiconductor device shown in FIG. 17, and detailed description thereof will be omitted.

Since the off-state current of the transistor using the oxide semiconductor is extremely small, it is possible to maintain the stored content for an extremely long period of time by using the transistor. That is to say, since the refresh operation is not required, or the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced. In addition, even if there is no power supply, the content can be stored for a long period of time.

In addition, the writing of information does not require high voltage, and there is no component retreat. Problem. Furthermore, information writing is performed according to the on state or the off state of the transistor, so that high speed operation can be easily realized. In addition, there is an advantage that an operation for erasing information required for flash memory or the like is not required.

Further, a transistor using a material other than an oxide semiconductor can achieve a sufficiently fast operation speed, and therefore, by using the transistor, high-speed reading of the stored content can be performed.

(Example 4)

In the present embodiment, an example of the circuit configuration of the storage element different from the second and third embodiments and an operation thereof will be described.

20A and 20B show an example of a circuit diagram of a memory cell which the semiconductor device has. Compared with the memory unit 200 shown in FIG. 10 and the memory unit 220 shown in FIG. 13, the memory unit 280a shown in FIG. 20A and the memory unit 280b shown in FIG. 20B have a first transistor and a third transistor, respectively. A structure in which the relationships of series connections are exchanged with each other.

Here, in the memory unit 280a shown in FIG. 20A, the gate electrode of the transistor 201 is electrically connected to one of the source electrode and the drain electrode of the transistor 202. Further, the first wiring is electrically connected to the source electrode of the transistor 203, and the drain electrode of the transistor 203 is electrically connected to the source electrode of the transistor 201. Further, the second wiring is electrically connected to the drain electrode of the transistor 201, the third wiring is electrically connected to the other of the source electrode and the drain electrode of the transistor 202, and the gate of the fourth wiring and the transistor 202 is connected. The electrode electrodes are electrically connected, and the fifth wiring is electrically connected to the gate electrode of the transistor 203.

Compared with the memory cell circuit shown in FIG. 20A, in the memory cell 280b shown in FIG. 20B, the directions of the third wiring and the fourth wiring are different. That is, in the memory cell circuit shown in FIG. 20B, the fourth wiring is disposed in the direction (row direction) of the second wiring, and the third wiring is disposed in the direction (column direction) of the fifth wiring.

Since the operations of the circuits of the memory unit 280a shown in FIG. 20A and the memory unit 280b shown in FIG. 20B are the same as those of the memory unit 200 shown in FIG. 10 and the memory unit 220 shown in FIG. 13, the detailed operation is omitted. Description.

(Example 5)

In the present embodiment, an example of the circuit configuration of the storage element different from the second to fourth embodiments and an operation thereof will be described.

FIG. 21 shows an example of a circuit diagram of a memory cell included in a semiconductor device. The circuit of the memory unit 290 shown in FIG. 21 has a structure having a capacitor between the node A and the first wiring, compared to the circuit of the memory unit 200 shown in FIG.

The memory unit 290 shown in FIG. 21 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 201, a transistor 202, a transistor 203, and a capacitor 205. The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

Here, one of the gate electrode of the transistor 201, the source electrode and the drain electrode of the transistor 202, and the electrode of the capacitor 205 One is an electrical connection. Further, the other of the first wiring, the source electrode of the transistor 201, and the electrode of the capacitor 205 is electrically connected, and the drain electrode of the transistor 201 is electrically connected to the source electrode of the transistor 203. In addition, the second wiring is electrically connected to the drain electrode of the transistor 203, the third wiring is electrically connected to the other of the source electrode and the drain electrode of the transistor 202, and the gate of the fourth wiring and the transistor 202 is connected. The electrode electrodes are electrically connected, and the fifth wiring is electrically connected to the gate electrode of the transistor 203.

Since the operation of the memory cell circuit shown in FIG. 21 is the same as the operation of the memory cell circuit shown in FIG. 10, detailed description is omitted. By having the above capacitor 205, the retention characteristics are improved.

(Example 6)

Hereinafter, an example of a readout circuit included in a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

The readout circuit shown in Fig. 22 has a transistor 206 and a differential amplifier.

At the time of reading the data, the terminal A is connected to the second wiring to which the memory unit to which the data is read is connected. In addition, a bias voltage Vbias is applied to the gate electrode of the transistor 206 to flow a predetermined current.

The memory unit has different resistances depending on the stored data "1" / "0". In particular, the memory cell is in a low resistance state when the transistor 201 of the selected memory cell is in an on state, and the memory cell is in a high resistance state when the transistor 201 of the selected memory cell is in an off state.

When the memory cell is in the high resistance state, the potential of the terminal A is higher than the reference potential Vref, and the data "1" is output from the output of the differential amplifier. On the other hand, when the memory cell is in the low resistance state, the potential of the terminal A is lower than the reference potential Vref, and the data "0" is output from the output of the differential amplifier.

As such, the readout circuitry can read data from the memory unit. Further, the readout circuit of this embodiment is just an example, and other known circuits may be used. For example, it is also possible to have a precharge circuit. It is also possible to adopt a structure in which a reference second wiring is connected instead of the reference potential Vref. It is also possible to use a latch type sense amplifier instead of a differential amplifier.

(Example 7)

In the present embodiment, an example of an electronic apparatus mounted with the semiconductor device obtained according to the above embodiment will be described with reference to Figs. 23A to 23F. The semiconductor device obtained according to the above embodiment can hold information even if there is no power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, the semiconductor device can be used to provide an electronic device having a new structure. In addition, the semiconductor device according to the above embodiment is integrated and mounted on a circuit substrate or the like, and is mounted inside each electronic device.

23A shows a notebook type personal computer including the semiconductor device according to the above embodiment, which includes a main body 301, a casing 302, a display portion 303, a keyboard 304, and the like. By applying a semiconductor device according to an embodiment of the present invention to a notebook type personal computer, it can be maintained even without power supply News. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, the semiconductor device according to one embodiment of the present invention is preferably applied to a notebook type personal computer.

23B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment, in which a display portion 313, an external interface 315, an operation button 314, and the like are provided in the main body 311. Further, as an operation accessory, there is a stylus 312. By applying the semiconductor device according to an embodiment of the present invention to a PDA, information can be held even without power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, a semiconductor device according to an embodiment of the present invention is preferably applied to a PDA.

As an example of the electronic paper including the semiconductor device according to the above embodiment, FIG. 23C shows the electronic book reader 320. The e-book reader 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrally formed by the shaft portion 337, and can be opened and closed with the shaft portion 337 as an axis. With this configuration, the e-book reader 320 can be used like a paper book. By applying the semiconductor device according to an embodiment of the present invention to electronic paper, information can be held even without power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, a semiconductor device according to an embodiment of the present invention is preferably applied to electronic paper.

A display portion 325 is attached to the housing 321 and a display portion 327 is attached to the housing 323. The display unit 325 and the display unit 327 can display a screen or a different screen (that is, display one image or a different image). By mining With the configuration for displaying different screens, for example, an article can be displayed on the display unit on the right side (display portion 325 in FIG. 23C), and an image can be displayed on the display portion on the left side (display portion 327 in FIG. 23C).

In addition, an example in which the casing 321 is provided with an operation portion and the like is shown in FIG. 23C. For example, the housing 321 includes a power source 331, an operation key 333, a speaker 335, and the like. With the operation key 333, the page can be turned. Note that a keyboard, a pointing device, or the like can be disposed on the same plane as the display portion of the casing. In addition, a structure such as an external connection terminal (a headphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like may be provided on the back surface and the side surface of the casing. . Furthermore, the e-book reader 320 may also have the function of an electronic dictionary.

In addition, the e-book reader 320 can also adopt a structure that transmits and receives information in a wireless manner. It is also possible to adopt a structure in which a desired book material or the like is purchased from an electronic book server in a wireless manner and then downloaded.

In addition, electronic paper can be used in electronic devices in all areas where information is displayed. For example, in addition to the application of electronic paper to an e-book reader, it can be applied to a car advertisement of a vehicle such as a poster or a train, a display of various cards such as a credit card, and the like.

Fig. 23D shows a mobile phone including the semiconductor device according to the above embodiment. The mobile phone is composed of a housing 340 and two housings of the housing 341. The casing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a photographing lens 347, an external connection terminal 348, and the like. Further, the casing 340 is provided with a solar battery unit 349 that performs charging of the mobile phone, an external storage slot 350, and the like. In addition, the antenna is inside It is placed in the housing 341. By applying the semiconductor device according to an embodiment of the present invention to a mobile phone, information can be held even without power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, a semiconductor device according to an embodiment of the present invention is preferably applied to a mobile phone.

The display panel 342 has a touch panel function, and FIG. 23D shows a plurality of operation keys 345 displayed using dashed lines. Further, the mobile phone is equipped with a booster circuit for boosting the voltage output from the solar battery cell 349 to a voltage required for each circuit. Further, in addition to the above configuration, a non-contact IC chip, a small recording device, or the like can be mounted.

The display panel 342 appropriately changes the direction of display according to the usage mode. In addition, since the photographing lens 347 is provided on the same surface as the display panel 342, a visual call can be made. The speaker 343 and the microphone 344 are not limited to voice calls, and can also be used for video call, recording, reproduction, and the like. Further, the casing 340 and the casing 341 are slid and can be in an unfolded state and an overlapped state as shown in FIG. 23D, and can be miniaturized for carrying.

The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable, so the mobile phone can be charged or data can be communicated. In addition, the recording medium is inserted into the external storage slot 350 to store and move data corresponding to a larger capacity. In addition, the mobile phone may have an infrared communication function, a television reception function, and the like in addition to the above functions.

23E shows a digital device including the semiconductor device according to the above embodiment camera. The digital camera includes a main body 361, a display portion A367, a viewfinder 363, an operation switch 364, a display portion B365, a battery 366, and the like. By applying a semiconductor device according to an embodiment of the present invention to a digital camera, information can be held even without power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, a semiconductor device according to an embodiment of the present invention is preferably applied to a digital camera.

Fig. 23F shows a television device including the semiconductor device according to the above embodiment. A display portion 373 is attached to the casing 371 of the television device 370. The map can be displayed by the display unit 373. Further, a structure in which the housing 371 is supported by the bracket 375 is shown here.

The operation of the television device 370 can be performed by using an operation switch provided in the casing 371 and a separately provided remote controller 380. The channel and volume can be controlled by the operation keys 379 provided in the remote controller 380, and the image displayed on the display unit 373 can be controlled. Further, a configuration in which the display unit 377 that displays information output from the remote controller 380 is provided in the remote controller 380 may be employed. By applying the semiconductor device according to an embodiment of the present invention to a television device, information can be held even without power supply. In addition, degradation caused by writing and erasing does not occur. Moreover, its operation speed is fast. Thus, a semiconductor device according to an embodiment of the present invention is preferably applied to a television device.

Further, the television device 370 is preferably provided with a receiver, a data machine, and the like. A general television broadcast can be received by the receiver. In addition, when the display device is connected to the communication network via a data machine by wire or wirelessly, the executable device Information communication in one direction (from transmitter to receiver) or bidirectional (between transmitter to receiver or between receivers).

The structure, method, and the like shown in this embodiment can be used in combination with any of the structures, methods, and the like shown in the other embodiments.

The present application is made based on Japanese Patent Application No. 2009-251261, filed on Jan.

160‧‧‧Optoelectronics

162‧‧‧Optoelectronics

3rd Line‧‧‧3rd wiring (first signal line)

4th Line‧‧‧fourth wiring (second signal line)

2nd Line‧‧‧Second wiring (bit line)

1st Line‧‧‧First wiring (source line)

Claims (7)

A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a plurality of storage elements connected in parallel between the first wiring and the second wiring; One of the plurality of storage elements includes: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; having a second gate electrode, a second source electrode, and a second electrode a second transistor of the pole electrode; and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode, wherein the first transistor is disposed in the substrate including the semiconductor material, wherein The second transistor includes an oxide semiconductor layer including indium, gallium, and zinc, wherein the first gate electrode and one of the second source electrode and the second drain electrode An electrical connection, wherein the first wiring is electrically connected to the first source electrode, wherein the first drain electrode is electrically connected to the third source electrode, wherein the second wiring and the third drain electrode Electrical connection, wherein The third wiring is electrically connected to the other of the second source electrode and the second drain electrode, wherein the fourth wiring is electrically connected to the second gate electrode, wherein the fifth wiring and the The third gate electrode is electrically connected thereto, wherein the oxide semiconductor layer includes a crystalline portion, wherein the crystalline portion includes a crystal grain whose C axis is aligned in a direction perpendicular to a surface of the oxide semiconductor layer, and wherein the second electricity The off current of the crystal is 1 × 10 ^-13 A or less. The semiconductor device according to the first aspect of the invention, wherein the third transistor comprises: a channel formation region provided in the substrate including the semiconductor material; an impurity region sandwiching the channel formation region therebetween; Forming a third gate insulating layer over the region; the third gate electrode over the third gate insulating layer, and the third source electrode and the third drain electrically connected to the impurity region electrode. A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a plurality of storage elements connected in parallel between the first wiring and the second wiring; One of the plurality of storage elements includes: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; having a second gate electrode, a second source electrode, and a second electrode a second transistor of the electrode; and a capacitor, wherein the first transistor is disposed in a substrate comprising a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer comprising indium, gallium, and a zinc, wherein one of the electrodes of the capacitor is electrically connected to one of the first gate electrode, the second source electrode, and the second drain electrode, wherein the first wiring and the first a source electrode is electrically connected, wherein the second wiring is electrically connected to the first drain electrode, wherein the third wiring is electrically connected to the other of the second source electrode and the second drain electrode , which, the first The fourth wiring is electrically connected to the second gate electrode, wherein the fifth wiring is electrically connected to the other of the electrodes of the capacitor, wherein the oxide semiconductor layer comprises a crystalline portion, wherein the crystalline portion comprises a C-axis The crystal grains aligned in a direction perpendicular to a surface of the oxide semiconductor layer, and wherein the second transistor has an off current of 1 × 10 ^-13 A or less. The semiconductor device according to any one of claims 1 to 2, wherein the first transistor comprises: a channel formation region provided in the substrate including the semiconductor material; and the channel is formed therebetween An impurity region of the region; a first gate insulating layer over the channel formation region; the first gate electrode over the first gate insulating layer; and the first source electrically connected to the impurity region a pole electrode and the first drain electrode. The semiconductor device according to any one of claims 1 to 2, wherein the second transistor comprises: the second gate electrode over the substrate including the semiconductor material; a second gate insulating layer over the gate electrode; the oxide semiconductor layer over the second gate insulating layer; and the second source electrode and the second electrode electrically connected to the oxide semiconductor layer Bottom electrode. According to the semi-guideline of any of the scopes 1, 2 and 3 of the patent application The body device, wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate. The semiconductor device according to any one of claims 1 to 2, wherein the second transistor is disposed over the first transistor and between the second transistor and the first transistor An insulating film is disposed, wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode through a conductive layer, and wherein the conductive layer and the second gate electrode It is formed by processing a common conductive film.