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TWI527177B - 晶片構件與晶片封裝體 - Google Patents

晶片構件與晶片封裝體 Download PDF

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Publication number
TWI527177B
TWI527177B TW102146859A TW102146859A TWI527177B TW I527177 B TWI527177 B TW I527177B TW 102146859 A TW102146859 A TW 102146859A TW 102146859 A TW102146859 A TW 102146859A TW I527177 B TWI527177 B TW I527177B
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TW
Taiwan
Prior art keywords
wafer
disposed
chip package
substrate
pad
Prior art date
Application number
TW102146859A
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English (en)
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TW201526187A (zh
Inventor
陳伯欽
黃祿珍
Original Assignee
相豐科技股份有限公司
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Publication date
Application filed by 相豐科技股份有限公司 filed Critical 相豐科技股份有限公司
Priority to TW102146859A priority Critical patent/TWI527177B/zh
Priority to US14/576,132 priority patent/US20150171041A1/en
Publication of TW201526187A publication Critical patent/TW201526187A/zh
Application granted granted Critical
Publication of TWI527177B publication Critical patent/TWI527177B/zh

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1329—Protecting the fingerprint sensor against damage caused by the finger
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Description

晶片構件與晶片封裝體
本發明是有關於一種晶片構件(chip element)，且特別是有關於一種晶片封裝體(chip package)。
在半導體產業中，積體電路(integrated circuits，IC)的生產主要可分為三個階段：積體電路的設計(IC design)、積體電路的製作(IC process)及積體電路的封裝(IC package)。
在積體電路的製作中，晶片(chip)是經由晶圓(wafer)製作、形成積體電路以及切割晶圓(wafer sawing)等步驟而完成。晶圓具有一主動面(active surface)，其泛指晶圓之具有主動元件(active element)的表面。當晶圓內部之積體電路完成之後，晶圓之主動面上更配置有多個接墊(pad)，以使最終由晶圓切割所形成的晶片可經由這些接墊而向外電性連接於一承載器(carrier)。承載器例如為一導線架(leadframe)或一基板(substrate)。晶片的這些接墊可以透過打線接合技術(wire bonding technology)或覆晶接合技術(flip-chip bonding technology)而電性連接至承載器之多個接點(contact)，以構成一晶片封裝體。
就覆晶接合技術而言，首先，是於配置在晶圓之主動面上的 多個接墊上，分別形成多個導電凸塊(conductive bump)。在晶圓切割之後，以將晶片之主動面朝向基板的方式將晶片配置於基板上，並且利用這些導電凸塊而將晶片的這些接墊分別電性連接至基板的這些接點。由於這些導電凸塊通常以面陣列(area array)的方式排列於晶片之主動面上，因此覆晶接合技術可適於運用在高接點數及高接點密度之晶片封裝體。此外，相較於打線接合技術，由於各個導電凸塊可提供晶片與基板之間較短的電性傳輸路徑，因此覆晶接合技術可提升晶片封裝體之電性效能(electrical performance)。
然而，導電凸塊之材質通常為金或錫鉛合金。導電凸塊的材質若為金，則晶片與基板通常以熱壓合的方式連接，使得晶片與基板之間的連接強度較差且金的價格較貴。在此必須說明的是，導電凸塊的材質若為金，則無法以使用焊錫(soldering tin)作為焊料(solder)的焊接方式讓金凸塊與基板之接點電性連接，因為焊錫中的錫最終會完全取代金凸塊中的金。導電凸塊的材質若為錫鉛合金，則導電凸塊彼此之間的間距(pitch)較大且導電性與導熱性較差。
本發明之目的在於提供一種晶片封裝體，其中外表面的一部分配置有抗氧化層(anti-oxidation layer)的銅凸塊(copper bump)是用來電性連接晶片與基板。
本發明之目的在於提供一種晶片構件，其具有外表面配置有抗氧化層的銅凸塊。
本發明提供一種晶片封裝體，包括一基板、一晶片、至少一 電性連接件(electrical connecting element)與一焊料層(solder layer)。基板具有至少一接點。晶片配置於基板上，且具有至少一接墊。電性連接件包括一銅凸塊與一抗氧化層。銅凸塊配置於接墊上，抗氧化層配置於銅凸塊不與接墊連接的一外表面的至少一部份上。焊料層配置於銅凸塊與接點之間。接墊藉由電性連接件與焊料層而電性連接至接點。
在本發明一實施例中，抗氧化層的材質為錫、金、銀、或有機保焊劑(organic solderability preservative，OSP)。
在本發明一實施例中，抗氧化層是以化學電鍍、浸泡、或噴塗的方式形成。
在本發明一實施例中，晶片為一指紋辨識晶片(fingerprint identification chip)，其具有一二維感測區域，並且基板具有一貫穿口(through opening)，其對應於二維感測區域。
在本發明一實施例中，晶片封裝體更包括一保護層(protective layer)，配置於二維感測區域上。此外，保護層之材質可包括奈米鑽石(nanodiamond)。
在本發明一實施例中，基板更具有至少一應力釋放孔(stress-releasing hole)，其連接貫穿口之一角落。
本發明提供一種晶片構件，包括一晶片與至少一電性連接件。晶片具有至少一接墊。電性連接件包括一銅凸塊與一抗氧化層。銅凸塊配置於接墊上，抗氧化層配置於銅凸塊不與接墊連接的一外表面上。
在本發明一實施例中，抗氧化層的材質為錫、金、銀、或有機保焊劑。
在本發明一實施例中，抗氧化層是以化學電鍍、浸泡、或噴塗的方式形成。
在本發明一實施例中，晶片為一指紋辨識晶片，其具有一二維感測區域。
相較於習知技術所使用之金凸塊，本發明實施例之晶片構件或晶片封裝體的銅凸塊在價格上較為便宜，且晶片封裝體的晶片與基板之間經由焊接(通常使用焊料之材質為錫)而連接的強度較強。此外，相較於習知技術所使用之錫鉛凸塊，本發明實施例之銅凸塊具有較好的散熱與導電特性，並且銅凸塊彼此之間的間距可較小。另外，由於在本發明實施例之晶片構件或晶片封裝體的製作過程中，在銅凸塊不與接墊連接的外表面上配置抗氧化層，所以銅凸塊較不容易在晶片構件或晶片封裝體的製作過程中氧化。
參考以下說明及隨附申請專利範圍或利用如下文所提之本發明的實施方式，即可更加明瞭本發明的這些特色及優點。
200、400、600‧‧‧晶片封裝體
210、410、610‧‧‧基板
212‧‧‧介電層
212a、212b‧‧‧表面
214‧‧‧線路層
214a、414a、614a‧‧‧接點
216、616‧‧‧貫穿口
220、420、620‧‧‧晶片
222、422‧‧‧接墊
224、624‧‧‧二維感測區域
230、430、630‧‧‧電性連接件
232、432‧‧‧銅凸塊
232a、432a‧‧‧外表面
234、434‧‧‧抗氧化層
240、440‧‧‧焊料層
250‧‧‧底膠
300‧‧‧晶片構件
616a‧‧‧角落
618‧‧‧應力釋放孔
660‧‧‧保護層
B2、B4‧‧‧底面部分
S2、S4‧‧‧側面部分
圖1A繪示本發明一實施例之一種晶片封裝體的俯視示意圖。
圖1B繪示圖1A之晶片封裝體沿著線I-I的剖面示意圖。
圖2繪示本發明第二實施例之一種晶片封裝體的剖面示意圖。
圖3A繪示本發明第三實施例之一種晶片封裝體的剖面示意圖。
圖3B繪示圖3A之基板的俯視示意圖。
【第一實施例】
圖1A繪示本發明第一實施例之一種晶片封裝體的俯視示意圖。圖1B繪示圖1A之晶片封裝體沿著線I-I的剖面示意圖。請參考圖1A與圖1B，本實施例之晶片封裝體200包括一基板210、一晶片220、至少一電性連接件230(圖1A與圖1B示意地繪示多個)與一焊料層240。基板210包括一介電層212與至少一線路層214(圖1B示意地繪示一層且圖1A省略繪示)，其具有至少一接點214a(圖1B示意地繪示多個)。介電層212的材質可為玻璃、聚醯亞胺樹脂(polyimide，PI)或其他合適的介電材料。線路層214配置介電層212之一表面212a上。本實施例之線路層214除了這些接點214a之外還可包含其他線路，但是並未於圖面中繪示。此外，在另一實施例中，基板210可包括另一線路層，其可配置於介電層212之另一表面212b上，然而上述另一實施例並未以圖面繪示。
晶片220配置於基板210之介電層212之表面212a上，且晶片220具有至少一接墊222(圖1B示意地繪示多個且圖1A省略繪示)。本實施例中，晶片220可為一指紋辨識晶片，其具有一二維感測區域224。就位置關係而言，晶片220之二維感測區域224對應於基板210之一貫穿口216。在此必須說明的是，在晶片220之配置這些接墊222的表面(亦即主動面)上，可配置一保護層(passivation layer)(其暴露出各個接墊222之一部分與二維 感測區域224)，以及在保護層所暴露出的各個接墊222上，可配置一凸塊下金屬層(under bump metal layer，UBM layer)，然而上述保護層與凸塊下金屬層並未以圖面繪示。
各個電性連接件230包括一銅凸塊232與一抗氧化層234。各個電性連接件230中，銅凸塊232配置於接墊222的其中之一上，抗氧化層234配置於銅凸塊232的一外表面232a上，並且此銅凸塊232的外表面232a是不與此銅凸塊232所配置的接墊222連接。本實施例各個抗氧化層234的材質為錫或銀。若各個抗氧化層234的材質為錫，則各個抗氧化層234可以化學電鍍或噴塗的方式形成。若各個抗氧化層234的材質為銀，則各個抗氧化層234可以化學電鍍的方式形成。晶片220與這些電性連接件230可視為一晶片構件300，且晶片220與基板210之間可配置底膠(underfill)250，以包覆與保護這些電性連接件230。
焊料層240配置於各個銅凸塊232與對應的接點214a之間。各個接墊222藉由這些電性連接件230的其中之一與焊料層240而電性連接至這些接點214a的其中之一。在此必須說明的是，若各個抗氧化層234的材質為錫，且焊料層240的材料為錫，則各個抗氧化層234在對應之銅凸塊232之外表面232a的底面部分B2上的那部分的與焊料層240之間接合的界線將不甚明顯。然而，在各個銅凸塊232之外表面232a的側面部分S2(亦即各個銅凸塊232之外表面232a其不用來與對應之接墊222以及對應之接點214a連接的那部分)上仍可明顯察覺對應之抗氧化層234的存在。若各個抗氧化層234的材質為銀，則各個抗氧化層234與焊料層240之間接合的界線將較為明顯。因此，本實施例中，為了示意地表示上述狀況，圖1B中各個抗氧化層234與焊料層240之間接合的界線以虛線表示。
在此簡述本實施例晶片封裝體的製作方法。在切割晶圓(未繪示)以形成各個晶片220之前，這些銅凸塊232分別形成於晶圓之這些接墊222之上且各個抗氧化層234形成於對應之銅凸塊232之暴露於外的外表面232a上，使得多個電性連接件230得以形成。接著，將配置有這些電性連接件230的晶圓進行切割，使得單體化的各個晶片構件300(包含對應的晶片220與對應的這些電性連接件230)得以形成。接著，在一陣列基板(未繪示)的所有接點214a上形成焊料層240。然後，將這些晶片構件300藉由覆晶接合技術與焊接技術而分別配置於陣列基板的多個預定區域，使得這些晶片220之這些接墊222與陣列基板之這些接點214a藉由焊料層240與這些電性連接件230而電性連接。接著，這些晶片220與陣列基板之間可形成底膠250，以包覆與保護這些電性連接件230。最後，切割陣列基板以分離出多個基板210，使得包含對應之晶片構件300與對應之基板210的各個晶片封裝體200得以形成。
相較於習知技術所使用之金凸塊，本實施例之晶片封裝體200的銅凸塊232在價格上較為便宜，且晶片220與基板210之間經由焊接(通常使用焊料之材質為錫)而連接的強度較強。此外，相較於習知技術所使用之錫鉛凸塊，銅凸塊232具有較好的散熱與導電特性，並且銅凸塊232彼此之間的間距可較小。另外，由於在晶片構件300或晶片封裝體200的製作過程中，在銅凸塊232不與接墊222連接的外表面232a上配置抗氧化層234,所以銅凸塊232較不容易在晶片構件300或晶片封裝體200的製作過程中氧化。
【第二實施例】
圖2繪示本發明第二實施例之一種晶片封裝體的剖面示意圖。請參考圖2，本實施例之晶片封裝體400與第一實施例之晶片封裝體200 的不同之處在於，本實施例之晶片封裝體400的這些抗氧化層434的材質為金或有機保焊劑。若各個抗氧化層434的材質為金，則各個抗氧化層434可以化學電鍍的方式形成。若各個抗氧化層434的材質為絕緣的有機保焊劑，則各個抗氧化層434可以浸泡的方式形成。
在此必須說明的是，若各個抗氧化層434的材質為金或有機保焊劑，且焊料層440的材料為錫，則各個電性連接件430中，抗氧化層434通常只在銅凸塊432之外表面432a的側面部分S4(亦即各個銅凸塊432之外表面432a其不用來與對應之接墊422以及對應之接點414a連接的那部分)上。在此必須說明的是，在將晶片420與基板410的接合之前，各個電性連接件430中抗氧化層434是形成於銅凸塊432不與對應之接墊422連接的整個外表面432a上。然而，晶片420與基板410的接合之後，各個電性連接件430中，例如為錫的焊料層440通常會取代或去除位於銅凸塊432之外表面432a的底面部分B4的部分抗氧化層434，使得殘留的抗氧化層434通常只在銅凸塊432之外表面432a的側面部分S4上。
【第三實施例】
圖3A繪示本發明第三實施例之一種晶片封裝體的剖面示意圖。圖3B繪示圖3A之基板的俯視示意圖。請參考圖3A與圖3B，本實施例之晶片封裝體600與第一實施例之晶片封裝體200的不同之處在於，本實施例之晶片封裝體600更包括配置於晶片620之二維感測區域624上的一保護層(protective layer)660，且基板610更具有至少一應力釋放孔618(圖3B示意地繪示多個)。保護層660之材質可包括奈米鑽石(nanodiamond)，其具有高效防水防污之功能。
各個應力釋放孔618連接貫穿口616之一角落616a。本實施例 中，就圖3B之視角而言，貫穿口616例如為一矩形，其四個角落616a通常為應力集中區域。四個應力釋放孔618分別連接至貫穿孔616的四個角落616a，使得這些電性連接件630藉由焊料層(未繪示)在高溫(若焊料層為錫，則焊接溫度約為攝氏200度)下分別焊接至基板610之這些接點614a(圖3B省略繪示)後，基板610仍可保持預定的平整度而不會過於翹曲。
包括奈米鑽石之保護層與應力釋放孔也可應用於第二實施例，於此不再贅述。
本發明實施例之晶片構件與晶片封裝體具有以下其中之一或其他的優點。相較於習知技術所使用之金凸塊，本發明實施例之晶片構件或晶片封裝體的銅凸塊在價格上較為便宜，且晶片封裝體的晶片與基板之間經由焊接(通常使用焊料之材質為錫)而連接的強度較強。此外，相較於習知技術所使用之錫鉛凸塊，本發明實施例之銅凸塊具有較好的散熱與導電特性，並且銅凸塊彼此之間的間距可較小。另外，由於在本發明實施例之晶片構件或晶片封裝體的製作過程中，在銅凸塊不與接墊連接的外表面上配置抗氧化層，所以銅凸塊較不容易在晶片構件或晶片封裝體的製作過程中氧化。
即使本發明已基於特定具體實施例加以說明，但熟習本技術者如藉由個別具體實施例之特徵的組合及/或交換，可明顯看出許多變化及替代性具體實施例。因此，對於熟習本技術者，不言可喻的是，本發明亦涵蓋此類變化及替代性具體實施例，及本發明範疇僅限制在隨附申請專利範圍及其等效物的意義內。
200‧‧‧晶片封裝體
210‧‧‧基板
212‧‧‧介電層
212a、212b‧‧‧表面
214‧‧‧線路層
214a‧‧‧接點
216‧‧‧貫穿口
220‧‧‧晶片
222‧‧‧接墊
224‧‧‧二維感測區域
230‧‧‧電性連接件
232‧‧‧銅凸塊
232a‧‧‧外表面
234‧‧‧抗氧化層
240‧‧‧焊料層
250‧‧‧底膠
300‧‧‧晶片構件
B2‧‧‧底面部分
S2‧‧‧側面部分

Claims (9)

  1. 一種晶片封裝體，包括：一基板，具有至少一接點、一貫穿口與至少一應力釋放孔，其中該應力釋放孔連接該貫穿口之一角落；一晶片，配置於該基板上且為一指紋辨識晶片，其中該晶片具有至少一接墊與一二維感測區域，並且該貫穿口對應於該二維感測區域；至少一電性連接件，包括：一銅凸塊，配置於該接墊上；以及一抗氧化層，配置於該銅凸塊不與該接墊連接的一外表面的至少一部份上；以及一焊料層，配置於該銅凸塊與該接點之間；其中該接墊藉由該電性連接件與該焊料層而電性連接至該接點。
  2. 一種晶片封裝體，包括：一基板，具有至少一接點與一貫穿口；一晶片，配置於該基板上且為一指紋辨識晶片，其中該晶片具有至少一接墊與一二維感測區域，並且該貫穿口對應於該二維感測區域；至少一電性連接件，包括：一銅凸塊，配置於該接墊上；以及一抗氧化層，配置於該銅凸塊不與該接墊連接的一外表面的至少一部份上；一焊料層，配置於該銅凸塊與該接點之間；以及一保護層，配置於該二維感測區域上，其中該保護層之材質包括奈米鑽石；其中該接墊藉由該電性連接件與該焊料層而電性連接至該接點。
  3. 如申請專利範圍第1或2項所述之晶片封裝體，其中該抗氧化層的材質為錫、金、銀、或有機保焊劑。
  4. 如申請專利範圍第1或2項所述之晶片封裝體，其中該抗氧化層是以化學電鍍、浸泡、或噴塗的方式形成。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一保護層，配置於該二維感測區域上。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該保護層之材質包括奈米鑽石。
  7. 如申請專利範圍第2項所述之晶片封裝體，其中該基板更具有至少一應力釋放孔，其連接該貫穿口之一角落。
  8. 一種晶片構件，包括：一晶片，具有至少一接墊，其中該晶片為一指紋辨識晶片，其具有一二維感測區域；至少一電性連接件，包括：一銅凸塊，配置於該接墊上；以及一抗氧化層，配置於該銅凸塊不與該接墊連接的一外表面上；以及一保護層，配置於該二維感測區域上，其中該保護層之材質包括奈米鑽石。
  9. 如申請專利範圍第8項所述之晶片構件，其中該抗氧化層的材質為錫、金、銀、或有機保焊劑。
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