TWI511265B - 3d semiconductor structure and manufacturing method thereof - Google Patents

Description

Three-dimensional semiconductor structure and method of manufacturing same

The present invention relates to semiconductor structures, particularly to 3-dimensional (3D) semiconductor memory structures.

Due to the strong demand for high-density memory in the semiconductor industry (eg, floating gate memory, charge trapping memory, non-volatile memory, and embedded memory), the architecture of memory cells has changed from planar to The 3-dimensional structure, 3-dimensional structure helps to increase the storage capacity within a limited wafer area. Cross-point arrays are a form of a 3D memory structure that includes a plurality of word lines, a plurality of bit lines, and a memory layer sandwiched between the word lines and the bit lines.

In the trend of decreasing component size, not only the size of the bit line (and the word line) itself shrinks, but also the distance between them shrinks. In the case of a cross-point array, by generating a plurality of memory cells in the occupied area of the intersection, the aspect ratio of the bit lines is continuously increased in order to pursue a higher storage density. The problem that arises in the process of forming a structure having a large aspect ratio also occurs in the word line, which is due to the stacked structure of the 3D memory. Strip patterns (bit lines or word lines) define programs such as a non-isotropic etch that can be more severely tested due to the narrow aspect space between the larger aspect ratio and the bit line (character line). If the above pattern definition procedure is flawed, it will cause the bridge. The bridging effect causes the memory device to be inoperable.

In the conventional cross-point 3D memory structure, word-line to word-line coupling becomes a serious problem as the space between the word lines decreases. The word line coupling can be attributed to the longer word line and the narrower spacing between the word lines, and of course, the conventional 3D memory structure forms a high overlap area between adjacent word lines, thereby increasing the coupling capacitance. .

Therefore, the 3D memory structure needs to effectively overcome the occurrence of bridging and coupling effects. However, if the manufacturing process is simple and the cost is controlled, the structure will have greater demand.

It is an object of the present invention to provide a 3-dimensional (3D) semiconductor memory structure and a method of fabricating the same.

An embodiment exemplifies a semiconductor structure including: a substrate; a plurality of stacked strips disposed in parallel with each other and positioned on the substrate; and a plurality of conductive lines disposed in parallel with each other and positioned orthogonally These stacks are on the belt. Because not all of the bottom surfaces of the conductive lines are conformal to the stacked strip, a first gap fills the space between two adjacent stacked strips and below the conductive lines, the conductive lines are positioned at the two Adjacent to the stacking strip; and a second gap between the two adjacent conductive lines. The distance between two adjacent stacked strips is below 200 nm, and the stacking strip has an aspect ratio of at least 1.

The above semiconductor structure can be fabricated by at least two methods. One example of the present invention is the formation of a plurality of stacked strips on a substrate, and then a conductive liner conforming to the topography of the stacked strips by a conformal deposition. A non-conformal conductive film layer is deposited and supported by the underlying stacked strips, followed by a non-conformal conductive film layer etching step defining a pattern of the conductive lines.

Another example of the present invention is to form a plurality of stacked strips on a substrate, and form a conductive liner conforming to the topography of the stacked strips by a conformal deposition. pad. A planarization process is followed by filling the top surface of the stack with an ashable material and then etching back the ashable material to expose the conformal conductive liner. A plurality of conductive lines are formed in parallel with each other on the layer of ashable material and in contact with the exposed conductive pads. In this example, the layer of ashable material is removed after forming the conductive lines.

As used herein, "or" is an inclusive "or" and is equivalent to "and/or" unless the context clearly indicates otherwise. In addition, throughout this specification, the meaning of "a" and "the" includes plural reference. "Coupled" means that the elements may be directly connected or may be connected via one or more intermediates.

The technical features and advantages of the present disclosure have been broadly described above, and the detailed description of the present disclosure will be better understood. Other technical features and advantages of the subject matter of the claims of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present invention may be practiced with the same or equivalents. It is also to be understood by those of ordinary skill in the art that this invention is not limited to the spirit and scope of the disclosure as defined by the appended claims.

10‧‧‧3D memory structure

11‧‧‧Substrate

12A‧‧‧Stacking belt

12B‧‧‧Stacking belt

13A‧‧‧Flexible wire

13B‧‧‧Flexible wire

14‧‧‧ memory layer

15‧‧‧Electrical gasket

16‧‧‧Insulation/Interlayer Dielectric (ILD)

21‧‧‧Substrate

22‧‧‧Stacking belt

34‧‧‧Electrical gasket

35‧‧‧ memory layer

42‧‧‧Stacking belt

43‧‧‧Electrical film

46‧‧‧ side wall

53‧‧‧Electrical film

54‧‧‧Electrical gasket

57‧‧‧Light resistance

63‧‧‧Electrical film

64‧‧‧Electrical gasket

65‧‧‧ memory layer

67‧‧‧resist pattern

72‧‧‧Stacking belt

73‧‧‧Flexible wire

76‧‧‧First gap

77‧‧‧Insulation

78‧‧‧Second gap

84‧‧‧Electrical gasket

86‧‧‧Ashedable materials

87‧‧‧ memory layer

94‧‧‧Electrical gasket

96‧‧‧TOPAZ

103‧‧‧Electrical film

104‧‧‧Electrical gasket

106‧‧‧TOPAZ

113‧‧‧Electrical film

115‧‧‧Light resistance

121‧‧‧ Conductive tape

122‧‧‧Insulation tape

123‧‧‧ Conductive tape

123'‧‧‧Flexible wire

124‧‧‧Insulation tape

124'‧‧‧Electrical gasket

125‧‧‧Light resistance

126‧‧‧TOPAZ

133‧‧‧Flexible wire

134‧‧‧Electrical gasket

135‧‧‧Light resistance

136‧‧‧TOPAZ

137‧‧‧ memory layer

142A‧‧‧Stacking belt

142B‧‧‧Stacking belt

143‧‧‧Flexible wire

151‧‧‧First gap

152‧‧‧Stacking belt

153‧‧‧Flexible wire

156‧‧‧Second gap

158‧‧‧Insulation

159‧‧‧ side wall

D‧‧‧Distance

H‧‧‧ Height

W‧‧‧Width

1 is a perspective view of a 3-dimensional (3D) semiconductor memory structure in accordance with an embodiment of the present invention; FIGS. 2 through 7 illustrate a method of fabricating a 3-dimensional (3D) semiconductor memory structure in accordance with an embodiment of the present invention. A top view and a corresponding cross-sectional view of the steps; and FIGS. 8 through 15 are top views and corresponding cross-sectional views of steps of another method of fabricating a three-dimensional (3D) semiconductor memory structure in accordance with an embodiment of the present invention.

The invention will be described in accordance with the drawings.

FIG. 1 illustrates a portion of a 3D memory structure 10 in accordance with an embodiment of the present invention. The two stacked strips (12A, 12B) include conductive strips (121, 123) and the insulating strips (122, 124) are positioned on the substrate 11 in parallel with each other along the x-axis. The two conductive lines (13A, 13B) are parallel to each other along the y-axis and are positioned on the two stacked strips. In this embodiment, the orientation of the stacked strips (x-axis) is orthogonal to the orientation of the conductive lines (y-axis). However, the scope of the invention is not limited to this configuration and any angle may be encompassed within the scope of the invention. In the present embodiment, the distance D between the two stacked strips (12A, 12B) is 150 nm, and the aspect ratio of the stacked strips (i.e., the height H and the width W) is 10. However, any distance D below 200 nm and any aspect ratio (H/W) above 1 can be applied to the memory structure 10.

At least two voids are present in the memory structure 10. One of the voids fills the space between the two stacked strips (12A, 12B) and under the conductive line 13A. In other words, the conductive line 13A is structurally supported by the lower stacking strips (12A, 12B). Another gap is between the two conductive lines (13A, 13B) and below the insulating layer 16. In an embodiment, the stacked strips (12A, 12B) may be bit lines and the conductive lines (13A, 13B) may be word lines. The presence of at least two voids separates adjacent conductive lines and adjacent stacked strips. In one embodiment, the two voids form a connected structure.

For the sake of brevity, the following description focuses on a stacked strip or a conductive line, and the materials and structural configurations described are applicable to all stacked strips/conducting lines in a memory structure. The stacked tape 12A in this embodiment is composed of a plurality of insulating tapes/conductive tapes 121 to 124 in which two different materials are alternately arranged. For example, the insulating tapes 122 and 124 may be insulating materials such as hafnium oxide, other hafnium oxide or tantalum nitride; and the conductive strips 121 and 123 may be electrically conductive materials such as undoped or have n-type or p-type Doped polycrystalline germanium or single crystal germanium. Insulating tapes 122 and 124 are cerium oxide prepared by low pressure chemical vapor deposition LPCVD (not described in a limiting manner). The number of insulating tapes/conductive tapes is not limited to the description of the present invention, and a combination of a pair of insulating tape-conductive tapes can perform the function of the memory structure of the present invention. In the following description The figure does not show the detailed structure of the stacked strip, but the stacked strip structure according to the above description can be applied to the following description.

The memory layer 14 is formed to conform to the surface of the stacked tape 12A. The material of the memory layer 14 is a composite tunneling dielectric layer designed through an energy gap, which comprises a ruthenium dioxide layer, a tantalum nitride layer and a ruthenium dioxide layer. The thickness of each oxide or nitride layer is within the nanometer scale, and other embodiments may have five alternating thin dielectric layers (ie, hafnium oxide, tantalum nitride, hafnium oxide, tantalum nitride, oxide).矽) as the memory layer 14. In one embodiment, LPCVD is used to form a nitride or oxide thin dielectric layer.

A conductive pad 15 of 1 nm to 5 nm is formed to conform to the surface of the previously deposited memory layer 14. The memory layer 14 is sandwiched between the conductive pad 15 and the stacked tape 12A. The conductive pads 15 are deposited to provide a smooth interface of the stacked strips 12A and to form an electrical coupling between the stacked strips 12A and the conductive lines (13A, 13B). The conformality of the conductive gasket 15 avoids any gap between the conductive gasket 15 and the under-covered stacking strip 12A. The material of the conductive pad 15 may be selected from TiN, TaN, p-type or n-type polysilicon, TANOS (TaN/WN/N, Al ₂ O ₃ , SiN, SiO ₂ , Si), WN, W, or a combination thereof. Available technologies include CVD procedures. In the preferred embodiment, the conductive pad 15 and the conductive line 13A differ in etching rate. For example, it can be a different material having a different etch rate relative to a particular etch process.

The conductive lines (13A, 13B) are positioned on the stacked strips (12A, 12B) and electrically connected between the bottom surface of the conductive lines (13A, 13B) and the conductive pads 15 of the stacked strips (12A, 12B). The conductive wire may be made of a conductive material such as tungsten carbide, aluminum or TiN/TaN. An insulating layer or interlayer dielectric (ILD) 16 is positioned on the conductive lines and deposited in a non-conformal manner to form a continuous film. According to a manufacturing procedure applied to the memory structure 10, the program can have a portion of the sidewalls of the stacked strip having a trace amount of material constituting the conductive lines, and the portion can be a section in which the stacked strips are shielded by the conductive lines. More specifically, the thickest portion of the electrically conductive wire material on the sidewalls of the stacked strip is at most one tenth of the thickness of the electrically conductive wire. Other manufacturing procedures may not lead The wire material is on this particular portion of the stacking strip. Another manufacturing procedure may have a sidewall of one of the stacked strips having an insulating layer or ILD material, and the portion includes a section of the stacked strip that is not obscured by the conductive lines.

2 through 7 are top views and corresponding cross-sectional views of steps of a method of fabricating a three-dimensional (3D) semiconductor memory structure in accordance with an embodiment of the present invention. As shown in FIG. 2, 20A is a top view of the memory structure in manufacture, and 20B is a cross section along the dashed line AA of 20A. A plurality of stacked strips 22 are formed in parallel with each other on the substrate 21. The stacking structure inside the stacking strip has been described in the previous paragraph, so the detailed manufacturing procedure of the stacking structure will not be described in this paragraph. In FIG. 3, 30A is a top view of a memory structure in a manufacturing process, and 30B is a cross section along a broken line AA of 30A. 30B shows blanket deposition of memory layer 35, followed by another blanket deposition of conductive pad 34. The two blanket depositions and the surface profile of the stacked strip are conformal, the pattern of the stacked strips has an aspect ratio (H/W) of at least 1, and the distance D between the two adjacent strips is preferably 150 nm. In one embodiment, the deposition process can be performed by LPCVD, wherein deposition of the memory layer 35 can include multiple depositions of a thin dielectric layer, such as an ONO structure (ie, yttrium oxide (1.5 nm)-yttrium nitride (3.0 nm). ) - yttrium oxide (3.5 nm) or ONONO structure. The material of the conductive pad 34 may be selected from TiN, TaN, p-type or n-type polysilicon, TANOS (TaN/WN/N, Al ₂ O ₃ , SiN, SiO ₂ , Si), WN, W, or a combination thereof. 30A shows a top view of blanket deposition of conductive pads 34.

As shown in FIG. 4, 40A is a top view of the memory structure in fabrication, 40B is a cross section along the dashed line AA of 40A, and 40C shows the structure of 40B after the chemical mechanical polishing (CMP) procedure. In this step, a first non-conformal deposition is performed. A continuous conductive film layer is formed by deposition of a non-conformal film. For example, tungsten telluride can be deposited using CVD, while aluminum, TiN/TaN can be formed using PVD. Although PVD is often used as a tool for producing a non-conformal film, in the present invention, a layer of a conductive wire material does not necessarily have to be formed using PVD. A CVD deposited conductive material such as tungsten telluride can also achieve the desired non-conformal film. The process of PVD and CVD can also be used interchangeably. Non-conformal deposition as shown in Figure 40B By forming the electroconductive thin film 43 on the stacked strip 42, the thin film is planarly projected on the top of the stacked strip 42 and laterally grown to meet the film accumulated on the adjacent stacked strip 42 due to the poor conformality of the conductive film. The encounter of the film 43 forms a continuous conductive film and ensures a continuous electrical path on the stacked strip 42. However, traces of conductive material may deposit on the sidewalls 46 of the stack strip 42. In one embodiment, the thickest portion of the conductive material deposited on the sidewalls 46 of the stacked strip 42 is at most one tenth of the thickness of the conductive film 43 on the stacked strip. Therefore, the first gap is formed due to the non-conformal deposition of the electroconductive thin film 43. The first void is between two adjacent stacked strips 42 and below the layer of conductive film 43. In 40C, the incident conductive film 43 is flattened by a CMP process to have a relatively uniform thickness and a flat surface.

As shown in FIG. 5, 50A is a top view of the memory structure in fabrication, 50B is a cross section along the dashed line AA of 50A, and 50C is a cross section along the dashed line BB of 50A. A pattern of photoresist 57 is formed on the conductive film 53, followed by a first anisotropic etch, preferably reactive ion etching (RIE), to remove the region of the conductive film 53 that is not protected by the photoresist and the etch stops. At the conductive pad 54. In other words, for the first etchant used in the RIE process, the etching selectivity ratio between the conductive film 53 and the conductive pad 54 is sufficiently high (for example, more than 10). In one embodiment, the material of the conductive film 53 is tungsten (W), and the material of the conductive pad is TiN. In another embodiment, the material of the conductive film 53 is Al, and the material of the conductive pad is TiN. 50A shows conductive pad 54 exposed to areas without photoresist protection. Maintaining a high etch selectivity ratio between the conductive line material and the conductive pad material will ensure that the over-etch process does not damage the stacked tape. Because of the high aspect ratio (over 10) of stacked strips (or word lines) in a typical 3D memory structure, overetching is a common approach in order to remove residues in the trench.

As shown in Figure 6, 60A is a top view of the memory structure in fabrication, 60B is a cross section along the dashed line AA of 60A, and 60C is a cross section along the dashed line BB of 60A. In this step, a second anisotropic etch is performed to remove the conductive pads 64 that are not masked by the photoresist pattern 67. Because the choice of materials for use as conductive pads 64 and as conductive film 63 is based on their relative etch The individual etch selection ratios are so that in order to remove the conductive pads 64, the second etchant used in the RIE process should have a different chemical than the first etchant used in the first anisotropic etch. Maintaining a high etch selectivity ratio between the conductive line material and the conductive pad material will ensure that the second anisotropic etch does not damage the conductive lines. The 60A display memory layer 65 is exposed to areas that are not protected by photoresist. If the etch selectivity is not sufficiently high, the sidewalls of the conductive lines may be attacked by the second etchant to form a narrower conductive line. The sheet resistance of a narrower conductive line will increase. Therefore, it is preferable to keep the etching selection ratio high in this processing step.

As shown in Figure 7, 70A is a top view of the memory structure in fabrication, 70B is a cross section along the dashed line AA of 70A, 70C is a cross section along the dashed line BB of 70A, and 70D is a dashed line along 70A. Cross section of CC. The broken line AA is cut on the conductive line 73; the broken line BB is parallel to the broken line AA, but not on the conductive line 73; the broken line CC is perpendicular to the broken lines AA and BB, but not on the stacked strip 72. After the photoresist to define the conductive lines is removed, a second non-conformal deposition is performed to deposit an insulating layer 77 (such as an IDL). The second non-conformal deposition can utilize oxide deposition techniques available in the art. However, as shown at 70C, a trace amount of insulating material has an opportunity to deposit on the sidewalls of a portion of the stacking strip 72, which is a section that is not obscured by conductive lines.

As shown at 70D, the first void 76 between two adjacent stacked strips 72 and under the masking region of the conductive line 73 is defined when the conductive line is formed, while the second gap between the two adjacent conductive lines 73 is defined. 78 is then defined at the completion of the present non-conformal oxide deposition step.

8 through 15 are top plan views and corresponding cross-sectional views of steps of another method of fabricating a three-dimensional (3D) semiconductor memory structure in accordance with an embodiment of the present invention. The steps of forming a plurality of parallel stacked strips and forming a conformal conductive underlayer on the strips may be the same as or similar to those described in prior methods of fabrication (see Figures 2 and 3), and the subsequent description in Figure 8 step. As shown in Figure 8, 80A is a top view of the memory structure being fabricated, and 80B is a cross-section along the dashed line AA of 80A. According to the manufacturing method, the distance D between two adjacent stacked strips can be Below 200 nm. A planarization process is performed using an ashable material 86 to fill the stacked strips coated with the memory layer 87 and the conductive pads 84. A spin coating technique with a suitable rate of rotation can be used in response to different ashable materials to properly fill the trenches between the stacked strips. The ashable material comprises materials such as organic dielectric materials (ODL), TOPAZ, SHB, and BARC that can be ashed by oxygen plasma. In one embodiment, TOPAZ is used as an ashable material because the TOPAZ can withstand the deposition temperatures used in subsequent conductive line deposition steps without significant degradation. In one embodiment, the temperature at which the TOPAZ does not significantly degrade may be 500 degrees Celsius.

90A of Fig. 9 is a plan view of the memory structure in manufacture, and 90B is a cross section along the dotted line AA of 90A. This step etches back the TOPAZ 96 in this structure to expose a portion of the conductive pad 94, specifically the portion that is on the stacked tape. A blanket etch (eg, an isotropic oxygen plasma etch) can be utilized to perform this etch back step. 100A of FIG. 10 is a top view of the memory structure in fabrication, and 100B is a cross section along the dashed line AA of 100A. The conductive film 103 is deposited on the TOPAZ 106 and the exposed conductive pads 104, wherein the conductive film 103 can be p+ or n+ polysilicon, aluminum, tungsten or a combination thereof. In one embodiment, the material selection has a deposition temperature below 400 degrees Celsius, and the selected TOPAZ does not significantly degrade during deposition of the conductive film 103. On the other hand, the conductive film 103 deposition process is produced without any oxygen or oxygen derivative because the oxygen or oxygen derivative easily reacts with the TOPAZ and damages the structural integrity of the ODL. The thickness of the conductive film 103 may be greater than the thickness of the exposed conductive pad 104.

As shown in FIG. 11, 110A is a top view of the memory structure in fabrication, 110B is a cross section along the dashed line AA of 110A, and 110C is a cross section along the dashed line BB of 110A. This step forms the photoresist pattern 115 on the conductive film 113 and defines the conductive line 123 after the anisotropic etching as shown in FIG. As shown in FIG. 12, 120A is a top view of the memory structure in fabrication, 120B is a cross section along the dashed line AA of 120A, and 120C is along Cross section of the broken line BB of 120A. The anisotropic etch (e.g., RIE) utilizes a third etchant to remove portions of the conductive film 113 that are not protected by the photoresist pattern 115, and as shown at 120C, the RIE is exposed to be protected by the photoresist pattern 125. A portion of the lower conductive pad 124'. Conductive lines 123' are defined in this step and are formed orthogonally on the stacked strip to contact the exposed conductive pads 124'.

As shown in FIG. 13, subsequent anisotropic etching further removes the exposed conductive pads 124' and the exposed TOPAZ 126 of FIG. As shown in FIG. 13, 130A is a top view of the memory structure in fabrication, 130B is a cross section along the dashed line AA of 130A, and 130C is a cross section along the dashed line BB of 130A. An anisotropic etch (such as RIE) utilizes a fourth etchant to remove the exposed TOPAZ 136 and the exposed conductive pads 134 and stop at the memory layer 137. Because of the deep trench configuration between two adjacent stacked strips, the conductive line 133 and the ODL 136/conductive pad 134 should have a high etch selectivity ratio (eg, 5:1) relative to the fourth etchant because of the deep trench Most of the configuration of the structure requires over etching. If the etch selectivity ratio of the fourth etchant exceeds 10:1, the lateral degradation that may occur due to the conductive lines 133 during overetching may be reduced. In one embodiment, the third etchant and the fourth etchant used in the present fabrication method are different.

In FIG. 14, 140A is a top view of the memory structure in fabrication, 140B is a cross section along the dashed line AA of 140A, and 140C is a cross section along the dashed line BB of 140A. As shown in Figure 13, photoresist 135 and TOPAZ 136 are removed by a strip/ashing process. An isotropic oxygen plasma etch can be used to strip the TOPAZ below the conductive line 143. A first void positioned between two adjacent stacked strips (142A, 142B) and under the masking region of conductive line 143 is then formed. Conductive pads 144 that are shielded by conductive lines 143 are retained during this stripping/ashing process. A residue cleaning procedure can be selectively implemented to ensure complete removal of the layer of ashable material.

In Fig. 15, 150A is a top view of the memory structure in manufacture, 150B is a cross section along a broken line AA of 150A, 150C is a cross section along a broken line BB of 150A, and 150D is a broken line CC along 150A. Cross section surface. The dotted line AA is cut on the conductive line 153; the broken line BB is parallel to the broken line AA, but not on the conductive line 153; the broken line CC is perpendicular to the broken lines AA and BB, but not on the stacked strip 152. An insulating layer 158 (eg, an interlayer dielectric) is then deposited on the conductive lines 153 in a non-conformal manner. 150C shows a second gap 156 between two adjacent conductive lines 153 after completion of the non-conformal oxide deposition process. The deposition procedure can be PVD, CVD, or a combination thereof. However, as shown at 150C, a trace amount of insulating material has the opportunity to deposit on the sidewall 159 of a portion of the stacking strip 152, which may be a section that is not obscured by the conductive lines 153.

As shown at 150D, a first void 151 between two adjacent stacked strips 152 and under the masking region of the conductive line 153 is defined when the conductive line is formed, while a second gap between the two adjacent conductive lines 153 is defined. 156 is then defined at the completion of the present non-conformal oxide deposition step.

The technical content and the technical features of the present disclosure have been disclosed as above, but those skilled in the art should understand that the teachings and disclosures of the present disclosure are disclosed without departing from the spirit and scope of the disclosure as defined by the appended claims. Can be used for various substitutions and modifications. For example, many of the processes disclosed above may be implemented in different ways or in other processes, or a combination of the two. Moreover, the scope of the present invention is not limited to the particular process, machine, manufacture, composition, means, method or method of the particular embodiments disclosed. It should be understood by those of ordinary skill in the art that, based on the teachings of the present disclosure, the process, the machine, the manufacture, the composition of the material, the device, the method, or the steps, whether present or future developers, The revealer performs substantially the same function in substantially the same manner, and achieves substantially the same result, and can also be used in the present disclosure. Accordingly, the scope of the following claims is intended to cover such <RTIgt; </ RTI> processes, machines, manufactures, compositions, devices, methods or steps.

10‧‧‧3D memory structure

11‧‧‧Substrate

12A‧‧‧Stacking belt

12B‧‧‧Stacking belt

13A‧‧‧Flexible wire

13B‧‧‧Flexible wire

14‧‧‧ memory layer

15‧‧‧Electrical gasket

16‧‧‧Insulation/Interlayer Dielectric (ILD)

121‧‧‧ Conductive tape

122‧‧‧Insulation tape

123‧‧‧ Conductive tape

123'‧‧‧Flexible wire

124‧‧‧Insulation tape

124'‧‧‧Electrical gasket

D‧‧‧Distance

H‧‧‧ Height

W‧‧‧Width

Claims (12)

A semiconductor structure comprising: a substrate; a plurality of stacked strips on the substrate, which are disposed in parallel with each other; a plurality of conductive lines on the stacked strip, which are disposed in parallel with each other, and the conductive lines are arranged in a direction opposite to The arrangement direction of the lower stacked strip has an included angle; and a conductive pad conforming to the stacked strip, wherein the conductive pad and the conductive line are made of different materials; wherein a first gap is located in two adjacent stacked strips And under the at least one conductive line, the at least one conductive line is positioned on the two adjacent stacked strips, and the distance between the two adjacent stacked strips is below 200 nm, and the aspect ratio of the stacked strip is at least 1. The semiconductor structure of claim 1, further comprising a memory layer interposed between the conductive pad and the stacked tape, wherein the memory layer can be an ONO or ONONO structure. The semiconductor structure of claim 1, wherein the sidewall of one of the stacked strips comprises a small amount of material constituting the conductive line, and the portion includes a region where the stacked strip is shielded by the conductive line. The semiconductor structure of claim 1 further comprising a second gap positioned between two adjacent conductive lines. The semiconductor structure of claim 4, wherein the first void and the second void form a connected structure. A method for fabricating a semiconductor structure, comprising: forming a plurality of stacked strips disposed in parallel with each other on a substrate; forming a conductive liner conforming to the topography of the stacked strips by performing a conformal deposition And forming a plurality of conductive lines disposed in parallel with each other and orthogonally positioned on the stacked strips by performing a first non-conformal deposition. The method of claim 6, further comprising the step of forming an insulating layer on the conductive line by a second non-conformal deposition. The method of claim 6, further comprising the step of forming a memory layer between the stacked strips and the conductive pads. The method of claim 6, wherein the distance between two adjacent stacked strips is below 200 nm and the stacking strip has an aspect ratio of at least one. A method for fabricating a semiconductor structure, comprising: forming a plurality of stacked strips disposed in parallel with each other on a substrate; forming a conductive liner conforming to the topography of the stacked strips by performing a conformal deposition Flattening the stacked strips by a layer of ashable material; exposing a portion of the electrically conductive liner by etching back the layer of ashable material; And forming a plurality of conductive lines disposed in parallel with each other and orthogonally positioned on the stacked strip, and the conductive lines contact the exposed conductive pads. The method of claim 10, further comprising the step of forming a memory layer between the stacked strips and the electrically conductive pad. The method of claim 10, wherein the distance between two adjacent stacked strips is below 200 nm.