TWI505452B - Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic equipment - Google Patents

Description

Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic equipment

The present invention relates to a backside illumination type solid-state imaging device, a method of manufacturing a solid-state imaging device, and an electronic device using the same.

In the past, a CCD type solid-state imaging device or a CMOS type solid-state imaging device has been known as a solid-state imaging device used in a digital camera or a video camera. In such solid-state imaging devices, a light sensing section is formed for each pixel of a plurality of pixels formed in a two-dimensional matrix, and in the light sensing section, a light is generated depending on the amount of received light. Signal charge. Then, the signal charge generated in the light sensing section is transmitted and amplified, thereby obtaining an image signal.

Further, in recent years, a back-illumination type solid-state imaging device has been proposed which illuminates the back-illuminated type solid-state imaging device with light from a side opposite to a side on which a substrate on one of the wiring layers is formed. In the back-illuminated type solid-state imaging device, since a wiring layer, a circuit component or the like is not disposed on the light-irradiating side, the aperture ratio of the light sensing section formed in a substrate can be increased, and Since the incident light is incident on the light sensing section without being reflected by the wiring layer or the like, an improvement in sensitivity can be obtained.

Incidentally, in the back-illuminated solid-state imaging device, in order to take out an electrode pad of the wiring layer formed on the surface side of the substrate to the back side (which is the light-irradiating side of the substrate), A light-irradiating surface of the substrate penetrates the substrate and exposes one of the via holes of the electrode pad. In the past manufacturing method of a solid-state imaging device, the through hole was formed after or before the formation of an on-line lens, and the crystal carrier lens was formed on the light incident plane side of the substrate.

In the back-illuminated type solid-state imaging device, a configuration in which an in-line lens is formed after forming the through hole exposing the electrode pad is described in Japanese Laid-Open Patent Publication No. 2005-285814. In this manner, in the case where one of the crystal-carrying lenses is formed after the formation of the through hole, there is a problem in that the application of the resist material causes unevenness in application of the resist material due to the influence of the through hole, so that the crystal The shape of the carrier lens becomes uneven in a plane. In the case where the shape of the crystal lens is not uniform, there is a concern that a change in photocoagulation characteristics occurs in a wafer.

Further, in the case where an electrode layer is formed on the back side of the substrate after the formation of the crystal lens, the possibility of changing the shape of the crystal lens caused by patterning the electrode layer or due to etching of the electrode layer to The difference in adhesion of the scattering particle components caused by the difference in the crystal lens is high. For this reason, in the case where the electrode layer is formed on the back side of the substrate after the formation of the crystal lens, there is a concern that a defect due to particle composition occurs.

Further, in the case of one of the electrode pads formed on the back side of the substrate from the back side of the substrate to the surface side formed on the surface side of the substrate, it is necessary, as in the case of Japanese Unexamined Patent Application Publication No. 2005-285814 The bonding wire is inserted into the through hole penetrating the substrate. For this reason, it is difficult to connect to an external terminal by the bonding wire, so there is a concern that the yield at the time of assembly is reduced.

It is desirable to provide an improved solid-state imaging device in which an in-line lens is accurately formed and the yield at the time of assembly can be obtained. Further, it is desirable to provide electronic equipment using the solid-state imaging device.

According to an embodiment of the present invention, there is provided a solid-state imaging device comprising: a substrate, a wiring layer, a surface electrode pad segment, a light shielding film, a pad segment substrate layer, and an on-board a lens layer, a through hole, a back electrode pad section, and a through electrode layer. In the substrate, a plurality of pixels including a photoelectric conversion section are formed. The wiring layer is formed on a front side of one of the substrates. The surface electrode pad section is formed in the wiring layer. The light shielding film is formed on one of the back sides of the substrate. The pad segment base layer is formed in the same layer as the light shielding film. The crystal lens layer is formed over the light shielding film and the pad segment base layer on one side opposite to the substrate side. The back electrode pad section is formed over the crystallographic lens layer. The via is formed to penetrate the crystallographic lens layer, the pad segment base layer, and the substrate such that the surface electrode pad segment is exposed. The through electrode layer is formed to connect the surface electrode pad segment and the back electrode pad segment through the via.

In the solid-state imaging device according to the embodiment of the present invention, the through electrode layer formed in the through hole and the back electrode pad section formed on the back side of the substrate are formed on the substrate The surface electrode pad section in the wiring layer on the surface side is taken out to the back side of the substrate. That is, since the back electrode pad section may be formed on one of the upper layers of the substrate, bonding can be easily performed.

According to another embodiment of the present invention, there is provided a method of fabricating a solid-state imaging device, the method comprising: forming a plurality of pixels in a substrate, each pixel having a photoelectric conversion region that generates a signal charge according to the amount of received light And forming a wiring layer having a plurality of laminated wires and a surface electrode pad segment on the surface side of the substrate. In addition, the method includes: forming a pad segment base layer and a light shielding film in the same layer on the wiring layer; and opposite to the pad segment base layer and the substrate side of the light shielding film An on-chip lens layer is formed on the light incident side of one of the upper layers. In addition, the method includes: forming a through hole penetrating the base layer of the pad segment from the top of the crystal lens layer and reaching the surface electrode pad segment; and forming a through electrode layer in the via hole and also A contact electrode pad section electrically connected to one of the surface electrode pad segments is formed on the crystal lens layer. Additionally, the method includes processing the surface of the crystallographic lens layer above the pixel into a convex shape, thereby forming an on-board lens.

According to still another embodiment of the present invention, there is provided a method of manufacturing a solid-state imaging device, the method comprising: laminating in a same manner by bonding a wiring layer of an upper layer section and a lower layer section to each other The upper layer section formed by the substrate and a wiring layer and the lower layer section formed by a substrate and a wiring layer. In the substrate constituting the upper layer section, a plurality of pixels each having a photoelectric conversion section which generates a signal charge according to the amount of received light are formed. Further, the wiring layer is formed on the surface side of the substrate. Further, a light shielding film is formed on the back side of the substrate and a pad segment substrate layer is formed in the same layer as the light shielding film. Further, a crystal lens layer is formed on a light incident side of an upper layer on a side opposite to the light shielding film and the substrate side of the pad segment base layer. Further, a surface electrode pad section is formed in the wiring layer of the lower layer section. Next, the method includes, after laminating the upper layer segment and the lower layer segment, forming a through hole penetrating the base layer of the pad segment from the crystal lens layer and reaching the surface electrode pad segment. In addition, the method includes: forming a through electrode layer in the via hole and also forming a back electrode pad portion electrically connected to one of the surface electrode pad segments on the crystal lens layer; and processing the pixel The surface of the crystal lens layer, thereby forming an on-board lens.

In the method of manufacturing a solid-state imaging device according to the above embodiment of the present invention, after the crystal lens layer is formed, the surface electrode pad region formed in the wiring layer is exposed from the light incident side of the substrate The through hole of the segment. In this way, since the crystal lens layer is formed without being affected by the unevenness caused by the through hole, the application unevenness is reduced. Further, the processing of the crystal carrying lens is performed after the through electrode layer and the back electrode pad segment are formed. Therefore, the retention of the scattering metal generated when the through electrode layer and the back electrode pad section are formed or the collapse of the shape of the crystal lens is suppressed.

According to still another embodiment of the present invention, there is provided an electronic apparatus comprising: an optical lens; a solid-state imaging device, light condensed by the optical lens is incident on the solid-state imaging device; and a signal processing circuit processed from The solid-state imaging device outputs one of the output signals. Next, the solid-state imaging device, a substrate, a wiring layer, a surface electrode pad segment, a light shielding film, a pad segment substrate layer, a crystal lens layer, a back electrode pad segment, and a pass a hole and a through electrode layer. In the substrate, a plurality of pixels are formed, each of which has a photoelectric conversion section that generates a signal charge according to the amount of received light. The wiring layer is formed on the surface side of the substrate. The surface electrode pad section is formed in the wiring layer. The light shielding film is formed on the back side of the substrate. The pad segment base layer is formed in the same layer as the light shielding film. The crystal lens layer is formed on a light incident side of an upper layer on a side opposite to the substrate side of the light shielding film and the pad segment base layer. The back electrode pad section is formed over the crystallographic lens layer. The via is formed to penetrate the crystallographic lens layer, the pad segment base layer, and the substrate such that the surface electrode pad segment is exposed. The through electrode layer is formed to connect the surface electrode pad segment and the back electrode pad segment through the via.

According to an embodiment of the present invention, a solid-state imaging device which improves the light agglomeration characteristics of a crystal carrying lens can be obtained and an improvement in yield at the time of assembly can be obtained. Further, by using the solid-state imaging device, electronic equipment can be obtained in which image quality improvement can be obtained.

Hereinafter, an example of a solid-state imaging device and electronic equipment related to an embodiment of the present invention will be described with reference to FIGS. 1 through 16. Embodiments of the invention will be described in the following order. Further, the invention is not limited to the following examples.

1. First Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

1-1 Overall configuration

1-2 Configuration of the main section

1-3 Manufacturing method

2. Second Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

3. Third Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

4. Fourth Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

5. Fifth Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

6. Sixth Embodiment: Electronic Equipment

1. First Embodiment: Example of CMOS Type Backside Illumination Type Solid-State Imaging Device

A solid-state imaging device relating to the first embodiment of the present invention will be described. This embodiment example is an example of a CMOS type back-illumination type solid-state imaging device.

1-1 Overall configuration

First, the overall configuration of the solid-state imaging device of the example of this embodiment will be described before explaining the configuration of the main section. Fig. 1 is a schematic configuration diagram showing the entirety of a solid-state imaging device relating to an example of this embodiment.

A solid-state imaging device 1 includes an imaging region 3 (which includes a plurality of pixels 2) on a substrate 11 made of germanium, a vertical driving circuit 4, a row of signal processing circuits 5, a horizontal driving circuit 6, and an output circuit. 7. A control circuit 8 and the like, as shown in FIG.

The pixel 2 is composed of a light sensing section, and includes: a photodiode that generates a signal charge according to the amount of received light; and a plurality of MOS transistors for reading and transmitting the signal charge, And a plurality of pixels 2 are regularly arranged on the substrate 11 in a two-dimensional array.

The imaging area 3 is composed of the plurality of pixels 2 regularly arranged in a two-dimensional array. The imaging area 3 includes: an effective pixel area that can surely receive light and accumulate signal charges generated by photoelectric conversion; and an invalid pixel area (hereinafter referred to as an optical black body area) formed around the effective pixel area And used to output an optical black body that becomes a black body level standard.

The control circuit 8 generates a clock signal, a control signal or the like based on a vertical sync signal, a horizontal sync signal, a master clock, and the signal becomes the vertical drive circuit 4, the line signal processing circuit 5, the level The standard of operation of one of the drive circuits 6 and the like. Then, the clock signal, the control signal or the like generated in the control circuit 8 is input to the vertical drive circuit 4, the signal processing circuit 5, the horizontal drive circuit 6, and the like.

For example, the vertical driving circuit 4 is composed of a shift register and sequentially selects and scans each pixel 2 of the imaging region 3 in a column in a vertical direction. Next, a pixel signal based on one of the signal charges generated in one of the photoelectric conversion elements of each of the pixels 2 is supplied to the line signal processing circuit 5 through a vertical signal line 9.

For example, the row signal processing circuit 5 is arranged for each row of the pixels 2 and by a signal pair from the optical blackbody region (although not shown in the figure, but formed around the effective pixel region) Signal processing (such as noise reduction or signal amplification for each pixel row) is performed from one of the signals output by the pixels 2. At an output stage of the row signal processing circuit 5, a horizontal selection switch (not shown) is disposed between the output stage and a horizontal signal line 10.

For example, the horizontal driving circuit 6 is composed of a shift register and sequentially selects each of the row signal processing circuits 5 by sequentially outputting a horizontal scanning pulse, thereby causing a pixel signal from Each of the equal signal processing circuits 5 is output to the horizontal signal line 10.

The output circuit 7 performs signal processing on the pixel signals sequentially supplied from the line signal processing circuits 5 through the horizontal signal line 10 and then outputs the processed signals.

1-2 Configuration of the main section

In Fig. 2, a cross-sectional configuration diagram of one of main sections of the solid-state imaging device 1 of this embodiment example is shown. The solid-state imaging device 1 of this embodiment example is an example of the CMOS type back-illumination type solid-state imaging device, and FIG. 2 shows an effective pixel region 50, an optical black body region 51, and a pad region 52 in cross section. Moreover, in the example of this embodiment, the pad region 52 is an example of one of the portions of the grounding wiring or one of the negative potentials.

As shown in FIG. 2, the solid-state imaging device 1 of this embodiment example includes a substrate 12 and a wiring layer 13 formed on the surface side of the substrate 12. In addition, the solid-state imaging device 1 includes an insulating film 18, a pad segment base layer 19a, an ineffective pixel light-shielding film 19b, and an inter-pixel light-shielding film 19c formed on the back side of the substrate 12. The above film and a color filter layer 27 and a crystal lens layer 21 above the layer. Further, in the pad region 52, a surface electrode pad segment 15, a through hole 22, a back electrode pad segment 24, and a through electrode layer 23 are provided. Further, a support substrate 17 is attached to a surface on the side opposite to the substrate 12 side of the wiring layer 13.

The substrate 12 is composed of a germanium semiconductor and forms, for example, one of the thicknesses ranging from 2000 nm to 6000 nm. As shown in FIG. 1, in the imaging region 3 of the substrate 12, a plurality of pixels 2 are formed, each of which includes a photoelectric conversion section and a plurality of pixel transistors (not shown). The photoelectric conversion section is composed of a photodiode PD and generates a signal charge in accordance with the amount of incident light from the back side of the substrate 12. Then, the signal charge generated in the photodiode PD is read by the pixel transistor and output as a pixel signal. Further, although not shown in FIG. 2, a peripheral circuit including the vertical drive circuit 4 or the horizontal drive circuit 6 is formed in the substrate 12.

The wiring layer 13 is formed on the surface side opposite to the light incident side of the substrate 12 and is laminated in a plurality of layers (four layers in FIG. 2) in which an interlayer insulating film 14 is interposed. The wiring is composed of 1M to 4M. It is desirable that the wiring or the wirings 1M to 4M and the pixel transistors (not shown) are connected to each other by the contact section 16. In this way, the pixel transistor of each pixel 2 is driven from the wiring layer 13. Further, in the pad region 52, the surface electrode pad section 15 is formed by the fourth wiring 4M of the topmost layer (the lower layer in Fig. 2). As a constituent material of each of the wirings 1M to 4M constituting the wiring layer 13, for example, a metal material such as aluminum (Al) or copper Cu may be used. In this embodiment example, the first to third wirings 1M to 3M are formed of copper and the fourth wiring 4M forming the surface electrode pad section 15 is formed of aluminum. Further, as a constituent material of the contact section 16, for example, a metal material such as tungsten or copper may be used. Further, although in FIG. 2, the fourth wiring 4M is only shown as the surface electrode pad section 15, it can be used as a common wiring in other areas.

The insulating film 18 is formed on the back side which becomes the light incident side of the substrate 12 and is formed as a single layer or a plurality of layers. In the case where the insulating film 18 is formed in one of a plurality of layers, for example, it may be formed in a three-layer structure including a layer of ruthenium oxide film formed on the back side of the substrate 12 in order. , a layer of yttrium oxynitride film and a layer of tantalum nitride film. In this case, an anti-reflection effect is obtained.

Further, a film having a negative fixed charge can also be used as the insulating film 18. In this case, the insulating film 18 is formed in a three-layer structure including a layer of ruthenium oxide film in the substrate 12, a high-refractive-index insulating film having a negative charge, and a layer of ruthenium oxide. A film or a layer of tantalum nitride film. Since the hole accumulation state of the interface between the substrate 12 and the insulating film 18 is enhanced by the high refractive index insulating film having a negative charge, it is advantageous to suppress the generation of a dark current.

Here, it is desirable that the high refractive index insulating film has a refractive index lower than or approximately equal to yttrium and larger than a refractive index of a ruthenium oxide film.

For example, a metal film having a negative fixed charge consists of a thin film of aluminum oxide (Al ₂ O ₃ ), a thin film of zirconium oxide (ZrO ₂ ), a thin film of hafnium oxide (HfO ₂ ), and a layer of tantalum oxide (Ta ₂ O). ₅ ) A film or a layer of titanium oxide (TiO ₂ ) film is formed. As a film forming method, a chemical vapor deposition method, a sputtering method, an atomic layer evaporation method or the like can be given as an example. If the atomic layer evaporation method is used, it is preferred to simultaneously form a thin film of SiO ₂ which reduces an interface level by about 1 nm during film formation. Further, as a material other than the above, lanthanum oxide (La ₂ O ₃ ), strontium oxide (Pr ₂ O ₃ ), cerium oxide (CeO ₂ ), cerium oxide (Nd ₂ O ₃ ), cerium oxide ( Pm ₂ O ₃ ) and the like. Further, as the above materials, cerium oxide (Sm ₂ O ₃ ), cerium oxide (Eu ₂ O ₃ ), cerium oxide (Gd ₂ O ₃ ), cerium oxide (Tb ₂ O ₃ ), cerium oxide (Dy _{2) can be given.} O ₃ ) or the like. Further, as the above materials, ruthenium oxide (Ho ₂ O ₃ ), ruthenium oxide (Tm ₂ O ₃ ), yttrium oxide (Yb ₂ O ₃ ), lanthanum oxide (Lu ₂ O ₃ ), yttrium oxide (Y _{2 ) can be given.} O ₃ ) or the like. In addition, the film having a negative fixed charge may also be formed of a tantalum nitride film, a layer of aluminum nitride film, a thin film of yttrium oxynitride or a film of aluminum oxynitride.

In the film having a negative fixed charge, bismuth (Si) or nitrogen (N) may be added to the film in a range not impairing an insulating property. The concentration is appropriately determined within a range that does not impair the insulating properties of the film. In this way, by adding bismuth (Si) or nitrogen (N), it is possible to increase the thermal resistance properties of the film or the ability to block ion implantation during a process.

Although the thickness of the insulating film 18 varies depending on a material, the thickness of the insulating film 18 is preferably in the range of 10 nm to 500 nm.

The pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c are formed on the insulating film 18 on the side opposite to the side facing the substrate 12 of the insulating film 18. In the same layer.

The inter-pixel light shielding film 19c is formed between adjacent pixels 2 and 2. Further, the invalid pixel light shielding film 19b is formed in the optical black body region 51. Further, the pad segment base layer 19a is formed in the pad region 52. Further, although described later, in this embodiment example, an example in which the inter-pixel light shielding film 19c, the ineffective pixel light shielding film 19b, and the pad segment base layer 19a are electrically connected to each other is employed.

As a constituent material of the spacer segment underlayer 19a, the ineffective pixel light-shielding film 19b, and the inter-pixel light-shielding film 19c, tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride can be used. TiN). Further, a laminated structure of TiN and Al or a laminated structure of Ti and W which are formed in order in the layer stack direction may be employed. The film thickness of a base metal layer is acceptable if it is determined to have a light-shielding property. Further, since the pad segment base layer 19a is formed in the pad region 52 in which wire bonding is performed in an assembly process, it may be desirable to select one of the materials having a high hardness in consideration of the bonding pressure. As the material having a high hardness, W, Ti or TiN is typical.

The color filter layer 27 is formed over a planarization insulating film 20 and is formed corresponding to each of the pixels 2 of the effective pixel region 50. The planarization insulating film is made of an organic material or an inorganic material and formed The pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c are covered. The color filter layer 27 is configured to selectively transmit, for example, green, red, blue, cyan, yellow, black, or the like in each pixel 2. Alternatively, the color filter layer 27 can also be configured to transmit all of the light, such as white light, and not to transmit an infrared range of light. The color filter layer 27 for transmitting different colors for each pixel 2 may also be used and the color filter layer 27 of the same color in all of the pixels 2 may also be used. As for the color combination in the color filter layer 27, various options are possible depending on the specifications.

The crystal lens layer 21 is formed over the color filter layer 27, and in the effective pixel region 50, the surface of the crystal lens layer 21 is formed into a convex shape for each pixel 2, so that a crystal is formed. The lens 21 is loaded. The incident light is agglomerated by the crystal carrying lens 21a and is effectively incident on the photodiode PD of each of the pixels 2. As a constituent material of the crystal lens layer 21, for example, an organic material having one of refractive indices in the range of 1.0 to 1.3 can be used.

The through hole 22 is formed by a first opening portion 22a (which is formed such that the surface electrode pad portion 15 is exposed to the light incident side) and a second opening portion 22b (which is formed to have a larger than the first opening portion 22a) The diameter is larger and the pad segment base layer 19a is exposed to the light incident side. That is, the through hole 22 is formed to penetrate the crystal lens layer 21, the pad segment base layer 19a, and the substrate 12 in the pad region 52.

The back electrode pad section 24 is formed over the crystal lens layer 21 of the pad region 52 and is formed to be connectable to one of an external terminal shape, and in this embodiment example, the back electrode pad region Segment 24 is formed to extend upwardly to the optical black body region 51. That is, the back electrode pad section 24 is formed to extend upward directly above the effective pixel light shielding film 19b.

The through electrode layer 23 is formed along the inner wall of the through hole 22 and electrically connects the surface electrode pad section 15 and the back electrode pad section 24. The back electrode pad section 24 and the through electrode layer 23 are formed of the same material in the same process. As a constituent material of the back electrode pad section and the through electrode layer, for example, an alloy mainly composed of Al-Si-Cu is preferably used, and in addition to Al-Si, Alloy, Al, alloy based on Al-Si-W or the like. As for the film thickness, it is necessary to have a film thickness of 300 nm or more in consideration of the alloy ratio at the time of bonding.

Incidentally, since the second opening portion 22b is formed to expose the pad segment base layer 19a, the through electrode layer 23 and the pad segment base layer 19a are electrically connected to each other. Therefore, the surface electrode pad section 15, the pad section base layer 19a, and the back electrode pad section 24 are electrically connected to each other.

Further, in this embodiment example, as shown in FIG. 2, an insulating layer 25 is formed by an impurity diffusion region around the region of the substrate 12 on which the through hole 22 is formed. For example, in the case where the substrate 12 is set to an n-type and an electron is used as one of signal charges, the insulating layer 25 may be formed of a p-type impurity diffusion region. Therefore, a configuration is made in which the imaging region 3 or one of the peripheral circuits formed in the substrate 12 is not electrically connected to the through electrode layer 23.

1-3 Manufacturing method

Next, a method of manufacturing the solid-state imaging device 1 of the example of this embodiment will be described. 3 to 9B are views showing the process of the solid-state imaging device 1 of Fig. 2.

Here, a description is given from a process after the wiring layer 13 is formed on the surface of the substrate 12, and the support substrate 17 is then bonded to an upper portion of the wiring layer 13, and the reverse surface is also performed, and polished. The substrate 12 is to a predetermined thickness. Thus, in the cross-sectional configuration of FIG. 3, the photodiodes PD or the pixel transistors have been formed in the substrate 12. Further, in the region corresponding to the pad region 52 of the substrate 12, the insulating layer 25 is formed by performing ion implantation of impurities of a predetermined conductivity type (a p-type in this embodiment example). Since the manufacturing method has been hitherto formed using the same manufacturing method as that of the past one of the back-illuminated type solid-state imaging devices, a detailed description is omitted.

After the substrate 12 is polished to a predetermined thickness, as shown in FIG. 3, the insulating film 18 composed of a single layer or a laminated layer is formed on the back side of the substrate 12. In the case where the insulating film 18 is formed into a laminated film, the insulating film 18 can be formed in a laminated structure of one highly refractive material and another insulating material. Further, as the highly refractive material, it is preferable to use a material having a negative potential in order to increase a dark current suppressing effect. In addition, as an insulating material constituting the insulating film 18, a ruthenium oxide film, a tantalum nitride film, and a yttrium oxynitride film may be used, and by a plasma CVD (Chemical Vapor Deposition) method. These films are formed. Further, in the case where the insulating film 18 is formed of a film having a negative fixed charge, as described above, a CVD method, a sputtering method, an atomic layer evaporation method or the like can be used. Thereafter, a base metal layer 19 is formed over the insulating film 18. The base metal layer 19 can be formed using a sputtering method or a CVD method.

Next, as shown in FIG. 4A, a resist layer 26 is formed on the base metal layer 19 and is shaped into a predetermined mask pattern by exposure and development. Thereafter, the pad segment underlayer 19a, the ineffective pixel light-shielding film 19b, and the inter-pixel light-shielding film 19c are formed by performing etching using the resist layer 26 as a mask. 4B is a view showing a schematic plan configuration of the pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c in FIG. 4A. As shown in FIG. 4B, the inter-pixel light shielding film 19c is formed in a lattice shape such that a portion above the photodiode PD of the substrate 12 is opened, and the ineffective pixel light shielding film 19b is formed to shield the optical black body. The entire surface of the area 51. Further, the pad segment base layer 19a is formed to have a larger diameter than the second opening portion 22b formed in a later process. Next, in this embodiment example, the pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c are formed to be electrically connected to each other.

Next, as shown in FIG. 5, the planarization insulating film 20 is formed so as to cover the pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c. In the case where the planarization insulating film 20 is formed of an organic material, the planarization insulating film 20 can be formed by application, and in the case where the planarization insulating film 20 is formed of an inorganic material, The planarization insulating film 20 is formed by a CVD method. Thereafter, the color filter layer 27 and the crystal lens layer 21 are formed in order. The color filter layer 27 is formed for each pixel by forming a thin film of one of organic materials having a transfer characteristic corresponding to a desired wavelength and performing patterning. Further, the crystal carrying lens layer 21 is formed by applying an organic material to the entire layer so as to cover the color filter layer 27.

In this embodiment example, since the through hole 22 is not formed in the step of forming the color filter layer 27 and the crystal lens layer 21, formation of the color filter layer 27 or the crystal lens may be prevented. Layer 21 is an application of organic material non-uniformity. In this way, the color filter layer 27 or the crystal lens layer 21 may be uniformly formed in the pixel.

Further, in this step, the surface of the crystal lens layer 21 is made flat and does not perform a lens shape process.

Next, as shown in FIG. 6, the first opening portion 22a is formed by anisotropic etching, which penetrates the crystal lens layer 21, the pad segment base layer 19a, and the pad region 52. The substrate 12 is exposed to the surface electrode pad section 15 formed in the wiring layer 13. In the anisotropic etch, CF ₄ /O ₂ , CF ₄ or SF ₆ /O ₂ gas may be used, and the gas is changed and used for each material of the etching. For example, a CF ₄ -based gas is used in etching an organic material layer such as the wiring layer 13, the insulating film 18, and the crystal lens layer 21, and the substrate 12 is formed by etching. A gas based on SF ₆ is used. Here, since the first opening portion 22a is formed such that the surface electrode pad section 15 is exposed at the bottom, the surface electrode pad section 15 is preferably considered in consideration of uniform matching misalignment or the like when open. It is formed to be larger than the diameter of the first opening portion 22a by about 10 μm.

Incidentally, as in the case of one of the solid-state imaging devices of the past, in the case where the wire bonding is directly performed on the surface electrode pad section, it is necessary to form an opening portion in which the surface electrode pad section is exposed so that It has a diameter that allows one of the wire bonds to be performed, and it is necessary to form a diameter of the surface electrode pad section of about 100 nm. On the other hand, in this embodiment example, since the first opening portion 22a is formed to electrically connect the surface electrode pad section 15 and the back electrode pad section 24 (to be described later), it is acceptable The through electrode layer 23 may be formed inside an opening (inside the through hole 22), and the first opening portion 22a may be accepted to have a diameter of at least 3 μm or more. For this reason, it is acceptable that the diameter of the surface electrode pad section 15 is formed in the range of 15 μm to 20 μm even if it has a margin of about +10 μm with respect to the diameter of the first opening portion 22a. form.

In this manner, in the example of this embodiment, it is possible to form a more reduced diameter of the surface electrode pad section 15 than in the case of performing wire bonding on the surface electrode pad section. That is, it is possible to reduce the area of the surface electrode pad section 15 in the wiring layer 13.

Next, as shown in FIG. 7A, the second opening portion 22b is formed by removing the crystal lens layer 21 and the planarization insulating film 20 by anisotropic etching in a region surrounding the first opening portion 22a. In order to expose the surface of a portion of the pad segment base layer 19a (hereinafter referred to as a step portion 29). In this etching process, in order to remove the planarization insulating film 20 and the crystal lens layer 21 by etching, for example, a CF ₄ -based gas is used.

In FIG. 7B, a planar configuration diagram in which the first opening portion 22a and the second opening portion 22b are formed in the section of the through hole 22 is shown. As shown in FIG. 7B, the second opening portion 22b is formed larger than the diameter of the first opening portion 22a and smaller than the diameter of the pad segment base layer 19a. Next, the width W1 of the step portion 29 is determined by the difference between the diameters of the second opening portion 22b and the first opening portion 22a, and the step portion 29 is exposed to the first opening portion 22b by the second opening portion 22b. At the bottom of the two opening portions 22b. The step portion 29 is formed as a portion of a connecting portion between the back electrode pad section 24 and the pad segment base layer 19a in a later process. Then, since the back electrode pad section 24 and the pad segment base layer 19a are electrically connected in the step portion 29, the width W1 of the step portion 29 is preferably formed to be not less than 1 μm and not larger than 10 microns.

Next, as shown in FIG. 8, an electrode material layer 28 is formed on the entire surface including the inner surface of the through hole 22 and the upper surface of the crystal lens layer 21 by using a sputtering method or a CVD method. The electrode material layer 28 formed on the crystal lens layer 21 is used to form the back electrode pad section 24 and the through electrode layer 23 in a later process. For this reason, the thickness of the electrode material layer 28 is set to be necessary for one of the wire bonding and sufficient film thickness. The necessary film thickness for wire bonding is one film thickness necessary for a eutectic reaction of one bonding wire with one of the back electrode pad segments 24, and the electrode material layer 28 is made of, for example, Al-Si-Cu In the case of one of the main alloy formations, the thickness of the film is preferably 500 nm or more. In this embodiment example, since the electrode material layer 28 is formed by a sputtering method or a CVD method, the risk of contamination is small and available as compared with the case where one of the electrode material layers 28 is formed using a Cu damascene technique. A reduction in cost or an improvement in production.

Next, as shown in FIG. 9A, patterning is performed such that the electrode material layer 28 remains only in the pad region 52. In this manner, the through electrode layer 23 is formed in the via 22 and the back electrode pad section 24 is also formed over the crystal lens layer 21 of the pad region 52. FIG. 9B is a plan view showing only one of the back electrode pad section 24 and the through electrode layer 23. The back electrode pad section 24 is formed to have a necessary area for wire bonding. Next, in this embodiment example, since the back electrode pad section 24 is formed at the topmost layer which becomes the light incident side, the back electrode pad section 24 can be unaffected by the wiring layer 13 Freely arranged. For this reason, one of the wafer areas can be reduced. Moreover, in this embodiment example, the back electrode pad section 24 is arranged to extend up to the optical black body region 51. For this reason, it is possible to further improve one of the optical blocking effects in the optical black body region 51.

In addition, a scattering material is produced during the patterning process of the back electrode pad section 24. However, in this embodiment example, since the crystal lens layer 21 has not been processed into a lens shape in the effective pixel region 50, it is easy to remove the scattering as compared with the case where one lens shape has been processed. material. For this reason, it is possible to reduce one of the defects caused by the scattering materials generated at the time of patterning processing of the back electrode pad section 24.

Further, in this embodiment example, since the step portion 29 is formed such that the pad segment base layer 19a is exposed in the through hole 22, the through electrode layer 23 can be electrically connected at the step portion 29 and Pad section base layer 19a.

Next, after the back electrode pad section 24 is formed, the crystal lens 21a is formed by forming a concavo-convex shape in the surface of the crystal lens layer 21 in the effective pixel region 50. At this time, in the pad region 52, since the electrode material layer 28 (the back electrode pad segment 24) is formed on the crystal lens layer 21 and the back electrode pad segment 24 serves as a mask, Therefore, the crystal lens layer 21 is not processed.

The solid-state imaging device shown in Fig. 2 is completed when the above description is made.

In this embodiment example, since the processing of the shape of the crystal carrying lens 21a is performed after the back electrode pad section 24 is formed or the through electrode layer 23 is formed, it may not depend on the back electrode pad section. The crystal carrying lens 21a is processed into a predetermined shape in the case of processing conditions of 24 or the like. Further, since the crystal carrying lens layer 21 is formed before the formation of the through hole 22, application unevenness due to the influence of a step or the like is reduced, making it possible to reduce unevenness in the plane of the crystal carrying lens 21a. Sex. Further, since the processing of the crystal lens 21a is performed after the formation of the back electrode pad section 24, the retention of the scattering metal which occurs when the back electrode pad section 24 is formed, the shape of the crystal lens 21a Collapse or the like does not occur.

In this embodiment example, the connection to an external terminal may be performed by connecting a bonding wire to the back electrode pad section 24. In this embodiment example, since the back electrode pad section 24 can be disposed at the topmost layer, it is possible to easily perform bonding, making it possible to improve an assembly yield.

In addition, in this embodiment example, the pad segment base layer 19a, the invalid pixel light shielding film 19b, and the inter-pixel light shielding film 19c are electrically connected to each other and the pad segment base layer 19a is also electrically connected to the Back electrode pad section 24. Thus, for example, in the case where a grounding connection is connected to one of the back electrode pad sections 24, a grounding is supplied to the surface electrode pad section 15 and a ground potential is also supplied to the ineffective pixel light. The shielding film 19b and the inter-pixel light shielding film 19c are held at a stable potential. Further, since the step portion 29 is formed, the through electrode layer 23 and the pad segment base layer 19a are also electrically connected.

As described above, in the method of manufacturing the solid-state imaging device 1 of the embodiment example, the crystal lens layer 21 is formed before the through hole 22 is formed and the through hole 22, the through electrode layer 23, and the back surface are formed. The electrode pad section 24 is followed by processing of the shape of the crystal lens 21a. Therefore, the attachment of the scattering material to the upper portion of the crystal carrying lens 21a or the collapse of the shape of the crystal carrying lens 21a is reduced and the change in the light agglomeration characteristics can be reduced. Next, according to the method of manufacturing the solid-state imaging device 1 of the example of the embodiment, the shape of the crystal lens 21a can be formed without change in a plane and the surface electrode pad segment 15 can be electrically connected to the back electrode. Pad section 24.

In the solid-state imaging device 1 of the embodiment example, an example in which the pad segment base layer 19a, the ineffective pixel light shielding film 19b, and the inter-pixel light shielding film 19c are formed to be electrically connected to each other has been taken. However, they may also be formed separately from each other and their configurations may be selected differently. Hereinafter, an example in which the pad segment base layer 19a is formed to be electrically separated from the ineffective pixel light-shielding film 19b and the inter-pixel light-shielding film 19c will be described.

2. Second Embodiment

In Fig. 10A, a cross-sectional configuration of one of main sections of a solid-state imaging device relating to a second embodiment of the present invention is shown. Since the overall configuration of the solid-state imaging device of this embodiment example is the same as that of FIG. 1, the repeated explanation is omitted. In addition, in FIG. 10A, the same component symbols are applied to the portions corresponding to those in FIG. 2 and the repeated explanation is omitted.

A solid-state imaging device 60 of this embodiment is separated from the back-side pad electrode section 24 for a light-shielding film 32. A pad section is disposed in an ineffective pixel light-shielding film 49b constituting the optical black body region 51. One of the above examples is shown in Figure 10A.

FIG. 10B is a plan view showing a planar configuration of a pad segment base layer 49a, an ineffective pixel light shielding film 49b, and an inter-pixel light shielding film 49c in the solid-state imaging device 60 of the embodiment. Upon completion, the first opening portion 22a is formed in the pad segment base layer 49a. However, in Fig. 10B, the pad segment base layer 49a is shown corresponding to Fig. 4B in the first embodiment. In this embodiment example, the ineffective pixel light shielding film 49b and the inter-pixel light shielding film 49c are electrically connected to each other. However, the pad segment base layer 49a is not electrically connected to the ineffective pixel light shielding film 49b and the inter-pixel light shielding film 49c. In this manner, in the case where the pad segment base layer 49a is not electrically connected to one of the ineffective pixel light-shielding film 49b and the inter-pixel light-shielding film 49c, it is necessary to separately supply a voltage to the ineffective pixel light-shielding film 49b. .

In the solid-state imaging device 60 of the embodiment example, as shown in FIG. 10A, an opening portion 30 exposing the ineffective pixel light-shielding film 49b is formed over the ineffective pixel light-shielding film 49b. Next, an electrode layer 31 is formed on the bottom and side walls of the opening portion 30, and a pad portion for forming a light-shielding film 32 continuously with the electrode layer 31 is formed on the lens material layer 21. That is, in this embodiment example, the ineffective pixel light shielding film 49b is electrically connected to the pad section for a light shielding film 32 through the electrode layer 31. Further, the pad section for a light-shielding film 32 is formed to be separated from the back electrode pad section 24 and the pad section for a light-shielding film 32 is used as one to an external terminal. pad.

As shown in FIG. 10B, in the case where the pad segment base layer 49a is not electrically connected to one of the ineffective pixel light-shielding film 49b and the inter-pixel light-shielding film 49c (as in the example of this embodiment), it is used for formation. Connected to the pad section of the light-shielding film 32 of one of the ineffective pixel light-shielding films 49b. In this way, it is possible to supply a given voltage to the ineffective pixel light-shielding film 49b and the inter-pixel light-shielding film 49c, and it is possible to stably maintain the potential of the ineffective pixel light-shielding film 49b and the inter-pixel light-shielding film 49c. .

Figure 11 is a process diagram of the solid-state imaging device 60 of the example of this embodiment. Here, only one description will be given regarding one of the processes different from the process in the first embodiment. In this embodiment example, after the process of FIG. 6 in the first embodiment example, as shown in FIG. 11, the opening portion 30 exposing the ineffective pixel light shielding film 49b is formed while forming the second opening portion 22b. . Thereafter, the electrode layer 31 and the pad portion for a light shielding film 32 are formed while forming the through electrode layer 23 and the back electrode pad segment 24. Since the other processes are the same as those in the first embodiment, the repeated explanation is omitted.

For example, an example of this embodiment can be applied in the case where the pad segment base layer 49a is used as a ground wiring and the ineffective pixel light shielding film 49b is fixed at a negative potential. In this case, since the pad segment base layer 49a functions as a guard ring, it is electrically connected to the surface electrode pad segment 15 in the step portion 29.

As in the example of this embodiment, also in the case where the pad section for a light-shielding film 32 is provided separately from the back electrode pad section 24, it may be formed for a light-shielding film 32. The pad section is then processed to the shape of the crystallized lens 21a. For this reason, it is possible to reduce variations in the light agglomeration characteristics of the crystal lens 21a. In addition to this, the same effects as those of the first embodiment can be obtained.

3. Third Embodiment

In Fig. 12, a cross-sectional configuration of one of main sections of a solid-state imaging device relating to a third embodiment of the present invention is shown. Since the overall configuration of the solid-state imaging device 61 of one embodiment of this embodiment is the same as that of FIG. 1, the repeated explanation is omitted. Further, in FIG. 12, the same component symbols are applied to the portions corresponding to those in FIG. 2 and the repeated explanation is omitted.

The solid-state imaging device 61 of this embodiment example is an example in which the insulation between the through electrode layer 23 and the substrate 12 is performed by forming an insulating layer 33 by embedding an insulating material in the substrate 12.

As shown in FIG. 12, in the solid-state imaging device 61 of this embodiment example, the insulating layer 33 is formed in the substrate 12 so as to surround the first opening portion 22a. Before the insulating film 18 is formed, the insulating layer 33 can be formed by forming an opening to penetrate the substrate 12 and embedding, for example, an insulating material such as a tantalum oxide film in the opening.

Further, in the example of this embodiment, the insulating layer 33 is preferably formed at a position directly below the step portion 29 and formed in a shape falling into the region of the step portion 29. In this way, the necessary area for one of the insulating layers 33 can be minimized.

In this embodiment example, the insulation between the through electrode layer 23 and the substrate 12 is maintained by the insulating layer formed to surround the via 22 .

Then, also in the example of this embodiment, the same effect as that of the first embodiment can be obtained.

4. Fourth Embodiment

In Fig. 13, a cross-sectional configuration of one of main sections of a solid-state imaging device relating to a fourth embodiment of the present invention is shown. Since the overall configuration of the solid-state imaging device 62 of one embodiment of this embodiment is the same as that of FIG. 1, the repeated explanation is omitted. Further, in FIG. 13, the same component symbols are applied to the portions corresponding to those in FIG. 2 and the repeated explanation is omitted.

The solid-state imaging device 62 of this embodiment example is an example of performing insulation between the through electrode layer 23 and the substrate 12 by an insulating film 34 formed on the sidewall of the through hole 22.

As shown in Fig. 13, in the solid-state imaging device 62 of this embodiment example, the insulating film 34 made of a ruthenium oxide film is formed on the side walls of the first opening portion 22a and the second opening portion 22b. Next, the through electrode layer 23 is formed in the first opening portion 22a and the second opening portion 22b including the insulating film 34.

14A and 14B are process diagrams of the solid-state imaging device 62 of the embodiment of the embodiment. Here, only one description will be given regarding one of the processes different from the process of the first embodiment. In this embodiment example, after the via hole 22 is formed in FIG. 7A in the first embodiment example, as shown in FIG. 14A, the insulating film 34 made of SiO ₂ is subjected to a P-CVD method or a A CVD method is formed on the entire surface including the inner surface of the through hole 22 and the upper surface of the crystal carrying lens layer 21. The insulating film 34 having good coverage can be formed in the through hole 22 by using a P-CVD method or a CVD method.

By performing etch back after the film formation of the insulating film 34, as shown in FIG. 14B, an unnecessary portion such as the insulating film 34 or the second opening portion 22b at the bottom of the first opening portion 22a is removed. The insulating film 34 of the bottom portion (step portion 29). Thereafter, the solid-state imaging device 62 of this embodiment example can be formed in the same manner as the first embodiment.

In this embodiment example, since the substrate 12 exposed by the first opening portion 22a is covered by the insulating film 34, the through electrode layer 23 and the substrate 12 formed in the first opening portion 22a can be prevented from being mutually in contact with each other. Electrical connection.

Then, also in the example of this embodiment, the same effect as that of the first embodiment can be obtained.

5. Fifth embodiment

In Fig. 15, a cross-sectional configuration of one main section of a solid-state imaging device relating to a fifth embodiment of the present invention is shown. One of the examples of the embodiment of the solid-state imaging device 63 is formed to have one configuration in which the imaging region 3 and the peripheral circuit region are formed in a separate substrate and the respective substrates are laminated. That is, the solid-state imaging device 63 of the embodiment example is in which the imaging region 3 of the solid-state imaging device 1 of FIG. 1 is formed in an upper layer section which becomes a light incident side and such peripheral circuits (such as the vertical drive circuit) 4. The row signal processing circuit 5, the horizontal drive circuit 6 and the control circuit 8) are formed in one instance of the lower layer section. In FIG. 15, the same component symbols are applied to the portions corresponding to those in FIG. 2 and the repeated explanation is omitted.

In the solid-state imaging device 63 of the embodiment example, the lower layer portion 36b is composed of a substrate 37 and a wiring layer 41 formed on the substrate 37. In the lower layer section 36b, a plurality of transistors for driving the peripheral circuits are formed. However, the description of these transistors is omitted. Further, in the wiring layer 41 of the lower layer portion 36b, wiring layers 1M to 4M of a plurality of layers (four layers in Fig. 15) are formed, and an interlayer insulating film 38 is interposed therebetween. Next, in the pad region 52, a surface electrode pad section 39 is formed by the topmost wiring 4M.

Further, an upper layer section 36a is formed to have the same configuration as that of the solid-state imaging device 1 of the first embodiment. However, in this embodiment example, the surface electrode pad section is not formed in the wiring layer 13 of the upper layer section 36a. The wiring portion 13 of the upper layer portion 36a and the wiring portion 41 of the lower layer portion 36b are bonded to each other through a bonding layer 44, thereby stacking the upper layer portion 36a and the lower layer portion 36b. Next, a through hole 42 is formed from the side of the upper layer section 36a so as to reach the surface electrode pad section 39 formed in the lower layer section 36b, and in the through hole 42, electrical connection is made to the surface electrode pad One of the pad section 39 to the back electrode pad section 24 penetrates the electrode layer 43.

In the method of manufacturing the solid-state imaging device 63 of the example of the embodiment, the upper layer section 36a (which is formed according to the process of FIG. 5 of the first embodiment example) and the lower layer section 36b (which are formed to constitute the The transistors or the wiring layers 41) of the peripheral circuits are adhered to each other through the bonding layer 44 such that the wiring layer 13 and the wiring layer 41 are laminated. Thereafter, a first opening portion 42a of the surface electrode pad section 39 reaching the lower layer section 36b is formed from the back side of the upper layer section 36a. Thereafter, in the same manner as the first embodiment, a second opening portion 42b is formed such that the through hole 42 is formed.

Next, after the via hole 42 is formed, the through electrode layer 23, the back electrode pad section 24, and the crystal carrying lens 21a are formed in the same manner as the processes of FIGS. 8 and 9 of the first embodiment. In this way, the solid-state imaging device 63 of the example of this embodiment is completed.

In this manner, also in the case of having one of the substrates of the laminated plural layer (two layers in this embodiment example), the crystal lens layer 21 can be formed before the through hole 42 is formed and can be After the through electrode layer 23 is formed, the shape of the crystal lens 21a is processed. For this reason, the change in the light agglomeration characteristics of the crystal carrying lens 21a can be reduced. In addition to this, the same effects as those of the first embodiment can be obtained.

The present invention is not limited to the solid-state imaging device applied to detect the distribution of incident light amount of visible light and capture it as an image, which can also be applied to capture the distribution of the incident amount of infrared rays, X-rays, particles or the like as a One of the images of a solid-state imaging device. Moreover, in a broad sense, the present invention is generally applicable to detecting a distribution of other physical quantities (such as pressure or electrostatic capacity) and capturing it as one of the images of a solid-state imaging device (a physical quantity distribution detecting device), such as A fingerprint detection sensor.

Furthermore, the present invention is not limited to a solid-state imaging device that reads out one of the pixel signals from each of the unit pixels by sequentially scanning each unit pixel of one pixel segment in units of columns. The present invention is also applicable to an X-Y address type solid-state imaging device that selects one of arbitrary pixels in a pixel unit and reads out a signal from one of the pixel units of the selected pixel.

In addition, the solid-state imaging device may be formed in one form of a single wafer and may also have a modular form of an imaging function, wherein a pixel segment and a signal processing segment or an optical system are packaged together.

Further, the present invention is not limited to the application to the solid-state imaging device and can also be applied to an imaging device. Here, the imaging device means a camera system (such as a digital camera or a video camera) or an electronic device having an imaging function (such as a mobile phone). In addition, there is also a case of the above modular form installed in electronic equipment, that is, a camera module is set as an imaging device.

6. Sixth Embodiment: Electronic Equipment

Next, an electronic apparatus related to the sixth embodiment of the present invention will be described. Figure 16 is a schematic configuration diagram of an electronic apparatus 200 relating to a sixth embodiment of the present invention.

The electronic equipment 200 of this embodiment example represents one of the cases in which the solid-state imaging device 1 of the first embodiment of the present invention described above is used in electronic equipment (a camera).

The electronic device 200 related to this embodiment includes the solid-state imaging device 1, an optical lens 210, a shutter device 211, a driving circuit 212, and a signal processing circuit 213.

The optical lens 210 images image light (incident light) from an object on an imaging area of the solid-state imaging device 1. In this way, a related signal charge is accumulated in the solid-state imaging device 1 for a certain period of time.

The shutter device 211 controls one light irradiation period and one light shielding period to the solid-state imaging device 1.

The drive circuit 212 supplies a drive signal that controls one of the transmission operations of the solid-state imaging device 1 and one shutter operation of the shutter device 211. The signal transmission of the solid-state imaging device 1 is performed by the drive signal (a timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. One of the video signals for which signal processing has been performed is stored in a storage medium such as a memory or output to a monitor.

In the electronic equipment 200 of the embodiment example, since the change in the light agglomeration characteristics of the crystal lens is reduced in the solid-state imaging device 1, an improvement in image quality can be obtained.

As the electronic equipment 200 to which the solid-state imaging device 1 can be applied, it is not limited to a camera and can be applied to a digital camera or an imaging device (such as a camera module) for use in a mobile device such as a mobile phone.

In this embodiment example, the solid-state imaging device 1 has been adopted for configuration in one of electronic equipment. However, it is also possible to use the solid-state imaging devices manufactured in the second to fifth embodiments described above.

The present invention contains the subject matter disclosed in the Japanese Priority Patent Application No. 2010-229753, filed on Jan.

It will be appreciated by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made, depending on the design requirements and other factors, as long as they are within the scope of the appended claims and their equivalents.

1. . . Solid-state imaging device

2. . . Pixel

3. . . Imaging area

4. . . Vertical drive circuit

5. . . Line signal processing circuit

6. . . Horizontal drive circuit

7. . . Output circuit

8. . . Control circuit

9. . . Vertical signal line

10. . . Horizontal signal line

11. . . Substrate

12. . . Substrate

13. . . Wiring layer

14. . . Interlayer insulating film

15. . . Surface electrode pad section

16. . . Contact section

17. . . Support substrate

18. . . Insulating film

19. . . Base metal layer

19a. . . Liner segment base layer

19b. . . Invalid pixel light shielding film

19c. . . Inter-pixel light shielding film

20. . . Flattening insulating film

twenty one. . . Crystal lens layer

21a. . . Crystal lens

twenty two. . . Through hole

22a. . . First opening portion

22b. . . Second opening portion

twenty three. . . Through electrode layer

twenty four. . . Back electrode pad section

25. . . Insulation

26. . . Resist layer

27. . . Color filter layer

28. . . Electrode material layer

29. . . Step part

30. . . Opening part

31. . . Electrode layer

32. . . Light shielding film

33. . . Insulation

34. . . Insulating film

36a. . . Upper section

36b. . . Lower section

37. . . Substrate

38. . . Interlayer insulating film

39. . . Surface electrode pad section

41. . . Wiring layer

42. . . Through hole

43. . . Through electrode layer

44. . . Bonding layer

49a. . . Liner segment base layer

49b. . . Invalid pixel light shielding film

49c. . . Inter-pixel light shielding film

50. . . Effective pixel area

51. . . Optical black body area

52. . . Pad area

60. . . Solid-state imaging device

61. . . Solid-state imaging device

62. . . Solid-state imaging device

63. . . Solid-state imaging device

200. . . Electronic equipment

210. . . optical lens

211. . . Shutter device

212. . . Drive circuit

213. . . Signal processing circuit

1M. . . Wiring

2M. . . Wiring

3M. . . Wiring

4M. . . Wiring

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing the entirety of a solid-state imaging device relating to a first embodiment of the present invention.

Fig. 2 is a cross-sectional configuration diagram of one main section of a solid-state imaging device relating to the first embodiment of the present invention.

Fig. 3 is a process diagram (part 1) of a solid-state imaging device relating to the first embodiment of the present invention.

4A and 4B are respectively a cross-sectional configuration diagram (part 2) of one of the processes of the solid-state imaging device relating to the first embodiment of the present invention, and a pad segment substrate of the solid-state imaging device. A diagram of a schematic planar configuration of a layer, an ineffective pixel light-shielding film, and an inter-pixel light-shielding film.

Fig. 5 is a process diagram (part 3) of a solid-state imaging device relating to the first embodiment of the present invention.

Fig. 6 is a process diagram (part 4) of a solid-state imaging device relating to the first embodiment of the present invention.

7A and 7B are respectively a process diagram (part 5) of a solid-state imaging device according to a first embodiment of the present invention, and a first opening portion and a second opening portion are formed in a through-hole portion. A planar configuration diagram.

Fig. 8 is a process diagram (part 6) of a solid-state imaging device relating to the first embodiment of the present invention.

9A and 9B are respectively a process diagram of a solid-state imaging device relating to a first embodiment of the present invention, and a plan view showing only one of a back electrode pad section and a through electrode layer of the solid-state imaging device.

10A and 10B are respectively a cross-sectional configuration diagram of a main portion of a solid-state imaging device according to a second embodiment of the present invention, and a base layer of a pad segment of the solid-state imaging device, A planar configuration diagram of an ineffective pixel light shielding film and an inter-pixel light shielding film.

Figure 11 is a cross-sectional view showing one of the processes of a solid-state imaging device relating to a second embodiment of the present invention.

Figure 12 is a cross-sectional configuration diagram of one main section of a solid-state imaging device relating to a third embodiment of the present invention.

Figure 13 is a cross-sectional configuration diagram of one main section of a solid-state imaging device relating to a fourth embodiment of the present invention.

14A and 14B are process diagrams (Parts 1 and 2) of a solid-state imaging device relating to a fourth embodiment of the present invention.

Figure 15 is a cross-sectional configuration diagram of one main section of a solid-state imaging device relating to a fifth embodiment of the present invention.

Figure 16 is a schematic cross-sectional configuration diagram of one of the electronic equipment relating to a sixth embodiment of the present invention.

12. . . Substrate

13. . . Wiring layer

14. . . Interlayer insulating film

15. . . Surface electrode pad section

16. . . Contact section

17. . . Support substrate

18. . . Insulating film

19a. . . Liner segment base layer

19b. . . Invalid pixel light shielding film

19c. . . Inter-pixel light shielding film

20. . . Flattening insulating film

twenty one. . . Crystal lens layer

21a. . . Crystal lens

twenty two. . . Through hole

22a. . . First opening portion

22b. . . Second opening portion

twenty three. . . Through electrode layer

twenty four. . . Back electrode pad section

25. . . Insulation

27. . . Color filter layer

50. . . Effective pixel area

51. . . Optical black body area

52. . . Pad area

1M. . . Wiring

2M. . . Wiring

3M. . . Wiring

4M. . . Wiring

Claims (12)

A solid-state imaging device comprising: a substrate, wherein a plurality of pixels including a photoelectric conversion section are formed, the substrate has a back side and a back side; and a wiring layer is formed on a front side of the substrate; a surface electrode pad segment formed in the wiring layer; a light shielding film formed on the rear side of the substrate; a pad segment substrate layer formed on the same layer as the light shielding film a crystal carrying lens layer formed on the light shielding film and the pad segment base layer at the rear side of the substrate; a back electrode pad segment formed over the crystal lens layer a through hole formed to penetrate the crystal lens layer, the pad segment base layer and the substrate to expose the surface electrode pad segment; and a through electrode layer formed in the through hole and connected The surface electrode pad segment and the back electrode pad segment, wherein the light shielding film comprises: an inter-pixel light shielding film shielded between adjacent pixels; and an invalid pixel light shielding film, which is used Masking the plurality of pixels One of inter-effective pixel area. The solid-state imaging device of claim 1, wherein the through electrode layer electrically connects the surface electrode pad segment, the back electrode pad segment, and the pad segment base layer. The solid-state imaging device of claim 1, wherein the inter-pixel light shielding film and the ineffective pixel light shielding film are electrically connected to each other. The solid-state imaging device of claim 3, wherein the inter-pixel light shielding film, the ineffective pixel region, and the pad segment substrate layer are electrically connected to each other. The solid-state imaging device of claim 1, wherein the through hole comprises: a first opening portion formed such that the surface electrode pad portion is exposed to a light incident side; and a second opening portion formed to have a ratio The first opening portion is larger in diameter and formed such that the pad segment base layer is exposed to the light incident side. A solid-state imaging device according to claim 1, wherein the back electrode pad section is formed to extend upward over the ineffective pixel light-shielding film. An electronic device comprising: an optical lens; a solid-state imaging device comprising: a substrate, wherein a plurality of pixels are formed, each pixel having a photoelectric conversion section that generates a signal charge according to the amount of received light; a wiring layer formed on a front side of the substrate; a surface electrode pad section formed in the wiring layer; a light shielding film formed on a back side of the substrate; a pad area a segment base layer formed in the same layer as the light shielding film; a crystal lens layer formed on one of the back side of the substrate on one of the light shielding film and one of the upper layers of the pad layer base layer a light-incident side; a back electrode pad section formed over the crystal-carrying lens layer; a via formed to penetrate the crystal-carrying lens layer, the pad segment base layer, and the substrate to expose the a surface electrode pad segment; and an electrode layer through which the surface electrode pad segment and the back electrode pad segment are connected, and light condensed by the optical lens is incident thereon; a signal processing circuit for processing an output signal from the solid-state imaging device, wherein the light-shielding film comprises: an inter-pixel light shielding film shielded between adjacent pixels; and an invalid pixel light shielding film, It is used to mask one of the invalid pixel regions between the plurality of pixels. The electronic device of claim 7, wherein the through electrode layer electrically connects the surface electrode pad segment, the back electrode pad segment, and the pad segment base layer. The electronic device of claim 7, wherein the inter-pixel light shielding film and the ineffective pixel light shielding film are electrically connected to each other. The electronic device of claim 9, wherein the inter-pixel light shielding film, the ineffective pixel region, and the pad segment substrate layer are electrically connected to each other. The electronic device of claim 7, wherein the through hole comprises: a first opening portion formed to expose the surface electrode pad segment to a light incident side; and a second opening portion formed to have a ratio One of the opening portions is larger in diameter and formed such that the pad segment base layer is exposed to the light incident side. The electronic device of claim 7, wherein the back electrode pad section is formed to extend upwardly above the inactive pixel light shielding film.