TWI599998B - Display apparatus and operation method of timing controller thereof - Google Patents

Description

Display device and its timing controller operation method

The present invention relates to a display device and a method of operating the same, and more particularly to a method of operating a timing controller of a display device and its timing controller.

The display device generally displays the corresponding image according to the screen provided by the video source. However, in the case of displaying a still image, the display device continues to receive the picture transmitted from the video source and displays the same image. In order to reduce the power consumption of the receiving screen when the display device displays the still image, a screen buffer for storing an entire screen can be configured in the display device. In the case of displaying a moving image, the display device can display the corresponding image according to the picture provided by the video source; in the case of displaying the still image, the display device can store the still picture in the picture buffer, and the display device according to the picture The static picture stored in the buffer is displayed.

However, when the picture buffer is configured in the display device, the timing controller configures the circuit for accessing the picture buffer accordingly. According to the above, when there is a picture buffer When the display device of the device operates, the power consumption is relatively increased. Therefore, how to reduce the power consumption of the display device having the picture buffer during operation becomes a design focus of this type of display device.

The invention provides a method for operating a timing controller of a display device and a timing controller thereof, which can reduce power consumption of the display device.

The display device of the present invention includes a picture buffer, a timing controller, a display panel, and a driving circuit. The timing controller is coupled to the video source and the picture buffer to receive the video control signal and the video data signal from the image source, and output the display data. The driving circuit is coupled to the timing controller and the display panel to drive the display panel according to the display data. The timing controller determines an operation mode according to the audio and video control signal, and the timing controller outputs the display data corresponding to the audio and video data signal or the display data corresponding to the picture stored in the picture buffer according to the operation mode, and the timing controller adjusts the picture buffer according to the operation mode. Access frequency.

In an embodiment of the invention, when the operation mode is the standard mode, the timing controller outputs display data corresponding to the audiovisual material signal, and sets the access frequency of the picture buffer to zero.

In an embodiment of the invention, the display device further includes a power supply unit coupled to the timing controller and the picture buffer for providing a system voltage to the picture buffer and the portion of the timing controller that accesses the picture buffer. Circuit. When the operation mode is the standard mode, the timing controller controls the power supply unit to stop providing the system voltage.

In an embodiment of the invention, when the operation mode is the cache mode, the timing controller outputs the display data corresponding to the video data signal, stores the picture transmitted by the video data signal in the picture buffer, and sets the picture buffer. The access frequency is the frequency corresponding to the video data signal.

In an embodiment of the invention, when the operation mode is the self-updating mode, the timing controller outputs display data corresponding to the screen stored in the picture buffer, and sets the access frequency of the picture buffer to the frequency corresponding to the display data.

In an embodiment of the present invention, when the operation mode is the screen update mode, the timing controller outputs display data corresponding to the screen stored in the screen buffer, and stores the screen transmitted by the video material signal in the screen buffer, and sets The access frequency of the picture buffer is the sum of the frequency corresponding to the video data signal and the frequency of the displayed data.

In an embodiment of the present invention, when the operation mode is the resynchronization mode, the timing controller outputs display data corresponding to the screen stored in the picture buffer, and stores the picture transmitted by the video material signal in the picture buffer, and sets The access frequency of the picture buffer is the sum of the frequency corresponding to the video data signal and the frequency of the displayed data.

In an embodiment of the invention, the timing controller includes a data multiplexer, a picture controller, a picture interface circuit, a picture clock generator, and a state determination unit. The data multiplexer has a first input end, a second input end and an output end. The first input end is coupled to the audio and video source to receive the audio and video data signal, and the output end outputs the display data. The picture controller has a first data register and a second data register, and the first data is temporarily stored. The input end of the device is coupled to the video source to receive the video data signal, and the output end of the second data register is coupled to the second input end of the data multiplexer. The screen interface circuit is configured to be coupled to the output end of the first data buffer of the picture controller and the input end of the picture buffer, and coupled to the input end of the second data buffer of the picture controller and the output of the picture buffer end. The picture clock generator is coupled to the picture controller and the picture interface circuit to provide the first clock signal to the picture controller and the picture interface circuit, and is coupled to the picture buffer to provide the second clock signal to the picture buffer. The state determining unit is coupled to the audio and video source to receive the video and audio control signal to determine the operating mode according to the video and audio control signal, and coupled to the data multiplexer to control the output end of the data multiplexer to be coupled to the first input end or the second input end, coupled The screen clock generator adjusts the frequency of the first clock signal and the second clock signal according to the operation mode, and couples the picture controller to control the operation of the picture controller.

In an embodiment of the invention, the first data register and the second data register are respectively a first in first out (FIFO) register.

In an embodiment of the invention, when the operation mode is the standard mode, the state determining unit controls the output end of the data multiplexer to be coupled to the first input end, the control picture controller is in a stop state, and the first clock signal is adjusted. And the frequency of the second clock signal is zero.

In an embodiment of the invention, the display device further includes a power supply unit, a state determination unit, a picture controller, a picture interface circuit, and a picture buffer for providing system voltage to the picture controller and the picture interface circuit. Picture buffer. The state determination unit controls the power supply unit when the operation mode is the standard mode Stop providing system voltage.

In an embodiment of the invention, when the operation mode is the cache mode, the state determining unit controls the output end of the data multiplexer to be coupled to the first input end, the control picture controller is in an operational state, and the first clock is adjusted. The frequency of the signal and the second clock signal is the frequency corresponding to the video data signal.

In an embodiment of the invention, when the operation mode is the self-updating mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, controls the picture controller to be in an operational state, and adjusts the first clock. The frequency of the signal and the second clock signal is the frequency corresponding to the displayed data.

In an embodiment of the present invention, when the operation mode is the picture update mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, and the control picture controller is in an operational state, and adjusts the first clock. The frequency of the signal and the second clock signal is the sum of the frequency of the corresponding audiovisual data signal and the frequency of the displayed data.

In an embodiment of the invention, when the operation mode is the resynchronization mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, the control picture controller is in an operational state, and the first clock signal is adjusted. And the frequency of the second clock signal is the sum of the frequency of the corresponding audio and video data signal and the frequency of the displayed data.

In an embodiment of the invention, when the operation mode is the resynchronization mode and the video data signal transmits the first display screen, the first data register is controlled by the state determining unit to receive the first display screen and provide the received A display screen. When the operation mode is the resynchronization mode and the video data signal transmits the second display screen, the first data register is controlled by the state determination unit to stop receiving the second display screen and stops. Provide a display.

In an embodiment of the invention, when the operation mode is the resynchronization mode and the video data signal is transmitted to the second display screen, the picture clock generator is controlled by the state determining unit to stop providing the first clock signal to the first data temporary. Save.

In an embodiment of the invention, the picture interface circuit provides control of the state determination unit to provide a phase setting signal. When the picture clock generator is controlled by the state determining unit to adjust the frequency of the first clock signal and the second clock signal, the picture clock generator stops providing the first clock signal to the picture controller, and adjusts the first clock. And synchronizing the first clock signal and the second clock signal according to the phase setting signal, and then providing the synchronized first clock signal to the picture controller.

In an embodiment of the invention, the capacity of the second data buffer is greater than or equal to the frequency of the first clock signal and the second clock signal adjusted by the picture clock generator and the first clock signal is synchronized and the second time is synchronized. The capacity corresponding to the time required for the pulse signal.

In an embodiment of the invention, the picture clock generator includes a clock generation circuit, a phase adjustment unit, and a pulse switch unit. The clock generation circuit is coupled to the state determination unit and the picture buffer to control the state determination unit to generate the second clock signal. The phase adjustment unit is coupled to the picture interface circuit and the pulse generation circuit to provide the first clock signal according to the phase setting signal and the second clock signal. The clock switch unit is coupled to the state determining unit, the picture controller and the phase adjusting unit to transmit the first clock signal provided by the phase adjusting unit to the picture controller by the state determining unit.

In an embodiment of the invention, the clock switch unit is in the first clock signal When the ground voltage is applied, the first clock signal is transmitted or stopped to the picture controller.

The method of operating the timing controller of the display device of the present invention includes the following steps. The timing controller determines the operation mode according to the video control signal provided by the video source. The timing controller outputs display data corresponding to the video data signal or display data corresponding to the screen stored in the picture buffer according to the operation mode. The timing controller adjusts the access frequency of the picture buffer of the display device according to the operation mode.

In an embodiment of the invention, the step of the timing controller adjusting the access frequency of the picture buffer of the display device according to the operation mode comprises: when the operation mode is the standard mode, the timing controller outputs the display data corresponding to the video data signal, And setting the access frequency of the picture buffer is zero; when the operation mode is the cache mode, the timing controller outputs the display data corresponding to the video data signal, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture. The access frequency of the buffer is the frequency corresponding to the video data signal; when the operation mode is the self-updating mode, the timing controller outputs the display data corresponding to the picture stored in the picture buffer, and sets the access frequency of the picture buffer to correspond. The frequency of the data is displayed; when the operation mode is the screen update mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture buffer. The access frequency is the frequency of the corresponding audio and video data signal and the display data. When the operation mode is the resynchronization mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture buffer storage. The frequency is the sum of the frequency of the corresponding audio and video data signal and the frequency of the displayed data.

In an embodiment of the invention, the method for operating the timing controller of the display device further includes: when the operation mode is the standard mode, the timing controller controls a system voltage provided by a power supply unit to stop providing to the picture buffer in time. Part of the circuit that accesses the picture buffer in the sequence controller.

In an embodiment of the invention, the method for operating the timing controller of the display device further includes: when the operation mode is the resynchronization mode and the video data signal is transmitted to the first display screen, the timing controller will receive the first The display screen is transmitted to the picture buffer; when the operation mode is the resynchronization mode and the video material signal is transmitted to the second display picture, the timing controller stops receiving the second display picture and stops providing the received display picture to the picture buffer.

Based on the above, the display device of the embodiment of the present invention and the operation method of the timing controller of the timing controller thereof, the timing controller can adjust the access frequency of the picture buffer of the display device according to the operation mode, thereby being partially operable The mode reduces the access frequency of the picture buffer to reduce the power consumption of the display device.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Video source

100, 200, 300‧‧‧ display devices

110, 210, 310‧‧‧ timing controller

120, 220‧‧‧ picture buffer

130‧‧‧Drive circuit

140‧‧‧ display panel

150‧‧‧Power supply unit

211‧‧‧Data multiplexer

213‧‧‧ Picture Controller

215‧‧‧ Picture interface circuit

217, 311‧‧‧ Picture Clock Generator

219‧‧‧State Judgment Unit

220a, 231a, 233a‧‧‧ inputs

220b, 231b, 233b, O‧‧‧ output

231‧‧‧First data register

233‧‧‧Second data register

313‧‧‧ Clock generation circuit

315‧‧‧ phase adjustment unit

317‧‧‧clock switch unit

A‧‧‧ first input

AVC‧‧‧Video Control Signal

AVD‧‧‧ audio and video data signal

B‧‧‧second input

CLK1‧‧‧ first clock signal

CLK2‧‧‧ second clock signal

CMD1‧‧‧Entering instructions

CMD2‧‧‧ screen update instruction

CMD3‧‧‧ jumping out command

DD‧‧‧ Output display data

FD10~FD13, FD20~FD27, FD31~FD33, FD41~FD44‧‧‧ display screen

SPS‧‧‧ phase setting signal

ST‧‧‧ status signal

VDDA‧‧‧ system voltage

S510, S520, S530, S610, S620, S630‧‧ steps

FIG. 1A is a schematic diagram of a system of a display device according to an embodiment of the invention.

FIG. 1B is a timing diagram of video and audio data signals and display materials according to an embodiment of the invention.

FIG. 1C is a schematic diagram showing a state of an operation mode of a display device according to an embodiment of the invention.

2 is a schematic diagram of a system of a display device in accordance with another embodiment of the present invention.

FIG. 3 is a schematic diagram of a system of a display device according to still another embodiment of the present invention.

4 is a timing diagram of video and audio data signals and display materials according to another embodiment of the present invention.

FIG. 5 is a flow chart showing a method of operating a timing controller of a display device according to an embodiment of the invention.

6 is a flow chart showing a method of operating a timing controller of a display device in accordance with another embodiment of the present invention.

FIG. 1A is a schematic diagram of a system of a display device according to an embodiment of the invention. Referring to FIG. 1A , in the embodiment, the display device 100 includes a timing controller 110 , a screen buffer 120 , a driving circuit 130 , a display panel 140 , and a power supply unit 150 . The timing controller 110 is coupled to the video source 10 and the picture buffer 120 to receive the video control signal AVC and the video data signal AVD from the image source 10, and outputs the display data DD, wherein the video source 110 can be a video player or a computer.

The driving circuit 130 is coupled to the timing controller 110 and the display panel 140 to drive the display panel 127 according to the display data DD. The power supply unit 150 is coupled to the timing controller 110 and the picture buffer 120 for providing system voltage VDDA to timing control. Controller 110 and picture buffer 120. Wherein, the power supply unit 150 can be controlled by the timing controller 110 to provide the system voltage VDDA.

In the present embodiment, the timing controller 110 determines an operation mode of the display device 100 according to the video control signal AVC, such as a standard mode, a cache mode, a self-updating mode, a picture update mode, and a resynchronization mode. Moreover, in different operation modes, the manner in which the timing controller 110 generates the display material DD may be different, and the transmission mode of the timing controller 110 and the picture buffer 120 may also be different, that is, the degree of use of the picture buffer 120. It will be different. When the degree of use of the picture buffer 120 is low, the timing controller 110 can reduce the operating frequency (ie, access frequency) of the access picture buffer 120 without affecting the transfer of data, and can reduce the power of the timing controller 110 as a whole. Consumption. In other words, the timing controller 110 outputs the display material DD corresponding to the video material data signal AVD or the display material DD corresponding to the picture stored in the picture buffer 120 according to the operation mode, and the timing controller 110 adjusts the memory of the picture buffer 110 according to the operation mode. Take the frequency.

In addition, in some modes of operation, the picture buffer 120 may be in an idle state, so the timing controller 110 may control the power supply unit 150 to stop providing the system voltage VDDA to the picture buffer 120 and access the picture buffer in the timing controller 110. Part of the circuit of the device 120 to further reduce the power consumption of the display device 100 as a whole.

FIG. 1B is a timing diagram of video and audio data signals and display materials according to an embodiment of the invention. FIG. 1C is a schematic diagram showing a state of an operation mode of a display device according to an embodiment of the invention. Please refer to FIG. 1A to FIG. 1C, in the video and audio control signal AVC Before the transmission enter command CMD1, that is, before the timing controller 110 receives the entry command CMD1, the operation mode of the display device 100 is set to the standard mode, and the video source 10 continuously transmits the display screen (such as FD10) through the video data signal AVD to Timing controller 110. When the operation mode of the display device 100 is the standard mode, the timing controller 110 outputs the display data DD corresponding to the audio-visual data signal AVD, that is, the display data DD forms a display screen corresponding to the display image of the audio-visual data signal AVD (such as FD10). (such as FD20). Since the timing controller 110 generates the display material DD by using the corresponding video material signal AVD, the picture buffer 120 is not used. At this time, the timing controller 110 can turn off the picture buffer 120, and can also set the access of the picture buffer 120. The frequency is zero, and even the control power supply unit 120 can stop supplying the system voltage VDDA to the picture buffer 120 and a part of the circuit of the timing controller 110 that accesses the picture buffer 120.

When the video control signal AVC transmits the incoming command CMD1, that is, the timing controller 110 receives the incoming command CMD1, the operating mode of the display device 100 first enters the cache mode, and the video source 10 transmits a display through the video data signal AVD. (e.g., FD11) to the timing controller 110, wherein the cache mode is maintained for substantially one picture period. When the operation mode is the cache mode, the timing controller 110 still outputs the display data DD corresponding to the video data signal AVD, that is, the display data DD forms a display screen corresponding to the display screen of the video data signal AVD (such as FD11) (eg, FD21).

At this time, the timing controller 110 stores the display screen (such as FD11) transmitted by the video material data signal AVD in the picture buffer 120, that is, the picture buffer 120. In the write state, the timing controller 110 can set the access frequency of the picture buffer 120 to the frequency of the corresponding video material signal AVD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the bit rate of the video material signal AVD is 24 BPS, and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 112.5 MHz (ie, 150M×24/32).

After the cache mode ends, the operation mode of the display device 100 enters the self-updating mode. When the operation mode is the self-updating mode, the timing controller 110 outputs the display data DD corresponding to the display screen stored in the screen buffer 120, that is, the timing controller 110 accesses the display screen stored in the screen buffer 120 to form a display screen. Display screen (such as FD22, FD23).

At this time, since the picture buffer 120 is in the read state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the frequency corresponding to the display material DD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the frame rate of the video material signal AVD is 60 Hz, and the refresh rate of the display panel 140 is 40 Hz, the display data DD can be set to 100 MHz (ie, 150M×40/60). Further, assuming that the bit rate of the display material DD is 24 BPS and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 75 MHz (i.e., 100 M × 24/32).

When the video control signal AVC transmits the picture update command CMD2, that is, the timing controller 110 receives the picture update command CMD2, the operation mode of the display device 100 enters the picture update mode, and the video source 10 transmits a display through the video material signal AVD. a picture (such as FD12) to the timing controller 110, wherein the picture The face update mode generally maintains one screen period and returns to the self-updating mode after the screen update mode ends. When the operation mode is the screen update mode, the timing controller 110 also outputs the display data DD corresponding to the screen stored in the screen buffer 120, that is, the timing controller 110 also accesses the display screen stored in the screen buffer 120. A display screen (such as FD24~FD26) is formed, and the timing controller 110 stores the display screen (such as FD12) transmitted by the video material signal AVD in the picture buffer 120.

At this time, since the picture buffer 120 is in the read/write state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the picture update rate of the video material signal AVD is 60 Hz, and the update rate of the display panel 140 is 40 Hz, the display material DD can be set to 100 MHz (ie, 150 M×40/60). Moreover, assuming that the bit rate of the video material signal AVD and the display material DD are both 24 BPS, and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 187.5 MHz (ie, 150 M×24/ 32+100M×24/32).

When the video control signal AVC transmits the bounce command CMD3, that is, the timing controller 110 receives the bounce command CMD3, the operation mode of the display device 100 first enters the resynchronization mode, and the video source 10 continuously transmits the display screen through the video data signal AVD. (e.g., FD13) to the timing controller 110, returning to the standard mode after the resynchronization mode ends. When the operation mode is the resynchronization mode, the timing controller 110 outputs a display corresponding to the display screen stored in the screen buffer 120. The data DD, that is, the timing controller 110 also accesses the display screen stored in the picture buffer 120 to form a display screen (such as FD 27). The display screen (such as FD 13) transmitted by the video material signal is stored in the picture buffer 120. At this time, since the picture buffer 120 is in the read/write state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

2 is a schematic diagram of a system of a display device in accordance with another embodiment of the present invention. Referring to FIG. 1A and FIG. 2, in the present embodiment, the display device 200 is substantially the same as the display device 100, except that the timing controller 210 and the picture buffer 220 are the same or similar elements. The timing controller 210 includes a data multiplexer 211, a picture controller 213, a picture interface circuit 215, a picture clock generator 217, and a state determination unit 219. The power supply unit 150 is shown as being coupled to the picture buffer 220, the picture controller 213, and the picture interface circuit 215 to provide the system voltage VDDA picture buffer 220, the picture controller 213, and the picture interface circuit 215, but other embodiments of the present invention The power supply unit 150 can also provide the system voltage VDDA to other circuits (such as the data multiplexer 211, the picture clock generator 217, and the state determining unit 219), which is not limited thereto.

The data multiplexer 211 has a first input terminal A, a second input terminal B, and an output terminal O. The first input terminal A of the data multiplexer 211 is coupled to the video source 10 to receive the video data signal AVD, and the data multiplexer 211. The second input terminal B is coupled to the picture controller 213, and the output terminal O of the data multiplexer 211 outputs the display data DD. The picture controller 213 has a first data register 231 and a second data register 233, wherein A data register 231 and a second data register 233 can be first in first out (FIFO) registers, respectively. The input end 231a of the first data register 231 is coupled to the video source 10 to receive the video data signal AVD, and the output end 231b of the first data register 231 is coupled to the picture interface circuit 215. The input end 233a of the second data register 233 is coupled to the picture interface circuit 215, and the output end 233b of the second data register 233 is coupled to the second input end B of the data multiplexer 211.

The interface interface circuit 215 is configured to be coupled to the output end 231b of the first data register 231 of the picture controller 213 and the input end 220a of the picture buffer 220, and coupled to the second data register 233 of the picture controller 213. The input terminal 233a and the output terminal 220b of the picture buffer 220. The picture clock generator 217 is coupled to the picture controller 213 and the picture interface circuit 215 to provide the first clock signal CLK1 to the picture controller 213 and the picture interface circuit 215, and is coupled to the picture buffer 220 to provide the second clock. Signal CLK2 to picture buffer 220. The state judging unit 219 is coupled to the video source 10 to receive the video and audio control signal AVC to determine the operation mode of the display device 200 according to the video control signal AVC. The state determining unit 219 is coupled to the data multiplexer 211 to control the output terminal O of the data multiplexer 211 to be coupled to the first input terminal A or the second input terminal B. The state determining unit 219 is coupled to the screen clock generator 217 to adjust the frequency of the first clock signal CLK1 according to the operation mode of the display device 200. And, the state determining unit 219 is coupled to the picture controller 213 to control the operation of the picture controller 213 through the status signal ST.

According to the above, the picture controller 213 operates according to the status signal ST, and transmits data to the picture interface circuit 215 or from the first clock signal CLK1. The screen interface circuit 215 receives the data; the screen interface circuit 215 transmits the data from the picture controller 213 to the picture buffer according to the first clock signal CLK1 or transfers the data from the picture buffer 220 to the picture controller 213; the picture buffer 220 The data from the picture interface circuit 215 or the transmission data is received to the picture interface circuit 215 according to the second clock signal CLK2.

Assuming that the first clock signal CLK1 is synchronized with the second clock signal CLK2, the picture interface circuit 215 can smoothly access the data of the picture buffer 220, so the picture interface circuit 215 can access the data of the picture buffer 220. It is determined whether the first clock signal CLK1 is synchronized with the second clock signal CLK2. Moreover, the screen interface circuit 215 can calculate a time difference (or phase difference) from the first clock signal CLK through the data timing of the picture buffer 220, and the picture interface circuit 215 provides a phase setting signal according to the calculated time difference (or phase difference). SPS to the picture clock generator 217, so that the picture clock generator 217 adjusts the first clock signal CLK1 and/or the second clock signal CLK2 according to the phase setting signal SPS to make the first clock signal CLK1 and the second time The pulse signal CLK2 is synchronized. The picture buffer 220 can be configured with a specific area for performing an access test to prevent the display picture from being changed, and the action of adjusting the first clock signal CLK1 and/or the second clock signal CLK2 can be performed continuously or The first clock signal CLK1 is executed without being synchronized with the second clock signal CLK2.

Referring to FIG. 1B and FIG. 2, before the video control signal AVC transmits the entry command CMD1, the operation mode of the display device 200 is set to the standard mode. When the operation mode of the display device 200 is the standard mode, the state determination unit 219 controls the data. The output end O of the multiplexer 211 is coupled to the first input terminal A, that is, the video data signal AVD is output as the display data DD, and the state determining unit 219 controls the picture controller 213 to be in a stopped state (even if the picture controller 213 stops operating). The simultaneous state determination unit 219 adjusts the frequency of the first clock signal CLK1 and the second clock signal CLK2 to be zero. Further, the state judging unit 219 can control the power supply unit 120 to stop supplying the system voltage VDDA to the picture controller 213, the picture interface circuit 215, and the picture buffer 220.

When the video control signal AVC transmits the incoming command CMD1, the operation mode of the display device 200 first enters the cache mode. When the operation mode is the cache mode, the state determining unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the first input terminal A; the state determining unit 219 controls the screen controller 213 to be in an operational state, so that the video data is The display screen of the signal AVD (such as FD11) is transmitted to the picture buffer 220 through the picture controller 213 and the picture interface circuit 215 and stored in the picture buffer 220; and the state determining unit 219 can control the picture clock generator 217 to adjust The frequencies of the first clock signal CLK1 and the second clock signal CLK2 are frequencies corresponding to the video data signal AVD.

After the cache mode ends, the operation mode of the display device 200 enters the self-updating mode. When the operation mode is the self-updating mode, the state determining unit 219 controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determining unit 219 controls the picture controller 213 to be in an operational state to enable picture buffering. The display screen stored in the device 220 can be transmitted to the second input terminal B of the data multiplexer 211 through the picture controller 213 and the screen interface circuit 215. At this time, the state judging unit 219 The controllable picture clock generator 217 adjusts the frequency of the first clock signal CLK1 and the second clock signal CLK2 to the frequency corresponding to the display data DD.

When the video control signal AVC transmits the picture update command CMD2, the operation mode of the display device 200 enters the picture update mode, and returns to the self-updating mode after the picture update mode ends. When the operation mode is the picture update mode, the state determination unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determination unit 219 controls the picture controller 213 to be in an operational state. At this time, the state determining unit 219 can control the picture clock generator 217 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 as the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

When the video control signal AVC transmits the jump command CMD3, the operation mode of the display device 200 first enters the resynchronization mode, and returns to the standard mode after the resynchronization mode ends. When the operation mode is the resynchronization mode, the state determination unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determination unit 219 controls the picture controller 213 to be in an operational state. At this time, the state determining unit 219 can control the picture clock generator 217 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 as the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

In an embodiment of the invention, when the picture clock generator 217 is controlled by the state determining unit 219 to adjust the frequencies of the first clock signal CLK1 and the second clock signal CLK2, the picture clock generator 214 stops. Providing the first clock signal CLK1 to the picture controller 213, so that the first data of the picture controller 213 is temporarily stored The device 231 no longer transmits the data, and the second data register 233 of the picture controller 213 no longer receives the data. At this time, the picture clock generator 217 is controlled by the state determining unit 219 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 to the target frequency, wherein the target frequency can refer to the above embodiment, and no longer Narration. Moreover, the picture clock generator 217 synchronizes the first clock signal CLK1 and the second clock signal CLK2 according to the phase setting signal SPS. After the first clock signal CLK1 and the second clock signal CLK2 are synchronized, the picture clock generator 217 supplies the synchronized first clock signal CLK1 to the picture controller 213.

According to the above, when the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are adjusted, the second data register 233 of the picture controller 213 no longer receives the data, but the driving circuit 130 still receives the second data. The scratchpad 233 retrieves the data, that is, the display data DD is still continuously transmitted. Therefore, the capacity of the second data register 233 can be designed to be greater than or equal to the frequency of the first clock signal CLK1 and the second clock signal CLK2, and the first clock signal CLK1 and the second signal are synchronized. The capacity corresponding to the time required for the clock signal CLK2. The picture clock generator 217 can transmit or stop transmitting the first clock signal CLK1 to the picture controller 213 when the first clock signal CLK1 is a ground voltage, to prevent the picture controller 213 from malfunctioning.

FIG. 3 is a schematic diagram of a system of a display device according to still another embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the embodiment, the display device 300 is substantially the same as the display device 200, and is different in the screen clock generator 311 of the timing controller 310, and the state determining unit 219 is further coupled to the screen. Interface circuit 215, wherein the same Or similar elements use the same or similar reference numerals. The picture clock generator 311 includes a clock generation circuit 313, a phase adjustment unit 315, and a pulse switch unit 317, wherein the phase adjustment unit 315 can utilize a Phase Locked Loop (PLL) or a Delay Lock Loop (DLL). The implementation of the present invention is not limited thereto.

The clock generation circuit 313 is coupled to the state determination unit 219 and the picture buffer 220 to control the state determination unit 219 to generate the second clock signal CLK2. The phase adjustment unit 315 is coupled to the picture interface circuit 215 and the pulse generation circuit 313 to provide the first clock signal CLK1 according to the phase setting signal SPS and the second clock signal CLK2. The clock switch unit 317 is coupled to the state determining unit 219, the picture controller 213, and the phase adjusting unit 315 to control the state determining unit 219 to transmit the first clock signal CLK1 provided by the phase adjusting unit 315 to the picture controller 213.

Further, when the picture clock generator 311 is controlled by the state determining unit 219 to adjust the frequencies of the first clock signal CLK1 and the second clock signal CLK2, the clock switch unit 317 is controlled by the state determining unit 219. The first clock signal CLK1 is stopped from being supplied to the picture controller 213, and the clock generation circuit 313 is controlled by the state determining unit 219 to adjust the frequency of the second clock signal CLK2 to the target frequency, wherein the target frequency can be referred to the above embodiment. I will not repeat them here. At this time, the screen interface circuit 215 is controlled by the state determining unit 219 to provide the phase setting signal SPS, so that the picture clock generator 217 provides the synchronized first clock signal according to the phase setting signal SPS and the second clock signal CLK2. CLK1, wherein the first clock signal CLK1 is synchronized with the second clock signal CLK2. At the first clock signal CLK1 and After the second clock signal CLK2 is synchronized, the clock switching unit 317 is controlled by the state determining unit 219 to supply the synchronized first clock signal CLK1 to the picture controller 213.

In an embodiment of the invention, the clock switch unit 317 transmits or stops transmitting the first clock signal CLK1 to the picture controller 213 when the first clock signal CLK1 is the ground voltage to prevent the picture controller 213 from malfunctioning.

4 is a timing diagram of video and audio data signals and display materials according to another embodiment of the present invention. Referring to FIG. 4, in the embodiment, it is assumed that the time when the display device (eg, 100, 200, 300) is in the resynchronization mode corresponds to a plurality of screen periods, that is, the video material data signal AVD transmits a plurality of display screens FD31 to FD33. The display data DD transmits a plurality of display screens FD41 to FD44. Moreover, in this embodiment, the display screens FD31 FD FD33 transmitted by the video material data signal AVD are not all written to the picture buffer (eg, 120, 220), and the picture buffers (eg, 120, 220) are not written. When the picture buffer (such as 120, 220) is in the read state, the access frequency of the picture buffer (such as 120, 220) can be adjusted to the frequency corresponding to the display data DD.

For example, when the display device (eg, 100, 200, 300) is in the resynchronization mode, the first display screen (such as FD31) can be written to the picture buffer in the display screens FD31~FD33 transmitted by the video material data signal AVD. (such as 120, 220), write an odd number of display screens (such as FD31, FD33) to the picture buffer (such as 120, 220), write an even number of display pictures (such as FD32) to the picture buffer (such as 120, 220) , or write a display screen to the picture buffer every n display screens (eg 120, 220). The counting of the display screen can be completed by using a counter, and the counting function can be integrated into the timing controller (such as 110, 210, 310).

Referring to FIGS. 1A and 4, when the operation mode of the display device 100 is the resynchronization mode and the display picture transmitted by the video material signal AVD is written to the picture buffer 120 (corresponding to the first display picture), the timing controller 110 will The display screen of the AV material signal AVD transmission is transmitted to the screen buffer 120. When the operation mode of the display device 100 is the resynchronization mode and the display picture transmitted by the video material signal AVD is not written to the picture buffer 120 (corresponding to the second display picture), the timing controller 110 does not transmit the video material signal AVD. The display screen is transferred to the screen buffer 120.

Referring to FIG. 2, FIG. 3 and FIG. 4, when the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is written to the picture buffer 220 (corresponding to the first display picture), the first data is used. The register 231 is controlled by the state judging unit 219 to receive the display screen transmitted by the video material signal AVD and to provide the received display screen. When the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is not written to the picture buffer 220 (corresponding to the second display picture), the first data register 231 is controlled by the state determination. The unit 219 stops receiving the display screen of the video material signal AVD transmission and stops providing the display screen.

In an embodiment of the present invention, when the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is not written to the picture buffer 220 (corresponding to the second display picture), the picture clock is Generator (such as 217, 311) The controlled state determination unit 219 stops providing the first clock signal CLK1 to the first data register 231.

FIG. 5 is a flow chart showing a method of operating a timing controller of a display device according to an embodiment of the invention. Referring to FIG. 5, in the embodiment, the operation method of the timing controller includes the following steps. The timing controller determines an operation mode according to the video control signal provided by the video source (step S510). The timing controller outputs display data corresponding to the audio/visual material signal or display data corresponding to the screen stored in the picture buffer according to the operation mode (step S520). The timing controller adjusts the access frequency of the picture buffer of the display device in accordance with the operation mode (step S530).

6 is a flow chart showing a method of operating a timing controller of a display device in accordance with another embodiment of the present invention. Referring to FIG. 5 and FIG. 6 , in the embodiment, the operation method of the timing controller further includes steps S610, S620, and S630. In step S610, the timing controller determines whether the operation mode is the resynchronization mode. When the operation mode is the resynchronization mode and the video data signal transmits the first display picture (that is, the display picture to be written to the picture buffer), the timing controller transmits the received first display picture to the picture buffer (step S620). ). When the operation mode is the resynchronization mode and the video data signal transmits the second display picture (that is, the display picture not written to the picture buffer), the timing controller stops receiving the second display picture and stops providing the received display picture to the picture buffer. (step S630). The steps S610, S620, and S630 are continuously performed when the operation mode is the resynchronization mode, but the embodiment of the present invention is not limited thereto. The order of the above steps S510, S520, S530, S610, S620, and S630 is for illustrative purposes, and the embodiments of the present invention are not limited thereto. And the above steps For details of S510, S520, S530, S610, S620, and S630, reference may be made to the embodiments of FIG. 1A to FIG. 1C, FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.

In summary, the display device of the embodiment of the present invention and the operation method of the timing controller of the timing controller thereof, the timing controller can adjust the access frequency of the picture buffer of the display device according to the operation mode, thereby The access frequency of the picture buffer is reduced in the partial operation mode to reduce the power consumption of the display device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Video source

100‧‧‧ display device

110‧‧‧Sequence Controller

120‧‧‧ Picture buffer

130‧‧‧Drive circuit

140‧‧‧ display panel

150‧‧‧Power supply unit

AVC‧‧‧Video Control Signal

AVD‧‧‧ audio and video data signal

DD‧‧‧Display information

VDDA‧‧‧ system voltage

Claims (24)

A display device includes: a picture buffer; a timing controller coupled to a video source and the picture buffer for receiving an audio and video control signal and a video data signal from the image source, and outputting a display data; a display panel, and a driving circuit coupled to the timing controller and the display panel to drive the display panel according to the display data; wherein the timing controller determines an operation mode according to the audio and video control signal, the timing controller And outputting the display data corresponding to the video data signal or the display data corresponding to the picture stored in the picture buffer according to the operation mode, and the timing controller adjusts the access frequency of the picture buffer according to the operation mode; When the operation mode is a standard mode, the timing controller outputs the display material corresponding to the video data signal, and sets the access frequency of the picture buffer to zero. The display device of claim 1, further comprising a power supply unit coupled to the timing controller and the picture buffer for providing a system voltage to the picture buffer and the timing controller And taking part of the circuit of the picture buffer, when the operation mode is the standard mode, the timing controller controls the power supply unit to stop providing the system voltage. The display device of claim 1, wherein when the operation mode is a cache mode, the timing controller outputs the corresponding audio and video data signal. The data is displayed, and the picture transmitted by the video data signal is stored in the picture buffer, and the access frequency of the picture buffer is set to a frequency corresponding to the video data signal. The display device of claim 1, wherein when the operation mode is a self-updating mode, the timing controller outputs the display material corresponding to the picture stored in the picture buffer, and sets the picture buffer. The access frequency is the frequency corresponding to the data displayed. The display device of claim 1, wherein when the operation mode is a screen update mode, the timing controller outputs the display material corresponding to the screen stored in the screen buffer, and the video data signal is The transmitted picture is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the displayed data. The display device of claim 1, wherein when the operation mode is a resynchronization mode, the timing controller outputs the display material corresponding to the picture stored in the picture buffer, and the video data signal is The transmitted picture is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the displayed data. The display device of claim 1, wherein the timing controller comprises: a data multiplexer having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled The audio and video source receives the video data signal, and the output end outputs the display data; a picture controller having a first data register and a second data register, wherein the input end of the first data register is coupled to the video source to receive the video data signal, and the second data is temporarily stored The output end of the device is coupled to the second input end of the data multiplexer; a picture interface circuit is configured to couple the output end of the first data register of the picture controller and the input end of the picture buffer, And an input end of the second data buffer coupled to the picture controller and an output end of the picture buffer; a picture clock generator coupled to the picture controller and the picture interface circuit to provide a first a clock signal to the picture controller and the picture interface circuit, and coupled to the picture buffer to provide a second clock signal to the picture buffer; and a state determining unit coupled to the video source to receive the The audio and video control signal is configured to determine the operation mode according to the audio and video control signal, and coupled to the data multiplexer to control the output end of the data multiplexer to be coupled to the first input end or the second input end, coupled to the Picture time production It is adjusted according to the operating mode of the first clock signal and the frequency of the second clock signal, and coupled to the controller to control the operation of the picture screen of the controller. The display device of claim 7, wherein the first data register and the second data register are respectively a first in first out (FIFO) register. The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the first input terminal to control the screen control when the operating mode is a standard mode. The device is in a stopped state, and the frequency of the first clock signal and the second clock signal is adjusted to be zero. The display device of claim 9, further comprising a power supply unit coupled to the state determination unit, the picture controller, the picture interface circuit and the picture buffer for providing a system voltage to the The picture controller, the picture interface circuit and the picture buffer, when the operation mode is the standard mode, the state determining unit controls the power supply unit to stop providing the system voltage. The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the first input terminal to control the screen when the operating mode is a cache mode. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a frequency corresponding to the video data signal. The display device of claim 7, wherein when the operation mode is a self-updating mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input terminal to control the screen. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a frequency corresponding to the data to be displayed. The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the second input terminal to control the screen when the operation mode is a screen update mode. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a sum of a frequency corresponding to the video data signal and a frequency of the display data. The display device of claim 7, wherein the state determining unit controls the data multiplexer when the operation mode is a resynchronization mode The output end is coupled to the second input end, and controls the picture controller to be in an operational state, and adjusts a frequency of the first clock signal and the second clock signal to a frequency corresponding to the video data signal and a frequency of the display data Sum. The display device of claim 14, wherein the first data register is controlled by the state determining unit when the operating mode is the resynchronization mode and the video data signal transmits a first display picture. Receiving the first display screen and providing the received first display screen, when the operation mode is the resynchronization mode and the video data signal transmits a second display screen, the first data register is controlled by the state The determination unit stops receiving the second display screen and stops providing the display screen. The display device of claim 15, wherein when the operation mode is the resynchronization mode and the video data signal transmits the second display picture, the picture clock generator is controlled by the state determination unit to stop. Providing the first clock signal to the first data register. The display device of claim 7, wherein the picture interface circuit provides control by the state determining unit to provide a phase setting signal, and when the picture clock generator is controlled by the state determining unit, adjusting the first The clock signal generator stops providing the first clock signal to the picture controller to adjust the frequency of the first clock signal and the second clock signal when the frequency of the clock signal and the second clock signal is Up to a target frequency, and synchronizing the first clock signal and the second clock signal according to the phase setting signal, and then providing the synchronized first clock signal to the picture controller. The display device of claim 17, wherein the capacity of the second data register is greater than or equal to the frequency of the first clock signal and the second clock signal of the picture clock generator and is synchronized The capacity corresponding to the time required by the first clock signal and the second clock signal. The display device of claim 17, wherein the picture clock generator comprises: a clock generation circuit coupled to the state determination unit and the picture buffer, to be controlled by the state determination unit to generate the a second clock signal; a phase adjustment unit coupled to the picture interface circuit and the clock generation circuit to provide the first clock signal according to the phase setting signal and the second clock signal; and a clock switch unit, The state determining unit, the picture controller and the phase adjusting unit are coupled to the state determining unit to transmit the first clock signal provided by the phase adjusting unit to the picture controller. The display device of claim 19, wherein the clock switch unit transmits or stops transmitting the first clock signal to the picture controller when the first clock signal is a ground voltage. A method for operating a timing controller of a display device includes: determining, by the timing controller, an operation mode according to an audio and video control signal provided by an audio and video source; and outputting, by the timing controller, a display data corresponding to the audio and video data signal according to the operation mode Or corresponding to the display material stored in the screen buffer; and The timing controller adjusts an access frequency of a picture buffer of the display device according to the operation mode. The method of operating a timing controller of a display device according to claim 21, wherein the step of adjusting the access frequency of the picture buffer of the display device according to the operation mode comprises: when the operation mode In a standard mode, the timing controller outputs the display data corresponding to the video data signal, and sets the access frequency of the picture buffer to zero; when the operation mode is a cache mode, the timing controller outputs And corresponding to the display data of the audio and video data signal, storing the picture transmitted by the video data signal in the picture buffer, and setting the access frequency of the picture buffer to correspond to the frequency of the video data signal; when the operation mode is In a self-updating mode, the timing controller outputs the display data corresponding to the picture stored in the picture buffer, and sets the access frequency of the picture buffer to the frequency corresponding to the data; when the operation mode is a picture In the update mode, the timing controller outputs the display material corresponding to the screen stored in the screen buffer, and the The picture transmitted by the audio data signal is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the display data; and when the operation mode is a resynchronization In the mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the access frequency of the picture buffer. The ratio is the sum of the frequency of the audiovisual data signal and the frequency of the displayed data. The method for operating a timing controller of a display device according to claim 22, further comprising: when the operating mode is the standard mode, the timing controller controls a system voltage provided by a power supply unit to stop providing The picture buffer and a part of the circuit of the timing controller that access the picture buffer. The method for operating the timing controller of the display device of claim 22, further comprising: when the operating mode is the resynchronization mode and the video data signal transmits a first display screen, the timing controller The received first display screen is transmitted to the picture buffer; and when the operation mode is the resynchronization mode and the video material signal transmits a second display picture, the timing controller stops receiving the second display picture and The supply of the received display screen to the screen buffer is stopped.