TWI555183B - Thin film transistor and pixel structure - Google Patents

Description

Thin film transistor and pixel structure

The present invention relates to a thin film transistor and a pixel structure, and more particularly to a thin film transistor and a pixel structure of a display panel.

With the advancement of modern information technology, displays of various specifications have been widely used in the screens of consumer electronic products, such as mobile phones, notebook computers, digital cameras and personal digital assistants (PDAs). Among these displays, since liquid crystal displays (LCDs) and organic electroluminescence displays (OELDs or OLEDs) have advantages of being thin and light and having low power consumption, they have become mainstream products in the market. The process of LCD and OLED includes arranging an array of semiconductor elements on a substrate, and the semiconductor elements include thin film transistors (TFTs).

Conventionally, thin film transistors include top-gate TFTs and bottom-gate TFTs. The thin film transistor includes a semiconductor layer as an active layer or a channel layer. Therefore, if an external light source (for example, a backlight) is irradiated, the semiconductor layer of the TFTs is likely to be caused by illumination. Photo-induced current leakage. Among them, the leakage current caused by the illumination not only affects the performance of the thin film transistor component itself, but also causes cross-talk problems when the screen is displayed, resulting in a decrease in the display quality of the display.

The invention provides a thin film transistor and a pixel structure, which can avoid the problem that the semiconductor layer of the conventional TFTs easily generates leakage current due to illumination.

The thin film transistor of the present invention includes a gate, a gate insulating layer, an active layer, an ohmic contact layer, a source, and a drain. The gate has a recessed structure. The gate insulating layer is on the gate and conformally covers the recessed structure. The active layer is on the gate insulating layer, wherein the active layer is located within the recessed structure of the gate and does not extend to the outside of the recessed structure. The ohmic contact layer is on the active layer and exposes a portion of the active layer. The source and the drain are located above the ohmic contact layer.

The invention further provides a pixel structure comprising a data line, a scan line, a thin film transistor, a protective layer and a pixel electrode. The thin film transistor is as described above. The thin film transistor described above is electrically connected to the data line and the scan line. The protective layer is located above the source and the drain, wherein the protective layer has an opening to expose the drain. The pixel electrode is located above the protective layer, and the pixel electrode is electrically connected to the drain via the opening.

Based on the above, in the thin film transistor of the present invention, since the active layer is located in the recessed structure of the gate and does not extend outside the recessed structure of the gate, the external light source (for example, a backlight) can be blocked from being irradiated to the active layer. . Therefore, the thin of the present invention The membrane transistor can avoid the generation of leakage current caused by illumination.

The above described features and advantages of the invention will be apparent from the following description.

100, 200, 300, 400‧‧‧ film transistors

110, 210, 310, 410‧‧‧ substrates

120, 220, 320, 420‧‧ ‧ gate

125, 225, 325, 425‧‧ ‧ recessed structure

125B, 225B, 325B, 425B‧‧‧ bottom of the recessed structure

Side walls of 125W, 225W, 325W, 425W‧‧‧ recessed structures

130, 230, 330, 430‧‧ ‧ brake insulation

140, 240, 340, 440‧ ‧ active layers

150, 250, 350, 450‧ ‧ ohm contact layer

160‧‧‧Protective layer

C‧‧‧ openings

CL‧‧‧Shared line

D _R ‧‧‧ Thickness of the recessed structure

D _A ‧‧‧ thickness of the active layer

D _I ‧‧‧ thickness of the gate insulating layer

D _G ‧‧‧ gate recess structure is not provided at a thickness

D _BM ‧‧‧ thickness of the gate below the bottom of the recessed structure

D _O ‧‧‧ thickness of ohmic contact layer

D‧‧‧汲

DL‧‧‧ data line

I-I’‧‧‧ cut line

PE‧‧‧ pixel electrode

S‧‧‧ source

SL‧‧‧ scan line

1A to 5A are schematic top views of a manufacturing process of a pixel structure according to an embodiment of the present invention.

1B to 5B are schematic views showing a manufacturing flow corresponding to the section line I-I' of Figs. 1A to 5A, respectively.

Figure 6 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention.

Figure 7 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention.

Figure 8 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention.

The thin film transistor of the present invention can be applied to a pixel structure of a display panel. Therefore, in order to explain in detail the design of the thin film transistor of the present invention, the following description is based on a single pixel structure having the thin film transistor of the present invention. For example, the text will be described in conjunction with the drawings.

1A to 5A are top plan views showing a manufacturing process of a thin film transistor and a pixel structure having the above-described thin film transistor according to an embodiment of the present invention. 1B to 5B are schematic views showing a manufacturing process of a cross section taken along line I-I' of Figs. 1A to 5A, respectively. Take The process flow of the thin film transistor and the pixel structure of the present invention will be sequentially described.

Referring to FIG. 1A and FIG. 1B simultaneously, a substrate 110 is provided. The material of the substrate 110 may be glass, quartz, organic polymer, or other applicable materials.

A gate 120, a scanning line SL, and a common line CL are formed on the substrate 110. The gate 120 has a recessed structure 125, and the recessed structure 125 has a bottom portion 125B and a sidewall 125W. The gate 120 is not provided with a recess structure having a thickness D _G and a thickness D _G equal to or greater than 0.525 μm; the gate 120 located below the bottom of the recess structure has a thickness D _BM and a thickness D _BM equal to or greater than 0.050 μm . The recess structure 125 has a depth D _R and a depth D _R equal to or greater than 0.475 microns and equal to or less than 0.675 microns, as shown in FIG. 1B. In the embodiment, the method for manufacturing the gate 120, the scan line SL, the common line CL, and the recess structure 125 is formed by first forming a metal material layer (not shown) on the substrate 110. The process is to form the gate 120, the scan line SL, and the common line CL; then, the gate 120 is subjected to another patterning process to form the recess structure 125. The above patterning process is, for example, a lithography process, but the invention is not limited thereto. The material of the gate 120, the scan line SL, and the common line CL includes a metal, a metal oxide, an organic conductive material, or a combination thereof.

In the pixel structure of the present embodiment, the scan line SL is electrically connected to the gate 120, and the scan line SL and the common line CL are separated from each other as shown in FIG. 1A. In other embodiments, the scan lines SL and the common lines CL may be the same or different film layers, and are electrically insulated from each other and do not overlap.

Next, a gate insulating layer 130 is formed on the substrate 110, and the gate insulating layer 130 is disposed over the gate 120 and conformably covers the recess structure 125. Here, as shown in FIG. 1B, the gate insulating layer 130 has a thickness D _I , and the thickness D _I is equal to or greater than 0.350 μm and equal to or less than 0.450 μm. In the present embodiment, the material of the gate insulating layer 130 comprises an inorganic material (for example: yttria, tantalum nitride, ytterbium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or the like. Suitable materials, or combinations of the above.

Referring to FIG. 2A and FIG. 2B simultaneously, the active layer 140 is formed on the gate insulating layer 130. The active layer 140 is located within the recess structure 125 of the gate 120 and the active layer 140 does not extend to the exterior of the recess structure 125. Here, as shown in FIG. 2B, the active layer 140 has a thickness D _A and a thickness D _A is equal to or greater than 0.125 μm and equal to or less than 0.165 μm. The active layer 140 is formed by, for example, chemical vapor deposition (CVD) or other suitable processes, first forming an active material layer (not shown), and then passing through a patterning process to define a pattern. The active layer 140 is formed. The above patterning process is, for example, a lithography process, but the invention is not limited thereto. The active layer 140 may be a metal oxide semiconductor material, polycrystalline germanium, amorphous germanium or other suitable semiconductor material, such as Indium-Gallium-Zinc Oxide (IGZO), zinc oxide (Indium-Gallium-Zinc Oxide, IGZO) ZnO) SnO, Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) or Indium-Indium- Tin Oxide, ITO).

Referring to FIG. 3A and FIG. 3B simultaneously, an ohmic contact layer 150 is formed on the active layer 140, and the ohmic contact layer 150 exposes a portion of the active layer 140. Wherein, the ohmic contact layer 150 has a thickness D _O and a thickness D _O is equal to or greater than 0.040 μm and equal to or less than 0.060 μm as shown in FIG. 3B. In the present embodiment, the ohmic contact layer 150 is located in the recess structure 125 of the gate 120 and does not extend to the outside of the recess structure 125, but the invention is not limited thereto. The ohmic contact layer 150 is formed by, for example, chemical vapor deposition (CVD) or other suitable processes, first forming a material layer (not shown), and then patterning the process to form an ohmic layer. Contact layer 150. The above patterning process is, for example, a lithography process, but the invention is not limited thereto. The material of the ohmic contact layer 150 may be a metal oxide semiconductor material containing a dopant, a polysilicon containing a dopant, an amorphous germanium containing a dopant, or other suitable semiconductor material containing a dopant. Or other suitable materials, or a combination of the above.

Referring to FIG. 4A and FIG. 4B simultaneously, a data line DL is formed on the substrate 110, and a source S and a drain D are formed on the ohmic contact layer 150. The method for forming the source S, the drain D, and the data line DL is to form a conductive material layer (not shown) and then patterning to form the source S, the drain D, and the data line DL. For example, the patterning process is performed by lithography and etching, but not limited thereto. In the present embodiment, the pattern of the ohmic contact layer 150 is different from the pattern of the source S and the drain D, but the present invention is not limited thereto. Up to this point, the thin film transistor 100 of the present invention has been formed as shown in Fig. 4B.

In the pixel structure of this embodiment, the data line DL is electrically connected to the source S of the thin film transistor 100, as shown in FIG. 4A. The scan line SL and the data line DL are respectively located in different film layers with an insulating layer interposed therebetween (for example: gate insulation) The layer 130), and the common line CL and the data line DL are respectively located in different film layers with an insulating layer interposed therebetween (for example, the gate insulating layer 130). The extending direction of the scanning line SL is different from the extending direction of the data line DL. Preferably, the extending direction of the scanning line SL is perpendicular to the extending direction of the data line DL, and the invention is not limited thereto.

Based on the above, the thin film transistor 100 of the present embodiment includes the gate 120, the gate insulating layer 130, the active layer 140, the ohmic contact layer 150, the source S, and the drain D. The gate 120 has a recessed structure 125. The gate insulating layer 130 is located on the gate 120 and conformally covers the recess structure 125. The active layer 140 is on the gate insulating layer 130. The active layer 140 is located within the recess structure 125 of the gate 120 and does not extend to the exterior of the recess structure 125. The ohmic contact layer 150 is on the active layer 140 and exposes a portion of the active layer 140. The source S and the drain D are located above the ohmic contact layer 150. In other words, the gate 120, the gate insulating layer 130, the recess structure 125, the active layer 140, the ohmic contact layer 150, the source S, and the drain D constitute the thin film transistor 100 (as shown in FIG. 4B). In the thin film transistor 100 of the present embodiment, the active layer 140 is located in the recess structure 125 of the gate 120 and does not extend to the outside of the recess structure 125; the ohmic contact layer 150 is located in the recess structure 125 of the gate 120 and does not extend to The outside of the recess structure 125, and the pattern of the ohmic contact layer 150 is different from the pattern of the source S and the drain D.

As described above, in the thin film transistor 110, since the active layer 140 is located in the recess structure 125 of the gate 120 and does not extend to the outside of the recess structure 125 of the gate 120, the external light source can be blocked from being irradiated onto the active layer 140. Therefore, leakage current caused by illumination can be avoided.

Please refer to FIG. 5A and FIG. 5B simultaneously, above the source S and the drain D A protective layer 160 is formed in which the protective layer 160 has an opening C to expose the drain D. In the present embodiment, for example, the protective layer 160 is deposited first, and then patterned to form the opening C. The above patterning process is, for example, a lithography process, but the invention is not limited thereto. The material of the protective layer 160 may be the same or different material as the gate insulating layer 130. For example, the material of the protective layer 160 comprises an inorganic material (eg, yttria, tantalum nitride, ytterbium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable material. Or a combination of the above, but the invention is not limited thereto.

Next, a pixel electrode PE is formed on the protective layer 160, wherein the pixel electrode PE penetrates the protective layer 160 via the opening C to electrically connect the drain D. The method for forming the pixel electrode PE is, for example, first forming an electrode material layer (not shown), and then patterning it to form a pixel electrode PE. The above patterning process is, for example, a lithography process, but the invention is not limited thereto. The pixel electrode PE may be a transmissive pixel electrode (for example, a metal oxide), a reflective pixel electrode (for example, a metal material having high reflectivity), or a transflective pixel electrode. Up to this step, the pixel structure of the present invention has been formed. The common line CL is coupled to the pixel electrode PE to form a storage capacitor (not labeled); and the thin film transistor 100 and the storage capacitor are electrically connected to each other (not shown).

As described above, the pixel structure of the present embodiment includes the thin film transistor 100, the data line DL, the scanning line SL, the protective layer 160, and the pixel electrode PE. Since the active layer 140 of the thin film transistor 100 of the pixel structure is located in the recess structure 125 of the gate 120 and does not extend outside the recess structure 125, an external light source (eg, a backlight) can be blocked from being irradiated to the active layer 140. Avoid leakage current caused by illumination The display panel that prevents the use of this pixel structure is cross-talked when the screen is displayed, and the display panel is normally displayed.

Figure 6 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention. The embodiment of FIG. 6 is similar to the structure of FIG. 4B described above, and thus the same elements are denoted by the same reference numerals and the description is not repeated. The structure of FIG. 6 is different from FIG. 4B in that the active layer 240 of the thin film transistor 200 of FIG. 6 is also located within the recessed structure 225 of the gate 220 and does not extend outside of the recessed structure 225. Specifically, the height of the upper surface of the ohmic contact layer 250 of the thin film transistor 200 of FIG. 6 coincides with the height of the upper surface of the gate 220 where the recessed structure 225 is not provided (also the height of the scanning line).

Figure 7 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention. The thin film transistor 300 of FIG. 7 is similar to the above-described thin film transistor 100 of FIG. 4B, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. The main difference between the thin film transistor 300 of FIG. 7 and the thin film transistor 100 of FIG. 4B is that the active layer 340 of the thin film transistor 300 of FIG. 7 is also located within the recessed structure 325 of the gate 320 and does not extend to the recessed structure 325. External. The ohmic contact layer 350 is located within the recess structure 325 and extends further beyond the recess structure 325 of the gate 320.

Figure 8 is a cross-sectional view showing a thin film transistor of another embodiment of the present invention. The thin film transistor 400 of FIG. 8 is similar to the above-described thin film transistor 100 of FIG. 4B, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. The main difference between the thin film transistor 400 of FIG. 8 and the thin film transistor 100 of FIG. 4B is that the active layer 440 of the thin film transistor 400 of FIG. 8 is also located in the recessed structure 425 of the gate 420 and does not extend to the recessed structure 425. External. The ohmic contact layer 450 is located in the concave The recessed structure 325 is further extended to the outside of the recessed structure 325 of the gate 420, wherein the pattern of the ohmic contact layer 450 is the same as the pattern of the source S and the drain D.

In summary, in the thin film transistor of the present invention, since the active layer is located in the recessed structure of the gate and does not extend to the outside of the recessed structure of the gate, the external light source can be blocked from being irradiated to the active layer. Therefore, the thin film transistor of the present invention and the pixel structure having the above-described thin film transistor can avoid leakage current caused by illumination, thereby preventing mutual crosstalk when the screen is displayed, and ensuring normal display of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧film transistor

110‧‧‧Substrate

120‧‧‧ gate

125‧‧‧ recessed structure

The bottom of the 125B‧‧‧ recessed structure

125W‧‧‧ sidewalls of recessed structures

130‧‧‧Brake insulation

140‧‧‧Active layer

150‧‧‧ohm contact layer

D‧‧‧汲

I-I’‧‧‧ cut line

S‧‧‧ source

Claims (10)

A thin film transistor comprising: a gate having a recessed structure; a gate insulating layer on the gate and compliantly covering the recessed structure; an active layer on the gate insulating layer, wherein the active layer Located in the recessed structure of the gate and not extending to the outside of the recessed structure to block a light from being incident on the active layer; an ohmic contact layer on the active layer, and exposing a portion of the active layer; A source and a drain are located above the ohmic contact layer. The thin film transistor according to claim 1, wherein the gate is not provided with a thickness of the recessed structure equal to or greater than 0.525 micrometers, and the recessed structure has a depth equal to or greater than 0.475 micrometers, and is equal to or Less than 0.675 microns. The thin film transistor according to claim 1, wherein the ohmic contact layer is located in the recessed structure of the gate and does not extend to the outside of the recessed structure. The thin film transistor according to claim 1, wherein the ohmic contact layer is located in the recess structure of the gate, and a height of an upper surface of the ohmic contact layer and the gate is not provided with the recess structure The height of the upper surface is the same. The thin film transistor of claim 1, wherein the ohmic contact layer is located within the recessed structure and extends beyond the recessed structure. The thin film transistor according to claim 1, wherein the pattern of the ohmic contact layer is different from the pattern of the source and the drain. The thin film transistor according to claim 1, wherein the ohmic connection The pattern of the contact layer is the same as the source and the pattern of the drain. The thin film transistor according to claim 1, wherein the recessed structure of the gate has a bottom and a sidewall, and the gate under the bottom of the recess has a thickness equal to or greater than 0.050 μm. The thin film transistor according to claim 1, wherein the thickness of the gate insulating layer is equal to or greater than 0.350 μm and equal to or less than 0.450 μm, and the thickness of the active layer is equal to or greater than 0.125 μm and equal to or less than 0.165 microns, and the thickness of the ohmic contact layer is equal to or greater than 0.040 microns and equal to or less than 0.060 microns. A pixel structure includes: a data line and a scan line; a thin film transistor electrically connected to the data line and the scan line, wherein the thin film transistor is as described in claim 1; a protective layer Located above the source and the drain, wherein the protective layer has an opening to expose the drain; a pixel electrode is located above the protective layer, and the pixel electrode passes through the opening Extremely electrical connection.