TWI553799B - Semiconductor package structure - Google Patents
Semiconductor package structure Download PDFInfo
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- TWI553799B TWI553799B TW104127972A TW104127972A TWI553799B TW I553799 B TWI553799 B TW I553799B TW 104127972 A TW104127972 A TW 104127972A TW 104127972 A TW104127972 A TW 104127972A TW I553799 B TWI553799 B TW I553799B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本發明是有關於一種半導體封裝結構，且特別是有關於一種具有較佳散熱效果的半導體封裝結構。The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having a preferred heat dissipation effect.
在半導體產業中， 積體電路(Integrated Circuits, IC)的生產，主要分為三個階段：晶片(die)的製造、積體電路(IC)的製作以及積體電路(IC)的封裝(Package)等。其中，晶片係經由晶圓(Wafer)製作、電路設計、光罩製作以及切割晶圓等步驟而完成，而每一顆由晶圓切割所形成的晶片，經由晶片上之焊墊(Bonding Pad)與外部訊號電性連接後， 再以包封體將晶片包覆著，其封裝之目的在於防止晶片受到濕氣、熱量、雜訊的影響，並提供晶片與外部電路， 比如與印刷電路板(Printed Circuit Board, PCB)或其他封裝用基板之間電性連接的媒介，如此即完成積體電路的封裝(Package)步驟。In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the manufacture of chips, the fabrication of integrated circuits (ICs), and the packaging of integrated circuits (ICs). )Wait. The wafer is completed by steps of wafer fabrication, circuit design, mask fabrication, and wafer dicing, and each wafer formed by wafer dicing is passed through a bonding pad on the wafer (Bonding Pad). After being electrically connected to the external signal, the wafer is coated with an encapsulation, the purpose of which is to prevent the wafer from being affected by moisture, heat, noise, and to provide a wafer and an external circuit, such as a printed circuit board ( The printed circuit board, PCB, or other medium for electrical connection between the package substrates, thus completing the package step of the integrated circuit.
為了連接上述之晶片和封裝用基板，通常會使用導線(Wire)及/或焊球(Bump)作為接合之媒介。其中，打線接合(Wire bonding ) 是透過導線將晶片及導線架(lead frame)連接起來的技術。覆晶接合技術(Flip Chip Interconnect Technology)即是在晶片之焊墊上以陣列排列的方式形成焊球，接著再將晶片翻覆之後，利用晶片上之焊球分別對應連接至封裝用基板上的接點，使得晶片可經由焊球而電性連接至封裝用基板，再經由封裝用基板之內部線路及表面之接點而與外部訊號電性連接。In order to connect the above wafer and the package substrate, a wire (Wire) and/or a bump (bump) is usually used as a bonding medium. Among them, wire bonding is a technique of connecting a wafer and a lead frame through a wire. Flip Chip Interconnect Technology (Flip Chip Interconnect Technology) is to form solder balls in an array on the pads of the wafer, and then flip the wafers, and then connect the contacts on the substrate for packaging by solder balls on the wafers. The wafer can be electrically connected to the package substrate via the solder ball, and electrically connected to the external signal via the contact between the internal circuit and the surface of the package substrate.
隨著晶片的效能越高，晶片運作時產生的熱量也愈高，如此將導致晶片之本身的溫度逐漸升高。當晶片之本身的溫度一旦超出其正常的工作溫度範圍時，晶片之內部電路可能會發生運算錯誤的現象，或是暫時性地失效。如何能夠提升半導體封裝結構的散熱效果則是本領域所欲探討的其中一項重點。As the efficiency of the wafer is higher, the heat generated during operation of the wafer is higher, which will result in a gradual increase in the temperature of the wafer itself. When the temperature of the wafer itself exceeds its normal operating temperature range, the internal circuitry of the chip may malfunction or temporarily fail. How to improve the heat dissipation effect of the semiconductor package structure is one of the key points to be explored in the field.
本發明提供一種半導體封裝結構， 其具有較佳的散熱效果。The invention provides a semiconductor package structure which has better heat dissipation effect.
本發明的一種半導體封裝結構，包括一基座、一第一晶片、一包封體、一導熱組件及一散熱板件。第一晶片配置於基座上且包括一第一貫通孔。包封體配置於基座上且包封第一晶片，包封體包括對應於第一貫通孔的一孔洞。導熱組件填充於第一貫通孔及孔洞中，且導熱組件不與第一晶片電性連接。散熱板件配置於包封體上且接觸導熱組件。A semiconductor package structure of the present invention includes a susceptor, a first wafer, an encapsulant, a thermally conductive component, and a heat sink. The first wafer is disposed on the base and includes a first through hole. The encapsulation body is disposed on the pedestal and encloses the first wafer, and the encapsulation body includes a hole corresponding to the first through hole. The heat conducting component is filled in the first through hole and the hole, and the heat conducting component is not electrically connected to the first chip. The heat dissipation plate member is disposed on the enclosure and contacts the heat conduction component.
在本發明的一實施例中，上述的基座為一導線架，導線架包括一晶片座與多個導腳，第一晶片透過多條導線連接於這些導腳。In an embodiment of the invention, the pedestal is a lead frame, and the lead frame includes a wafer holder and a plurality of lead pins, and the first wafer is connected to the lead pins through a plurality of wires.
在本發明的一實施例中，上述的第一晶片透過一散熱膠層連接於晶片座，且散熱膠層接觸導熱組件。In an embodiment of the invention, the first wafer is connected to the wafer holder through a heat dissipation adhesive layer, and the heat dissipation adhesive layer contacts the heat conduction component.
在本發明的一實施例中，上述的上述的導熱組件包括位在第一貫通孔內的一晶片導熱柱、位在包封體內的一包封體導熱柱以及連接於晶片導熱柱與包封體導熱柱的一銲球。In an embodiment of the invention, the heat conducting component comprises a wafer thermal conduction post located in the first through hole, an envelope thermal conduction post in the encapsulation body, and a thermal conduction post and an encapsulation connected to the wafer. A solder ball of a heat conduction column.
在本發明的一實施例中，上述的第一晶片包括多個第一貫通孔，包封體包括多個孔洞，這些孔洞分別對應於這些第一貫通孔。In an embodiment of the invention, the first wafer includes a plurality of first through holes, and the enclosure includes a plurality of holes, and the holes respectively correspond to the first through holes.
在本發明的一實施例中，上述的半導體封裝結構更包括一第二晶片，配置於第一晶片上且包括一第二貫通孔，其中第二貫通孔對應於第一晶片的第一貫通孔以及該封體的孔洞，導熱組件填充於第二貫通孔且不與第二晶片電性連接。In an embodiment of the present invention, the semiconductor package structure further includes a second wafer disposed on the first wafer and including a second through hole, wherein the second through hole corresponds to the first through hole of the first wafer And the hole of the sealing body, the heat conducting component is filled in the second through hole and is not electrically connected to the second wafer.
在本發明的一實施例中，上述的第二晶片透過一導線電性連接於第一晶片。In an embodiment of the invention, the second wafer is electrically connected to the first wafer through a wire.
在本發明的一實施例中，上述的第一晶片包括多個第一貫通孔，第二晶片包括多個第二貫通孔，包封體包括多個孔洞，這些孔洞分別對應於這些第一貫通孔與這些第二貫通孔。In an embodiment of the invention, the first wafer includes a plurality of first through holes, and the second wafer includes a plurality of second through holes, and the enclosure includes a plurality of holes, the holes respectively corresponding to the first through holes Holes and these second through holes.
在本發明的一實施例中，上述的第一晶片的第一貫通孔、第二晶片的第二貫通孔以及包封體的孔洞的直徑分別約在50微米至100微米之間。In an embodiment of the invention, the diameter of the first through hole of the first wafer, the second through hole of the second wafer, and the hole of the encapsulant are respectively between about 50 micrometers and 100 micrometers.
在本發明的一實施例中，上述的導熱組件包括位在第一貫通孔與第二貫通孔內的一晶片導熱柱、位在包封體內的一包封體導熱柱以及連接於晶片導熱柱與包封體導熱柱的一銲球。In an embodiment of the invention, the heat conducting component comprises a wafer thermal conduction post located in the first through hole and the second through hole, an envelope thermal conduction post in the encapsulation body, and a thermal conduction column connected to the wafer. A solder ball with a thermally conductive column of the encapsulation.
基於上述，本發明的半導體封裝結構透過在第一晶片中未影響電路處設有第一貫通孔、包封體在對應於第一貫通孔處設有孔洞，導熱組件填充於第一貫通孔及孔洞中且不與第一晶片電性連接，導熱組件向下透過散熱膠層接觸導熱組件，向上接觸散熱板件，以將第一晶片所發出的熱量向上下方向傳遞，而提升半導體封裝結構整體的散熱效果。此外，本發明的半導體封裝結構也可以是多晶片封裝結構，堆疊在第一晶片上的第二晶片在對應於第一貫通孔且未影響電路處設有第二貫通孔，導熱組件也填充第二貫通孔，如此一來，第一晶片與第二晶片所發出的熱量便能夠透過導熱組件向上下方向傳遞，而提升半導體封裝結構整體的散熱效果。Based on the above, the semiconductor package structure of the present invention is provided with a first through hole in the unaffected circuit of the first wafer, and the encapsulant is provided with a hole corresponding to the first through hole, and the heat conducting component is filled in the first through hole and The hole is not electrically connected to the first chip, and the heat conducting component contacts the heat conducting component downwardly through the heat sink layer, and contacts the heat sink plate upward to transfer the heat emitted by the first chip to the upper and lower directions, thereby improving the overall semiconductor package structure. Cooling effect. In addition, the semiconductor package structure of the present invention may also be a multi-chip package structure. The second wafer stacked on the first wafer is provided with a second through hole corresponding to the first through hole and not affected by the circuit, and the heat conduction component is also filled. The two through holes, so that the heat generated by the first wafer and the second wafer can be transmitted through the heat conducting component in the up and down direction, thereby improving the heat dissipation effect of the entire semiconductor package structure.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
在本實施例中，基座110為一導線架112，導線架112包括一晶片座114與多個導腳116，第一晶片120配置於導線架112的晶片座114上。更詳細地說，第一晶片120透過一散熱膠層170連接於導線架112的晶片座114。散熱膠層170的成分例如是銀膠，但散熱膠層170的種類並不以此為限制。In the present embodiment, the pedestal 110 is a lead frame 112. The lead frame 112 includes a wafer holder 114 and a plurality of guide pins 116. The first wafer 120 is disposed on the wafer holder 114 of the lead frame 112. In more detail, the first wafer 120 is connected to the wafer holder 114 of the lead frame 112 through a heat dissipation adhesive layer 170. The composition of the heat dissipation adhesive layer 170 is, for example, silver paste, but the type of the heat dissipation adhesive layer 170 is not limited thereto.
在本實施例中，第一晶片120以打線接合技術電性連接於基座110，更明確地說，第一晶片120透過導線180連接於導線架112的導腳116，需在此說明的是圖1僅示意性地繪示一條導線180，實際上第一晶片120透過導線180連接於導線架112的導腳116。當然，第一晶片120電性連接於基座110的方式並不以此為限制。在其他的實施例中，基座110也可以是電路板，第一晶片120也可以覆晶接合的技術，透過凸塊電性連接於基座110。第二晶片130配置於第一晶片120上且透過導線180電性連接於第一晶片120。包封體140配置於基座110上且包封第一晶片120、第二晶片130及導線180。In the present embodiment, the first wafer 120 is electrically connected to the susceptor 110 by a wire bonding technique. More specifically, the first wafer 120 is connected to the lead 116 of the lead frame 112 through the wire 180. FIG. 1 is only schematically shown as a wire 180. In fact, the first wafer 120 is connected to the lead 116 of the lead frame 112 through the wire 180. Of course, the manner in which the first wafer 120 is electrically connected to the susceptor 110 is not limited thereto. In other embodiments, the pedestal 110 can also be a circuit board. The first wafer 120 can also be bonded to the susceptor 110 through a bump. The second wafer 130 is disposed on the first wafer 120 and electrically connected to the first wafer 120 through the wires 180 . The encapsulant 140 is disposed on the susceptor 110 and encapsulates the first wafer 120, the second wafer 130, and the wires 180.
在本實施例中，特別採用下面的設計來提升半導體封裝結構100的散熱效果。詳細地說，第一晶片120包括第一貫通孔122，第一貫通孔122貫穿第一晶片120，且第一貫通孔122設置在第一晶片120中未影響電路處。第二晶片130包括對應於第一貫通孔122的第二貫通孔132，同樣地，第二貫通孔132貫穿第二晶片130，且第二貫通孔132設置在第二晶片130中未影響電路處。也就是說，在製作時，設計者可先根據第二晶片130要堆疊在第一晶片120上的何處，來確定第一晶片120與第二晶片130中哪些位置是能夠一起被穿孔而不會影響到第一晶片120與第二晶片130的電路，第一貫通孔122與第二貫通孔132便可以設置在上述的位置。In the present embodiment, the following design is particularly employed to enhance the heat dissipation effect of the semiconductor package structure 100. In detail, the first wafer 120 includes a first through hole 122, the first through hole 122 penetrates the first wafer 120, and the first through hole 122 is disposed in the first wafer 120 without affecting the circuit. The second wafer 130 includes a second through hole 132 corresponding to the first through hole 122. Similarly, the second through hole 132 penetrates the second wafer 130, and the second through hole 132 is disposed in the second wafer 130 without affecting the circuit. . That is, at the time of fabrication, the designer can first determine which positions of the first wafer 120 and the second wafer 130 can be pierced together according to where the second wafer 130 is to be stacked on the first wafer 120. The circuits of the first wafer 120 and the second wafer 130 are affected, and the first through holes 122 and the second through holes 132 may be disposed at the above positions.
包封體140包括對應於第一貫通孔122與第二貫通孔132的一孔洞142。在本實施例中，第一晶片120的第一貫通孔122、第二晶片130的第二貫通孔132以及包封體140的孔洞142的直徑尺寸實質上相同，第一晶片120的第一貫通孔122、第二晶片130的第二貫通孔132以及包封體140的孔洞142的直徑分別約在50微米至100微米之間，當然，在其他實施例中，第一晶片120的第一貫通孔122、第二晶片130的第二貫通孔132以及包封體140的孔洞142的直徑尺寸也可以不同，且第一晶片120的第一貫通孔122、第二晶片130的第二貫通孔132以及包封體140的孔洞142的尺寸並不以此為限制。The encapsulation body 140 includes a hole 142 corresponding to the first through hole 122 and the second through hole 132. In this embodiment, the first through hole 122 of the first wafer 120, the second through hole 132 of the second wafer 130, and the hole 142 of the encapsulant 140 have substantially the same diameter, and the first through hole of the first wafer 120 The diameter of the hole 122, the second through hole 132 of the second wafer 130, and the hole 142 of the encapsulant 140 are respectively between about 50 micrometers and 100 micrometers. Of course, in other embodiments, the first through-hole of the first wafer 120 The diameter of the hole 122, the second through hole 132 of the second wafer 130, and the hole 142 of the encapsulation body 140 may be different, and the first through hole 122 of the first wafer 120 and the second through hole 132 of the second wafer 130 may be different. The size of the hole 142 of the enclosure 140 is not limited thereto.
導熱組件150填充於第一貫通孔122、第二貫通孔132及孔洞142中。詳細地說，在本實施例中，導熱組件150包括位在第一貫通孔122與第二貫通孔132內的一晶片導熱柱152、位在包封體140的孔洞142內的一包封體導熱柱154以及連接於晶片導熱柱152與包封體導熱柱154的一銲球156。散熱板件160配置於包封體140上且接觸導熱組件150。在本實施例中，散熱板件160是一個平面的板體，導熱組件150貫穿第一晶片120、第二晶片130與包封體140，導熱組件150的下方接觸散熱膠層170，且導熱組件150的上方接觸散熱板件160。如此一來，當半導體封裝結構100的第一晶片120與第二晶片130在運作時，第一晶片120與第二晶片130所發出的熱，便可以透過晶片導熱柱152向下經過散熱膠層170與基座110的晶片座114而傳遞至外界，並且熱量也可透過晶片導熱柱152向上經過銲球156、包封體導熱柱154與散熱板件160而傳遞至外界，有效地提升半導體封裝結構100的散熱效果。The heat transfer component 150 is filled in the first through hole 122 , the second through hole 132 , and the hole 142 . In detail, in the embodiment, the heat conducting component 150 includes a wafer heat conducting column 152 located in the first through hole 122 and the second through hole 132, and an envelope located in the hole 142 of the envelope body 140. The heat conducting column 154 and a solder ball 156 connected to the wafer heat conducting column 152 and the encapsulating body heat conducting column 154. The heat dissipation plate member 160 is disposed on the encapsulation body 140 and contacts the heat conduction component 150. In this embodiment, the heat dissipation plate member 160 is a flat plate body, the heat conduction component 150 penetrates the first wafer 120, the second wafer 130 and the encapsulation body 140, and the lower portion of the heat conduction component 150 contacts the heat dissipation adhesive layer 170, and the heat conduction component The upper portion of 150 contacts the heat sink member 160. In this way, when the first wafer 120 and the second wafer 130 of the semiconductor package structure 100 are in operation, the heat generated by the first wafer 120 and the second wafer 130 can pass through the heat conduction pillar 152 of the wafer and pass through the heat dissipation adhesive layer. 170 is transferred to the outside of the wafer holder 114 of the susceptor 110, and the heat can also be transmitted to the outside through the solder ball 156, the heat-conducting column 154 and the heat-dissipating plate member 160 through the heat-conducting column 152 of the substrate, thereby effectively improving the semiconductor package. The heat dissipation effect of the structure 100.
當然，導熱組件150與散熱板件160的形式並不以此為限制。在其他實施例中，導熱組件150也可以是銲球156，經過加熱之後融熔流到第一貫通孔122與第二貫通孔132，散熱板件160也可以具有一凸出部（未繪示），凸出部可以伸入包封體140的孔洞142內接觸到未流入第一貫通孔122與第二貫通孔132內的銲球156。此外，雖然在圖1中，晶片導熱柱152是填滿於第一貫通孔122與第二貫通孔132，但在其他實施例中，晶片導熱柱152也可以是不填滿於第一貫通孔122與第二貫通孔132，也就是說，局部的第一貫通孔122與第二貫通孔132作為傳熱的空氣通道。Of course, the form of the heat conducting component 150 and the heat sink member 160 is not limited thereto. In other embodiments, the heat-conducting component 150 may also be a solder ball 156. After heating, the heat-melting component 150 may be melted to the first through-hole 122 and the second through-hole 132. The heat-dissipating plate member 160 may also have a protruding portion (not shown). The protrusions may protrude into the holes 142 of the encapsulation body 140 to contact the solder balls 156 that do not flow into the first through holes 122 and the second through holes 132. In addition, in FIG. 1 , the wafer thermal conduction column 152 is filled with the first through hole 122 and the second through hole 132 , but in other embodiments, the wafer thermal conduction column 152 may not fill the first through hole. 122 and the second through hole 132, that is, the partial first through hole 122 and the second through hole 132 serve as air passages for heat transfer.
值得一提的是，晶片導熱柱152與包封體導熱柱154的材料例如是銅，銲球156的材料例如是錫，但導熱組件150的材料種類與形式並不以此為限制。在本實施例中，由於第一晶片120的第一貫通孔122與第二晶片130的第二貫通孔132設置在不會影響電路的位置，因此，即便導熱組件150填充於第一晶片120的第一貫通孔122、第二晶片130的第二貫通孔132，導熱組件150也不與第一晶片120與第二晶片130電性連接，而僅具有散熱的效果。It is worth mentioning that the material of the heat conduction column 152 and the heat-conducting column 154 of the package is, for example, copper, and the material of the solder ball 156 is, for example, tin, but the material type and form of the heat-conductive component 150 are not limited thereto. In this embodiment, since the first through holes 122 of the first wafer 120 and the second through holes 132 of the second wafer 130 are disposed at positions that do not affect the circuit, even if the heat conducting component 150 is filled in the first wafer 120 The first through hole 122 and the second through hole 132 of the second wafer 130 are not electrically connected to the first wafer 120 and the second wafer 130, and have only the effect of dissipating heat.
另外，需說明的是，為了清楚地表示出第一貫通孔122、第二貫通孔132、孔洞142及導熱組件150的相對關係，在圖1所舉的例子中，僅繪示出一個第一貫通孔122、一個第二貫通孔132、一個孔洞142及一個導熱組件150，且放大了第一貫通孔122、第二貫通孔132、孔洞142及導熱組件150的尺寸。實際上第一貫通孔122、第二貫通孔132、孔洞142及導熱組件150的尺寸很小，因此，為了更為提升半導體封裝結構100的散熱效果，第一晶片120可包括多個第一貫通孔122，第二晶片130可包括多個第二貫通孔132，包封體140可包括多個孔洞142，這些孔洞142分別對應於這些第一貫通孔122與這些第二貫通孔132，以更快速地將第一晶片120與第二晶片130所發出的熱量向外傳遞。In addition, in order to clearly show the relative relationship between the first through hole 122, the second through hole 132, the hole 142, and the heat conducting component 150, in the example illustrated in FIG. 1, only one first is shown. The through hole 122, the second through hole 132, the one hole 142, and one heat conducting component 150 enlarge the dimensions of the first through hole 122, the second through hole 132, the hole 142, and the heat conducting component 150. In fact, the size of the first through hole 122, the second through hole 132, the hole 142, and the heat conducting component 150 is small. Therefore, in order to further improve the heat dissipation effect of the semiconductor package structure 100, the first wafer 120 may include a plurality of first through holes. The second wafer 130 may include a plurality of second through holes 132. The encapsulant 140 may include a plurality of holes 142 corresponding to the first through holes 122 and the second through holes 132, respectively. The heat emitted by the first wafer 120 and the second wafer 130 is quickly transferred outward.
此外，上述的半導體封裝結構100是以多晶片封裝結構為例，當然，半導體封裝結構100的種類並不以此為限制，在其他實施例中，即便半導體封裝結構100僅具有單一個晶片（例如僅具有第一晶片120），也可以透過上述的方式，在第一晶片120與包封體140中設有貫穿且彼此對應的第一貫通孔122與孔洞142，透過設置在第一貫通孔122與孔洞142中的導熱組件150將第一晶片120的熱量向上與向下傳遞至外界。In addition, the above-described semiconductor package structure 100 is exemplified by a multi-chip package structure. Of course, the type of the semiconductor package structure 100 is not limited thereto. In other embodiments, even if the semiconductor package structure 100 has only a single wafer (for example, The first through-holes 122 and the holes 142 that are penetrating and corresponding to each other are provided in the first wafer 120 and the encapsulation body 140 through the first through-holes 122. The heat transfer assembly 150 in the hole 142 transfers the heat of the first wafer 120 up and down to the outside.
綜上所述，本發明的半導體封裝結構透過在第一晶片中未影響電路處設有第一貫通孔、包封體在對應於第一貫通孔處設有孔洞，導熱組件填充於第一貫通孔及孔洞中且不與第一晶片電性連接，導熱組件向下透過散熱膠層接觸導熱組件，向上接觸散熱板件，以將第一晶片所發出的熱量向上下方向傳遞，而提升半導體封裝結構整體的散熱效果。此外，本發明的半導體封裝結構也可以是多晶片封裝結構，堆疊在第一晶片上的第二晶片在對應於第一貫通孔且未影響電路處設有第二貫通孔，導熱組件也填充第二貫通孔，如此一來，第一晶片與第二晶片所發出的熱量便能夠透過導熱組件向上下方向傳遞，而提升半導體封裝結構整體的散熱效果。In summary, the semiconductor package structure of the present invention is provided with a first through hole in the unaffected circuit of the first wafer, and the encapsulation body is provided with a hole corresponding to the first through hole, and the heat conduction component is filled in the first through hole. The hole and the hole are not electrically connected to the first chip, and the heat conducting component contacts the heat conducting component downward through the heat dissipating adhesive layer, and contacts the heat radiating plate member upward to transfer the heat emitted by the first chip to the upper and lower directions, thereby lifting the semiconductor package. The overall heat dissipation effect of the structure. In addition, the semiconductor package structure of the present invention may also be a multi-chip package structure. The second wafer stacked on the first wafer is provided with a second through hole corresponding to the first through hole and not affected by the circuit, and the heat conduction component is also filled. The two through holes, so that the heat generated by the first wafer and the second wafer can be transmitted through the heat conducting component in the up and down direction, thereby improving the heat dissipation effect of the entire semiconductor package structure.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧半導體封裝結構
110‧‧‧基座
112‧‧‧導線架
114‧‧‧晶片座
116‧‧‧導腳
120‧‧‧第一晶片
122‧‧‧第一貫通孔
130‧‧‧第二晶片
132‧‧‧第二貫通孔
140‧‧‧包封體
142‧‧‧孔洞
150‧‧‧導熱組件
152‧‧‧晶片導熱柱
154‧‧‧包封體導熱柱
156‧‧‧銲球
160‧‧‧散熱板件
170‧‧‧散熱膠層
180‧‧‧導線100‧‧‧Semiconductor package structure
110‧‧‧Base
112‧‧‧ lead frame
114‧‧‧ Wafer holder
116‧‧‧ lead
120‧‧‧First chip
122‧‧‧First through hole
130‧‧‧second chip
132‧‧‧Second through hole
140‧‧‧Encapsulation
142‧‧‧ holes
150‧‧‧thermal components
152‧‧‧ wafer thermal conduction column
154‧‧‧Encapsulated thermal column
156‧‧‧ solder balls
160‧‧‧Dissipation plate
170‧‧‧heating layer
180‧‧‧ wire
圖1 是依照本發明的一實施例的一種半導體封裝結構的示意圖。1 is a schematic diagram of a semiconductor package structure in accordance with an embodiment of the present invention.
100‧‧‧半導體封裝結構 100‧‧‧Semiconductor package structure
110‧‧‧基座 110‧‧‧Base
112‧‧‧導線架 112‧‧‧ lead frame
114‧‧‧晶片座 114‧‧‧ Wafer holder
116‧‧‧導腳 116‧‧‧ lead
120‧‧‧第一晶片 120‧‧‧First chip
122‧‧‧第一貫通孔 122‧‧‧First through hole
130‧‧‧第二晶片 130‧‧‧second chip
132‧‧‧第二貫通孔 132‧‧‧Second through hole
140‧‧‧包封體 140‧‧‧Encapsulation
142‧‧‧孔洞 142‧‧‧ holes
150‧‧‧導熱組件 150‧‧‧thermal components
152‧‧‧晶片導熱柱 152‧‧‧ wafer thermal conduction column
154‧‧‧包封體導熱柱 154‧‧‧Encapsulated thermal column
156‧‧‧銲球 156‧‧‧ solder balls
160‧‧‧散熱板件 160‧‧‧Dissipation plate
170‧‧‧散熱膠層 170‧‧‧heating layer
180‧‧‧導線 180‧‧‧ wire
Claims (10)
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| TW445610B (en) * | 2000-06-16 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Stacked-die packaging structure |
| TW201503315A (en) * | 2013-07-01 | 2015-01-16 | Powertech Technology Inc | Thermally dissipating flip-chip package |
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| TW445610B (en) * | 2000-06-16 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Stacked-die packaging structure |
| TW201503315A (en) * | 2013-07-01 | 2015-01-16 | Powertech Technology Inc | Thermally dissipating flip-chip package |
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