TWI550744B - Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof - Google Patents
Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof Download PDFInfo
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- TWI550744B TWI550744B TW103142114A TW103142114A TWI550744B TW I550744 B TWI550744 B TW I550744B TW 103142114 A TW103142114 A TW 103142114A TW 103142114 A TW103142114 A TW 103142114A TW I550744 B TWI550744 B TW I550744B
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- layer
- dielectric body
- circuit layer
- package substrate
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- 239000000758 substrate Substances 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000010410 layer Substances 0.000 claims description 131
- 239000002356 single layer Substances 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 27
- 239000003989 dielectric material Substances 0.000 claims description 18
- 239000008393 encapsulating agent Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 239000012792 core layer Substances 0.000 description 14
- 238000005553 drilling Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
Description
本發明係有關一種封裝基板及其製法、封裝結構及其製法，尤指一種不具核心層之封裝基板與封裝結構。 The invention relates to a package substrate, a preparation method thereof, a package structure and a preparation method thereof, in particular to a package substrate and a package structure without a core layer.
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。 With the rapid development of the electronics industry, many high-end electronic products are gradually moving toward light, thin, short, and small high integration. With the evolution of packaging technology, the packaging technology of wafers is becoming more and more diversified. The size or volume of the package is also shrinking, so that the semiconductor package is light, thin and short.
一般封裝基板的結構係由堆疊之銅層與絕緣層所組成，第1圖所示者係為習知封裝結構之剖視示意圖。 Generally, the structure of the package substrate is composed of a stacked copper layer and an insulating layer, and FIG. 1 is a schematic cross-sectional view of a conventional package structure.
如第1圖所示，習知封裝結構係包括：核心層10；形成於核心層10表面的第一線路層11與第二線路層13；導電孔15，係貫穿該核心層10，以電性連接該第一線路層11與第二線路層13；第一絕緣層12與第二絕緣層14，係 分別形成於該第一線路層11與第二線路層13上，並外露出部分該第一線路層11與第二線路層13；以及半導體元件31，係具有用以電性連接該第一線路層11之銲墊310。 As shown in FIG. 1, the conventional package structure includes: a core layer 10; a first circuit layer 11 and a second circuit layer 13 formed on the surface of the core layer 10; and a conductive hole 15 extending through the core layer 10 to be electrically The first circuit layer 11 and the second circuit layer 13 are connected to each other; the first insulating layer 12 and the second insulating layer 14 are Formed on the first circuit layer 11 and the second circuit layer 13, respectively, and partially expose the first circuit layer 11 and the second circuit layer 13; and the semiconductor component 31 is configured to electrically connect the first line Pad 310 of layer 11.
然而，習知封裝結構所用的封裝基板1(包括：第一線路層11、第一絕緣層12、第二線路層13、第二絕緣層14、導電孔15)中，通常係具有至少二層的線路層，並藉該導電孔電性連接該第一線路層與第二線路層。 However, the package substrate 1 (including the first wiring layer 11, the first insulating layer 12, the second wiring layer 13, the second insulating layer 14, and the conductive via 15) used in the conventional package structure usually has at least two layers. The circuit layer is electrically connected to the first circuit layer and the second circuit layer by the conductive holes.
然而，導電孔必須透過機械鑽孔或雷射鑽孔於該核心層上形成貫穿該核心層的通孔後，是以，於該貫穿之通孔中電鍍銅，更增加製程的複雜度。 However, the conductive holes must be formed by mechanical drilling or laser drilling on the core layer to form a through hole penetrating the core layer, so that copper is electroplated in the through holes, which further increases the complexity of the process.
此外，習知封裝結構中所用的基板係具有核心層，並於核心層上形成導電孔後，於該核心層上下表面形成增層線路，通常而言，該核心層具有至少兩層的線路層。因此，使基板厚度難以降低。在基板厚度難以降低的情況下，整體封裝結構之厚度亦難以有效的降低。 In addition, the substrate used in the conventional package structure has a core layer, and after forming a conductive hole on the core layer, a build-up line is formed on the upper and lower surfaces of the core layer. Generally, the core layer has at least two layers of circuit layers. . Therefore, it is difficult to reduce the thickness of the substrate. In the case where it is difficult to reduce the thickness of the substrate, the thickness of the entire package structure is also difficult to effectively reduce.
但隨著電子產品微小化、薄型化的需求增加，對於薄型基板的需求也日益增加。因此，如何降低基板厚度，遂使整體封裝結構的厚度降低，實為業界迫切待開發之方向。 However, as the demand for miniaturization and thinning of electronic products increases, the demand for thin substrates is also increasing. Therefore, how to reduce the thickness of the substrate and reduce the thickness of the overall package structure is an urgent development direction in the industry.
鑒於上述習知技術之缺失，本發明提供一種封裝基板之製法係包括：於一承載件上形成具有相對之第一表面與第二表面之線路層；於該承載件與線路層上形成介電體，該介電體係具有相對之第一側與該線路層之第二表面同側的第二側，且該介電體之第一側係具有外露出部分該線路 層之第一開口；以及移除該承載件，以外露出該介電體之第二側與該線路層之第二表面。 In view of the above-mentioned conventional techniques, the present invention provides a method for manufacturing a package substrate, comprising: forming a circuit layer having a first surface and a second surface opposite to a carrier; forming a dielectric on the carrier and the circuit layer The dielectric system has a second side opposite the first side of the second surface of the circuit layer, and the first side of the dielectric body has an exposed portion of the line a first opening of the layer; and removing the carrier to expose the second side of the dielectric body and the second surface of the circuit layer.
本發明復提供一種封裝基板，係包括：具有相對之第一表面與定義有複數電性連接區與電極區之第二表面線路層；以及具有相對之第一側與該線路層之第二表面同側的第二側之介電體，該第一側係具有外露出部分該線路層之第一開口。 The present invention further provides a package substrate comprising: a first surface circuit layer having a first surface opposite to each other and defining a plurality of electrical connection regions and electrode regions; and a second surface having an opposite first side and the circuit layer a dielectric body on a second side of the same side, the first side having a first opening exposing a portion of the circuit layer.
於本發明之封裝基板及其製法的一實施例中，於由前所述之製法所製得的封裝基板中，該介電體的第二側係與該線路層之第二表面共平面。 In an embodiment of the package substrate of the present invention and the method of fabricating the same, in the package substrate produced by the method described above, the second side of the dielectric body is coplanar with the second surface of the circuit layer.
本發明再提供一種封裝結構之製法，係包括：提供具有相對之第一側與第二側的介電體，該介電體中係嵌埋有具有相對之第一表面與第二表面的單一線路層，其中，該介電體之第二側與該線路層之第二表面同側，該第一側係具有外露出部分該線路層之第一開口；以及於該介電體之第二側設置半導體元件，以電性連接至該線路層之第二表面。 The invention further provides a method for fabricating a package structure, comprising: providing a dielectric body having a first side and a second side opposite to each other, wherein the dielectric body is embedded with a single surface having an opposite first surface and a second surface a circuit layer, wherein the second side of the dielectric body is on the same side as the second surface of the circuit layer, the first side has a first opening exposing a portion of the circuit layer; and the second side of the dielectric body The semiconductor component is disposed on the side to be electrically connected to the second surface of the circuit layer.
本發明又提供一種封裝結構，係包括：如前所述之單層線路式封裝基板；以及半導體元件，係設置於該介電體之第二側，並電性連接至該線路層之第二表面。 The present invention further provides a package structure comprising: a single-layer line package substrate as described above; and a semiconductor component disposed on the second side of the dielectric body and electrically connected to the second layer of the circuit layer surface.
於本發明之封裝結構及其製法的一實施例中，該介電體的第二側係與該線路層之第二表面共平面。 In an embodiment of the package structure of the present invention and the method of fabricating the same, the second side of the dielectric body is coplanar with the second surface of the circuit layer.
於本發明之封裝基板之製法的一實施方式中，該介電體之第一開口係以曝光顯影方式形成。 In an embodiment of the method of fabricating a package substrate of the present invention, the first opening of the dielectric body is formed by exposure development.
於本發明之封裝基板之製法的一實施方式中，復包括於形成該第一開口時，於該線路層之第一表面形成有對應該第一開口之第二開口。於前述封裝基板中，該線路層之第一表面係具有對應該第一開口之第二開口。於本發明之封裝結構及其製法的一實施方式中，該線路層之第一表面形成有對應該第一開口之第二開口。 In an embodiment of the method for fabricating a package substrate of the present invention, when the first opening is formed, a second opening corresponding to the first opening is formed on the first surface of the circuit layer. In the foregoing package substrate, the first surface of the circuit layer has a second opening corresponding to the first opening. In an embodiment of the package structure of the present invention and the method of fabricating the same, the first surface of the circuit layer is formed with a second opening corresponding to the first opening.
於本發明之封裝基板或封裝結構中，形成該介電體之材質係為感光型介電材料。 In the package substrate or package structure of the present invention, the material forming the dielectric body is a photosensitive dielectric material.
於本發明之封裝結構的一實施方式中，該半導體元件係具有複數導電凸塊，俾藉之電性連接至該線路層之第二表面。 In an embodiment of the package structure of the present invention, the semiconductor component has a plurality of conductive bumps electrically connected to the second surface of the circuit layer.
於本發明之封裝結構的另一實施方式中，復包括於設置半導體元件後，在該介電體上形成封裝膠體，使該半導體元件包覆於該封裝膠體中。於前述封裝結構中，復包括形成於該介電體上之封裝膠體，使該半導體元件包覆於該封裝膠體中。 In another embodiment of the package structure of the present invention, after the semiconductor device is disposed, an encapsulant is formed on the dielectric body to encapsulate the semiconductor device in the encapsulant. In the foregoing package structure, the encapsulant formed on the dielectric body is further included, and the semiconductor component is encapsulated in the encapsulant.
於前述封裝結構的又一實施方式中，復包括在該半導體元件與該介電體之第二側之間填充底膠。於前述封裝結構中，復包括填充於該半導體元件與該介電體之第二側之間的底膠。 In still another embodiment of the foregoing package structure, a primer is filled between the semiconductor component and the second side of the dielectric body. In the foregoing package structure, the underfill is filled between the semiconductor element and the second side of the dielectric.
於前述封裝結構之製法的再一實施方式中，該承載件上復形成有種子層，於前述封裝基板及具有該封裝基板之封裝結構中復包括形成於該線路層之第二表面上之種子層。於前述實施方式中，復包括以蝕刻方式移除該種子層， 並於該線路層之第一表面蝕刻形成對應該第一開口之第二開口。 In still another embodiment of the method for fabricating the package structure, a seed layer is formed on the carrier, and the package substrate and the package structure having the package substrate further include a seed formed on the second surface of the circuit layer. Floor. In the foregoing embodiment, the method includes removing the seed layer by etching, And etching a second opening corresponding to the first opening on the first surface of the circuit layer.
由上可知，本發明之封裝基板僅具有一層線路層，並藉由該線路層的第一表面與第二表面電性連接該半導體元件與後續設置的外部元件，即能藉由一層線路層達到線路重佈、連接半導體元件與外部元件之功效。 As can be seen from the above, the package substrate of the present invention has only one wiring layer, and the first surface and the second surface of the circuit layer are electrically connected to the semiconductor component and the subsequently disposed external component, that is, can be realized by a layer of the circuit layer. The effect of rewiring the line and connecting the semiconductor component to the external component.
此外，本發明係一種不具有核心層的封裝基板，因此得以降低整體封裝基板的厚度，進而應用於厚度較小之電子產品。 Further, the present invention is a package substrate having no core layer, thereby reducing the thickness of the entire package substrate, and thus being applied to an electronic product having a small thickness.
再者，本發明毋須形成供電鍍製作導電路徑之貫穿的通孔，可簡化製程的複雜度。又，當本發明之介電體材料係可使用感光型封裝材料時，藉由感光型封裝材料同時具有光阻與封裝之特性，而無需另外使用光阻劑，得以簡化製程。 Furthermore, the present invention does not require the formation of through-holes through which the conductive plating is formed by the power supply plating, which simplifies the process complexity. Moreover, when the dielectric material of the present invention can use a photosensitive packaging material, the photosensitive packaging material has both photoresist and package characteristics without requiring the use of a photoresist, thereby simplifying the process.
另外，當本發明之介電體材料係使用感光型封裝材料時，得以藉由圖案化該感光型介電材料來製作線路、通孔，亦或是介電體的開口，得以在不需使用機械鑽孔或雷射鑽孔的情況下，達到細線路的需求，遂增加佈線密集度。 In addition, when the dielectric material of the present invention is made of a photosensitive packaging material, the wiring, the via hole, or the opening of the dielectric body can be formed by patterning the photosensitive dielectric material, thereby eliminating the need for use. In the case of mechanical drilling or laser drilling, the need for fine wiring is achieved, and wiring density is increased.
1、2‧‧‧封裝基板 1, 2‧‧‧ package substrate
3‧‧‧封裝結構 3‧‧‧Package structure
10‧‧‧核心層 10‧‧‧ core layer
11‧‧‧第一線路層 11‧‧‧First line layer
12‧‧‧第一絕緣層 12‧‧‧First insulation
13‧‧‧第二線路層 13‧‧‧Second circuit layer
14‧‧‧第二絕緣層 14‧‧‧Second insulation
15‧‧‧導電孔 15‧‧‧Electrical hole
20‧‧‧承載件 20‧‧‧Carrier
201‧‧‧種子層 201‧‧‧ seed layer
21‧‧‧線路層 21‧‧‧Line layer
21a‧‧‧第一表面 21a‧‧‧ first surface
21b‧‧‧第二表面 21b‧‧‧ second surface
210‧‧‧電性連接區 210‧‧‧Electrical connection zone
211‧‧‧電路區 211‧‧‧ circuit area
212‧‧‧電極區 212‧‧‧Electrode zone
212a‧‧‧第二開口 212a‧‧‧ second opening
22‧‧‧介電體 22‧‧‧ dielectric
22a‧‧‧第一側 22a‧‧‧ first side
22b‧‧‧第二側 22b‧‧‧ second side
22c‧‧‧第一開口 22c‧‧‧ first opening
30‧‧‧導電凸塊 30‧‧‧Electrical bumps
31‧‧‧半導體元件 31‧‧‧Semiconductor components
310‧‧‧銲墊 310‧‧‧ solder pads
32‧‧‧封裝膠體 32‧‧‧Package colloid
33‧‧‧導電元件 33‧‧‧Conductive components
34‧‧‧底膠 34‧‧‧Bottom
第1圖係為習知封裝結構之剖視圖；第2A至2D圖係顯示本發明封裝基板之製法示意圖；以及第3A至3D圖係顯示本發明封裝結構之製法示意圖，其中，第3C’係為第3C圖之另一實施態樣。 1 is a cross-sectional view showing a conventional package structure; FIGS. 2A to 2D are views showing a method of manufacturing the package substrate of the present invention; and FIGS. 3A to 3D are views showing a method of manufacturing the package structure of the present invention, wherein the 3C' is Another embodiment of Figure 3C.
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。 The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「側」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。 It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. In the meantime, the terms "upper", "first", "second", "side" and the like, as used in this specification, are for convenience only, and are not intended to limit the scope of the creation of the creation. Changes or adjustments in their relative relationship are considered to be within the scope of the creation of the creation of the product without substantial changes.
請參閱第2A至2D圖係顯示本發明封裝基板之製法示意圖。 Please refer to FIGS. 2A to 2D for a schematic diagram showing the manufacturing method of the package substrate of the present invention.
如第2A圖所示，於一承載件20上形成具有相對之第一表面21a與第二表面21b之線路層21。 As shown in FIG. 2A, a wiring layer 21 having a first surface 21a and a second surface 21b opposite to each other is formed on a carrier 20.
於本實施例中，該線路層21係定義有複數電性連接區210、電極區212與電路區211，形成該線路層21的材料為 銅。於本實施例中，該承載件20上復形成有種子層201。 In this embodiment, the circuit layer 21 defines a plurality of electrical connection regions 210, an electrode region 212, and a circuit region 211. The material forming the circuit layer 21 is copper. In the embodiment, the carrier layer 20 is formed on the carrier 20 .
於本發明之封裝基板之製法中，對於該承載件20之材質並未有特殊限制，僅需為容易移除的材料即可，形成該線路層21的方法亦可使用一般圖案化之佈線方法即可。 In the method of manufacturing the package substrate of the present invention, the material of the carrier member 20 is not particularly limited, and only needs to be a material that can be easily removed. The method for forming the circuit layer 21 can also use a generally patterned wiring method. Just fine.
如第2B圖所示，於該承載件20與線路層21上形成介電體22，該介電體22係具有相對之第一側22a與該線路層21之第二表面21b同側的第二側22b，且該介電體22之第一側22a係具有外露出部分該線路層21之第一開口22c。 As shown in FIG. 2B, a dielectric body 22 is formed on the carrier 20 and the circuit layer 21, and the dielectric body 22 has a first side opposite to the second surface 21b of the circuit layer 21 opposite to the first side 22a. The two sides 22b, and the first side 22a of the dielectric body 22 has a first opening 22c exposing a portion of the circuit layer 21.
於本發明封裝基板之製法中，可先形成介電體22再於該介電體22的第一側22a以機械鑽孔或雷射鑽孔形成該第一開口22c。於本實施例中，該第一開口22c係外露出該線路層21之第一表面21a的電極區212。其中，形成該介電體22之材質係為模壓樹脂(molding compound)或預浸材(prepreg)。 In the method of fabricating the package substrate of the present invention, the dielectric body 22 may be formed first and then the first opening 22c may be formed by mechanical drilling or laser drilling on the first side 22a of the dielectric body 22. In the embodiment, the first opening 22c exposes the electrode region 212 of the first surface 21a of the circuit layer 21. The material forming the dielectric body 22 is a molding compound or a prepreg.
於本實施例中，形成該介電體22之材料亦可為感光型介電材料(Photo-Imageable Dielectric，PID)，因此，可使用曝光顯影方式形成該第一開口22c，且該第一開口22c係外露出部分該線路層21之第一表面21a。 In this embodiment, the material forming the dielectric body 22 may also be a Photo-Imageable Dielectric (PID). Therefore, the first opening 22c may be formed by exposure and development, and the first opening is formed. A portion of the first layer 21a of the wiring layer 21 is exposed outside the portion 22c.
於本發明之封裝基板的製法中，對於所使用的感光型介電材料並未有特殊限制，可依製程不同使用正型感光型介電材料或負型感光型介電材料，以負型感光型介電材料為例，該感光型介電材料係形成於該承載件20上，並使用光罩遮蓋住欲形成第一開口22c之位置，並曝光固化(通常 係使用紫外光固化(UV Curing))該感光型介電材料接著移除該未經曝光固化的感光型介電材料而得到具有第一開口22c的介電體22。於本實施例中對於移除該未經曝光固化的感光型介電材料之方法並未有特殊限制，僅需使用一般移除光阻劑的方法即可。 In the method for manufacturing the package substrate of the present invention, there is no particular limitation on the photosensitive dielectric material to be used, and a positive photosensitive material or a negative photosensitive dielectric material may be used depending on the process, and the negative photosensitive material may be used. For example, a type of dielectric material is formed on the carrier 20, and a mask is used to cover the position where the first opening 22c is to be formed, and exposed to cure (usually The photosensitive dielectric material is removed by UV curing, and then the unexposed curing photosensitive dielectric material is removed to obtain a dielectric body 22 having a first opening 22c. In the present embodiment, there is no particular limitation on the method of removing the non-exposure-cured photosensitive dielectric material, and it is only necessary to use a method of generally removing the photoresist.
如第2C圖所示，移除該承載件20，以外露出該種子層201。 As shown in FIG. 2C, the carrier 20 is removed and the seed layer 201 is exposed.
由於本發明之封裝基板2的製法中，係先將該線路層21形成於承載件20(如第2B圖所示)上，再於該承載件20上形成介電體22覆蓋該線路層21，因此，於本發明之封裝基板中，該介電體22的第二側22b與該線路層21的第二表面21b係為共平面，亦即，該第二側22b與第二表面21b齊平。 In the manufacturing method of the package substrate 2 of the present invention, the circuit layer 21 is first formed on the carrier 20 (as shown in FIG. 2B), and a dielectric body 22 is formed on the carrier 20 to cover the circuit layer 21. Therefore, in the package substrate of the present invention, the second side 22b of the dielectric body 22 and the second surface 21b of the circuit layer 21 are coplanar, that is, the second side 22b is aligned with the second surface 21b. level.
如第2D圖所示，蝕刻移除該種子層201，以外露出該介電體22之第二側22b與該線路層21之第二表面21b，得到本發明之封裝基板2。其中，於本發明之封裝結構之製法中，亦可於移除該種子層201的同時一併蝕刻形成該第二開口212a。 As shown in FIG. 2D, the seed layer 201 is removed by etching, and the second side 22b of the dielectric body 22 and the second surface 21b of the wiring layer 21 are exposed to obtain the package substrate 2 of the present invention. In the method of fabricating the package structure of the present invention, the second opening 212a may be formed by etching together while removing the seed layer 201.
於本實施例中，復包括蝕刻該第一開口22c所外露出的部分該電極區212上形成第二開口212a，使後續設置的導電元件與該線路層21之電極區212具有良好的結合效果，提升本發明之封裝基板2的可靠度。 In this embodiment, the portion of the electrode region 212 formed by etching the first opening 22c is formed to form a second opening 212a, so that the subsequently disposed conductive element has a good bonding effect with the electrode region 212 of the circuit layer 21. The reliability of the package substrate 2 of the present invention is improved.
另外，於本發明封裝基板之製法中，倘若當該第一開口22c係以機械鑽孔或雷射鑽孔所形成者，則該第二開口 212a係於形成該第一開口22c時同時形成。 In addition, in the manufacturing method of the package substrate of the present invention, if the first opening 22c is formed by mechanical drilling or laser drilling, the second opening 212a is formed simultaneously when the first opening 22c is formed.
請參閱第2D圖，本發明之封裝基板2係包括：具有相對之第一表面21a與第二表面21b之線路層21；以及具有相對之第一側22a與第二側22b之介電體22，該第一側22a係具有外露出部分該線路層21之第一開口22c，且該線路層21之第二表面21b係與該介電體22之第二側22b同側。 Referring to FIG. 2D, the package substrate 2 of the present invention includes: a wiring layer 21 having a first surface 21a and a second surface 21b opposite thereto; and a dielectric body 22 having a first side 22a and a second side 22b opposite to each other. The first side 22a has a first opening 22c exposing a portion of the circuit layer 21, and the second surface 21b of the circuit layer 21 is on the same side as the second side 22b of the dielectric body 22.
於本實施例中，該線路層21係定義有複數電性連接區210、電極區212與電路區211，且該線路層21之第二表面21b係外露於該介電體22之第二側22b，亦即，該電性連接區210、電極區212與電路區211皆外露於該介電體22之第二側22b，且該線路層21之第二表面21b係與該介電體22之第二側22b共平面。 In this embodiment, the circuit layer 21 defines a plurality of electrical connection regions 210, electrode regions 212 and circuit regions 211, and the second surface 21b of the circuit layer 21 is exposed on the second side of the dielectric body 22. 22b, that is, the electrical connection region 210, the electrode region 212 and the circuit region 211 are exposed on the second side 22b of the dielectric body 22, and the second surface 21b of the circuit layer 21 is connected to the dielectric body 22. The second side 22b is coplanar.
此外，於本發明之封裝基板中，該介電體22中僅具有一層線路層21。 Further, in the package substrate of the present invention, the dielectric body 22 has only one wiring layer 21 therein.
參閱第3A至3D圖係顯示本發明封裝結構之製法示意圖。 Referring to Figures 3A through 3D, there are shown schematic diagrams of the method of making the package structure of the present invention.
如第3A圖所示，提供嵌埋有一線路層21之介電體22，該介電體22係具有相對之第一側22a與第二側22b，該第一側22a係具有外露出部分該線路層21之第一開口22c，該線路層21係定義有複數電性連接區210與電極區212，該介電體22之第二側22b係外露出該線路層21之電性連接區210與電極區212。 As shown in FIG. 3A, a dielectric body 22 is provided having a wiring layer 21 embedded therein, the dielectric body 22 having an opposite first side 22a and a second side 22b, the first side 22a having an exposed portion. The first opening 22c of the circuit layer 21 defines a plurality of electrical connection regions 210 and electrode regions 212. The second side 22b of the dielectric body 22 exposes the electrical connection region 210 of the circuit layer 21. And the electrode region 212.
於本實施例中，該線路層21係定義有複數電性連接區 210、電極區212與電路區211。 In this embodiment, the circuit layer 21 defines a plurality of electrical connection regions. 210, electrode region 212 and circuit region 211.
如第3B圖所示，設置半導體元件31，該半導體元件31係電性連接該線路層21。 As shown in FIG. 3B, a semiconductor element 31 is provided, which is electrically connected to the wiring layer 21.
於本實施例中，該半導體元件31係藉由該導電凸塊30電性連接該線路層21之電性連接區210，藉此電性連接至該線路層21，且該電極區212係外露於該介電體22之第一開口22c。於本實施例中，該半導體元件31係具有用以電性連接該等導電凸塊30之銲墊310。 In this embodiment, the semiconductor device 31 is electrically connected to the electrical connection region 210 of the circuit layer 21 by the conductive bumps 30, thereby being electrically connected to the circuit layer 21, and the electrode region 212 is exposed. The first opening 22c of the dielectric body 22. In the embodiment, the semiconductor device 31 has a pad 310 for electrically connecting the conductive bumps 30.
如第3C圖所示，於該介電體22上形成封裝膠體32，使該半導體元件31包覆於該封裝膠體32中。 As shown in FIG. 3C, an encapsulant 32 is formed on the dielectric body 22, and the semiconductor element 31 is covered in the encapsulant 32.
於本實施例中，於該介電體22之第二表面22b上形成該封裝膠體32，而形成該封裝膠體32之方法係為依據習知製程即能完成者，於此便不再贅述。於另一實施態樣中，在該半導體元件與該介電體之第二側之間填充底膠34，如第3C’圖所示。 In the present embodiment, the encapsulant 32 is formed on the second surface 22b of the dielectric body 22. The method for forming the encapsulant 32 is completed according to a conventional process, and will not be described herein. In another embodiment, a primer 34 is applied between the semiconductor component and the second side of the dielectric, as shown in Figure 3C'.
如第3D圖所示，於該介電體22之第一開口22c中形成導電元件33。 As shown in FIG. 3D, a conductive member 33 is formed in the first opening 22c of the dielectric body 22.
於本實施例中，該封裝結構復包括形成於該第一開口22c中用以電性連接後續設置的外接元件的導電元件33，且該導電元件33係直接與該線路層21中的電極區212接觸並電性連接。 In this embodiment, the package structure includes a conductive element 33 formed in the first opening 22c for electrically connecting the subsequently disposed external component, and the conductive component 33 is directly connected to the electrode region in the circuit layer 21. 212 contact and electrical connection.
請參閱第3D圖，本發明之封裝結構3係包括：具有相對之第一表面21a與第二表面21b之線路層21，該線路層的第二表面21b係定義有複數電性連接區210與電極區 212；形成於該線路層21上具有相對之第一側22a與第二側22b之介電體22，該線路層21係嵌埋於該介電體22中，該介電體22的第一側22a與該線路層的第一表面21a係為同側，且該介電體22的第二側22b係外露出該線路層21之第二表面21b，其中，該第一側係具有外露出部分該線路層21之第一開口22c；以及半導體元件31，係設置於該介電體22之第二側22b，且該半導體元件31係電性連接該線路層21。 Referring to FIG. 3D, the package structure 3 of the present invention includes: a circuit layer 21 having a first surface 21a and a second surface 21b opposite thereto, the second surface 21b of the circuit layer defining a plurality of electrical connection regions 210 and Electrode zone a dielectric body 22 having a first side 22a and a second side 22b opposite to the circuit layer 21, the circuit layer 21 being embedded in the dielectric body 22, the first of the dielectric body 22 The side surface 22a is on the same side as the first surface 21a of the circuit layer, and the second side 22b of the dielectric body 22 exposes the second surface 21b of the circuit layer 21, wherein the first side has an outer surface. A portion of the first opening 22c of the circuit layer 21; and a semiconductor element 31 are disposed on the second side 22b of the dielectric body 22, and the semiconductor element 31 is electrically connected to the circuit layer 21.
於本實施例中，該線路層21係定義有複數電性連接區210、電路區211與電極區212，且該半導體元件31係藉由該導電凸塊30電性連接該電性連接區210，俾使該半導體元件31電性連接至該線路層21。 In this embodiment, the circuit layer 21 defines a plurality of electrical connection regions 210, a circuit region 211 and an electrode region 212, and the semiconductor device 31 is electrically connected to the electrical connection region 210 by the conductive bumps 30. The semiconductor element 31 is electrically connected to the wiring layer 21.
由上可知，本發明之封裝基板及封裝結構無需額外設置核心層，能有效降低整體封裝基板與封裝結構的厚度，且本發明之封裝基板僅具一層線路層，更無需藉由導電孔導通形成於核心層兩側的線路層，能大幅降低整體封裝基板與封裝結構的厚度。 It can be seen that the package substrate and the package structure of the present invention do not need to additionally provide a core layer, which can effectively reduce the thickness of the whole package substrate and the package structure, and the package substrate of the present invention has only one layer of the circuit layer, and is not required to be formed by conduction through the conductive holes. The circuit layers on both sides of the core layer can greatly reduce the thickness of the entire package substrate and package structure.
此外，當本發明的介電體係以感光型介電材料所構成時，更藉由該感光型介電材料形成介電體的開口，無需使用機械鑽孔或雷射鑽孔的製程，得以有效簡化製程並降低整體生產成本。 In addition, when the dielectric system of the present invention is formed of a photosensitive dielectric material, the opening of the dielectric body is formed by the photosensitive dielectric material, which is effective without using a mechanical drilling or laser drilling process. Simplify the process and reduce overall production costs.
另外，本發明更利用感光型介電體同時具有光阻特性與絕緣封裝特性，而得以無需另外使用光阻，進而達到簡化製程之效果。 In addition, the present invention further utilizes the photosensitive dielectric to have both photoresist characteristics and insulating package characteristics, thereby eliminating the need for additional photoresist, thereby achieving a simplified process.
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
2‧‧‧封裝基板 2‧‧‧Package substrate
21‧‧‧線路層 21‧‧‧Line layer
21a‧‧‧第一表面 21a‧‧‧ first surface
21b‧‧‧第二表面 21b‧‧‧ second surface
210‧‧‧電性連接區 210‧‧‧Electrical connection zone
211‧‧‧電路區 211‧‧‧ circuit area
212‧‧‧電極區 212‧‧‧Electrode zone
22‧‧‧介電體 22‧‧‧ dielectric
22a‧‧‧第一側 22a‧‧‧ first side
22b‧‧‧第二側 22b‧‧‧ second side
22c‧‧‧第一開口 22c‧‧‧ first opening
212a‧‧‧第二開口 212a‧‧‧ second opening
Claims (24)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103142114A TWI550744B (en) | 2014-12-04 | 2014-12-04 | Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof |
| CN201410794500.7A CN105762132A (en) | 2014-12-04 | 2014-12-18 | Single-layer circuit type packaging substrate and manufacturing method thereof, single-layer circuit type packaging structure and manufacturing method thereof |
| US14/876,404 US9735080B2 (en) | 2014-12-04 | 2015-10-06 | Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and method of fabricating the same |
| US15/648,089 US10068842B2 (en) | 2014-12-04 | 2017-07-12 | Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103142114A TWI550744B (en) | 2014-12-04 | 2014-12-04 | Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201622025A TW201622025A (en) | 2016-06-16 |
| TWI550744B true TWI550744B (en) | 2016-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW103142114A TWI550744B (en) | 2014-12-04 | 2014-12-04 | Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US9735080B2 (en) |
| CN (1) | CN105762132A (en) |
| TW (1) | TWI550744B (en) |
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|---|---|---|---|---|
| TWI559829B (en) | 2014-10-22 | 2016-11-21 | 矽品精密工業股份有限公司 | Package structure and method of fabricating the same |
| CN106971994A (en) * | 2017-03-01 | 2017-07-21 | 江苏长电科技股份有限公司 | A kind of lamina encapsulating structure and its process |
| TW201916180A (en) * | 2017-09-29 | 2019-04-16 | 矽品精密工業股份有限公司 | Substrate structure and the manufacture thereof |
| CN111627867A (en) * | 2019-02-28 | 2020-09-04 | 富泰华工业（深圳）有限公司 | Chip packaging structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046485A1 (en) * | 2004-08-24 | 2006-03-02 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing package substrate with fine circuit pattern using anodic oxidation |
| US20070132072A1 (en) * | 2005-12-13 | 2007-06-14 | Via Technologies, Inc. | Chip package and coreless package substrate thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1237274A (en) * | 1996-10-08 | 1999-12-01 | 日立化成工业株式会社 | Semiconductor, semiconductor chip mounting substrate, methods of manufacturing device and substrate, adhesive and adhesive double coated film |
| JP2004304151A (en) * | 2003-03-20 | 2004-10-28 | Seiko Epson Corp | Semiconductor wafer, semiconductor device and its manufacturing method, circuit board, and electronic apparatus |
| TWI446508B (en) * | 2011-05-24 | 2014-07-21 | Unimicron Technology Corp | Coreless package substrate and method of making same |
| US9230899B2 (en) * | 2011-09-30 | 2016-01-05 | Unimicron Technology Corporation | Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure |
| TWI503936B (en) * | 2013-02-07 | 2015-10-11 | 矽品精密工業股份有限公司 | Interconnection element of package structure and method of forming the same |
-
2014
- 2014-12-04 TW TW103142114A patent/TWI550744B/en active
- 2014-12-18 CN CN201410794500.7A patent/CN105762132A/en active Pending
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2015
- 2015-10-06 US US14/876,404 patent/US9735080B2/en active Active
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046485A1 (en) * | 2004-08-24 | 2006-03-02 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing package substrate with fine circuit pattern using anodic oxidation |
| US20070132072A1 (en) * | 2005-12-13 | 2007-06-14 | Via Technologies, Inc. | Chip package and coreless package substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20170309537A1 (en) | 2017-10-26 |
| US9735080B2 (en) | 2017-08-15 |
| CN105762132A (en) | 2016-07-13 |
| TW201622025A (en) | 2016-06-16 |
| US10068842B2 (en) | 2018-09-04 |
| US20160163621A1 (en) | 2016-06-09 |
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