TWI548217B - Output circuit - Google Patents

Description

Output circuit

The present invention relates to an output circuit including a P-type metal-oxide-semiconductor (PMOS) transistor for pull-up and a pull down for pull down An N-type metal-oxide-semiconductor (NMOS) transistor, and more particularly to an output circuit formed in a semiconductor integrated circuit or a semiconductor memory device or the like.

A push-pull type Complementary Metal-Oxide-Semiconductor Transistor (CMOS) inverter including a PMOS transistor and an NMOS transistor is used in an output circuit of a semiconductor device or the like. (inverter) or CMOS buffer (buffer). An output circuit in which a transistor constituting such a CMOS inverter has a low withstand voltage and can output a high voltage signal is disclosed (Patent Document 1), and an output circuit that suppresses switching noise (Patent Document 2) Wait.

[Prior Art Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2013-90278

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2012-65235

FIG. 1 is a view showing a configuration example of a conventional output circuit. The output circuit includes a pull-up PMOS transistor P1 and a pull-down NMOS transistor N1 that constitute a push-pull CMOS inverter. An output node (node) that couples the drain of the PMOS transistor P1 to the drain of the NMOS transistor N1 is, for example, electrically coupled to an output pad 10. A latch circuit or prebuffer circuit 20 includes an inverter IN1 or a NOT (NOR) gate that receives the data DATA, and supplies a pull-up control signal to the pull-up node PU. The inverter IN2, the non-(Not AND, NAND) gate, and the inverter IN3 that supplies the pull-down control signal to the pull-down node PD. The latch circuit 20 generates a pull-up control signal and a pull-down control signal for inverting the logic level of the material DATA, and supplies these signals to the pull-up node PU and the pull-down node PD.

The pull-up PMOS transistor P1 requires a certain driving capability in order to drive a load connected to the output node OUT, that is, connected to the output pad 10. However, with the miniaturization of the semiconductor integrated circuit, when the voltage of the internal power supply voltage VDD is lowered, the voltage Vgs between the gate and the source of the pull-up transistor P1 changes. It is small, so that it is impossible to drive the load connected to the output node OUT at a high speed. For example, when the power supply voltage VDD is changed from 3.3V to 1.8V, the gate/source voltage Vgs when the PMOS transistor P1 is turned on (ON) becomes small, so the drain current Id of the PMOS transistor P1 becomes small, It takes a lot of time to drive the load connected to the output pad 10.

An object of the present invention is to solve such conventional problems and to provide a push-pull type output circuit capable of driving a load connected to an output node at a higher speed.

The output circuit of the present invention comprises: a P-channel type pull-up transistor connected between the first power source and the output node; a pull-down transistor connected between the second power source and the output node; and a supply circuit The logic level of the input data is supplied to the pull-up control node of the pull-up transistor, and the pull-down control signal is supplied to the pull-down node of the pull-down transistor; and the circuit, when the pull-up transistor is pulled up by the pull-up When the control signal is turned on, the voltage of the pull-up node is changed to a negative voltage.

In a preferred embodiment, the circuit for changing the voltage of the pull-up node to a negative voltage includes: a PMOS transistor connected between the supply node of the pull-up control signal of the supply circuit and the pull-up node; And a delay circuit coupled to the supply node to delay the pull up control signal, and an output capacitance of the delay circuit coupled to the pull up node. Preferably, when the pull-up control signal migrates from a high level to a low level, the voltage of the pull-up node changes to a negative voltage. Preferably, the PMOS transistor includes an N well formed in the p-type semiconductor region, and a p-type first diffusion region and a second diffusion region formed in the N well, A diffusion region is connected to the supply node, a second diffusion region is connected to the pull-up node, and an N-well is electrically coupled to a positive supply voltage. Preferably, the output node is electrically coupled to an output pad of a semiconductor chip.

According to the present invention, by providing a circuit for changing the voltage of the pull-up node to a negative voltage when the upper pull-up crystal is turned on, the current flowing through the pull-up transistor can be increased, so that the output node can be driven at a higher speed.

10‧‧‧Output pad

20‧‧‧Latch circuit (pre-buffer circuit)

100‧‧‧Output circuit

200‧‧‧ logic circuit

210‧‧‧ Input Department

220‧‧‧Negative voltage generation circuit

240, IN1, IN2, IN3‧‧‧ inverter

300‧‧‧p type substrate

310‧‧‧N well

320‧‧‧n type diffusion area

330‧‧‧p type diffusion area

340‧‧‧p-type diffusion zone

DATA‧‧‧Information

DL‧‧‧ delay circuit

N1, TR2‧‧‧ NMOS transistor

NAND‧‧‧和非

NOR‧‧‧ or non

NPU, PU_C‧‧‧ nodes

OUT‧‧‧ output node

P1, P2‧‧‧ PMOS transistor

PD‧‧‧ drop-down node

PU‧‧‧Upper node

T1, t1‧‧‧ moments

T1~T5‧‧‧ moments

TR1‧‧‧ Pull-up transistor

Vcc‧‧‧ power supply

VDD‧‧‧Power supply voltage

Vth‧‧‧ threshold of PMOS transistor P2

FIG. 1 is a view showing an example of a conventional output circuit.

Fig. 2 is a view showing an example of the configuration of an output circuit of an embodiment of the present invention.

3(A) and 3(B) are diagrams for explaining an operation waveform of an output circuit according to an embodiment of the present invention.

4 is a view showing a specific configuration example of an output circuit of an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view showing a PMOS transistor of the output circuit shown in Fig. 4;

Fig. 6 is a view showing voltage waveforms of respective nodes of the output circuit shown in Fig. 4;

Fig. 7 is a view showing a bootstrap type output circuit.

The output circuit of the present invention is formed in a semiconductor device such as a semiconductor integrated circuit or a semiconductor memory device or a semiconductor wafer. Moreover, the output circuit of the present invention It can be used to drive circuits within a semiconductor device or to drive other semiconductor devices or circuits connected to the output terminals of the semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 2 is a view showing a configuration example of an output circuit of an embodiment of the present invention. The output circuit 100 of the present embodiment includes a logic circuit 200 and a push-pull type inverter 240. The logic circuit 200 receives the data DATA in the input unit 210, and generates a pull-up control signal and a pull-down control signal having a complementary relationship according to the logic level of the data DATA, and supplies the control signals to the pull-up node PU and Pull down the node PD.

The inverter 240 includes a pull-up PMOS transistor P1 and a pull-down NMOS transistor N1. The source of the PMOS transistor P1 is connected to the power supply voltage VDD, the gate is connected to the pull-up node PU, and the drain is connected to the output node OUT. The source of the NMOS transistor N1 is connected to the reference potential, that is, GND, the gate is connected to the pull-down node PD, and the drain is connected to the output node OUT. The PMOS transistor P1 and the NMOS transistor N1 perform a push-pull operation based on the pull-up control signal and the pull-down control signal. That is, when the pull-up control signal is at the L level and the pull-down control signal is at the L level, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off (OFF), and the drain current Id flows from the power supply voltage VDD to the output node OUT. On the other hand, when the pull-up control signal is at the H level and the pull-down control signal is at the H level, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, and the drain current Id flows from the output node OUT to GND. The output node OUT is connected to an output pad or other integrated circuit of the semiconductor device.

Furthermore, the logic circuit 200 of the present embodiment includes a negative voltage generating circuit 220 for conducting the PMOS transistor P1 for pull-up. At this time, the L-level pull-up control signal supplied to the pull-up node PU is changed to a negative voltage or in a negative direction. That is, when the PMOS transistor P1 is turned on, the pull-up node PU migrates to a negative voltage lower than 0 V, thereby causing the PMOS transistor P1 to be strongly turned on. The negative voltage generating circuit 220 is not particularly limited as long as it is a circuit that can shift the voltage of the pull-up node PU to the negative direction. The negative voltage generating circuit 220 changes the pull-up node PU to a negative voltage by capacitive coupling, for example, as will be described later.

3(A) schematically shows voltage waveforms of respective nodes of a conventional output circuit that does not include the negative voltage generating circuit 220, and FIG. 3(B) shows nodes of the output circuit including the negative voltage generating circuit of the present embodiment. Voltage waveform. When the data DATA transitions from the H level to the L level during the period from time t1 to time t2, the logic circuit 200 supplies the pull-up control signal of the L level to the pull-up node PU, and supplies the L level to the pull-down node PD. Pull down the control signal. Thereby, the pull-up PMOS transistor P1 is turned on, the pull-down NMOS transistor N1 is turned off, and the output node OUT outputs a signal of the H level which inverts the logic level of the data DATA. For example, when the power supply voltage VDD is low voltage (3.3V → 1.8V), the gate/source voltage of the PMOS transistor P1 becomes insufficient, and accordingly, the drain current Id becomes small, It takes time to drive the load capacitor connected to the output node OUT.

On the other hand, in the output circuit 100 of the present embodiment, when the data DATA is transferred from the H level to the L level, the negative voltage generating circuit 220 shifts the L level pull-up control signal as shown in FIG. 3(B). To negative voltage (-V). Therefore, compared with the output circuit shown in FIG. 3(A) that does not change to a negative voltage, the gate-source voltage of the pull-up PMOS transistor P1 can be increased, and as a result, it can flow through the PMOS. The drain current Id of the transistor P1 increases. Therefore, the load capacitance of the output node OUT can be driven at a high speed.

Next, a specific configuration example of the output circuit of the present embodiment will be described. 4 is an output circuit of the present embodiment, and the same components as those of the output circuit of FIG. 1 are denoted by the same reference numerals. As shown in FIG. 4, the output circuit 100 of the present embodiment includes, in addition to the structure of the latch circuit 20 and the CMOS inverter P1/N1, a negative voltage generating circuit 220 for pulling up. The voltage of the node PU changes to a negative voltage. On the source of the pull-up PMOS transistor P1, for example, a 1.8 V VDD power supply is connected. Further, an output pad or the like is connected to the output node OUT.

The latch circuit 20 generates a pull-up control signal for the node NPU, and generates a pull-down control signal for the pull-down node PD that is complementary to the pull-up control signal. The negative voltage generating circuit 220 includes a PMOS transistor P2 connected between the node NPU of the latch circuit 20 and the pull-up node PU, and a delay circuit DL connected to the node NPU to delay the pull-up control signal. The output capacitance of the delay circuit DL is coupled to the pull-up node PU, and when the pull-up control signal for the L level is supplied to the pull-up node PU, the voltage of the pull-up node PU is shifted to a negative voltage. The delay circuit DL may for example comprise a plurality of inverters.

FIG. 5 is a schematic cross-sectional view showing the PMOS transistor P2. As shown in FIG. 5, a PMOS transistor P2 is formed in an N well 310 formed in a p-type silicon substrate 300. GND (0 V) is supplied to the substrate 300, and a power supply Vcc of, for example, 3.3 V is supplied to the N well 310 via the n-type diffusion region 320. One of the p-type diffusion regions 330 of the PMOS transistor P2 is connected to the latch circuit The node NPU of 20, the other p-type diffusion region 340 is connected to the pull-up node PU. The gate is supplied with GND, and the PMOS transistor P2 is always in an on state.

Next, the operation of the output circuit of this embodiment will be described. Fig. 6 schematically shows voltage waveforms of respective nodes of the output circuit. At time T1, the data DATA toward the latch circuit 20 is shifted from the L level to the H level. In response to this, the output of the NAND gate migrates to the H level, so at time T2, the pull-down node PD migrates from the H level to the L level, and the pull-down NMOS transistor N1 is turned off.

The NOR gate outputs the H level according to the input from the L level of the inverter IN1 and the L level input of the pulldown node PD, so at time T3, the node NPU migrates from the H level (Vcc) to the L level. (0V). Further, at time T3, since the PMOS transistor P2 is in an on state, the L level pull-up control signal generated for the node NPU is supplied to the pull-up node PU. At this time, the voltage of the pull-up node PU falls from Vcc to Vth (Vth is the threshold of the PMOS transistor P2). The pull-up transistor P1 is turned on in response to the case where the pull-up node is driven to the L level.

Further, at time T4, the delay circuit DL outputs a pull-up control signal delayed by a fixed time to the node PU_C. That is, the node PU_C migrates from the H level to the L level. Since the node PU_C is capacitively coupled to the pull-up node PU, when the voltage of the node PU_C drops, correspondingly, the voltage of the pull-up node PU is pulled to the negative direction. In this embodiment, the capacitance coupling ratio of the pull-up node PU is adjusted to become a negative voltage. When the pull-up node PU migrates to a negative voltage, a forward bias is not formed between the diffusion region 340 and the N well 310, so no through current flows between the substrate 300 and the substrate 300.

Since the negative voltage of the pull-up node PU continues for a fixed period, during this period, the gate/source voltage of the PMOS transistor P1 becomes large, the PMOS transistor P1 is strongly turned on, and the large drain current Id is supplied to the output. Node OUT. Therefore, it is possible to drive the load connected to the output node OUT at a high speed.

Figure 7 is an output circuit for driving a pull-up transistor by bootstrap. The pull-up transistor TR1 includes an NMOS, and an NMOS transistor TR2 connected to VDD is connected to the gate of the transistor TR1. When the H-level pull-up control signal is supplied to the node NPU, the pull-up node PU becomes Vcc-Vth via the transistor TR2, the transistor TR1 is turned on, and the output node OUT is shifted to the H level. Since the capacitance is coupled to the pull-up node PU, the voltage of the output node OUT rises in response to an increase in the voltage of the output node OUT, and the voltage between the gate and the source of the pull-up transistor TR1 becomes large, and accordingly, The pull-up transistor TR1 is strongly turned on. However, if the load capacitance connected to the output node OUT is fixed or higher, the potential of the output node OUT is immediately lowered, so that the voltage of the pull-up node PU cannot be maintained at VDD+Vth. On the other hand, the output circuit of the present embodiment does not change the voltage of the pull-up node PU by the voltage of the output node OUT. Therefore, the negative voltage of the pull-up node PU can be stably maintained for a fixed period. Keep the pull-up transistor in a state of strong conduction.

In the above embodiment, the example in which the logic circuit 200 includes the latch circuit 20 is shown, but this is only an example and is not limited thereto. The logic circuit 200 may also include, for example, a level shifter (level shifter), and may also include other circuits such as a pre-buffer or circuit elements other than the logic circuit. The circuit changes the voltage of the logic level of the data input to the input unit 210 to another voltage. Further, in the above embodiment, the case where the logic circuit 200 includes the negative voltage generating circuit 220 is exemplified, but the negative voltage generating circuit 220 may not be included in the logic circuit 200, and a configuration independent of the logic circuit 200 may be employed. Further, the power source Vcc supplied to the logic circuit 200 and the power source VDD supplied to the pull-up transistor may be the same voltage value or different voltage values. Furthermore, the logic circuit 200 can also generate a pull-up control signal and a pull-down control signal having the same logic level as the logic level of the input data, or a logic level in which the logic level of the input data is inverted. Pull-up control signal and pull-down control signal.

Further, in the above-described embodiment, the negative voltage generating circuit 220 is exemplified as a circuit for changing the voltage of the pull-up node to a negative voltage. However, the present invention is not limited to the name of the negative voltage generating circuit 220, and is applicable to the above. A circuit that pulls the voltage of a node to change its function in the negative direction. Further, in the present embodiment, an example in which the output node of the output circuit is connected to the output pad is shown, but the output node can be applied to a case where various loads such as other circuits or other devices are driven.

As described above, the preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the invention.

20‧‧‧Latch circuit (pre-buffer circuit)

100‧‧‧Output circuit

220‧‧‧Negative voltage generation circuit

IN1, IN2, IN3‧‧‧ inverter

DATA‧‧‧Information

DL‧‧‧ delay circuit

N1‧‧‧ NMOS transistor

NAND‧‧‧和非

NOR‧‧‧ or non

NPU, PU_C‧‧‧ nodes

OUT‧‧‧ output node

P1, P2‧‧‧ PMOS transistor

PD‧‧‧ drop-down node

PU‧‧‧Upper node

VDD‧‧‧Power supply voltage

Claims (8)

An output circuit comprising: a P-channel type pull-up transistor connected between a first power supply and an output node; a pull-down transistor connected between the second power supply and the output node; and a supply circuit And providing a pull-up control signal to the pull-up node of the pull-up transistor according to the logic level of the input data, and supplying a pull-down control signal to the pull-down node of the pull-down transistor; and when the pull-up transistor is pulled up by the pull-up a circuit for changing a voltage of the pull-up node to a negative voltage when the control signal is turned on; wherein the circuit for changing a voltage of the pull-up node to a negative voltage comprises: a P-type metal oxide semiconductor transistor connected to a supply node of the pull-up control signal of the supply circuit and the pull-up node; and a delay circuit connected to the supply node to delay the pull-up control signal, the output capacitance of the delay circuit being coupled to The pull-up node. The output circuit of claim 1, wherein the voltage of the pull-up node changes to a negative voltage when the pull-up control signal transitions from a high level to a low level. The output circuit of claim 1, wherein the P-type metal oxide semiconductor transistor comprises an N-well formed in a p-type semiconductor region, and a first p-type formed in the N-well The diffusion region and the second diffusion region are connected to the supply node, the second diffusion region is connected to the pull-up node, and the N-well is electrically coupled to a positive power supply voltage. The output circuit of claim 2, wherein the P-type metal oxide semiconductor transistor comprises an N-well formed in a p-type semiconductor region, and a first p-type formed in the N-well The diffusion region and the second diffusion region are connected to the supply node, the second diffusion region is connected to the pull-up node, and the N-well is electrically coupled to a positive power supply voltage. The output circuit of claim 1, wherein the output node is electrically coupled to an output pad of the semiconductor wafer. The output circuit of claim 2, wherein the output node is electrically coupled to an output pad of the semiconductor wafer. The output circuit of claim 3, wherein the output node is electrically coupled to an output pad of the semiconductor wafer. The output circuit of claim 4, wherein the output node is electrically coupled to an output pad of the semiconductor wafer.