TWI548100B - Thin film transistor, display panel and manufacturing methods thereof - Google Patents

Description

Thin film transistor, display panel and method of manufacturing same

The present invention relates to a thin film transistor, a display panel, and a method of fabricating the same.

With the advancement of modern information technology, displays of various specifications have been widely used in the screens of consumer electronic products, such as mobile phones, notebook computers, digital cameras, and personal digital assistants (PDAs). Among these displays, liquid crystal displays (LCDs) and organic electro-luminescent displays (OELDs or OLEDs) have become the mainstream products in the market due to their advantages of thinness and low power consumption. . The process of LCD and OLED includes arranging an array of semiconductor elements on a substrate, and the semiconductor element comprises a Thin Film Transistor (TFT).

As the resolution of displays becomes higher and higher, the size of thin film transistors is getting smaller and smaller. A self-aligning top gate (self-align) has been developed Top-gate structure of thin film transistors to overcome alignment limitations in lithography processes and improve gate-drain and gate-source parasitic capacitance (ie, Cgd and Cgs). In the current technology, it is necessary to carry out the whole-surface aluminum film sputtering and the thickness needs to be controlled to about 5 nm, and the annealing process is used to make the high-resistance Indium Gallium Zinc Oxide (IGZO) and the aluminum film. The oxidation reaction turns into a low-resistance indium gallium zinc oxide. However, the full-face aluminum film is often not completely oxidized to insulating alumina in the process, but only in the portion contacting the indium gallium zinc oxide, sufficient oxygen can be obtained from indium gallium zinc oxide to completely oxidize to aluminum oxide. As a result, many of the lines that should be insulated from each other will be short-circuited because they are not completely oxidized by the aluminum film, resulting in failure to display properly.

The invention provides a thin film transistor, a display panel and a manufacturing method thereof, which can avoid the problem that the conventional aluminum film is not oxidized in the process and the display panel cannot be normally displayed.

The thin film transistor of the present invention includes an oxide semiconductor layer, a gate insulating pattern, a gate, a metal oxide insulating layer, an oxygen supply layer, a source, and a drain. The oxide semiconductor layer has a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region. The gate insulating pattern is located on the channel region of the oxide semiconductor layer. The gate is located on the gate insulation pattern. The metal oxide insulating layer covers the oxide semiconductor layer. The oxygen supply layer is in contact with the metal oxide insulating layer. The source and the drain are located above the oxygen supply layer, and are electrically connected to the source region of the oxide semiconductor layer to be the drain region.

The present invention further provides a method of manufacturing a thin film transistor, the method comprising the following steps. An oxide semiconductor layer is formed. A gate insulating pattern and a gate are formed on the oxide semiconductor layer in sequence. A metal layer is formed to cover the oxide semiconductor layer, the gate insulating pattern, and the gate. An oxygen supply layer is formed to bring the metal layer into contact with the oxygen supply layer. Performing a first annealing process to react the oxide semiconductor layer with the metal layer to form a source region and a drain region, wherein the oxide semiconductor layer between the source region and the drain region is a channel region, and at the same time, the metal layer The oxygen supply layer and the oxide semiconductor layer are reacted to form a metal oxide insulating layer. A source and a drain are formed above the oxygen supply layer, and the source and the drain are electrically connected to the source region and the drain region of the oxide semiconductor layer, respectively.

The present invention further provides a display panel including a substrate, a plurality of thin film transistors, a first electrode, a light emitting layer, a second electrode, a first power line, and a second power line. The substrate has a display area and a peripheral area located at the periphery of the display area. The thin film transistor includes an oxide semiconductor layer, a gate insulating pattern, a gate, a metal oxide insulating layer, an oxygen supply layer, a source, and a drain. The oxide semiconductor layer has a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region. The gate insulating pattern is located on the channel region of the oxide semiconductor layer. The gate is located on the gate insulation pattern. The metal oxide insulating layer covers the oxide semiconductor layer. The oxygen supply layer is in contact with the metal oxide insulating layer. The source and the drain are located above the oxygen supply layer, and are electrically connected to the source region of the oxide semiconductor layer to be the drain region. The first electrode is located above the source and the drain, and the first electrode is electrically connected to the drain. The luminescent layer is on the first electrode. The second electrode is located on the luminescent layer. The first power line is located in the peripheral area, and the first power line is electrically connected to the source. The second power line is located in the peripheral area, and the second power line is electrically connected to the second power The metal oxide insulating layer covers the first power line and the second power line, and the oxygen supply layer covers the metal oxide insulating layer above the first power line and the second power line.

Based on the above, since the oxygen supply layer is in contact with the metal layer to provide the oxygen required for the oxidation of the metal layer during the annealing process, the phenomenon that the metal layer is oxidized in the annealing process can be avoided.

The above described features and advantages of the invention will be apparent from the following description.

30‧‧‧First power cord

40‧‧‧second power cord

52‧‧‧ display area

54‧‧‧The surrounding area

100‧‧‧ pixel array

110‧‧‧Substrate

120‧‧‧First oxygen supply layer

122‧‧‧Isolation

130‧‧‧Oxide semiconductor layer

130S‧‧‧ source area

130C‧‧‧Channel area

130D‧‧‧Bungee Area

140‧‧‧Brake insulation pattern

150‧‧‧ gate

160‧‧‧metal layer

160a‧‧‧Metal oxide insulation

170‧‧‧Second oxygen supply layer/oxygen supply layer

180‧‧‧flat layer

192‧‧‧protection layer

194‧‧‧First electrode

195‧‧‧ pixel separation wall

196‧‧‧Lighting layer

198‧‧‧second electrode

C‧‧‧ capacitor

D‧‧‧汲

DL‧‧‧ data line

GL‧‧‧ power cord

OLED‧‧ Organic Light Emitting Diode

PL‧‧‧Power cord

S‧‧‧ source

SL‧‧‧ scan line

T1, T2‧‧‧ film transistor

V1’‧‧‧ first child opening

V2’‧‧‧ second child opening

V1‧‧‧ first opening

V2‧‧‧ second opening

V3‧‧‧ third opening

V4‧‧‧ fourth opening

1 is a schematic view of a display panel in accordance with an embodiment of the present invention.

2 is a partial equivalent circuit diagram of the display panel of the embodiment of FIG. 1.

3A to 3H are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to an embodiment of the present invention.

4 is a cross-sectional view of a display panel including a thin film transistor of the embodiment of FIG. 3H of the present invention.

5A to 5D are partial cross-sectional views showing a method of manufacturing a thin film transistor according to another embodiment of the present invention.

Figure 6 is a cross-sectional view of a display panel including a thin film transistor of the embodiment of Figure 5D of the present invention.

7A to 7G are diagrams of a method of manufacturing a thin film transistor according to another embodiment of the present invention; Flow chart of the process.

Figure 8 is a cross-sectional view showing a display panel of a thin film transistor of the embodiment of Figure 7G of the present invention.

9A to 9D are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to another embodiment of the present invention.

Figure 10 is a cross-sectional view showing a display panel of a thin film transistor of the embodiment of Figure 9D of the present invention.

11A to 11D are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to another embodiment of the present invention.

Figure 12 is a cross-sectional view showing a display panel of a thin film transistor of the embodiment of Figure 11D of the present invention.

Fig. 13A is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of a thin film transistor of a conventional display panel.

Figure 13B is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 4 of the present invention.

Figure 14 is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 8 of the present invention.

Figure 15 is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 12 of the present invention.

1 is a schematic view of a display panel in accordance with an embodiment of the present invention. 2 is a partial equivalent circuit diagram of the display panel of the embodiment of FIG. 1. Please also refer to Figure 1 and Figure 2. The display panel of this embodiment includes a substrate 110, and the substrate 110 includes a display area 52 and a peripheral area 54 located at the periphery of the display area 52. A pixel array 100 is located in display area 52. The pixel array 100 has a plurality of pixel structures (not labeled), and each pixel structure includes at least one thin film transistor T1, T2 and one organic light emitting diode OLED electrically connected to at least one thin film transistor T1, T2. . According to an embodiment of the present invention, the pixel array 100 further includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of power lines PL, GL (shown in FIG. 2), wherein the power lines PL, GL are respectively connected to A first power line 30 and a second power line 40 in the peripheral area 54. The first power line 30 is, for example, a high voltage power line (connected to the voltage OVDD), and the second power line 40 is, for example, a low voltage power line (connected to the voltage OVSS), and a metal oxide insulating layer 160a is overlaid on the display. The region 52 and the first power line 30 of the peripheral region 54 and the second power line 40 are electrically isolated from each other.

According to an embodiment of the present invention, the thin film transistor T1 has a gate, a source, and a drain (not labeled), wherein the source is electrically connected to the data line DL, and the gate is electrically connected to the scan line SL. And the drain is electrically connected to the thin film transistor T2. The thin film transistor T2 has a gate, a source and a drain (not shown), wherein the gate is electrically connected to the drain of the thin film transistor T1, and the source is electrically connected to the power line PL, and The pole is electrically connected to the organic light emitting diode OLED. One electrode end of a capacitor C is electrically connected to the drain of the thin film transistor T1, and the other electrode end of the capacitor C is electrically connected to the drain of the thin film transistor T2. The organic light emitting diode OLED includes a first electrode, a light emitting layer and a second electrode (not shown), wherein the first electrode is electrically connected to the drain of the thin film transistor T2, and the second electrode is electrically connected to the power line GL. Sexual links. in In this embodiment, each pixel structure is illustrated by taking two thin film transistors together with a capacitor (2T1C) as an example, but is not intended to limit the present invention, and the present invention is not limited to the thin film transistor in each pixel structure. The number of capacitors. 3A to 3H are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to an embodiment of the present invention. In the manufacturing flow of FIGS. 3A to 3H, the thin film transistor T2 is taken as an example. Although the drawing does not show the manufacturing flow of the thin film transistor T1, in practice, the manufacturing process of the thin film transistor T1 is the same as that of the thin film transistor T2.

First, referring to FIG. 3A, a substrate 110 is provided. The substrate 110 may be made of glass, quartz, organic polymer, or an opaque/reflective material (eg, conductive material, metal, wafer, ceramic, or other applicable material), or other applicable materials. . If a conductive material or metal is used, an insulating layer (not shown) is coated on the substrate 110 to avoid short circuit problems. An oxide semiconductor layer 130, a gate insulating pattern 140, and a gate 150 are sequentially formed on the substrate 110; and the gate insulating pattern 140 and the gate 150 expose a portion of the oxide semiconductor layer 130. In the present embodiment, the method for fabricating the oxide semiconductor layer 130, the gate insulating pattern 140, and the gate 150 is, for example, first depositing a layer of an oxidized semiconductor material (not shown) in a patterning process to form an oxide semiconductor. Layer 130; Next, a gate insulating material layer (not shown) and a gate material layer (not shown) are patterned to form a gate insulating pattern 140 and a gate 150. The above patterning process is, for example, a lithography process, but the invention is not limited thereto.

The material of the oxide semiconductor layer 130 is, for example, a metal oxide semiconductor material, for example, Indium-Gallium-Zinc Oxide (IGZO), oxidation. Zinc (ZnO) tin oxide (SnO), Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) or Indium Tin Oxide (Zinc-Tin Oxide, ZTO) Indium-Tin Oxide, ITO), or other suitable materials, or combinations thereof. The material of the gate insulating pattern 140 comprises an inorganic material (for example: hafnium oxide, tantalum nitride, niobium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable material, or The combination. The material of the gate 150 comprises a metal, a metal oxide, an organic conductive material, or a combination thereof. In the present embodiment, the gate insulating pattern 140 and the gate 150 are a single layer structure; however, in other embodiments, the gate insulating pattern 140 and the gate 150 may also be a two-layer structure or a multi-layer stacked structure, and the present invention is not limited thereto. In one embodiment, the gate 150 is, for example, a composite metal layer of a three-layer structure of titanium-aluminum-titanium.

Referring to FIG. 3B, a metal layer 160 is sequentially formed over the substrate 110 to cover the oxide semiconductor layer 130, the gate insulating pattern 140, and the gate 150, and the metal layer 160 directly contacts the exposed portion of the oxide semiconductor layer 130. Contact. The material of the metal layer 160 comprises aluminum, titanium, indium or other metals. Next, an oxygen supply layer 170 is formed over the metal layer 160 as shown in FIG. 3C. The material of the oxygen supply layer 170 comprises yttrium oxide or a metal oxide semiconductor material (for example: indium tin gallium zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, indium gallium tin oxide, tin gallium zinc oxide, indium) Zinc oxide, tin zinc oxide, indium tin oxide, indium gallium oxide, tin gallium oxide, zinc gallium oxide, indium oxide, tin oxide, gallium oxide, zinc oxide) or other suitable oxygen-containing materials.

Then, referring to FIG. 3D, a first annealing process is performed to make the metal layer 160 is converted into a metal oxide insulating layer 160a. The first annealing process is carried out, for example, in an environment of normal atmospheric pressure (for example, an atmospheric pressure, 1 atm), 340 ° C, and an oxygen concentration of 18%. In this embodiment, the entire surface of the oxygen supply layer 170 directly contacts the metal layer 160. In the first annealing process, the oxygen supply layer 170 can provide the oxygen required for the oxidation of the metal layer 160, thereby ensuring that the metal layer 160 is completely converted into the metal oxide insulating layer 160a, which solves the problem of incomplete oxidation of the conventional aluminum thin film. The problem. In addition, in the first annealing process, the metal layer 160 also takes oxygen from the contacted oxide semiconductor layer 130, so that the oxygen concentration of the portion of the oxide semiconductor layer 130 in contact with the metal layer 160 is lower than that of the metal. The oxygen concentration of the portion of the oxide semiconductor layer 130 that the layer 160 contacts. A region having a low oxygen concentration in the oxide semiconductor layer 130 (that is, a region having a relatively high conductivity) forms a source region 130S and a drain region 130D, and a region having a high oxygen concentration in the oxide semiconductor layer 130 (ie, a conductive region) A relatively low rate region) forms a channel region 130C.

In addition, a second annealing process may be performed after the formation of the metal layer 160 and before the formation of the oxygen supply layer 170. In other words, when both the first annealing process and the second annealing process are performed, the oxygen supply layer 170 is formed after the second annealing process is performed, and the first annealing process is performed after the oxygen supply layer 170 is formed. The second annealing process is carried out, for example, in an environment of normal atmospheric pressure (for example, an atmospheric pressure, 1 atm), 300 ° C, and an oxygen concentration of 40%. During the second annealing process, the metal layer 160 takes oxygen from the source region 130S and the drain region 130D of the contacted oxide semiconductor layer 130 and the annealing environment, so that the metal layer 160 is partially converted into metal oxide. Insulation layer 160a. The first annealing process of the present implementation is performed in a first environment, and the second annealing process The fire process is carried out in a second environment, the oxygen content of the second environment being equal to or higher than the oxygen content of the first environment, and the temperature of the first environment being equal to or higher than the temperature of the second environment. However, the present invention does not limit the conditions of the first annealing process and the second annealing process, for example, the oxygen content of the second environment may also be equal to the oxygen content of the first environment.

As shown in FIG. 3E, the oxygen supply layer 170 over the metal oxide insulating layer 160a is removed. Next, as shown in FIG. 3F, the metal oxide insulating layer 160a is patterned to form a first sub-opening V1' exposing the source region 130S and a second sub-opening V2' exposing the drain region 130D. Thereafter, as shown in FIG. 3G, a flat layer 180 is formed over the substrate 110, and the flat layer 180 is patterned to form a first opening V1 exposing the source region 130S and exposing one of the drain regions 130D. The second opening V2. The material of the flat layer 180 comprises an inorganic material (for example: cerium oxide, cerium nitride, cerium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material (for example, polyester (PET), Polyene, polypropylene, polycarbonate, polyalkylene oxide, polyphenylene, polyether, polyketone, polyalcohol, polyaldehyde, or other suitable material, or a combination thereof ), or other suitable materials, or a combination of the above. In the present embodiment, the metal oxide insulating layer 160a is first patterned, the flat layer 180 is formed, and the flat layer 180 is patterned; however, the present invention is not limited thereto. In another embodiment, the planarization layer 180 may be formed first, and then the planarization layer 180 and the metal oxide insulating layer 160a may be sequentially patterned to form an opening.

Next, as shown in FIG. 3H, a source S and a drain D are formed, and the source region 130S and the drain region 130D are electrically connected through the first opening V1 and the second opening V2, respectively. At this point, a thin film transistor has been formed. In this embodiment, it is top The gate type thin film transistor is exemplified, but the invention is not limited thereto. According to other embodiments, the active elements T1, T2 may also be bottom gate type thin film transistors.

4 is a cross-sectional view of a display panel including a thin film transistor of the embodiment of FIG. 3H of the present invention, wherein the manufacturing process for forming the display panel includes the following steps (not shown). A protective layer 192 is formed on the thin film transistor as shown in FIG. 3H, and the protective layer 192 is patterned to form a third opening V3 exposing the drain D. A first electrode 194 is formed on the protective layer 192. The first electrode 194 is electrically connected to the drain D through the third opening V3, and the first electrode 194 fills the third opening V3. A pixel isolation wall 195 is formed on the first electrode 194, and the pixel isolation wall 195 has a fourth opening V4. A light emitting layer 196 is formed in the fourth opening V4; and a second electrode 198 is formed on the light emitting layer 196. The first electrode 194, the light-emitting layer 196, and the second electrode 198 constitute an organic light-emitting diode OLED. The material of the light-emitting layer 196 of the present embodiment is exemplified by an organic light-emitting material, but the invention is not limited thereto. In an embodiment of the invention, the light-emitting layer 196 may be a single-layer light-emitting layer or a combination of a main light-emitting layer plus an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. The primary luminescent layer is, for example, a layer of white light luminescent material or a layer of luminescent material of other specific colored light (eg, red, green, blue, etc.). In another embodiment of the present invention, at least one of the electron transport layer, the electron injection layer, the hole transport layer, and the hole injection layer may be selected to be combined with the main light emitting layer to form two, three, four, or five layers. The stacked layers further enhance the luminous efficiency of the luminescent layer 196. In addition, the detailed materials and structures of other film layers of the organic light-emitting diode OLED are well known to those skilled in the art, and therefore will not be described again.

It is worth mentioning that this embodiment is further included before the formation of the metal layer 160. The first power line 30 and the second power line 40 are formed on the peripheral region 54 of the substrate 110, wherein the metal layer 160 covers the first power line 30 and the second power line 40, and subsequently covers the metal layer with the oxygen supply layer 170. 160. After the first annealing process is performed, the metal layer 160 located above the first power line 30 and the second power line 40 is converted into the metal oxide insulating layer 160a as shown in FIG. Here, due to the provision of the oxygen supply layer 170, the probability that the metal layer 160 is not converted into the metal oxide insulating layer 160a can be greatly reduced, thereby ensuring that the first power line 30 and the second power line 40 are electrically isolated from each other.

Based on the above, in the annealing process in this embodiment, the oxygen supply layer and the oxide semiconductor layer can provide sufficient oxygen for oxidation of the metal layer, avoiding the phenomenon of incomplete oxidation of the metal layer in the annealing process, and improving the source of the oxide semiconductor layer. The electrical uniformity of the polar regions and the drain regions further allows the drain of the thin film transistor of the present invention to have better current uniformity driven by the gate voltage. Moreover, since the metal layer avoids the phenomenon of incomplete oxidation during the annealing process, the resistance values of the first power line and the second power line located in the peripheral area of the display panel are improved, thereby avoiding the first power line and the second power source. A short circuit between the lines ensures that the display panel is displayed properly.

5A to 5D are partial process cross-sectional views of a thin film transistor according to another embodiment of the present invention. In the present embodiment, the method of manufacturing the thin film transistor is carried out by first performing the above steps of Figs. 3A to 3D. Next, referring to FIG. 5A, after the first annealing process is performed to convert the metal layer 160 into the metal oxide insulating layer 160a, the oxygen supply layer 170 located above the metal oxide insulating layer 160a is not removed.

Next, as shown in FIG. 5B, a flat layer 180 is formed over the substrate 110. Referring to FIG. 5C, the patterned flat layer 180, the oxygen supply layer 170, and the metal oxide are absolutely The edge layer 160a forms a first opening V1 exposing the source region 130S and a second opening V2 exposing the drain region 130D. In the present embodiment, the flat layer 180 is formed first, and then the flat layer 180, the oxygen supply layer 170, and the metal oxide insulating layer 160a are sequentially patterned to form openings; however, the present invention is not limited thereto. In another embodiment, the oxygen supply layer 170 and the metal oxide insulating layer 160a may be patterned first, then the planarization layer 180 may be formed, and the planarization layer 180 may be patterned. Referring to FIG. 5D, a source S and a drain D are formed, and the source region 130S and the drain region 130D are electrically connected through the first opening V1 and the second opening V2, respectively. At this point, another thin film transistor has been formed.

Similar to FIG. 4, FIG. 6 is a cross-sectional view of a display panel including the thin film transistor of the embodiment of FIG. 5D of the present invention. After the thin film transistor of FIG. 5D is completed, a protective layer 192, a first electrode 194, and a pixel are subsequently formed. The partition wall 195, the light emitting layer 196, and the second electrode 198 complete the structure of the display panel. The first electrode 194, the light-emitting layer 196, and the second electrode 198 constitute an organic light-emitting diode OLED. The detailed materials and structures of the respective layers of the organic light-emitting diode OLED are well known to those skilled in the art and will not be described again.

According to the above, in the annealing process in this embodiment, the oxygen supply layer and the oxide semiconductor layer provide sufficient oxygen for oxidation of the metal layer, so that the metal layer can be completely oxidized, and the source region and the drain region of the oxide semiconductor layer are improved. The electrical uniformity makes the drain of the thin film transistor of the invention have better current uniformity under the driving of the gate voltage, and simultaneously increases the resistance value of the first power line and the second power line, avoiding the first power line A short circuit with the second power line ensures that the display panel can be displayed normally.

Hereinafter, a method of manufacturing a thin film transistor according to another embodiment of the present invention will be described in detail with reference to the drawings. 7A to 7G are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to another embodiment of the present invention. Referring to FIG. 7A, a substrate 110 is provided, and a first oxygen supply layer 120, an isolation layer 122, an oxide semiconductor layer 130, a gate insulation pattern 140, and a gate are sequentially formed on the upper surface of the substrate 110. 150, the gate insulating pattern 140 and the gate 150 expose a portion of the oxide semiconductor layer 130. In this embodiment, the first structure of the first oxygen supply layer 120, an isolation material layer (not shown), and an oxide semiconductor material layer (not shown) are sequentially deposited on the substrate 110, and then The isolation material layer and the oxidized semiconductor material layer are subjected to a patterning process to form the isolation layer 122 and the oxide semiconductor layer 130. Next, a gate insulating material layer (not shown) and a gate material layer (not shown) are deposited, and patterned to form the gate insulating pattern 140 and the gate 150. The above patterning process is, for example, a lithography process, but the invention is not limited thereto.

The material of the first oxygen supply layer 120 comprises yttrium oxide or a metal oxide semiconductor material (for example: indium tin gallium zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, indium gallium tin oxide, tin gallium zinc oxide , indium zinc oxide, tin zinc oxide, indium tin oxide, indium gallium oxide, tin gallium oxide, zinc gallium oxide, indium oxide, tin oxide, gallium oxide, zinc oxide) or other suitable oxygen-containing materials . The material of the isolation layer 122 comprises an inorganic material (for example: cerium oxide, cerium nitride, cerium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable material, or the above combination. The material of the oxide semiconductor layer 130 is, for example, a metal oxide semiconductor material, for example, Indium-Gallium-Zinc Oxide (Indium-Gallium-Zinc Oxide, IGZO), zinc oxide (ZnO) tin oxide (SnO), indium-zinc oxide (IZO), gallium zinc oxide (GZO), zinc tin oxide (Zinc-Tin Oxide, ZTO) or Indium-Tin Oxide (ITO), or other suitable materials, or a combination thereof. In the present embodiment, the gate insulating pattern 140 and the gate 150 are a single layer structure; however, in other embodiments, the gate insulating pattern 140 and the gate 150 may also be a two-layer structure or a multi-layer stacked structure, and the present invention is not limited thereto. In one embodiment, the gate 150 is, for example, a composite metal layer of a three-layer structure of titanium-aluminum-titanium.

Referring to FIG. 7B, a metal layer 160 is formed over the substrate 110 to cover the oxide semiconductor layer 130, the gate insulating pattern 140, and the gate 150, and the metal layer 160 is in direct contact with the exposed portion of the oxide semiconductor layer 130. . The material of the metal layer 160 comprises aluminum, titanium, indium or other metals. Next, as shown in FIG. 7C, a second oxygen supply layer 170 is entirely formed on the metal layer 160. The material of the second oxygen supply layer 170 comprises yttrium oxide or a metal oxide semiconductor material (for example: indium tin gallium zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, indium gallium tin oxide, tin gallium zinc oxide , indium zinc oxide, tin zinc oxide, indium tin oxide, indium gallium oxide, tin gallium oxide, zinc gallium oxide, indium oxide, tin oxide, gallium oxide, zinc oxide) or other suitable oxygen-containing materials . The material of the second oxygen supply layer 170 may be the same as or different from the material of the first oxygen supply layer 120.

Referring to FIG. 7D, a first annealing process is performed to convert the metal layer 160 into the metal oxide insulating layer 160a. The first annealing process is carried out, for example, in an environment of normal atmospheric pressure (for example, an atmospheric pressure, 1 atm), 340 ° C, and an oxygen concentration of 18%. In this embodiment, the entire second oxygen supply layer 170 directly contacts the entire metal layer 160. in In the first annealing process, the second oxygen supply layer 170 can provide the oxygen required for the oxidation of the metal layer 160, thereby ensuring that the metal layer 160 is completely converted into the metal oxide insulating layer 160a, thereby solving the problem of incomplete oxidation of the conventional aluminum thin film. The problem that arises. In addition, in the first annealing process, the metal layer 160 also takes oxygen from the contacted oxide semiconductor layer 130 and the first oxygen supply layer 120, so that the metal layer 160 can be converted into the metal oxide insulating layer 160a. In particular, the oxygen concentration of the portion of the oxide semiconductor layer 130 that is in contact with the metal layer 160 is lower than the oxygen concentration of the portion of the oxide semiconductor layer 130 that is not in contact with the metal layer 160. A region of the oxide semiconductor layer 130 having a low oxygen concentration forms a source region 130S and a drain region 130D, and a region having a high oxygen concentration in the oxide semiconductor layer 130 forms a channel region 130C, wherein the source region 130S and the drain region 130D has a lower resistance value and has a better conductivity.

In addition, a second annealing process may be performed after the foregoing forming the metal layer 160 and before forming the second oxygen supply layer 170. In other words, when both the first annealing process and the second annealing process are performed, the second oxygen supply layer 170 is formed after the second annealing process is performed, and the first annealing process is performed after the second oxygen supply layer 170 is formed. . The second annealing process is carried out, for example, in an environment of normal atmospheric pressure (for example, an atmospheric pressure, 1 atm), 300 ° C, and an oxygen concentration of 40%. During the second annealing process, the metal layer 160 takes oxygen from the first oxygen supply layer 120, the source region 130S and the drain region 130D of the oxide semiconductor layer 130, and the annealing environment, so the metal layer 160 It is partially converted into a metal oxide insulating layer 160a. The first annealing process of the present embodiment is performed in a first environment, the second annealing process is performed in a second environment, the oxygen content of the second environment is equal to or higher than the oxygen content of the first environment, and the first environment Temperature Equal to or higher than the temperature of the second environment. However, the present invention does not limit the conditions of the first annealing process and the second annealing process.

As shown in FIG. 7E, a flat layer 180 is formed over the substrate 110. Thereafter, as shown in FIG. 7F, the planarization layer 180, the second oxygen supply layer 170, and the metal oxide insulating layer 160a are patterned to form a first opening V1 exposing the source region 130S and exposing the drain region 130D. a second opening V2. In the present embodiment, the flat layer 180 is formed first, and then the flat layer 180, the second oxygen supply layer 170, and the metal oxide insulating layer 160a are sequentially patterned to form openings; however, the present invention is not limited thereto. In another embodiment, the second oxygen supply layer 170 and the metal oxide insulating layer 160a may be patterned first, then the planarization layer 180 may be formed, and the planarization layer 180 may be patterned. Referring to FIG. 7G, a source S and a drain D are formed, and the source region 130S and the drain region 130D are electrically connected through the first opening V1 and the second opening V2, respectively. At this point, another thin film transistor has been formed. In the present embodiment, the top gate type thin film transistor is taken as an example, but the present invention is not limited thereto.

Similar to FIG. 4, FIG. 8 is a cross-sectional view of a display panel including the thin film transistor of the embodiment of FIG. 7G of the present invention, wherein the manufacturing process for forming the display panel includes the following steps (not shown). A protective layer 192 is formed on the thin film transistor as shown in FIG. 7G, and the protective layer 192 is patterned to form a third opening V3 exposing the drain D. A first electrode 194 is formed on the protective layer 192. The first electrode 194 is electrically connected to the drain D through the third opening V3, and the first electrode 194 fills the third opening V3. A pixel isolation wall 195 is formed on the first electrode 194, and the pixel isolation wall 195 has a fourth opening V4. Forming a light emitting layer 196 in the fourth opening V4; Above the light-emitting layer 196, a second electrode 198 is formed, thereby completing the structure of the display panel. The first electrode 194, the light-emitting layer 196, and the second electrode 198 constitute an organic light-emitting diode OLED. The detailed materials and structures of the respective layers of the organic light-emitting diode OLED are well known to those skilled in the art and will not be described again.

Based on the above, in the annealing process in this embodiment, the first oxygen supply layer, the second oxygen supply layer, and the oxide semiconductor layer can provide sufficient oxygen for oxidation of the metal layer, thereby avoiding oxidation of the metal layer during the annealing process. The phenomenon improves the electrical uniformity of the source region and the drain region of the oxide semiconductor layer, so that the drain of the thin film transistor of the present invention has better current uniformity driven by the gate voltage. Moreover, the metal layer located in the peripheral region of the display panel avoids the phenomenon of incomplete oxidation during the annealing process, thereby increasing the resistance value of the first power line and the second power line, thereby avoiding the relationship between the first power line and the second power line Short circuit to ensure that the display panel can be displayed normally.

9A to 9D are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to another embodiment of the present invention. In the present embodiment, the method of manufacturing the thin film transistor first performs the above-described steps of FIGS. 7A to 7D. Next, referring to FIG. 9A, after the first annealing process is performed to convert the metal layer 160 into the metal oxide insulating layer 160a, the second oxygen supply layer 170 located above the metal oxide insulating layer 160a is removed.

Next, as shown in FIG. 9B, a flat layer 180 is formed over the substrate 110. As shown in FIG. 9C, the planarization layer 180 and the metal oxide insulating layer 160a are patterned to form a first opening V1 exposing the source region 130S and a second opening V2 exposing the drain region 130D. In this embodiment, the flat layer 180 is formed first, and then the planarization layer 180 and the metal oxide insulating layer 160a are sequentially patterned to form An opening; however, the invention is not limited thereto. In another embodiment, the metal oxide insulating layer 160a may be patterned first, then the planarization layer 180 may be formed, and the planarization layer 180 may be patterned. Referring to FIG. 9D, a source S and a drain D are formed, and the source region 130S and the drain region 130D are electrically connected through the first opening V1 and the second opening V2, respectively. At this point, another thin film transistor has been formed.

Similar to FIG. 4, FIG. 10 is a cross-sectional view of a display panel including the thin film transistor of the embodiment of FIG. 9D of the present invention. After the thin film transistor of FIG. 9D is completed, a protective layer 192, a first electrode 194, and a pixel are formed. The partition wall 195, the light emitting layer 196, and the second electrode 198 complete the structure of the display panel. The first electrode 194, the light-emitting layer 196, and the second electrode 198 constitute an organic light-emitting diode OLED. The detailed materials and structures of the respective layers of the organic light-emitting diode OLED are well known to those skilled in the art and will not be described again.

According to the above, in the annealing process in this embodiment, the first oxygen supply layer, the second oxygen supply layer, and the oxide semiconductor layer provide sufficient oxygen for oxidation of the metal layer, so that the metal layer can be completely oxidized, and the oxide semiconductor layer is improved. The electrical uniformity of the source region and the drain region enables the drain of the thin film transistor of the present invention to have better current uniformity under the gate voltage driving, and also improves the first power line and the second power line. The resistance value avoids a short circuit between the first power line and the second power line, thereby ensuring that the display panel can be normally displayed.

11A to 11D are cross-sectional views showing the flow of a method of manufacturing a thin film transistor according to another embodiment of the present invention. In the present embodiment, the method of manufacturing the thin film transistor first performs the above steps of FIGS. 7A to 7B, and forms a gold over the substrate 110. The tributary layer 160 covers the oxide semiconductor layer 130, the gate insulating pattern 140, and the gate 150. Next, referring to FIG. 11A, a first annealing process is directly performed to convert the metal layer 160 into the metal oxide insulating layer 160a. The first annealing process is carried out, for example, in an environment of normal atmospheric pressure (for example, an atmospheric pressure, 1 atm), 340 ° C, and an oxygen concentration of 18%. In the first annealing process, the metal layer 160 takes oxygen from the contacted oxide semiconductor layer 130, the first oxygen supply layer 120, and the annealing environment, so that the metal layer 160 can be converted into the metal oxide insulating layer 160a. In particular, the metal layer 160 that is not in contact with the oxide semiconductor layer 130 and the first oxygen supply layer 120 is not converted into the metal oxide insulating layer 160a, so the metal layer 160 in this embodiment is partially converted into metal oxide. The insulating layer 160a is shown in Fig. 11A. The oxygen concentration of the portion of the oxide semiconductor layer 130 that is in contact with the metal layer 160 is lower than the oxygen concentration of the portion of the oxide semiconductor layer 130 that is not in contact with the metal layer 160. Therefore, a region of the oxide semiconductor layer 130 having a low oxygen concentration forms a source region 130S and a drain region 130D, and a region having a high oxygen concentration in the oxide semiconductor layer 130 forms a channel region 130C, wherein the source region 130S and the gate region The polar region 130D has a lower resistance value and has a better electrical conductivity.

As shown in FIG. 11B, a flat layer 180 is formed over the substrate 110. As shown in FIG. 11C, the planarization layer 180 and the metal oxide insulating layer 160a are patterned to form a first opening V1 exposing the source region 130S and a second opening V2 exposing the drain region 130D. In the present embodiment, the flat layer 180 is formed first, and then the flat layer 180 and the metal oxide insulating layer 160a are sequentially patterned to form an opening; however, the present invention is not limited thereto. In another embodiment, the metal oxide insulating layer 160a may be patterned first, then the planarization layer 180 may be formed, and the planarization layer 180 may be patterned. Referring to FIG. 11D, a source S and a drain D are formed, and the source region 130S and the drain region 130D are electrically connected through the first opening V1 and the second opening V2, respectively. At this point, another thin film transistor has been formed.

Similar to FIG. 4, FIG. 12 is a cross-sectional view of a display panel including the thin film transistor of the embodiment of FIG. 11D of the present invention. After the thin film transistor of FIG. 11D is completed, a protective layer 192, a first electrode 194, and a pixel are formed. The partition wall 195, the light emitting layer 196, and the second electrode 198 complete the structure of the display panel. The first electrode 194, the light-emitting layer 196, and the second electrode 198 constitute an organic light-emitting diode OLED. The detailed materials and structures of the respective layers of the organic light-emitting diode OLED are well known to those skilled in the art and will not be described again.

Based on the above, in the annealing process in this embodiment, the first oxygen supply layer and the oxide semiconductor layer can provide sufficient oxygen for oxidation of the metal layer, so that the metal layer avoids oxidation in a specific region during the annealing process. The electrical uniformity of the source region and the drain region of the oxide semiconductor layer can be improved, so that the drain of the thin film transistor of the present invention has better current uniformity driven by the gate voltage. Therefore, the resistance values of the first power line and the second power line located in the peripheral area of the display panel are improved, and a short circuit between the first power line and the second power line is avoided, so that the display panel can be normally displayed.

Fig. 13A is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of a conventional thin film transistor. Figure 13B is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 4 of the present invention. In FIGS. 13A and 13B, the solid line curve has a drain voltage (Vd) of 10 volts, and the dotted curve has a drain voltage (Vd) of 0.1 volt. The relationship between the gate current and the gate voltage (Id-Vg) is shown by Three measurement points are selected on the substrate of the display panel and are respectively obtained by electrically measuring the thin film transistors arranged in the three measurement points. As can be seen from FIG. 13A, the drain of the conventional thin film transistor is driven by the gate voltage (Vg), and the drain current (Id) uniformity is shifted and unstable. However, as can be seen from Fig. 13B, the drain of the thin film transistor of the present invention has stable and preferable current uniformity driven by the gate voltage.

In order to demonstrate that the design of the thin film transistor of the present invention does have better current uniformity, experiments have been carried out in other embodiments of the present invention for verification. Figure 14 is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 8 of the present invention. Figure 15 is a graph showing the relationship between the gate current and the gate voltage (Id-Vg) of the thin film transistor of the display panel of Figure 12 of the present invention. As is clear from Fig. 14 and Fig. 15, the drain of the thin film transistor of the present invention has better current uniformity driven by the gate voltage.

In summary, in the method for fabricating a thin film transistor of the present invention, an oxygen supply layer is used and the oxygen supply layer is brought into contact with the metal layer, so that the oxygen supply layer can provide the oxidation of the metal layer during the annealing process. Oxygen to avoid oxidation incompleteness of the metal layer during the annealing process, improve the electrical uniformity of the source region and the drain region of the oxide semiconductor layer (eg, electron mobility, subcritical swing (sub) -threshold swing) and threshold swing, which in turn allows the drain of the thin film transistor of the present invention to have better current uniformity driven by the gate voltage. Moreover, in the manufacturing process of the display panel of the present invention, the annealing process is performed after the oxygen supply layer is completely formed on the metal layer, thereby avoiding the conversion of the metal layer into a metal oxide insulating layer and causing a erroneous short circuit (for example: Leakage between a power line and a second power line (current leakage) caused by (current leakage). Since the metal layer is converted into a metal oxide insulating layer after the annealing process, the resistance values of the first power line and the second power line are increased, and the brightness of the display panel, the sub-pixel lighting rate, and the thin film transistor are also improved. The correctness of the switch and driving functions ensures that the display panel is displayed properly.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧Substrate

120‧‧‧First oxygen supply layer

122‧‧‧Isolation

130‧‧‧Oxide semiconductor layer

130S‧‧‧ source area

130C‧‧‧Channel area

130D‧‧‧Bungee Area

140‧‧‧Brake insulation pattern

150‧‧‧ gate

160a‧‧‧Metal oxide insulation

170‧‧‧Second oxygen supply layer

180‧‧‧flat layer

S‧‧‧ source

D‧‧‧汲

V1‧‧‧ first opening

V2‧‧‧ second opening

Claims (19)

A thin film transistor comprising: an oxide semiconductor layer having a source region, a drain region and a channel region, the channel region being located between the source region and the drain region; a gate insulating pattern located at a gate region of the oxide semiconductor layer; a gate on the gate insulating pattern; a metal oxide insulating layer covering the oxide semiconductor layer; and an oxygen supply layer in contact with the metal oxide insulating layer; And a source and a drain are disposed above the oxygen supply layer and electrically connected to the source region and the drain region of the oxide semiconductor layer, respectively. The thin film transistor of claim 1, wherein the oxygen supply layer is over the metal oxide insulating layer, and the metal oxide insulating layer further covers the gate and the gate insulating pattern. The thin film transistor according to claim 1, further comprising an isolation layer, wherein the oxygen supply layer is located under the metal oxide semiconductor, the isolation layer is located between the oxide semiconductor layer and the oxygen supply layer And the metal oxide insulating layer covers the isolation layer and the oxygen supply layer. The thin film transistor according to claim 3, further comprising a metal layer covering the gate and the gate insulating pattern. The thin film transistor according to claim 4, wherein the metal layer comprises aluminum, titanium or indium, and the metal oxide insulating layer comprises aluminum oxide, titanium oxide or indium oxide. The thin film transistor according to claim 1, further comprising an isolation layer, wherein the oxygen supply layer comprises: a first oxygen supply layer under the metal oxide semiconductor, wherein the isolation layer is located in the oxidation Between the semiconductor layer and the oxygen supply layer; and a second oxygen supply layer over the metal oxide insulating layer, and the metal oxide insulating layer further covers the gate, the gate insulating pattern, and the isolation layer And the first oxygen supply layer. The thin film transistor according to claim 1, wherein the metal oxide insulating layer comprises aluminum oxide, titanium oxide or indium oxide. The thin film transistor according to claim 1, wherein the material of the oxygen supply layer comprises ruthenium oxide or a metal oxide semiconductor material. A method for fabricating a thin film transistor includes: forming an oxide semiconductor layer; sequentially forming a gate insulating pattern and a gate on the oxide semiconductor layer; forming a metal layer to cover the oxide semiconductor layer, a gate insulating pattern and the gate; forming an oxygen supply layer to bring the metal layer into contact with the oxygen supply layer; performing a first annealing process to react the oxide semiconductor layer with the metal layer to form a source a region and a drain region, wherein the oxide semiconductor layer between the source region and the drain region is a channel region, and simultaneously reacting the metal layer with the oxygen supply layer and the oxide semiconductor layer to form a metal oxide insulating layer; and forming a source and a drain above the oxygen supply layer, the source and the anode The poles are electrically connected to the source region of the oxide semiconductor layer and the drain region, respectively. The method for producing a thin film transistor according to claim 9, wherein the forming of the metal layer and before forming the oxygen supply layer further comprises performing a second annealing process. The method for producing a thin film transistor according to claim 9, wherein the first annealing process is performed in an atmosphere at atmospheric pressure. The method of manufacturing a thin film transistor according to claim 9, wherein the oxygen supply layer is formed on the metal layer, and the metal oxide insulating layer formed after the first annealing process covers the gate a gate, the gate insulating pattern, and the oxide semiconductor layer. The method of manufacturing a thin film transistor according to claim 12, wherein after the performing the first annealing process, further comprising removing the oxygen supply layer. The method of manufacturing a thin film transistor according to claim 9, wherein the oxygen supply layer is formed under the oxide semiconductor layer, and the oxide semiconductor layer and the oxygen supply layer further comprise an isolation layer. And the metal oxide insulating layer formed after the first annealing process covers the oxide semiconductor layer, the isolation layer, and the oxygen supply layer. The method of manufacturing a thin film transistor according to claim 9, wherein the oxygen supply layer comprises a first oxygen supply layer and a second oxygen supply layer, and the first oxygen supply layer is formed on the oxide semiconductor layer. And forming an isolation layer between the oxide semiconductor layer and the oxygen supply layer, the second oxygen supply layer is formed on the metal layer; and the metal formed after the first annealing process Oxide insulation The gate, the gate insulating pattern, the oxide semiconductor layer, the isolation layer, and the oxygen supply layer. The method of manufacturing a thin film transistor according to claim 15, wherein after the performing the first annealing process, the second oxygen supply layer is further removed. The method for producing a thin film transistor according to claim 9, wherein the material of the oxygen supply layer comprises a ruthenium oxide or a metal oxide semiconductor material. A display panel comprising: a substrate having a display area and a peripheral area at a periphery of the display area; a plurality of thin film transistors located in the display area, wherein each of the thin film transistors is as described in claim 1 a thin film transistor; a first electrode located above the source and the drain, wherein the first electrode is electrically connected to the drain; a light emitting layer is located on the first electrode; and a second electrode is located a first power line is located in the peripheral area, and the first power line is electrically connected to the source; a second power line is located in the peripheral area, and the second power line is electrically connected In the second electrode, the metal oxide insulating layer covers the first power line and the second power line, and the oxygen supply layer covers the metal above the first power line and the second power line. On the oxide insulation layer. The display panel of claim 18, wherein the material of the oxygen supply layer comprises ruthenium oxide or a metal oxide semiconductor material.