TWI541946B - Semiconductor package and method of manufacture - Google Patents

Description

Semiconductor package and its manufacturing method

The invention relates to a method for manufacturing a semiconductor package, in particular to a semiconductor package for improving productivity and a method for manufacturing the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.

1A to 1E are schematic cross-sectional views showing a conventional method of fabricating a wafer-level semiconductor package 1.

As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.

Next, a plurality of semiconductor elements 12 are disposed on the thermal release adhesive layer 11, the semiconductor elements 12 having opposite active planes 12a and inactive surfaces 12b, each of which has a plurality of electrode pads 120 thereon, and Each of the active faces 12a is adhered to the thermal release adhesive layer 11.

As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release adhesive layer 11 to encapsulate the semiconductor component 12, and the semiconductor component 12 is formed. The inactive surface 12b is exposed to the encapsulant 13 .

As shown in FIG. 1C, a support member 17 is attached to the encapsulant 13 and the inactive surface 12b of the semiconductor device 12 by a bonding layer 170, and the encapsulant 13 is baked to harden the thermal release type. The adhesive layer 11 removes the thermal release adhesive layer 11 and the carrier 10 to expose the active surface 12a of the semiconductor component 12. Thereafter, the encapsulant 13 is cured.

As shown in FIG. 1D, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulant 13 and the active surface 12a of the semiconductor component 12, so that the circuit is re-wired. The electrode pad 120 of the semiconductor element 12 is electrically connected.

Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls.

As shown in FIG. 1E, a singulation process is performed along the dicing path S as shown in FIG. 1D to obtain a plurality of semiconductor packages 1 (ie, package units).

The conventional semiconductor package 1 is manufactured in a wafer form, and is manufactured in a panel form in order to reduce production costs. The size of the full-face form currently produced is 370 mm × 470 mm in length and width, and the target is developed to be 600 mm × 700 mm.

However, in the manufacturing method of the conventional semiconductor package 1, the current singulation machine can only be placed at a maximum size of 100 mm × 240 mm, and thus cannot be placed at a size of 370 mm × 470 mm or more, so that it is necessary to manually cut into a suitable size at this stage. Putting it into the existing singer, it is difficult to increase the output.

Furthermore, if you want to directly enter the layout of 370mm × 470mm or larger The line cutting process requires an extra special machine, which leads to an increase in production costs.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package, which is a full-surface structure, comprising: a carrier having a plurality of grooves; and a plurality of electronic units embedded in each of the grooves in.

In the above semiconductor package, the electronic unit includes: a package material formed in the grooves; and a plurality of electronic components embedded in the package in each of the grooves, and any of the grooves And a plurality of the electronic components; and a carrier formed on the package such that the carrier is correspondingly located on the groove. Furthermore, the electronic component has opposite active and inactive surfaces, and the carrier system covers the active surface of the electronic component.

In the foregoing semiconductor package, the electronic unit includes: a carrier having opposite first and second sides, and the first side has an area larger than the second side, and the carrier has the second side Correspondingly placed in the groove; a plurality of electronic components are disposed on the first side of the carrier, and any one of the electronic components is disposed on any of the carriers; and an encapsulating material is formed on the carrier Upper to cover the electronic components. Furthermore, the electronic component has opposing active and inactive surfaces, and the electronic component is bonded to the first side with its active surface. Also included is a support member disposed on the package. In addition, the groove is tapered.

The invention further provides a method for manufacturing a semiconductor package, comprising: providing a carrier having a plurality of grooves and a plurality of carriers, and each of the carriers Each of the packages is provided with a plurality of electronic components and a package covering the electronic components; each of the packages is embedded in each of the grooves, and each of the carriers protrudes from the carrier And removing each of the carriers to expose the packages; and performing a separation process along the grooves and removing the carrier.

In the above method, the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface.

In the above method, after removing each of the carriers, the electronic components are exposed to the carrier.

In the foregoing method, after the removal of each of the carriers, a line redistribution structure is formed on each of the packages, and the circuit redistribution structure electrically connects the electronic components.

In the above method, the singulation process is performed after the separation process is performed.

The invention provides a method for fabricating a semiconductor package, comprising: providing a carrier having a plurality of grooves and a plurality of carriers, each of the carriers having an opposite first side and a second side, and an area of the first side A plurality of electronic components are disposed on the first side, and the plurality of electronic components are disposed on the first side, and the electronic components are protruded from the recesses. Forming an encapsulating material on the carrier to cover the electronic components to form a plurality of packages on each of the carriers; removing each of the carrier and the carrier; and performing the package Separate the process.

In the above method, the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface.

In the above method, the shape of each of the grooves corresponds to the shape of the carrier.

In the foregoing method, the method further includes disposing a support member on the package before removing the carrier and the carrier. After the separation process is performed, the support member is removed; the method includes removing the support member first, and then performing the separation process.

In the above method, after the removal of each of the carrier and the carrier, a line redistribution structure is formed on the package, and the circuit redistribution structure electrically connects the electronic component.

In the above method, the singulation process is performed after the separation process is performed.

It can be seen from the above that the semiconductor package of the present invention and the method for manufacturing the same are designed by the carrier and the groove to separate the package block of the required size in the entire layout structure, and can be carried out in the subsequent process. The process of singulation, packaging and assembly is adopted, so that the size of the full-face can be increased according to the demand to increase the output, and the cost of machine development can be saved.

1,2,3‧‧‧Semiconductor package

10,20,30‧‧‧carriers

11‧‧‧heating release layer

12‧‧‧Semiconductor components

12a, 22a‧‧‧ active surface

12b, 22b‧‧‧ inactive surface

120,220‧‧‧electrode pads

13‧‧‧Package colloid

14,24‧‧‧Line redistribution structure

15‧‧‧Insulation protective layer

16,26‧‧‧ conductive elements

17,27‧‧‧Support

170, 270‧‧‧ bonding layer

2’, 3’‧‧‧Package Blocks

2a, 3a‧‧‧Packing unit

200,300‧‧‧ grooves

21,31‧‧‧Carrier

210,310,310’‧‧‧ adhesive layer

22‧‧‧Electronic components

23‧‧‧Package

240‧‧‧ dielectric layer

241‧‧‧Line layer

25‧‧‧Package

29,39‧‧‧Electronic unit

31a‧‧‧ first side

31b‧‧‧ second side

S, S’, S”‧‧‧ cutting path

L‧‧‧ split path

A, B, C, W, X‧‧‧ area

H‧‧‧depth

T‧‧‧thickness

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2F are cross-sectional views showing a first embodiment of a method of fabricating a semiconductor package of the present invention; wherein the 2F' is a 2F FIG. 3A to FIG. 3G are cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package of the present invention; wherein the 3Gth diagram is a lower view of the 3Gth diagram.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

2A to 2F are schematic cross-sectional views showing a first embodiment of the method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A to FIG. 2C, a carrier 20 having a plurality of recesses 200 and a plurality of carriers 21 are provided, and each of the carriers 21 is provided with a package 25, each of the packages 25 having a plurality of electronic components 22 and The package 23 covering the electronic components 22 is formed to constitute the electronic unit 29. Then, each of the electronic units 29 is placed in the recess 200 correspondingly with the package body 25, so that the carrier 21 protrudes from the carrier 20, thereby completing the panel structure. Semiconductor package 2.

In this embodiment, the carrier 20 is a semi-conductive such as a wafer or a raft. a body substrate or a glass substrate, and an area X of the top side or the bottom side of the carrier 20 is 610 mm × 720 mm, and the plurality of electronic components 22 are bonded to the single carrier 21, and the carrier 21 is The adhesive layer 210 on the surface is coupled to the electronic components 22, and the adhesive layer 210 also protrudes from the carrier 20.

Furthermore, the area A of the top side or the bottom side of the carrier 21 and the area W of the opening of the groove 200 are 100 mm×240 mm, so the carrier 21 and the groove 200 can be used as a puzzle structure. That is, the carrier 21 can be fabricated by cutting and separating the carrier 20 and the carrier 21 from a plate structure.

Moreover, the electronic component 22 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the electronic component 22 incorporates the adhesive layer 210 with its active surface 22a.

In addition, the encapsulating material 23 is formed on the adhesive layer 210 of the carrier 21 by a lamination method or a molding method, and the material of the encapsulant 23 is a package colloid and a dielectric photosensitive material. , Dry film type epoxy resin (Epoxy) or fluid epoxy resin, or organic material, such as ABF (Ajinomoto Build-up Film) resin.

As shown in FIG. 2D, each of the carrier 21 and the adhesive layer 210 are removed, and each of the packages 25 (such as the active surface 22a of the electronic component 22) is exposed.

As shown in Figure 2E, a redistribution layer is implemented. The RDL) process forms a line redistribution structure 24 on the package 23, the carrier 20 and the electronic components 22, and the line redistribution structure 24 is electrically connected to each of the electronic components 22. Next, a conductive element 26 such as a solder ball is bonded to a portion of the surface of the line redistribution structure 24 for connection to other electronic devices (such as a circuit board).

In this embodiment, the circuit redistribution structure 24 includes at least one circuit layer 241 and at least one dielectric layer 240 stacked on each other. The dielectric layer 240 is formed on the package 23, and the circuit layer 241 is The electronic component 22 is electrically connected.

As shown in FIGS. 2F and 2F', the separation process is performed along the division path L as shown in FIG. 2E (ie, along the edge of the grooves 200 or the edge of the package 25), and the carrier is completely removed. The bottom of 20.

In this embodiment, the separation process divides the full-page structure into a plurality of package strips 2', and the size of the package block 2' is 100 mm×240 mm, which is composed of a plurality of package units 2a (eg, 2F' is shown in the range of the cutting path S' of the singulation process. Specifically, the number of the electronic components 22 in the single package unit 2a can be determined according to requirements, that is, by adjusting the cutting path S' of the singulation process, for example, the single package unit 2a shown in FIG. 2F' has There are four electronic components 22, and in other embodiments, a single electronic component 22 can be included in a single package unit 2a.

Moreover, in other embodiments, the bottom of the carrier 20 may be removed first, and then the separation process is performed.

In the manufacturing method of the present invention, the design of the carrier 21 and the groove 200 is used to divide the entire surface structure into a package block having a size of 100 mm×240 mm. 2', and in the subsequent process, the package block 2' can be singulated to obtain the plurality of package units 2a, so the method can increase the size of the entire layout according to the requirements, and change the size of the entire layout to improve Yield.

Moreover, by the design of the carrier 21 and the groove 200, the entire layout structure can be divided into the singulation size required for the existing singulator (ie, the size of the package block 2'), and mass production can be performed. There is no need to develop additional machines, which can reduce the cost of machine development.

Moreover, by the design of the carrier 21 and the recess 200, the entire layout structure can be separated into the package block 2' of a desired size in an automated manner and placed in an existing singulator to increase the yield.

3A to 3G are schematic cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package 3 of the present invention.

As shown in FIGS. 3A to 3C, a carrier 30 having a plurality of grooves 300 and a plurality of carriers 31 are provided, and each of the carriers 31 has a first side 31a and a second side 31b opposite to each other, and the first side The area B of 31a is larger than the area C of the second side 31b, and a plurality of electronic components 22 are disposed on the first side 31a to constitute the electronic unit 39. Then, each of the electronic units 39 is placed in each of the grooves 300 corresponding to the second side 31b of the carrier 31 so that the electronic components 22 protrude from the carrier 30.

In this embodiment, the carrier 30 is a semiconductor substrate such as a wafer or a silicon plate or a glass substrate, and the area X of the top side or the bottom side of the carrier 30 is 610 mm×720 mm, and the single carrier is The body 31 is bonded with a plurality of electronic components 22, and the carrier 31 is bonded to the electronic components 22 by an adhesive layer 310 on the surface thereof. For example, the carrier 30 also has adhesive The layer 310' is disposed such that the upper side of the unitary structure is a flat surface by the arrangement of the adhesive layers 310, 310'.

Moreover, the depth h of the groove 300 is equal to the thickness t of the carrier 31. In other embodiments, the depth h of the groove 300 may be greater than the thickness t of the carrier 31 to facilitate placement of the carrier 31 in the groove 300.

Moreover, the area B of the first side 31a of the carrier 31 is 100 mm×240 mm, and the carrier 31 has a trapezoidal shape to facilitate placement in the recess 300, and the shape of each recess 300 is Corresponding to the shape of the carrier 31, the carrier 31 and the recess 300 can be used as a puzzle structure, that is, the carrier 31 can be fabricated by cutting and separating the carrier 30 from a board structure and Carrier 31.

In addition, the electronic component 22 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 22 has an opposite active surface 22a and an inactive surface 22b that is bonded to the active layer 22a (ie, the side having the electrode pads 220).

As shown in FIG. 3D, a package member 23 is formed on the carrier member 20 to cover the electronic components 22 to form a plurality of packages 25 corresponding to the carrier members 31. Thereby, the semiconductor package 3 of the full-panel structure is completed.

In this embodiment, the package material 23 is formed on the carrier member 30 by a lamination method or a molding method, and the material of the package material 23 is a package adhesive body and a dielectric material photosensitive insulation material. , Dry Film Type epoxy (Epoxy) or fluid epoxy resin, Or organic materials, such as ABF (Ajinomoto Build-up Film) resin.

Furthermore, a support member 27 can be coupled to the package member 23 (above the inactive surface 22b of the electronic component 22), and the support member 27 is disposed on the package member 23 by the bonding layer 270.

For example, the bonding layer 270 is made of a viscous material (such as a dry film epoxy resin), and the material of the support member 27 is an inorganic material or an organic material, such as glass, bismuth (Si), ceramic, Tantalum carbide (SiC), cerium oxide (SiO ₂ ), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), aluminum gallium arsenide (gallium aluminum arsenide, GaAlAs) or indium gallium phosphide (InGaP), etc., the organic material is, for example, plastic, glass fiber reinforced resin (such as bismaleimide-triazine, BT for short), fiberglass reinforced epoxy resin (fiberglass) Reinforced epoxy resin (such as FR-4) or epoxy (epoxy).

Moreover, the bonding layer 270 may be formed on the support member 27 by spin coating, and the bonding layer 270 may be bonded to the package member 23.

Alternatively, the bonding layer 270 may be formed on the package member 23, and the support member 27 may be bonded to the bonding layer 270.

As shown in FIG. 3E, the carrier 30, each of the carrier 31 and the adhesive layer 310, 310' are removed, and each of the packages 25 (such as the active surface 22a of the electronic component 22) is exposed.

As shown in Figure 3F, a redistribution layer (Redistribution layer, The RDL process is to form a line redistribution structure 24 on the package 23 and the electronic components 22, and the circuit redistribution structure 24 is electrically connected to each of the electronic components 22. Next, a conductive element 26 such as a solder ball is bonded to a portion of the surface of the line redistribution structure 24 for connection to other electronic devices (such as a circuit board).

In this embodiment, the circuit redistribution structure 24 includes at least one circuit layer 241 and at least one dielectric layer 240 stacked on each other. The dielectric layer 240 is formed on the package 23, and the circuit layer 241 is The electrode pads 220 of the electronic component 22 are electrically connected.

Furthermore, since the carrier 31 has a trapezoidal shape, the problem that the carrier 31 is displaced during the RDL process can be avoided, so that the problem of misalignment of subsequent processes can be avoided.

As shown in Figs. 3G and 3G', the separation process is performed along the division path L as shown in Fig. 3F (i.e., along the edges of the packages 25), and the support member 27 and the bonding layer 270 are completely removed.

In this embodiment, the separation process divides the full-page structure into a plurality of package strips 3', and the size of the package block 3' is 100 mm×240 mm, which is composed of a plurality of package units 3a (eg, 3G' is shown in the range of the cutting path S" of the singulation process. Specifically, the number of the electronic components 22 in the single package unit 3a can be determined according to requirements, that is, by adjusting the cutting path of the singulation process. For example, the single package unit 3a shown in FIG. 3G' has one electronic component 22, and in other embodiments, the single package unit 3a may have four electronic components 22.

Furthermore, in other embodiments, the support member 27 and the knot may also be removed first. The layer 270 is combined to perform the separation process.

In the manufacturing method of the present invention, the layout of the carrier 31 and the recess 300 is used to divide the full-surface structure into a package block 3' having a size of 100 mm × 240 mm, and in the subsequent process, the package block 3 can be 'The singulation process is performed to obtain the plurality of package units 3a. Therefore, the size of the entire layout surface can be increased according to the method, and the size of the entire layout surface can be changed to increase the yield.

Furthermore, by designing the carrier 31 and the recess 300, the entire layout structure can be divided into the singulation size required for the existing singulator (ie, the size of the package block 3'), and mass production can be performed. There is no need to develop additional machines, which can reduce the cost of machine development.

Moreover, by the design of the carrier 31 and the recess 300, the entire layout structure can be separated into the package block 3' of a desired size in an automated manner and placed in an existing singulator to increase the yield.

The present invention provides a semiconductor package 2, which is a full-surface structure, comprising: a carrier 20 having a plurality of recesses 200, a package 23 formed in the recesses 200, and embedded in each of the recesses The plurality of electronic components 22 in the package 23 of 200, and the plurality of carriers 21 formed on the package 23.

The electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the carrier 21 covers the active surface 22a of the electronic component 22.

Each of the carrier bodies 21 is correspondingly located on each of the grooves 200.

The present invention also provides a semiconductor package 3, which is a full-surface structure, comprising: a carrier 30 having a plurality of recesses 300, a plurality of carriers 31 disposed in each of the recesses 300, and a carrier 31 on the complex The electronic component 22 and the package 23 formed on the carrier 30 to cover the electronic components 22.

The carrier 31 has a first side 31a and a second side 31b, and the area B of the first side 31a is larger than the area C of the second side 31b. Each of the carriers 31 corresponds to the second side 31b. Placed in each of the grooves 300.

The electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the active surface 22a of the electronic component 22 is coupled to the first side 31a, and a plurality of the electronic components are disposed on the single carrier 31. Element 22.

In an embodiment, a support member 27 is formed on the package member 23.

In summary, the semiconductor package of the present invention and the manufacturing method thereof are mainly designed by separating the carrier and the groove of the puzzle type to separate the package block of the required size in the whole plate surface structure, in the subsequent process, It can be produced using existing machines, so it not only saves the cost of machine development, but also increases the size of the entire layout to increase production.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

20‧‧‧Carrier

200‧‧‧ grooves

21‧‧‧Carrier

210‧‧‧Adhesive layer

22‧‧‧Electronic components

23‧‧‧Package

25‧‧‧Package

29‧‧‧Electronic unit

W, X‧‧‧ area

Claims (19)

A semiconductor package, which is a full-surface structure, comprising: a carrier having a plurality of grooves; and a plurality of electronic units embedded in each of the grooves, and each of the electronic units comprises: a packaging material, Formed in the grooves; a plurality of electronic components embedded in the package in each of the grooves to be located in the groove, and any one of the plurality of electronic components in the groove; and a carrier , formed on the package and correspondingly located outside the groove. The semiconductor package of claim 1, wherein the electronic component has an opposite active surface and a non-active surface, and the carrier system covers the active surface of the electronic component. A semiconductor package includes: a carrier having a plurality of recesses; and a plurality of electronic units embedded in each of the recesses, and each of the electronic units includes: a carrier having a relative first The side and the second side, and the area of the first side is larger than the area of the second side, the carrier is placed in the groove corresponding to the second side; the plurality of electronic components are disposed on the carrier One side of the carrier is located outside the recess, and any one of the electronic components is disposed on any of the carriers; An encapsulating material is formed on the carrier to encapsulate the electronic components. The semiconductor package of claim 3, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the first side with its active surface. The semiconductor package of claim 3, further comprising a support member disposed on the package. The semiconductor package of claim 3, wherein the recess is tapered. A method for manufacturing a semiconductor package includes: providing a carrier having a plurality of recesses and a plurality of carriers; and each of the carriers is respectively provided with a package, each of the packages having a plurality of electronic components and covering the electronic components a package material of the component; the package body is embedded in each of the grooves, the electronic component and the package material are located in the groove, and each of the carrier body protrudes from the carrier member and is located in the groove Excluding each of the carriers, exposing each of the packages; and performing a separation process along the grooves and removing the carrier. The method of fabricating a semiconductor package according to claim 7, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface. The method of fabricating a semiconductor package according to claim 7, wherein after removing each of the carriers, each of the electronic components is exposed to the carrier. The method for manufacturing a semiconductor package according to claim 7 is characterized in that after removing each of the carriers, a line redistribution structure is formed on each of the packages, and the line redistribution structure is electrically connected to the package. Electronic component. The method for manufacturing a semiconductor package according to claim 7 is further included in the singulation process after performing the separation process. A method of manufacturing a semiconductor package, comprising: providing a carrier having a plurality of grooves and a plurality of carriers, each of the carriers having a first side and a second side opposite to each other, and the first side has an area larger than the second a plurality of electronic components are disposed on the first side of the carrier; the carrier is placed in each of the recesses corresponding to the second side thereof, so that the electronic components protrude from the carrier Upper and only outside the groove; forming a packaging material on the carrier to cover the electronic components to form a plurality of packages on each of the carriers; removing each of the carrier and the carrier; The separation process is performed according to each of the packages. The method of fabricating a semiconductor package according to claim 12, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface. The method of fabricating a semiconductor package according to claim 12, wherein each of the grooves has a shape corresponding to a shape of the carrier. The method of manufacturing a semiconductor package as described in claim 12, And comprising, before removing each of the carrier and the carrier, a support member is disposed on the package. The method for manufacturing a semiconductor package according to claim 15 is further included after the separation process is performed, and the support member is removed. The method for manufacturing a semiconductor package according to claim 15 further comprises removing the support member and performing the separation process. The method for manufacturing a semiconductor package according to claim 12, further comprising: after removing each of the carrier and the carrier, forming a line redistribution structure on the package, and the circuit is re-wired. Sexually connect the electronic component. The method for manufacturing a semiconductor package according to claim 12, further comprising performing a singulation process after performing the separation process.