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TWI421995B - 半導體封裝結構及其製法 - Google Patents

半導體封裝結構及其製法 Download PDF

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TWI421995B
TWI421995B TW100114747A TW100114747A TWI421995B TW I421995 B TWI421995 B TW I421995B TW 100114747 A TW100114747 A TW 100114747A TW 100114747 A TW100114747 A TW 100114747A TW I421995 B TWI421995 B TW I421995B
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Taiwan
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layer
metal
package structure
semiconductor package
semiconductor
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TW100114747A
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TW201244033A (en
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Tzyy Jang Tseng
Dyi Chung Hu
Yu Shan Hu
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Unimicron Technology Corp
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Priority to TW100114747A priority Critical patent/TWI421995B/zh
Priority to US13/456,660 priority patent/US8624366B2/en
Publication of TW201244033A publication Critical patent/TW201244033A/zh
Priority to US14/095,144 priority patent/US9111948B2/en
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Publication of TWI421995B publication Critical patent/TWI421995B/zh

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Description

半導體封裝結構及其製法
　　本發明係有關一種半導體封裝結構及其製法，尤指一種具薄化優勢的半導體封裝結構及其製法。
　　隨著電子產業的蓬勃發展，電子產品在型態上趨於輕薄短小，而在規格上仍需符合美國電子工程設計發展協會 (Joint Electronic Device Engineering Council，簡稱JEDEC)規範，故封裝方式相當重要。例如隨機記憶體（Dynamic Random Access Memory, 簡稱DRAM）之晶片因朝40奈米（nm）以下發展，其晶片尺寸越來越小，但封裝後的面積仍需相同，使封裝結構之用以接置電路板（PCB）之焊球間距（ball pitch）維持在0.8公釐（mm），以符合JEDEC的標準，因而擴散型（fan-out）晶圓尺寸封裝是可採用的封裝方法之一。又其中，第三代雙倍資料率同步動態隨機存取記憶體（Double-Data-Rate Three Synchronous Dynamic Random Access Memory，簡稱DDR3 SDRAM）是一種目前最新的電腦記憶體規格，其常用之封裝方式係為開窗型球柵陣列(Window BGA)。
　　請參閱第1圖，係為習知開窗型球柵陣列之半導體封裝結構之剖視圖；如圖所示，習知開窗型球柵陣列之半導體封裝結構係包含封裝基板10與半導體晶片11，其中該封裝基板10係具有至少一貫穿之開口100，而該半導體晶片11具有相對之作用面11a與非作用面11b，該作用面11a上具有複數電極墊111，且該半導體晶片11以其作用面11a接置於該封裝基板10之一表面，並封住該封裝基板10之開口100一端，然後藉由打線連接(wire bonding)技術將複數金線12穿過該開口100，使該半導體晶片11之電極墊111電性連接至該封裝基板10另一表面之電性接觸墊13，並形成包覆該金線12的第一封裝材料14，且於該封裝基板10之表面上形成包覆該半導體晶片11的第二封裝材料15，最後，於該封裝基板10上的其餘電性接觸墊13上接置有焊球16，其中，該封裝結構之整體高度（含焊球16）係為1.1至1.2公釐。
　　惟，於前述半導體封裝結構中，該半導體晶片11之電極墊111係藉由該金線12穿過該開口100以電性連接至該封裝基板10另一表面之電性接觸墊13，該金線12之長度較長而影響訊號傳輸效率；且由於近期國際黃金價格居高不下，使得應用金線12的封裝件的成本大幅上升；除此之外，該半導體晶片11係接置於該封裝基板10之開口100一端，並以該第一封裝材料14與第二封裝材料15覆蓋該金線12及半導體晶片11，使得該半導體晶片11的散熱不易，且整體封裝件的厚度較大，不利於應用於可攜式電子產品中。
　　因此，如何提出一種半導體封裝結構及其製法，以避免習知開窗型球柵陣列之半導體封裝結構的散熱性不佳、電性傳輸效率太低、與整體封裝厚度過大，導致產品可靠度不佳或產品應用範圍受限等問題，實已成為目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明之主要目的係提供一種可靠度較高且厚度較薄的半導體封裝結構及其製法。
　　為達上述及其他目的，本發明揭露一種半導體封裝結構，係包括：半導體晶片，係具有相對之作用面與非作用面、形成於該作用面上之複數電極墊、及形成於各該電極墊上之金屬凸塊，該金屬凸塊係用以對外電性連接；封裝材料層，係包覆該半導體晶片，並外露該作用面；介電層，係設於該作用面與封裝材料層上，且具有複數外露各該金屬凸塊的佈線圖案開口區；線路層，係設於各該佈線圖案開口區中，且電性連接該金屬凸塊，該線路層藉由該封裝材料層與介電層而延伸至面積比該作用面大的範圍，以有效將電性連接點向外扇出（fan out）；絕緣保護層，係設於該介電層與線路層上，且具有複數絕緣保護層開孔，以外露部分該線路層；以及金屬箔，係設於該封裝材料層上，且該金屬箔之一表面上具有複數金屬柱，各該金屬柱貫穿該封裝材料層以延伸至該半導體晶片之非作用面，以使該半導體晶片所產生的熱傳遞至環境中。
　　本發明復揭露一種半導體封裝結構之製法，係包括：提供一承載板，其一表面上具有第一黏著層；提供複數半導體晶片，各該半導體晶片具有相對之作用面與非作用面及形成於該作用面上之複數電極墊，各該電極墊上設有金屬凸塊，該金屬凸塊係用以對外電性連接；將該等半導體晶片以其具有該金屬凸塊之側接置於該第一黏著層上；於該第一黏著層上形成包覆該等半導體晶片的封裝材料層；將一表面具有複數金屬柱之金屬箔以其具有該等金屬柱之側接置於該封裝材料層上，並使各該金屬柱貫穿該封裝材料層以連接至各該半導體晶片之非作用面，藉以將該半導體晶片的熱能經由該金屬柱與金屬箔傳導至外界；移除該承載板與第一黏著層；於該封裝材料層與半導體晶片上形成介電層，該介電層具有複數外露各該金屬凸塊的佈線圖案開口區；於各該佈線圖案開口區中形成電性連接該金屬凸塊的線路層，該線路層藉由該封裝材料層與介電層而延伸至面積比該作用面大的範圍；於該介電層與線路層上形成絕緣保護層，該絕緣保護層具有複數絕緣保護層開孔，以外露部分該線路層；移除部分該金屬箔，以形成金屬箔溝槽，俾使各該半導體晶片上的該金屬箔彼此互不相連；以及沿著該金屬箔溝槽切割該封裝材料層、介電層與絕緣保護層，以形成複數半導體封裝結構。
　　由上可知，因為本發明之半導體封裝結構僅以介電層構成半導體封裝結構的本體，且不需使用習知技術之金線作電性傳導路徑，所以整體厚度較薄；再者，本發明係以金屬柱延伸至半導體晶片之非作用面，而可直接將熱量傳導至大面積之金屬箔，有助於整體封裝件的散熱；最後，本發明不需使用導通路徑較長之金線來傳輸電訊號，故能達到較佳之電性傳輸效率，進而提升最終產品的可靠度，且同時也能節省採購金線之高額材料成本。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　大體說來，本發明之實施可分成三個階段，首先，製備複數半導體晶片，請參閱第2A至2C圖，係本發明之半導體封裝結構之半導體晶片及其製法的剖視圖。
　　如第2A圖所示，提供一具有相對之作用面20a與非作用面20b的半導體晶圓20、及形成於該作用面20a上之複數電極墊21與緩衝層22。
　　如第2B圖所示，於各該電極墊21上形成金屬凸塊23。
　　如第2C圖所示，自該非作用面20b薄化該半導體晶圓20，並切割該半導體晶圓20以得到複數半導體晶片20’，各該半導體晶片20’具有相對之作用面20a’與非作用面20b’、及形成於該作用面20a’上之複數電極墊21與緩衝層22，且各該電極墊21上設有金屬凸塊23。
　　其次，製備一金屬箔，請參閱第3A至3D圖，係本發明之半導體封裝結構之金屬箔及其製法的剖視圖。
　　如第3A圖所示，提供一金屬板30，該金屬板30之材質可為銅。
　　如第3B圖所示，於該金屬板30上形成具有圖案化開口區310的阻層31，且部分該金屬板30外露於該圖案化開口區310。
　　如第3C圖所示，對該圖案化開口區310中的金屬板30進行蝕刻，而形成金屬箔30’與其上的複數金屬柱301。
　　如第3D圖所示，移除該阻層31。
　　最後，進行組合與封裝作業，請參閱第4A至4K圖，係本發明之半導體封裝結構及其製法的剖視圖。
　　如第4A圖所示，提供一承載板40，其一表面上依序具有第二黏著層411、塑膠膜410、與第一黏著層412，該第二黏著層411、塑膠膜410、與第一黏著層412可先構成雙面膠層41，再將該雙面膠層41貼附於該承載板40上。
　　如第4B圖所示，將該等半導體晶片20’以其具有該金屬凸塊23之側接置於該第一黏著層412上。
　　如第4C圖所示，於該第一黏著層412上形成包覆該等半導體晶片20’的封裝材料層42。
　　如第4D圖所示，將該金屬箔30’以其具有該等金屬柱301之側接置於該封裝材料層42上，並使各該金屬柱301貫穿該封裝材料層42以連接至各該半導體晶片20’之非作用面20b’；要注意的是，本發明之金屬柱301並非一定要接觸該非作用面20b’始能發生作用，即使該金屬柱301距離該非作用面20b’有50至300微米，仍能發揮該金屬柱301導熱之目的，而屬於本發明的權利範圍。
　　如第4E圖所示，移除該承載板40與雙面膠層41。
　　如第4F圖所示，於該封裝材料層42與半導體晶片20’上形成介電層43，該介電層43具有複數外露各該金屬凸塊23的佈線圖案開口區430。
　　如第4G圖所示，於各該佈線圖案開口區430中形成電性連接該金屬凸塊23的線路層44。
　　如第4H圖所示，於該介電層43與線路層44上形成絕緣保護層45，該絕緣保護層45具有複數絕緣保護層開孔450，以外露部分該線路層44；並於該金屬箔30’上形成具有覆蓋層溝槽470之覆蓋層47，且部分該金屬箔30’係外露於該覆蓋層溝槽470，該覆蓋層47之材質可為絕緣材料或金屬材料。
　　如第4I圖所示，移除該覆蓋層溝槽470中的該金屬箔30’，以形成金屬箔溝槽300’，俾使各該半導體晶片20’上的該金屬箔30’彼此互不相連。
　　如第4J圖所示，於各該絕緣保護層開孔450中的線路層44上形成焊球46。
　　如第4K圖所示，沿著該金屬箔溝槽300’切割該封裝材料層42、介電層43與絕緣保護層45，以形成複數半導體封裝結構4。
　　本實施例復揭露一種半導體封裝結構，係包括：半導體晶片20’，係具有相對之作用面20a’與非作用面20b’、形成於該作用面20a’上之複數電極墊21、及形成於各該電極墊21上之金屬凸塊23；封裝材料層42，係包覆該半導體晶片20’，並外露該作用面20a’；介電層43，係設於該作用面20a’ 與封裝材料層42上，且具有複數外露各該金屬凸塊23的佈線圖案開口區430；線路層44，係設於各該佈線圖案開口區430中，且電性連接該金屬凸塊23，該線路層44藉由該封裝材料層42與介電層43而延伸至面積比該作用面20a’大的範圍；絕緣保護層45，係設於該介電層43與線路層44上，且具有複數絕緣保護層開孔450，以外露部分該線路層44；以及金屬箔30’，係設於該封裝材料層42上，且該金屬箔30’之一表面上具有複數金屬柱301，各該金屬柱301貫穿該封裝材料層42以延伸至該半導體晶片20’之非作用面20b’，以使該半導體晶片20’所產生的熱傳遞至環境中。
　　於上述之半導體封裝結構中，復可包括覆蓋層47，係設於該金屬箔30’的頂面上，且該覆蓋層47之材質可為絕緣材料或金屬材料。
　　本實施例之半導體封裝結構中，復可包括焊球46，係設於各該絕緣保護層開孔450中的線路層44上。
　　依上所述之半導體封裝結構，復可具有緩衝層22，係形成於該作用面20a上。
　　綜上所述，不同於習知技術，由於本發明僅以介電層構成半導體封裝結構的本體，且不需使用習知技術之金線作電性傳導路徑，因此能有效縮減最終之整體厚度；再者，本發明係以金屬柱延伸至半導體晶片之非作用面，而可直接將熱量傳導至大面積之金屬箔，有助於整體封裝件的散熱；最後，本發明不使用金線來傳輸電訊號，故能達到較佳之電性傳輸效率，進而提升最終產品的可靠度，且同時也省下金線之高額材料成本。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10‧‧‧封裝基板
100‧‧‧開口
11,20’‧‧‧半導體晶片
11a,20a,20a’‧‧‧作用面
11b,20b,20b’‧‧‧非作用面
111,21‧‧‧電極墊
12‧‧‧金線
13‧‧‧電性接觸墊
14‧‧‧第一封裝材料
15‧‧‧第二封裝材料
16‧‧‧焊球
20‧‧‧半導體晶圓
22‧‧‧緩衝層
23‧‧‧金屬凸塊
30‧‧‧金屬板
31‧‧‧阻層
310‧‧‧圖案化開口區
30’‧‧‧金屬箔
300’‧‧‧金屬箔溝槽
301‧‧‧金屬柱
40‧‧‧承載板
41‧‧‧雙面膠層
410‧‧‧塑膠膜
412‧‧‧第一黏著層
411‧‧‧第二黏著層
42‧‧‧封裝材料層
43‧‧‧介電層
430‧‧‧佈線圖案開口區
44‧‧‧線路層
45‧‧‧絕緣保護層
450‧‧‧絕緣保護層開孔
46‧‧‧焊球
47‧‧‧覆蓋層
470‧‧‧覆蓋層溝槽
4‧‧‧半導體封裝結構
　　第1圖係為習知開窗型球柵陣列之半導體封裝結構之剖視圖；
　　第2A至2C圖係本發明之半導體封裝結構之半導體晶片及其製法的剖視圖；
　　第3A至3D圖係本發明之半導體封裝結構之金屬箔及其製法的剖視圖；以及
　　第4A至4K圖係本發明之半導體封裝結構及其製法的剖視圖。
20’‧‧‧半導體晶片
20a’‧‧‧作用面
20b’‧‧‧非作用面
21‧‧‧電極墊
22‧‧‧緩衝層
23‧‧‧金屬凸塊
30’‧‧‧金屬箔
300’‧‧‧金屬箔溝槽
301‧‧‧金屬柱
42‧‧‧封裝材料層
43‧‧‧介電層
430‧‧‧佈線圖案開口區
44‧‧‧線路層
45‧‧‧絕緣保護層
450‧‧‧絕緣保護層開孔
46‧‧‧焊球
47‧‧‧覆蓋層
470‧‧‧覆蓋層溝槽
4‧‧‧半導體封裝結構

Claims (13)

  1. 一種半導體封裝結構，係包括：
    　　半導體晶片，係具有：相對之作用面與非作用面、形成於該作用面上之複數電極墊、及形成於各該電極墊上之金屬凸塊；
    　　封裝材料層，係包覆該半導體晶片，並外露該作用面；
    　　介電層，係設於該作用面與封裝材料層上，且具有複數外露各該金屬凸塊的佈線圖案開口區；
    　　線路層，係設於各該佈線圖案開口區中，且電性連接該金屬凸塊，該線路層藉由該封裝材料層與介電層而延伸至面積比該作用面大的範圍；
    　　絕緣保護層，係設於該介電層與線路層上，且具有複數絕緣保護層開孔，以外露部分該線路層；以及
    　　金屬箔，係設於該封裝材料層上，且該金屬箔之一表面上具有複數金屬柱，各該金屬柱貫穿該封裝材料層以延伸至該半導體晶片之非作用面，以使該半導體晶片所產生的熱傳遞至環境中。
  2. 如申請專利範圍第1項所述之半導體封裝結構，復包括覆蓋層，係設於該金屬箔的頂面上。
  3. 如申請專利範圍第2項所述之半導體封裝結構，其中，該覆蓋層之材質係絕緣材料或金屬材料。
  4. 如申請專利範圍第1項所述之半導體封裝結構，復包括焊球，係設於各該絕緣保護層開孔中的線路層上。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中，復具有緩衝層，係形成於該作用面上。
  6. 一種半導體封裝結構之製法，係包括：
    　　提供一承載板，其一表面上具有第一黏著層；
    　　提供複數半導體晶片，各該半導體晶片具有相對之作用面與非作用面及形成於該作用面上之複數電極墊，各該電極墊上設有金屬凸塊；
    　　將該等半導體晶片以其具有該金屬凸塊之側接置於該第一黏著層上；
    　　於該第一黏著層上形成包覆該等半導體晶片的封裝材料層；
    　　將一表面具有複數金屬柱之金屬箔以其具有該等金屬柱之側接置於該封裝材料層上，並使各該金屬柱貫穿該封裝材料層以連接至各該半導體晶片之非作用面；
    　　移除該承載板與第一黏著層；
    　　於該封裝材料層與半導體晶片上形成介電層，該介電層具有複數外露各該金屬凸塊的佈線圖案開口區；
    　　於各該佈線圖案開口區中形成電性連接該金屬凸塊的線路層；
    　　於該介電層與線路層上形成絕緣保護層，該絕緣保護層具有複數絕緣保護層開孔，以外露部分該線路層；
    　　移除部分該金屬箔，以形成金屬箔溝槽，俾使各該半導體晶片上的該金屬箔彼此互不相連；以及
    　　沿著該金屬箔溝槽切割該封裝材料層、介電層與絕緣保護層，以形成複數半導體封裝結構。
  7. 如申請專利範圍第6項所述之半導體封裝結構之製法，其中，於移除該承載板與第一黏著層之後，復包括於該金屬箔上形成具有覆蓋層溝槽之覆蓋層，且部分該金屬箔係外露於該覆蓋層溝槽。
  8. 如申請專利範圍第7項所述之半導體封裝結構之製法，其中，該覆蓋層之材質係絕緣材料或金屬材料。
  9. 如申請專利範圍第6項所述之半導體封裝結構之製法，於切割成該等半導體封裝結構之前，復包括於各該絕緣保護層開孔中的線路層上形成焊球。
  10. 如申請專利範圍第6項所述之半導體封裝結構之製法，其中，該作用面上復具有緩衝層。
  11. 如申請專利範圍第6項所述之半導體封裝結構之製法，其中，該第一黏著層與該承載板之間復設有塑膠膜與第二黏著層，該塑膠膜係設於該第一黏著層與該第二黏著層之間，且該第二黏著層係設於該塑膠膜與該承載板之間，且移除該第一黏著層之步驟復包括移除該塑膠膜與第二黏著層。
  12. 如申請專利範圍第6項所述之半導體封裝結構之製法，其中，該等半導體晶片之形成步驟係包括：
    　　提供一具有相對之作用面與非作用面的半導體晶圓及形成於該作用面上之複數電極墊；
    　　於各該電極墊上形成金屬凸塊；
    　　自該非作用面薄化該半導體晶圓；以及
    　　切割該半導體晶圓以得到該等半導體晶片。
  13. 如申請專利範圍第6項所述之半導體封裝結構之製法，其中，該金屬箔之形成步驟係包括：
    　　於一金屬板上形成具有圖案化開口區的阻層，且部分該金屬板外露於該圖案化開口區；
    　　對該圖案化開口區中的金屬板進行蝕刻，而形成該金屬箔與其上的該等金屬柱；以及
    　　移除該阻層。
TW100114747A 2011-04-27 2011-04-27 半導體封裝結構及其製法 TWI421995B (zh)

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