TWI415219B - Method of forming via interconnects for 3-d wafer/chip stacking - Google Patents

Abstract

The present invention provides a method of forming via interconnects in a silicon wafer comprising: forming a mask on a substrate; performing an etching step on the mask to form an opening; etching the substrate at the opening to form a via interconnect, the via interconnect has a sidewall, a bottom, and a depth; performing a chemical vapor deposition step with sulfur hexafluoride and oxygen for depositing a insulating oxide layer, the insulating oxide layer covers the sidewall and the bottom of the via interconnect and the mask; performing an ion bombardment gas etching step to etch the insulating oxide layer covered on the bottom of the via interconnect with a ion bombardment gas, the ion bombardment gas comprises at least one of the argon, boron, helium, nitrogen, and fluorocarbon; and performing a physical vapor deposition step to form a conductive material layer, the conductive material layer covers the sidewall and the bottom of the via interconnect and the mask.

Description

Method for forming perforated wiring for 3-D wafer/wafer stack

The present invention relates to deep etching features into a substrate material to form a through silicon vias (TSV) and to remove redundant steps to save the cost of the 3D integrated circuit board process steps. The field of wiring, especially in the manufacturing industry, including semiconductors, micro-motor systems, packaging, solar cells (photovoltaic, PV), automotive, aerospace, electronics, chemistry, and research/development, even though the invention is Can be applied to any other related industry.

矽Through electrodes and 3D wafer/wafer stacking technology are considered to be the necessary technologies for next-generation high-priced semiconductors such as high-speed microprocessors and high-speed memories. “The complexity of the minimum component cost can be doubled every year,” says Moore’s law and the most influential driver in the microelectronics industry. This law emphasizes the lithography resolution and integration (in-plane) overall functionality on a single wafer, possibly through a system-on-chip (SOC). On the other hand, the integration of the overall functionality can be achieved through system-in-package (SIP) or ultimately through 3D integration. However, the application of perforated electrodes to package or semiconductor applications is costly and has not yet been of value for manufacturing implementation.

Various methods, systems, and devices relating to the present invention are disclosed in the following U.S. patents:

From a technical standpoint, the via process can be applied to the "first through" process and the "post through" process, and eliminates the need for a high temperature oxide deposition step during via isolation filling. From the point of view of the semiconductor/micro-motor system process, the "first-perforation" approach is suitable for most situations, and in some cases to minimize additional wafer-level post-processing and processing. For the packaging industry, the "post-perforation" approach is used to open via interconnects on the backside of the wafer after the wafer thickness is less than 200 microns (μm).

Stacking several semiconductor dies in a single package, using stereo (3D) wiring to provide a way to increase density and micro-mechanical device performance. For example, several flash memory dies can be stacked to increase the memory available in a single package. In another example, a plurality of DRAM cell lines are typically less than 200 microns, and the wiring between the dies is typically less than 50 microns, and the thickness of the plurality of stacked grains is typically less than 5 mm (mm). In addition to increasing the packing density, stacked dies have other advantages, including: reduced power consumption, increased bandwidth, and better performance.

The applicant has developed a unique through-electrode (TSV) process that eliminates the need for post-etch cleaning and etched via holes with insulating oxide. The insulating oxide is used to electrically isolate a perforation wire from the remaining perforation wires and avoid short circuit or cross talk of the associated integrated circuit structure. The cleaning of the perforation of the current dry etching and the filling of the insulating oxide are performed by the "perforation" and the "post-perforation".

The insulating oxide in the "first perforation" mode is typically 1,000 angstroms ( The insulating oxide in the "post-perforation" mode is typically 10,000 angstroms. The present invention utilizes a unique dry etching process to form deep via interconnects while forming a passivation layer for electrically isolating a silicon oxide sidewall. The yttria passivation layer may be further strengthened with nitrogen or by increasing the concentration of oxygen in the plasma reactor during etching to form a composite of an insulating oxide layer of a desired thickness and silicon nitride. After the formation of the perforations, in the "first perforation" and "post perforation" applications, a conductive material such as copper may be used to electrically connect the subsequent circuitry.

The present invention is a method for forming a tantalum through electrode, including deep perforation, to remove an additional deposited insulating oxide layer for electrical isolation. In addition, in some cases, cleaning may be performed after the perforated dry etch holes that may be problematic when the wafer is bonded to the handle substrate.

According to the present invention, a new method structure for fabricating a tantalum through electrode is provided. The method utilizes a wafer, dielectric deposition, photolithography, dielectric etching, and an electrochemical process to etch the germanium. In some cases, the dielectric layer is removed by the hard masking step of etching the germanium substrate with the puncturing feature and the use of other materials such as photoresist or dry film. In order to stack a plurality of dies into a 3D composition, electrical connections are required to transfer electrical signals vertically between the dies. These vertical connections across the wafer are generally considered to be 3D connections. A three-dimensional (3D) connection connects a plurality of dies (or wafers) using vertical wiring that traverses the die and the bond pads from the upper surface of one die to the lower surface of the other die. Vertical wiring through the die is typically created using a process that includes the formation of a via electrode or TSVs, and an insulating oxide layer that is subsequently accompanied by a conductive fill material of the TSVs.

A method of forming a tantalum through electrode in a wafer is disclosed herein, while eliminating expensive process steps and making the cost of the tantalum through-electrode process affordable.

The invention includes etching using an electrochemical process for perforation, removal of the via after the via, and removal of the insulating oxide layer. This allows the product to be moved directly from the perforation formation of the perforation process to the conductive fill step.

Figure 1 shows the standard 矽 through-electrode process flow for forming a perforated connection:

1) Step 1, etching - forming an opening in the mask by punching;

2) Step 2, etching-etching the substrate depth to form a perforation connection;

3) Step 3, chemical vapor deposition (CVD) - depositing an insulating oxide layer to electrically isolate the vias from the remaining integrated circuits;

4) Step 4, etching - removing the insulating oxide layer at the bottom of the via to facilitate electrical connection to subsequent circuitry;

5) Step 5, Physical Vapor Deposition (PVD) - filling the formed perforation wires with a conductive material to facilitate current flow through the substrate.

In step 1 of Figure 1, a mask is formed to insulate the substrate material 104 of Figure 2 from subsequent via depth etch chemistry and to define the via size. The material of the mask may use a material of a solid nature, such as an oxide for the mask, which etch chemistry to open the perforation size. Liquid materials such as photoresist, rather than oxides, can be used for masking, hardening after application to a substrate, and through basic lithography techniques to form openings. This step does not require an etching step. The mask is indicated by 101 in Fig. 2.

In step 2 of Fig. 1, the mixed gas 102 of sulfur hexafluoride and oxygen shown in Fig. 2 is used to etch the perforation size to a desired depth. Sometimes, the presence of argon is to make the etch directional. One of the key features of the present invention is that a deep etch is used in the etching process to form an insulating oxide layer 103. As shown in FIG. 2, the insulating oxide layer 103 can be used for through-electrode insulating oxide layers for through-electrode applications. In some cases, the insulating oxide layer 103 may be chemically assisted by other gases, such as nitrogen, to create a thickness between 500 angstroms and 20,000 angstroms. This thickness creates the insulation required for the perforation wiring for the application of "first perforation" and "post perforation".

In the plasma etching reactor, the etching gas chemistry is introduced into the plasma etching reaction chamber from the gas inlet. For example, a substrate of the wafer is introduced onto the cooling chuck before the introduction of the gas, and a radio frequency power source is applied to the etching reactor. In general, a plasma etch reactor interacts with two supply sources. A supply power source is used to dissociate gas molecules into free radicals. This supply power source is called the source power supply. Another supply power source is typically located at the bottom of the plasma etch chamber and applied to the platform in which the wafer is placed in the plasma etch chamber. This supply power directs free radicals to the wafer and is referred to as a bias supply.

In one embodiment, the source power source is between 300 watts (W) and about 6,000 watts, preferably between 1000 watts and 5,000 watts, and more preferably 4,500 watts (see Table 1 below). Parameters B, C and D). In one embodiment, the bias power source is generally lower than the source power source and may be between 10 watts and about 2000 watts, preferably between 30 watts and 1700 watts, more preferably 1500 watts (see parameters B, C, and D in [Table 1] below). In one embodiment, helium is typically induced to cool between the wafer and the wafer platform. The temperature of the wafer platform is controlled at room temperature, between about 0 ° C and about 70 ° C, preferably between about 15 ° C and about 60 ° C, more preferably 20 ° C (see below). The parameters A, B, C and D) in one]. In one embodiment, during plasma etching, the pressure in the plasma reaction chamber is preferably from 10 mTorr to 110 mTorr, preferably from 30 mTorr to 90 mTorr, more preferably 45 mTorr (see parameters B, C and D in [Table 1] below).

Plasma etching occurs after all of the conditions of the plasma etch reactor (pressure, temperature, power, gas flow) are met. As with the parameters A, B, C and D listed in [Table 1] below, the combination of gas ratios and changes in the conditions of the plasma etching reactor are used to achieve the requirements of the material to be etched. The etching chemistry is generally anisotropic and the etching depth is performed at a high speed, generally greater than 5 micrometers per minute (μm/minute). In addition, parameters A, B, and C listed in [Table 1] below. And D, nitrogen may be added to the etch chemistry along with the fluorocarbon gas to strengthen the insulating perforated sidewalls.

The following [Table 1] is an example of the process parameters for the oxidized insulating layer and the argon/boron associated with opening the bottom of the insulating oxide sleeve during the perforation etching in the plasma reactor.

As shown in FIG. 2, since the insulating oxide layer is formed during the germanium etching for the sidewall passivation layer, uniform distribution of the insulating oxide layer 103 is achieved. In some cases, it is not necessary because of the ionic bonding of the oxide and the use of a polymer gas (such as fluorocarbon (C _x F _x ) or hydrogen bromide (HBr)) in step 2 of Figure 1. Then etch clean. Sometimes, using polymer gas to assist in feature size control requires post-etch cleaning.

In an ion strike gas etching step, an ion bombardment gas, such as argon, may be applied to the same plasma reactor to open the front side of the insulating oxide layer directly after the deep etching of the via. The plasma reactor includes a reaction chamber. As shown in Fig. 3, fluorine and oxygen process gases can be removed after the formation of the perforations to facilitate sputtering of the bottom 201 (sleeve) of the oxide insulating layer, using, for example, argon or a boron-containing gas. The ions strike the gas for electrical connection. If the perforation connection application requires the opening of the bottom of the insulating oxide layer, this unique technique removes step 4 of Figure 1.

After performing the post-etch cleaning, if a polymer gas is used to form the via depth, as shown in step 5 of FIG. 1, the conductive material layer covering the via line can be immediately etched/cleaned after the via wiring. occur.

The unique integrated via forming process removes step 2 of FIG. 1 and then etch cleans, depositing an insulating oxide layer in the via hole as shown in step 3 of FIG. 1 and removing step 4 as shown in FIG. The oxidation sleeve bottom etching step is opened. The complete integrated perforation wiring procedure of the present invention is shown in Figure 4, with the masked substrate passing through a perforation depth step directly to the formation of a layer of electrically conductive material on the perforation line. After the formation of the conductive material layer, the "post-perforation forming process" can be used to electrically connect to the subsequent integrated circuit, which is not described in the present invention.

The foregoing is a description of the preferred embodiments of the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. Changes and modifications are to be covered in the scope defined by the scope of the patent application below.

101. . . Mask

102. . . mixed composition

103. . . Insulating oxide layer

104. . .矽 substrate

201. . . bottom

In order to further understand the nature, purpose and advantages of the present invention, the accompanying drawings, wherein the approximation of the component symbols represent the approximation elements, are clearly illustrated in the following description, in which: Figure 1 shows the standard 矽through electrode process flow and related a box step of displaying five process blocks to form an associated via electrode after the filling process; FIG. 2 shows the use of fluorine chemistry to react with the germanium substrate for hole etching and a mask to protect the upper surface of the germanium substrate Avoid etching by fluorine. Oxygen also forms a yttrium oxide passivation layer on the surface of the etched tantalum in response to ruthenium. Figure 3 shows the newly formed etched vias using an ionic ion such as argon to remove the bottom of the yttrium oxide passivation layer. Additional chemical reactions; and Figure 4 shows the integration of more than 50% of the required process steps compared to the standard process flow shown in Figure 1, through-electrode process flow, first process steps to etch perforations and form insulation The oxide layer is then introduced into the perforated conductive material filling process.

Claims (8)

A method for forming a via line in a germanium wafer includes: forming a mask on a substrate; performing an etching step to form an opening in the mask; etching the substrate at the opening to form a a perforation connection having a sidewall, a bottom, and a depth; performing a chemical vapor deposition step of depositing an insulating oxide layer using the sulfur hexafluoride and oxygen, the insulating oxide layer covering the perforation Performing an ion impact gas etching step on the sidewall of the line, the bottom portion, and the mask, and etching the insulating oxide layer on the bottom of the via wiring by an ion impact gas, the ion impact gas including argon, boron, At least one of niobium, nitrogen, and fluorocarbon; and performing a physical vapor deposition step to form a layer of electrically conductive material overlying the sidewall of the perforation line, the bottom, and the mask . The method of claim 1, wherein the oxidized insulating layer has a thickness of from 500 angstroms to 20,000 angstroms. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 10 mTorr to 110 mTorr The source power supply is 300 watts to 6000 watts, the bias power supply is 10 watts to 2000 watts, and the wafer platform temperature is 0 ° C to 70 ° C; the sulphur hexafluoride is 50 standard cubic centimeters per minute to 500 standard cubic centimeters per minute. And the oxygen is 10 standard cubic centimeters per minute to 300 standard cubic centimeters per minute; and the argon and boron are 50 standard cubic centimeters per minute to 500 standard cubic centimeters per minute, and the crucible is 100 standard cubic centimeters per minute to every minute. 400 standard cubic centimeters, the nitrogen is 5 standard cubic centimeters per minute to 200 standard cubic centimeters per minute and the fluorocarbon is 5 standard cubic centimeters per minute to 200 standard cubic centimeters per minute. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 30 mTorr to 90 mTorr. The source power is 1000 watts to 5000 watts, the bias power supply is 30 watts to 1700 watts, and the wafer platform temperature is 15 ° C to 60 ° C; the sulphur hexafluoride is 75 standard cubic centimeters per minute to 400 standard cubic centimeters per minute. And the oxygen is 20 standard cubic centimeters per minute to 200 standard cubic centimeters per minute; and the argon and boron are 100 standard cubic centimeters per minute to 400 standard cubic centimeters per minute, and the crucible is 150 standard cubic centimeters per minute to every minute. 250 standard cubic centimeters, the nitrogen is 10 standard cubic centimeters per minute to 100 standard cubic centimeters per minute and the fluorocarbon is 10 standard cubic centimeters per minute to 100 standard cubic centimeters per minute. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 60 mTorr and a source power source. 1000 watts, a bias power supply of 25 watts and a wafer platform temperature of 20 ° C; the sulphur hexafluoride is 45 standard cubic centimeters per minute and the oxygen is 35 standard cubic centimeters per minute; and the argon and boron are 200 per minute. The standard cubic centimeter and the crucible are 200 standard cubic centimeters per minute. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 45 mTorr and a source power source. 4500 watts, a bias power supply of 1500 watts and a wafer platform temperature of 20 ° C; the sulfur hexafluoride is 300 standard cubic centimeters per minute and the oxygen is 75 standard cubic centimeters per minute; and the argon and boron are 200 per minute. Standard cubic centimeters. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 45 mTorr and a source power source. 4500 watts, a bias power supply of 1500 watts and a wafer platform temperature of 20 ° C; the sulphur hexafluoride is 300 standard cubic centimeters per minute and the oxygen is 100 standard cubic centimeters per minute; and the argon and boron are 200 per minute. The standard cubic centimeter and the nitrogen are 10 standard cubic centimeters per minute. The method of claim 1, wherein the chemical vapor deposition step and the ion impact gas etching step are performed in a reaction chamber having a reaction chamber pressure of 45 mTorr and a source power source. 4500 watts, a bias power supply of 1500 watts and a wafer platform temperature of 20 ° C; the sulphur hexafluoride is 300 standard cubic centimeters per minute and the oxygen is 100 standard cubic centimeters per minute; and the argon and boron are 200 per minute. The standard cubic centimeter and the fluorocarbon are 35 standard cubic centimeters per minute.