TWI408642B - Display, pixel circuitry and operating method of pixel circuitry - Google Patents

Abstract

A display, a pixel circuitry and an operating method of the pixel circuitry are provided. The display includes a source driver and a pixel circuitry. The source driver converts a first pixel data to a first polar data voltage and a second polar data voltage in a first frame period and converts a second pixel data to a third polar data voltage and a fourth polar data voltage in a second frame period. The pixel circuitry is coupled to the source driver. The pixel circuitry stores the first polar data voltage and the second polar data voltage in the first frame period, displays the first polar data voltage and the second polar data voltage in a first sub-period and a second sub-period of the second frame period respectively, and stores the third polar data voltage and the fourth polar data voltage in the second frame period.

Description

Display device, pixel circuit, and operation method of pixel circuit

The present invention relates to a display technology, and more particularly to a display device, a pixel circuit, and a method of operating a pixel circuit.

Flat panel displays, such as liquid crystal displays (LCDs), liquid crystal on silicon (LCOS) displays, etc., which have high image quality, small size, light weight, low driving voltage, low power consumption, etc. Advantages, so it is widely used in consumer communication or electronic products such as video recorders, personal digital assistants (PDAs), mobile phones, notebook computers, desktop computer display screens and thin digital TVs. Gradually replace the cathode ray tube (CRT) and become the mainstream technology of the display.

In general, when a 矽-based liquid crystal display displays a picture at a display frequency of 60 Hz, a flickering phenomenon occurs. In order to reduce the flickering of the screen, the display frequency of the screen is increased to 120 Hz, and the flicker of the screen is suppressed with a higher display frequency. The method of increasing the display frequency may be to repeatedly transmit the same picture data to the source driver during the two picture periods, and the source driver respectively transmits the same picture data to the display panel with different polarities during the two pictures.

1A is a block diagram of a system of a conventional display. Referring to FIG. 1, the display device 100 includes a timing controller (T-con) 110, a source driver 120, and a gate driver (gate). Driver) 130 and a display panel 140. The timing controller 110 outputs the data signal DD to the source driver 120, and the source driver 120 outputs a corresponding output voltage to the display panel 140, wherein the data voltage can be positive or negative. At this time, the gate driver 130 is controlled by the timing controller 110 to turn on the pixel circuit PX of the display panel 140 to receive the data voltage. Next, the pixel circuit PX that drives the display panel 140 is displayed in accordance with the stored data voltage.

FIG. 1B is a timing chart showing driving of the data signal DD and the pixel circuit PX of FIG. 1A. During the data writing period dw1 of the fp1 during the picture period, the data signal DD transmits the picture material F1, wherein the picture material F1 contains the first pixel data D1. At this time, the source driver 120 outputs the positive polarity data voltage D1+ to the pixel circuit PX of the display panel 140 corresponding to the first pixel data D1. In the data blanking period vb1 of the screen period fp1 and the data writing period dw2 of the screen period fp2, the pixel circuit PX is displayed by the gate driver 130 in accordance with the positive polarity data voltage D1+.

During the data writing period dw2 of the fp2 during the picture period, the data signal DD also transmits the picture data F1, and at this time, the source driver 120 outputs the negative polarity data voltage D1 to the pixel circuit of the display panel 140 corresponding to the first pixel data D1. PX. In the vertical blanking period vb2 of the screen period fp2 and the data writing period dw3 of the screen period fp3, the pixel circuit PX is subjected to display by the gate driver 130 in accordance with the negative polarity data voltage D1-.

According to the above, the source driver 120 receives the screen data F1 twice to output a positive polarity data voltage (such as D1+) and a negative polarity data voltage (such as D1-) during different picture periods (such as the picture periods fp1 and fp2). with For example, if the display device 100 is to display the screen data F2 including the second pixel data D2, the data signal DD transmits the secondary image data F2 to the source driver 120 to generate a positive polarity data voltage (such as D2+) and Negative data voltage (such as D2-). Moreover, the pixel circuit PX is also controlled by the gate driver 130 and is displayed according to a positive polarity data voltage (such as D2+) and a negative polarity data voltage (such as D2-) during different periods.

Since the pixel circuit PX of the display 100 can only store one data voltage during one screen period, the positive polarity data voltage and the negative polarity data voltage corresponding to the same pixel data are respectively transmitted to the pixel circuit PX during the adjacent two picture periods. Therefore, while the display 100 increases the display frequency of the screen, the associated data transmission rate of the source driver 120 is increased, and the power consumption of the source driver 120 is correspondingly increased. Moreover, when the data transmission rate is too high, the data signal DD received by the source driver 120 may be distorted. At this time, the pin of the source driver 120 receiving the data signal DD can be increased to reduce the data transmission rate. However, increasing the pin of the source driver 120 receiving the data signal DD not only increases the cost of the hardware configuration, but also the circuit of the source driver 120 must be modified accordingly, thereby increasing the cost of the circuit design.

The invention provides a display device, a pixel circuit and a method for operating the same, wherein the source driver can generate a corresponding first polarity data voltage and a second polarity data voltage according to a pixel data, and the pixel circuit can receive and store the first polarity at the same time. Data voltage and second polarity data voltage.

The invention provides a display device comprising a source driver and a pixel circuit. The source driver converts the first pixel data into the first polarity data voltage and the second polarity data voltage during the first picture, and converts the second pixel data into the third polarity data voltage and the fourth polarity during the second picture Data voltage. The pixel circuit is coupled to the source driver. The pixel circuit stores the first polarity data voltage and the second polarity data voltage during the first picture period, and displays the first polarity data voltage and the second polarity data voltage in the first sub-period and the second sub-period during the second picture period, respectively, and The third polarity data voltage and the fourth polarity data voltage are stored during the second picture period.

The invention further provides a pixel circuit of a display device, comprising a display unit and a storage unit. The storage unit includes a first write switch, a second write switch, a third write switch, a first memory unit, a second memory unit, a third memory unit, and a switching unit. A first end of the first write switch is coupled to the source driver. The first memory unit is coupled to the second end of the first write switch. A first end of the second write switch is coupled to the source driver. The second memory unit is coupled to the second end of the second write switch. A first end of the third write switch is coupled to the source driver. The third memory unit is coupled to the second end of the third write switch. The first input end of the switching unit is coupled to the first memory unit, the second input end of the switching unit is coupled to the second memory unit, the third input end of the switching unit is coupled to the third memory unit, and the output end of the switching unit is coupled To the display unit.

The present invention also provides a method for operating a pixel circuit. The method includes the steps of: storing a first polarity data voltage and a second polarity data voltage of the first pixel data during the first picture; During the sub-period and the second sub-period, the first polarity data voltage and the first The bipolar data voltage is output to the display unit; during the second picture, the third polarity data voltage and the fourth polarity data voltage of the second pixel data are stored.

Based on the above, the display device, the pixel circuit, and the method for operating the same according to the embodiments of the present invention can simultaneously store two data voltages of different polarities corresponding to the same pixel data in a pixel period, and sequentially output the previously stored data. Two different polar data voltages. Thereby, the data transfer rate of the source driver can be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings

2 is a block diagram of a system of a display device in accordance with an embodiment of the present invention. Referring to FIG. 2 , the display device 200 includes a timing controller (T-con) 210 , a source driver 220 , a gate driver 230 , and a display panel 240 . The gate driver 230 is controlled by the timing controller 210 and outputs a first scan signal SC1 or a second scan signal SC2 to drive the pixel circuit Pix within the display panel 240. The first scan signal SC1 and the second scan signal SC2 are output during different picture periods, and the first scan signal SC1 The number of second scan signals SC2 depends on the number of columns of the pixel circuit Pix array in the display panel 240.

The source driver 220 receives the data signal DD provided by the timing controller 210, and provides a corresponding positive polarity data signal DV+ and negative polarity data signal DV- during a picture period to the pixel circuit Pix driven by the gate driver 230 in the display panel 240. The positive polarity data signal DV+ and the negative polarity data signal DV- may correspond to the same picture, and the number of the positive polarity data signal DV+ and the negative polarity data signal DV- depends on the number of rows of the pixel circuit Pix array in the display panel 240.

After the source driver 220 supplies the corresponding positive polarity data signal DV+ and the negative polarity data signal DV- to all the pixel circuits in the liquid crystal display panel 140, the gate driver 230 outputs the first display signal SP1 and the second display signal SP2. The third display signal SP3 or the fourth display signal SP4 is used to drive the pixel circuit Pix to display the screen, wherein the first display signal SP1, the second display signal SP2, the third display signal SP3 or the fourth display signal SP4 are presented in time series Do not overlap.

In addition, if the display element in the pixel circuit Pix is a non-light-emitting element, the display device 200 may further include a backlight module 250 to provide a surface light source required by the display panel 440, thereby causing the liquid crystal display panel 240 to display an image frame. Show it to the user.

FIG. 3A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the first embodiment of the present invention. Referring to FIG. 3A, the pixel circuit Pix includes a storage unit 310 and a display unit 320. The storage unit 310 includes a first write switch WSW1, a second write switch WSW2, a third write switch WSW3, The fourth write switch WSW4, the first memory unit 311, the second memory unit 313, the third memory unit 315, the fourth memory unit 317, and the switching unit 319.

Referring to FIG. 2 and FIG. 3A, the first end of the first write switch WSW1 is coupled to the source driver 220 to receive the positive polarity data voltage transmitted by the positive polarity data signal DV+, and the first write switch WSW1 is controlled by the first A scan signal SC1. The first end of the first memory unit 311 is coupled to the second end of the first write switch WSW1, and the second end of the first memory unit 311 receives the first reference voltage VR1. The first memory unit 311 stores the positive polarity data voltage via the first write switch WSW1. The first input end 319a of the switching unit 319 is coupled to the first memory unit 311. The switching unit 319 outputs the positive polarity data voltage stored by the first memory unit 311 at its output terminal 319e according to the first display signal SP1.

The first end of the second write switch WSW2 is coupled to the source driver 220 to receive the negative polarity data voltage transmitted by the negative polarity data signal DV-, and the second write switch WSW2 is controlled by the first scan signal SC1. The first end of the second memory unit 313 is coupled to the second end of the second write switch WSW2, and the second end of the second memory unit 313 receives the first reference voltage VR1. The second memory unit 313 stores the negative polarity data voltage via the second write switch WSW2. The second input end 319b of the switching unit 319 is coupled to the second memory unit 313. The switching unit 319 outputs the negative polarity data voltage stored by the second memory unit 313 at its output end 319e according to the second display signal SP2.

The first end of the third write switch WSW3 is coupled to the source driver 220 to receive the positive polarity data voltage transmitted by the positive polarity data voltage DV+, and And the third write switch WSW3 is controlled by the second scan signal SC2. The first end of the third memory unit 315 is coupled to the second end of the third write switch WSW3, and the second end of the third memory unit 315 receives the first reference voltage VR1. The third memory unit 315 stores the positive polarity data voltage via the third write switch WSW3. The third input end 319c of the switching unit 319 is coupled to the third memory unit 315. The switching unit 319 outputs the positive polarity data voltage stored by the third memory unit 315 at its output terminal 319e according to the third display signal SP3.

The first end of the fourth write switch WSW4 is coupled to the source driver 220 to receive the negative polarity data voltage transmitted by the negative polarity data voltage DV-, and the fourth write switch WSW4 is controlled by the second scan signal SC2. The first end of the fourth memory unit 317 is coupled to the second end of the fourth write switch WSW4, and the second end of the fourth memory unit 317 receives the first reference voltage VR1. The fourth memory unit 317 stores the negative polarity data voltage via the fourth write switch WSW3. The fourth input end 319d of the switching unit 319 is coupled to the fourth memory unit 317. The switching unit 319 outputs the negative polarity data voltage stored by the fourth memory unit 317 at its output terminal 319e according to the fourth display signal SP4.

The switching unit 319 includes a first display switch DSW1, a second display switch DSW2, a third display switch DSW3, and a fourth display switch DSW4. The first display switch DSW1 is coupled to the first input end 319a of the switching unit 319, the second end of the first display switch DSW1 is coupled to the output end 319e of the switching unit 319, and the first display switch DSW1 is controlled by the first display. Signal SP1. The first end of the second display switch DSW2 serves as the switching unit 319 The second input end 319b, the second end of the second display switch DSW2 is coupled to the output end 319e of the switching unit 319, and the second display switch DSW2 is controlled by the second display signal SP2.

The first end of the third display switch DSW3 is the third input end 319c of the switching unit 319, the second end of the third display switch DSW3 is coupled to the output end 319e of the switching unit 319, and the third display switch DSW3 is controlled by the third display. Signal SP3. The first display of the fourth display switch DSW4 is the fourth input end 319d of the switching unit 319, the second end of the fourth display switch DSW4 is coupled to the output end 319e of the switching unit 319, and the fourth display switch is controlled by the fourth display signal. SP4.

The display unit 320 includes a display element DP. One end of the display element DP is coupled to the output end 319e of the switching unit 319 to receive the positive polarity data voltage stored by the first memory unit 311, the negative polarity data voltage stored by the second memory unit 313, and the third memory via the switching unit 319. The positive polarity data voltage stored by the unit 315 or the negative polarity data voltage stored by the fourth memory unit 317.

In addition, the display unit 320 may further include a display memory unit 321, the first end of which is coupled to the output end 319e of the switching unit 319, and the second end of the display memory unit 321 receives the second reference voltage VR2. In the present embodiment, the display element DP is, for example, a liquid crystal capacitor DP. The liquid crystal capacitor DP drives and changes the liquid crystal angle in the liquid crystal capacitor DP by the potential difference between the pixel voltage Vlc and the common voltage Vcom.

FIG. 3B is a timing chart of driving of the display device 200 according to an embodiment of the invention. Please refer to FIG. 2, FIG. 3A and FIG. 3B. In this embodiment, Each picture period (such as FP1, FP2 or FP3) includes a data writing period (such as DW1, DW2 or DW3) and a vertical blanking period (such as VB1, VB2 or VB3). In the picture period FP1, the material signal DD transmits the picture material F1 containing the first pixel data D1. When receiving the first pixel data D1, the source driver 220 converts the first pixel data D1 into a positive polarity data voltage D1+ and a negative polarity data voltage D1-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D1+, and the negative polarity data signal DV- transmits the negative polarity data voltage D1-.

In the picture period FP1, the first scan signal SC1 is switched to the high level in the data writing period DW1, and the second scanning signal SC2 is at the low level. Actually, the time at which the first scan signal SC1 is at the high level is inversely proportional to the number of the first scan signals SC1, and the times at which the first scan signal SC1 is at the high level do not overlap each other. Moreover, since the second scan signal SC2 is at a low level, the third write switch WSW3 and the fourth write switch WSW4 are in an off state. When the first scan signal SC1 is at the high level, the first write switch WSW1 and the second write switch WSW2 are in an on state.

Assuming that the first scan signal SC1 is at a high level, the positive polarity data signal DV+ and the negative polarity data signal DV- are respectively transmitting the positive polarity data voltage D1+ and the negative polarity data voltage D1-, and then the first in the first memory unit 311 The capacitor CS1 receives the positive polarity data voltage D1+ via the first write switch WSW1, so the first capacitor CS1 facilitates storing the charge at this time such that the voltage across the first capacitor CS1 is approximately the positive data voltage D1+. And, the second capacitor CS2 in the second memory unit 313 is via the second write switch WSW2. The negative polarity data voltage D1- is received, so the second capacitor CS2 facilitates storing the charge at this time such that the voltage across the second capacitor CS2 is approximately the negative data voltage D1-. Thereby, the pixel circuit Pix can simultaneously store the positive polarity data voltage D1+ and the negative polarity data voltage D1- during one screen to reduce the data transmission rate of the source driver 120.

In addition, in the picture period FP1, the first display signal SP1 and the second display signal SP2 are at a low level, so the first display switch DSW1 and the second display switch DSW2 in the switching element 319 are in an off state. Moreover, in the first half period FA1 of the picture period FP1, the third display signal SP3 is at a high level during the period FA1, so that the voltage stored in the third capacitor CS3 in the third memory unit 315 passes through the third display switch. The DSW 3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 of the display memory unit 231. At this time, the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the third capacitor CS3, the fifth capacitor CS5, and the liquid crystal capacitor DP itself.

During the second half of the FP1 period FB1, the fourth display signal SP4 is at a high level during the period FB1, so that the voltage stored in the fourth capacitor CS4 in the fourth memory unit 317 is transmitted to the fourth display switch DSW4. The liquid crystal capacitor DP and the fifth capacitor CS5 of the display memory unit 231. At this time, the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the fourth capacitor CS4, the fifth capacitor CS5, and the liquid crystal capacitor DP itself. In this embodiment, the voltages stored in the third capacitor CS3 and the fourth capacitor CS4 in the screen period FP1 are not for display, so the influence of the conduction of the third display switch DSW3 and the fourth display switch DSW4 is here. Ignore it without explanation. In other embodiments, the display memory unit 231 may be omitted due to design requirements, and the data voltage is saved by the third capacitor CS3 or the fourth capacitor CS4 and the liquid crystal capacitor 150 itself.

In the picture period FP2, the material signal DD transmits the picture material F2 containing the second pixel data D2. When receiving the second pixel data D2, the source driver 220 converts the second pixel data D2 into a positive polarity data voltage D2+ and a negative polarity data voltage D2-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D2+, and the negative polarity data signal DV- transmits the negative polarity data voltage D2-.

In the picture period FP2, the first scan signal SC1 is at a low level, and the second scan signal SC2 is switched to a high level in the data writing period DW2. Actually, the time when the second scan signal SC2 is at the high level is inversely proportional to the number of the second scan signals SC2, and the time when the second scan signal SC2 is at the high level does not overlap each other. In the picture period FP2, since the first scan signal SC1 is at a low level, the first write switch WSW1 and the second write switch WSW2 are in an off state. When the second scan signal SC2 is at the high level, the third write switch WSW3 and the fourth write switch WSW4 are in an on state.

Assuming that the second scan signal SC2 is at a high level, the positive polarity data signal DV+ and the negative polarity data signal DV- are respectively transmitting the positive polarity data voltage D2+ and the negative polarity data voltage D2-, and then the third capacitance CS3 is written via the third write. The switch WSW3 receives the positive polarity data voltage D2+, so the third capacitor CS3 facilitates storage of the charge at this time such that the voltage across the third capacitor CS3 is approximately the positive data voltage D2+. And, the fourth capacitor CS4 is opened via the fourth write The off WSW4 receives the negative polarity data voltage D2-, so the fourth capacitor CS4 facilitates storing the charge at this time so that the voltage across the fourth capacitor CS4 is approximately the negative data voltage D2-.

In addition, in the picture period FP2, the third display signal SP3 and the fourth display signal SP4 are at a low level, so the third display switch DSW3 and the fourth display switch DSW4 are in an off state. Moreover, in the first half period FA2 of the picture period FP2, the first display signal SP1 is at a high level during the period FA2, so that the positive polarity data voltage D1+ stored by the first capacitor CS1 is transmitted to the first display switch DSW1 to The liquid crystal capacitor DP and the fifth capacitor CS5. At this time, the pixel voltage Vlc will be approximately equal to the positive polarity data voltage D1+, and the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the first capacitor CS1, the fifth capacitor CS5, and the liquid crystal capacitor DP itself.

During the second half of the FP2 period FB2, the second display signal SP2 is at a high level during the period FB2, so that the negative polarity data voltage D1 stored by the second capacitor CS2 is transmitted to the liquid crystal capacitor through the second display switch DSW2. DP and fifth capacitor CS5. At this time, the pixel voltage Vlc will be approximately equal to the negative data voltage D1-, and the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the second capacitor CS2, the fifth capacitor CS5, and the liquid crystal capacitor DP itself. In other embodiments, the display memory unit 321 may be omitted due to design requirements, and the data voltage is saved by the first capacitor CS1 or the second capacitor CS2 and the liquid crystal capacitor 150 itself.

In the picture period FP3, the material signal DD transmits the picture material F3 including the third pixel data D3. When the source driver 220 receives the third pixel data D3, the third pixel data D3 is converted into a positive polarity data. Press D3+ and negative data voltage D3-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D3+, and the negative polarity data signal DV- transmits the negative polarity data voltage D3-.

In the picture period FP3, the first write switch WSW1, the second write switch WSW2, the third write switch WSW3, the fourth write switch WSW4, the first display switch DSW1, the second display switch DSW2, and the third display switch The actions of the DSW 3 and the fourth display switch DSW4 are similar to those described in the picture period FP1. At this time, the first capacitor CS1 is received to the positive polarity data voltage D3+ through the first write switch WSW1, and the second capacitor CS2 is received to the negative polarity data voltage D3+ through the second write switch WSW2. The positive polarity data voltage D2+ stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3 during the first half period FA3 of the picture period FP3, so that the pixel voltage Vlc is approximately equal to the positive polarity. Data voltage D2+. The negative polarity data voltage D2- stored in the fourth capacitor CS4 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fourth display switch DSW4 during the second half period FB3 of the picture period FP3, so that the pixel voltage Vlc is approximately equal to the negative polarity data. Voltage D2-.

According to the above, the embodiment of the present invention controls the first write switch WSW1, the second write switch WSW2, the third write switch WSW3, the fourth write switch WSW4, the first display switch DSW1, and the second display switch DSW2. The third display switch DSW3 and the fourth display switch DSW4 are turned on or off, so that the first capacitor CS1 and the third capacitor CS3 alternately store positive polarity data voltages (such as D1+, D2+ or D3+) corresponding to different pixel data during different screen periods, and Alternately output the stored positive polarity data Voltage (such as D1+, D2+ or D3+). Moreover, the second capacitor CS2 and the fourth capacitor CS4 alternately store negative polarity data voltages (such as D1-, D2- or D3-) corresponding to different pixel data during different screen periods, and alternately output the stored negative polarity data voltages (such as D1). -, D2- or D3-).

4 is a circuit diagram of the source driver 220 of FIG. 2. Referring to FIG. 2 and FIG. 4 , in the embodiment, the source driver 220 includes a displacement register 420 and a plurality of data channels 410 , and the number of data channels 410 and the number of rows of the pixel circuits Pix array in the display panel 240 are Just proportional. The shift register 420 sequentially outputs a plurality of control signals (for example, control signals COL1, COL2, and COL3) according to the start signal STH and the pulse signal CLK. These data channels 410 simultaneously receive the data signal DD and receive one of the control signals (eg, control signal COL1), respectively. The circuit structures of these data channels 410 are similar. The following describes one of the data channels 410 as an example.

The data channel 410 includes a first data latch 411, a second data latch 413, a first digital-to-analog converter (DAC) 415, and a second digital analog converter 417. The data input end of the first data latch 411 receives the pixel data (such as D1) transmitted by the data signal DD, and the trigger end of the first data latch 411 receives the control signal COL1. The data input end of the second data latch 413 is coupled to the data output end of the first data latch 411, and the trigger end of the second data latch 413 receives the latch signal LAT from the timing controller 210. The input ends of the first digital analog converter 415 and the second digital analog converter 417 are coupled to the data output end of the second data latch 413.

The first data latch 411 determines whether to latch the pixel data (such as D1) transmitted by the data signal DD according to the control signal COL1. The first data latch 411 outputs the latched pixel data D1 to the second data latch 413. The second data latch 413 determines whether to latch the received pixel data (such as D1) according to the latch signal LAT. The second data latch 413 outputs the latched pixel data D1 to the digital to analog converters 415 and 417. The first digital analog converter 415 outputs a positive polarity data signal DV+ according to the received pixel data (such as D1), and the second digital analog converter 417 outputs negative polarity data according to the received pixel data (such as D1). Signal DV-.

In this embodiment, the data channel 410 further includes amplifiers 419 and 421. The input terminal A of the amplifier 419 is coupled to the output of the digital analog converter 415, the input terminal B of the amplifier 419 is coupled to the output terminal C thereof, and the output terminal C thereof outputs the positive polarity data signal DV+, wherein the circuit structure of the amplifier 419 can be regarded as A voltage follower. The circuit configuration of the amplifier 421 is similar to that of the amplifier 419, and the input terminal A of the amplifier 421 is coupled to the output of the digital analog converter 417, and the output terminal C of the amplifier 421 outputs the negative polarity data signal DV-.

FIG. 5 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a second embodiment of the present invention. Referring to FIG. 3A and FIG. 5, the circuit operation principle of the second embodiment is similar to that of the first embodiment of FIG. 3A, but differs in the switching unit 511. In the present embodiment, the switching unit 511 includes a first voltage follower 521, a second voltage follower 523, a third voltage follower 525, a fourth voltage follower 527, and a turn-on switch CSW. First voltage follower The input end of the 521 is the first input end 511a of the switching unit 511 and is coupled to the first memory unit 311. The first voltage follower 521 is controlled by the first display signal SP1. The input end of the second voltage follower 523 is used as the second input end 511b of the switching unit 511 and coupled to the second memory unit 313, and the second voltage follower 523 is controlled by the second display signal SP2.

The input end of the third voltage follower 525 is used as the third input end 511c of the switching unit 511 and coupled to the third memory unit 315, and the third voltage follower 415 is controlled by the third display signal SP3. The input end of the fourth voltage follower 527 is used as the fourth input end 511d of the switching unit 511 and coupled to the fourth memory unit 317, and the fourth voltage follower 527 is controlled by the fourth display signal SP4. The first end of the turn-on switch CSW is coupled to the output of the first voltage follower 521, the output of the second voltage follower 523, the output of the third voltage follower 525, and the fourth voltage follower 527. The output end, the second end of the conduction switch CSW serves as the output end 511e of the switching unit 511 and is coupled to the display unit 320. The conduction switch CSW is controlled by the first display signal SP1, the second display signal SP2, the third display signal SP3 and the The four display signal SP4. The voltage followers 521, 523, 525, and 527 can be implemented by referring to the circuits of the amplifiers 419 or 421, and are not described herein.

Further, in the circuit design, the voltage follower (such as 521) is generally kept in operation, but in practical circuit applications, the voltage follower can be enabled in addition to the input and output. ) Pin or power pin. By controlling the voltage of the voltage follower or the power pin to control whether the voltage follower is operated, that is, the display signal can be applied. Control the voltage follower operation of the voltage follower enable pin or power pin.

According to the above and FIG. 3B, the first voltage follower 521 operates in the first half period FA2 of the picture period FP2, the second voltage follower 523 operates in the second half period FB2 of the picture period FP2, and the third voltage follower 525 operates on the screen. In the first half period FA1 of the period FP1 and the first half period FA3 of the screen period FP3, the fourth voltage follower 527 operates in the second half period FB1 of the screen period FP1 and the second half period FB3 of the screen period FP3.

Furthermore, the voltage followers 521, 523, 525, 527 can isolate the current at the input and output. In other words, for example, when the first voltage follower 521 operates, the charge sharing effect of the first capacitor CS1 and the fifth capacitor CS5 and the liquid crystal capacitor DP can be avoided. Similarly, the second voltage follower 523, the third voltage follower 525, and the fourth voltage follower 527 can also avoid the charge sharing effect described above.

FIG. 6 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a third embodiment of the present invention. Referring to FIG. 3A and FIG. 6, the circuit of the third embodiment operates in a similar manner to the first embodiment of FIG. 3A, but differs in the storage unit 610 of the third embodiment. The switching unit 611 of the storage unit 610 further includes a buffer 613. The input end of the buffer 613 is coupled to the second end of the first display switch DSW1, the second end of the second display switch DSW2, and the second end of the third display switch DSW3. And the second end of the fourth display switch DSW4, the output end of the buffer 613 is used as an output end of the switching unit 611 and coupled to the liquid crystal capacitor DP. The buffer 613 can be implemented by using a voltage follower, but does not limit the embodiment of the present invention. Thereby avoiding the first The capacitor CS1, the second capacitor CS2, the third capacitor CS3, or the fourth capacitor CS4 have a charge sharing effect with the fifth capacitor CS5 and the liquid crystal capacitor DP.

FIG. 7A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the fourth embodiment of the present invention. Please refer to FIG. 3A and FIG. 7A , which are different from the fifth write switch WSW5 of the storage unit 710 of the fourth embodiment and the fifth display switch DSW5 of the switching unit 711 . The fifth write switch WSW5 can be regarded as a combination of the second write switch WSW2 and the fourth write switch WSW4, and the fifth display switch DSW5 can be regarded as a combination of the second display switch DSW2 and the fourth display switch DSW4.

FIG. 7B is a timing chart showing driving of a display device according to another embodiment of the present invention. Referring to FIG. 2, FIG. 7A and FIG. 7B, in this embodiment, each picture period (such as FP4, FP5, and FP6) also includes data writing periods (such as DW4, DW5, and DW6) and vertical blank periods (such as VB4). , VB5 and VB6), and the vertical blank periods (such as VB4, VB5, and VB6) during each picture period (such as FP4, FP5, and FP6) are arranged before the data writing period (such as DW4, DW5, and DW6). The driving waveforms of the first scan signal SC1, the second scan signal SC2, the data signal DD, the positive polarity data signal DV+, and the negative polarity data signal DV- of the FP4, FP5 or FP6 during the picture period are similar to those described in the picture period FP1, FP2 or FP3 Therefore, the details are not repeated.

During the data writing period DW4 of the picture period FP4, the first write switch WSW1 and the fifth write switch WSW5 are turned on according to the first scan signal SC1, so that the first capacitor CS1 is received via the first write switch WSW1. And store the positive data voltage D1+, the second capacitor CS2 will The negative polarity data voltage D1- is received and stored via the fifth write switch WSW5. Moreover, the third display signal SP3 will be at a high level, and the first display signal SP1, the second display signal SP2, and the fourth display signal SP4 will be at a low level. At this time, the voltage stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3. It is assumed here that the voltage stored in the third capacitor CS3 is not the data voltage for display, so the change in the pixel voltage Vlc is ignored.

During the vertical blank period VB5 of the screen period FP5, the second display signal SP2 will be at a high level, and the first display signal SP1, the third display signal SP3, and the fourth display signal SP4 will be at a low level. At this time, the negative polarity data voltage D1- stored by the second capacitor CS2 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fifth display switch DSW5, so that the pixel voltage Vlc is approximately equal to the negative polarity data voltage D1-.

In the data writing period DW5 of the picture period FP5, the third write switch WSW3 and the fifth write switch WSW5 are in an on state, and the third capacitor CS3 receives and stores the positive polarity data voltage D2+ via the third write switch WSW3. The second capacitor CS2 receives and stores the negative polarity data voltage D2- via the fifth write switch WSW5. Moreover, the first display signal SP1 will be at a high level, and the second display signal SP2, the third display signal SP3, and the fourth display signal SP4 will be at a low level. At this time, the positive polarity data voltage D1+ stored by the first capacitor CS1 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the first display switch DSW1, so that the pixel voltage Vlc is approximately equal to the positive polarity data voltage D1+.

During the vertical blank period VB6 of the picture period FP6, the fourth display signal SP4 will be at a high level, and the first display signal SP1, the second display signal SP2, and the third display signal SP3 will be at a low level. At this time, the negative polarity data voltage D2- stored in the second capacitor CS2 is also transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fifth display switch DSW5, so that the pixel voltage Vlc is approximately equal to the negative polarity data voltage D2-.

During the data writing period DW6 of the picture period FP6, the first capacitor CS1 receives and stores the positive polarity data voltage D3+ via the first write switch WSW1, and the second capacitor CS2 receives and stores the negative polarity via the fifth write switch WSW5. Data voltage D3-. The positive polarity data voltage D2+ stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3, so that the pixel voltage Vlc is approximately equal to the positive polarity data voltage D2+.

According to the above, the embodiment of the present invention controls the conduction between the first write switch WSW1, the third write switch WSW3, the fifth write switch WSW5, the first display switch DSW1, the third display switch DSW3, and the fifth display switch DSW5. Otherwise, the first capacitor CS1 and the third capacitor CS3 are caused to alternately store the positive polarity data voltage during different screens, and alternately output the stored positive polarity data voltage. The second capacitor CS2 stores the negative data voltage of different screens, and outputs the stored negative data voltage during the vertical blank period.

FIG. 8 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a fifth embodiment of the present invention. Referring to FIG. 7A and FIG. 8, the circuit operation principle of the fifth embodiment is similar to the fourth embodiment of FIG. 7A, but the difference lies in the storage. The switching unit 811 of the storage unit 810. The switching unit 811 includes a first voltage follower 521, a third voltage follower 525, a fifth voltage follower 821, and a turn-on switch CSW, wherein the first voltage follower 521, the third voltage follower 525, and the turn-on The switch CSW can be referred to the description of the second embodiment, and details are not described herein again. In this embodiment, the input end of the fifth voltage follower 821 is used as the second input end of the switching unit 811 to be coupled to the second memory unit 313, and the voltage follower 821 is controlled by the second display signal SP2 and the 4 The display signal SP4, that is, the voltage follower 821 operates in the vertical blank periods VB5 and VB6 of FIG. 7B.

FIG. 9 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a sixth embodiment of the present invention. Referring to FIG. 7A and FIG. 9, the circuit operation principle of the sixth embodiment is similar to that of the fourth embodiment of FIG. 7A, but the difference is that the switching unit 911 of the sixth embodiment further includes a buffer 613, wherein the buffer 613 Reference may be made to the description of the third embodiment, and details are not described herein again.

According to the above embodiment, the driving method of one pixel circuit can be integrated. FIG. 10 is a flow chart showing a method of operating a pixel circuit in accordance with an embodiment of the invention. Referring to FIG. 10, the positive polarity data voltage and the negative polarity data voltage of the first pixel data are stored during the first screen period (step S110). The first sub-period and the second sub-period of the second picture period respectively output the positive polarity data voltage and the negative polarity data voltage of the first pixel data to the display unit (step S120). During the second screen period, the positive polarity data voltage and the negative polarity data voltage of the second pixel data are stored (step S130). Outputting the positive polarity data voltage and the negative polarity data voltage of the second pixel data to the display unit in the third sub-period and the fourth sub-period of the third picture period (Step S140). For details of the above steps, reference may be made to the above description, and details are not described herein again.

In summary, the display device, the pixel circuit, and the method for operating the same according to the embodiments of the present invention have three or more capacitors disposed in the pixel circuit, and the corresponding write control switches and the switching unit are respectively caused to cause the capacitors to be respectively stored correspondingly. The positive polarity data voltage and the negative polarity data voltage, and sequentially output the stored positive polarity data voltage and negative polarity data voltage. Thereby, the data transfer rate of the source driver can be reduced. Also, a voltage follower can be configured in the switching unit of the pixel circuit to avoid the effect of charge sharing.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ display devices

110, 210‧‧‧ timing controller

120, 220‧‧‧ source drive

130, 230‧‧ ‧ gate driver

140, 240‧‧‧ display panel

250‧‧‧Backlight module

310, 510, 610, 710, 810, 910‧‧‧ storage units

311, 313, 315, 317‧‧‧ memory unit

319, 511, 611, 711, 811, 911 ‧ ‧ switching unit

Inputs 319a, 319b, 319c, 319d, 511a, 511b, 511c, 511d, A, B‧‧

319e, 511e, C‧‧‧ outputs

320‧‧‧ display unit

321‧‧‧ display memory unit

410‧‧‧ data channel

411‧‧‧Displacement register

413‧‧‧Information latch

415, 417‧‧‧Digital Analog Converter

419, 421‧‧ amps

521, 523, 525, 527, 821‧‧‧ voltage followers

613‧‧‧buffer

CS1~CS5‧‧‧ capacitor

D1~D3‧‧‧Pixel data

D1+, D1-, D2+, D2-, D3+, D3-‧‧‧ data voltage

DD‧‧‧Information signal

DP‧‧‧ display components / liquid crystal capacitors

DS‧‧‧Display information

DSW1~DSW5‧‧‧ display switch

DV+, DV-‧‧‧ data signal

F1~F3‧‧‧ screen data

FA1, FB1, FA2, FB2, FA3, FB3‧‧‧

Fp1~fp3, FP1~FP6‧‧‧ during the screen

Dw1~dw3, DW1~DW6‧‧‧ data writing period

Vb1~vb3, VB1~VB6‧‧‧ vertical blank period

CLK‧‧‧ clock signal

COL1~COL3‧‧‧ control signal

LAT‧‧‧Latch signal

PX, Pix‧‧‧ pixel circuits

SC1, SC2‧‧‧ scan signals

SCW‧‧‧Switch

STH‧‧‧ start signal

SP1~SP4‧‧‧ display signal

Vlc‧‧‧ pixel voltage

VR1, VR2‧‧‧ reference voltage

Vcom‧‧‧Common voltage

WSW1~WSW5‧‧‧Write switch

S110, S120, S130, S140‧‧ steps

1A is a block diagram of a system of a conventional display.

FIG. 1B is a timing chart showing driving of the data signal DD and the pixel circuit PX of FIG. 1A.

2 is a block diagram of a system of a display device in accordance with an embodiment of the present invention.

FIG. 3A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the first embodiment of the present invention.

FIG. 3B is a timing chart of driving of the display device 200 according to an embodiment of the invention.

4 is a circuit diagram of the source driver 220 of FIG. 2.

FIG. 5 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a third embodiment of the present invention.

FIG. 7A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the fourth embodiment of the present invention.

FIG. 7B is a timing chart showing driving of the display device 200 according to another embodiment of the present invention.

FIG. 8 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a sixth embodiment of the present invention.

FIG. 10 is a flow chart showing a method of operating a pixel circuit in accordance with an embodiment of the invention.

310‧‧‧ storage unit

311, 313, 315, 317‧‧‧ memory unit

319‧‧‧Switch unit

320‧‧‧ display unit

321‧‧‧ display memory unit

CS1~CS5‧‧‧ capacitor

DP‧‧‧ display components / liquid crystal capacitors

DSW1~DSW4‧‧‧ display switch

DV+, DV-‧‧‧ data signal

Pix‧‧‧pixel circuit

SC1, SC2‧‧‧ scan signals

SP1~SP4‧‧‧ display signal

Vlc‧‧‧ pixel voltage

VR1, VR2‧‧‧ reference voltage

Vcom‧‧‧Common voltage

WSW1~WSW4‧‧‧Write switch

Claims (19)

A display device includes: a source driver for converting a first pixel data into a first polarity data voltage and a second polarity data voltage during a first picture, and a second during a second picture Converting the pixel data into a third polarity data voltage and a fourth polarity data voltage; and a pixel circuit coupled to the source driver, the pixel circuit storing the first polarity data voltage and the first The second polarity data voltage displays the first polarity data voltage and the second polarity data voltage during a first sub-period and a second sub-period of the second picture period, and stores the third time during the second picture period Polar data voltage and the fourth polarity data voltage. The display device of claim 1, wherein the pixel circuit comprises: a display unit; and a storage unit, the storage unit comprising: a first write switch, the first end of which is connected to the source driver a first memory unit coupled to the second end of the first write switch; a second write switch having a first end coupled to the source driver; a second memory unit coupled to the first Writing a second end of the switch; a third write switch having a first end connected to the source driver; a third memory unit coupled to the second end of the third write switch; and a switching unit, the first input of the switching unit The second input end of the switching unit is coupled to the second memory unit, the third input end of the switching unit is coupled to the third memory unit, and the output end of the switching unit is coupled To the display unit. The display device of claim 2, wherein the first write switch and the second write switch are turned on during the first screen, and the first memory unit is stored through the first write switch that is turned on. The second polarity data channel stores the second polarity data voltage through the second write switch that is turned on, and the second write switch and the third write switch are turned on during the second picture During the second sub-segment, the second memory unit stores the fourth polarity data voltage through the second write switch that is turned on, and the third memory unit stores the third polarity data voltage through the third write switch that is turned on. The output end of the switching unit is coupled to the second input end of the switching unit during the first sub-phase, and the output end of the switching unit is coupled to the first input end of the switching unit during the second sub-phase, the switching unit The output terminal is coupled to the second input end of the switching unit during a third sub-period of the third picture period, and the output end of the switching unit is coupled to the switching unit during a fourth sub-period of the third picture period First Three inputs. The display device of claim 3, wherein the switching unit comprises: a first voltage follower having an input terminal as a first input of the switching unit, the first voltage follower operating in the second sub-period; a second voltage follower, the input being the switching a second input end of the unit, the second voltage follower operates in the first sub-period and the third sub-period; a third voltage follower, the input end thereof serving as a third input end of the switching unit, a third voltage follower operates during the fourth sub-period; and a turn-on switch having an input coupled to the output of the first voltage follower, the output of the second voltage follower, and the third voltage An output end of the pass-through switch serves as an output end of the switching unit, and the conduction switch is turned on in the first sub-period, the second sub-period, the third sub-period, and the fourth sub-period. The display device of claim 3, wherein the switching unit comprises: a first display switch, the first end of which is the first input end of the switching unit, and the second end of the first display switch is coupled An output terminal of the switching unit, the first display switch is turned on during the second sub-period; a second display switch has a first end serving as a second input end of the switching unit, and a second end coupling of the second display switch Connected to the output end of the switching unit, the second display switch is turned on during the first sub-period and the third sub-period; and a third display switch, the first end of which is the third input end of the switching unit, the first The second end of the three display switch is coupled to the output end of the switching unit, and the third display switch is turned on during the fourth sub-period. The display device of claim 5, wherein the switching unit further comprises: a buffer, the input end of which is coupled to the second end of the first display switch, the second end of the second display switch, and the The second end of the third display switch, the output of the buffer serves as the output of the switching unit. The display device of claim 2, wherein the storage unit further comprises: a fourth write switch, the first end of which is connected to the source driver; and a fourth memory unit coupled to the fourth Writing a second end of the switch; wherein a fourth input end of the switching unit is coupled to the fourth memory unit. The display device of claim 7, wherein the first write switch and the second write switch are turned on during the first screen, and the first memory unit is stored through the first write switch that is turned on. The first polarity data voltage, the second memory unit stores the second polarity data voltage through the second write switch that is turned on, and the third write switch and the fourth write switch are turned on during the second screen. The third memory unit stores the third polarity data voltage through the turned-on third write switch, and the fourth memory unit stores the fourth polarity data voltage through the turned-on fourth write switch, the output of the switching unit The first input end of the switching unit is coupled to the first input end of the switching unit. The output end of the switching unit is coupled to the second input end of the switching unit during the second sub-phase, and the output end of the switching unit is a third sub-period of the three-picture period is coupled to the third input end of the switching unit, the switching The output of the unit is coupled to the fourth input of the switching unit during a fourth sub-phase of the third picture. The display device of claim 8, wherein the switching unit comprises: a first voltage follower, the input end of which is the first input end of the switching unit, the first voltage follower operates on the a first sub-period; a second voltage follower having an input terminal as a second input of the switching unit, the second voltage follower operating in the second sub-period; a third voltage follower, The input end serves as a third input end of the switching unit, the third voltage follower operates in the third sub-period; a fourth voltage follower, the input end thereof serves as a fourth input end of the switching unit, the first a fourth voltage follower operates during the fourth sub-period; and a conduction switch having an input coupled to the output of the first voltage follower, the output of the second voltage follower, and the third voltage An output end of the coupler and an output end of the fourth voltage follower, the output end of the conduction switch is used as an output end of the switching unit, and the conduction switch is turned on in the first sub-period, the second sub-period, the first The three sub-periods and the fourth sub-period. The display device of claim 8, wherein the switching unit comprises: a first display switch, the first end of which is the first input end of the switching unit, and the second end of the first display switch is coupled An output end of the switching unit, the first display switch is turned on during the first sub-period; a second display switch having a first end as a second input end of the switching unit, a second end of the second display switch coupled to an output end of the switching unit, the second display switch being conductive to the second sub-period And a third display switch having a first end as a third input end of the switching unit, a second end of the third display switch coupled to an output end of the switching unit, the third display switch being conductive to the third And a fourth display switch having a first end serving as a fourth input end of the switching unit, a second end of the fourth display switch coupled to an output end of the switching unit, the fourth display switch being conductive The fourth sub-period. The display device of claim 10, wherein the switching unit further comprises: a buffer, the input end of which is coupled to the second end of the first display switch, the second end of the second display switch, The second end of the third display switch and the second end of the fourth display switch, the output end of the buffer serves as an output end of the switching unit. The display device of claim 2, wherein the display unit further comprises a display memory unit coupled to the output of the switching unit. The display device of claim 1, wherein the source driver comprises a data channel, the data channel comprising: a first data latch, receiving the first pixel data during the first picture, Receiving the second pixel data during the two pictures; a second data latch coupled to the first data latch; a first digit to analog converter coupled to the second data latch for converting the first pixel data into the first polarity data voltage and converting the second pixel data into the third polarity a data voltage; and a second digit to analog converter coupled to the second data latch for converting the first pixel data into the second polarity data voltage and converting the second pixel data into the The fourth polarity data voltage. A pixel circuit of a display device, comprising: a display unit; and a storage unit, the storage unit comprising: a first write switch, the first end of which is connected to a source driver; and a first memory unit coupled The second write switch has a first end connected to the source driver; a second memory unit coupled to the second end of the second write switch; a third write switch having a first end connected to the source driver; a third memory unit coupled to the second end of the third write switch; and a switching unit having a first input end The second memory unit is coupled to the first memory unit, and the second input end of the switching unit is coupled to the second memory unit The third input end of the switching unit is coupled to the third memory unit, and the output end of the switching unit is coupled to the display unit. The pixel circuit of the display device of claim 14, wherein the first write switch and the second write switch are turned on during a first picture, and the first memory unit transmits the first write through The switch stores a first polarity data voltage of the first pixel data, and the second memory unit stores a second polarity data voltage of the first pixel data through the second write switch that is turned on, and the output end of the switching unit is a first sub-period of the second picture is coupled to the second input end of the switching unit, and the output end of the switching unit is coupled to the first input end of the switching unit during a second sub-period of the second picture During the second sub-switch, the second write unit stores a fourth polarity data voltage of the second pixel data through the second write switch that is turned on. The third memory unit stores a third polarity data voltage of the second pixel data through the third write switch that is turned on, and the output end of the switching unit is coupled during a third sub-period of a third picture period. A second input terminal of the switching means, the output terminal of the switch unit is coupled to a third input of the switch unit during a fourth sub-period of the third screen. The pixel circuit of the display device of claim 14, wherein the storage unit further comprises: a fourth write switch, the first end of which is connected to the source driver; and a fourth memory unit coupled to the a second end of the fourth write switch; A fourth input end of the switching unit is coupled to the fourth memory unit. The pixel circuit of the display device of claim 16, wherein the first write switch and the second write switch are turned on during a first picture, and the first memory unit transmits the first write through The switch stores a first polarity data voltage of the first pixel data, and the second memory unit stores a second polarity data voltage of the first pixel data through the second write switch that is turned on, the third write switch and During the second write switch, the third memory unit stores a third polarity data voltage of the second pixel data through the turned-on third write switch, and the fourth memory unit is turned on. The fourth write switch stores a fourth polarity data voltage of the second pixel data, and the output end of the switching unit is coupled to the first input end of the switching unit during a first sub-period of the second picture period, The output end of the switching unit is coupled to the second input end of the switching unit during a second sub-period of the second picture period, and the output end of the switching unit is coupled to a third sub-period during a third picture period The third input of the switching unit, the switching unit output terminal coupled to the fourth input of the switch unit during a fourth sub-period of the third screen. A method for operating a pixel circuit, the method includes: storing a first polarity data voltage and a second polarity data voltage of a first pixel data in a pixel during a first picture; And outputting, by the first sub-period and the second sub-period, the first polarity data voltage and the second polarity data voltage to a display unit of the pixel; During the second picture, a third polarity data voltage and a fourth polarity data voltage of the second pixel data are stored in the pixel. The method for operating a pixel circuit according to claim 18, further comprising: respectively, the third polarity data period and the fourth time period during a third sub-period and a fourth sub-period of a third picture period The polarity data voltage is output to the display unit.