TWI406077B - Thin film transistor array substrate - Google Patents

Abstract

A thin film transistor (TFT) array substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixels is provided. The plurality of scan lines comprises a first conductive layer. Each data line includes a plurality of first conductive wire and a plurality of second conductive wire, wherein the first conductive wires and the second conductive wires are arranged in an interlacing manner and connected to each other. The second conductive wires cross over the scan line and the first conductive wires disposed between adjacent scan lines. The first conductive wires comprise the first conductive layer and the second conductive wires comprise a second conductive layer, wherein the distance between the first conductive layer and the substrate is smaller than the distance between the second conductive layer and the substrate. Each pixel includes a TFT and a pixel electrode, wherein the TFT is electrically connected to the corresponding scan line and the corresponding second conductive wire. The pixel electrode electrically connects to the TFT and at least part of the pixel electrode extends to there above the adjacent first conductive wires.

Description

Thin film transistor array substrate

The present invention relates to a thin film transistor array substrate, and more particularly to a thin film transistor array substrate having a data line in which film layers that are not coplanar are connected in series.

In response to the requirements of high speed, high efficiency, light weight and shortness of modern products, all electronic components are actively developing towards miniaturization. A variety of portable electronic devices have also become mainstream, such as: notebooks, cell phones, electronic dictionaries, personal digital assistants (PDAs), web pads, and tablets. Tablet PC, etc. For the image display of the portable electronic device, in order to meet the demand for miniaturization of the product, a flat panel display having superior space utilization efficiency, high image quality, low power consumption, and no radiation is widely used. Among them, a liquid crystal display (LCD) is widely used.

A liquid crystal display generally includes a scan line, a data line, and a plurality of pixel structures arranged in an array, and each pixel structure has a thin film transistor and a pixel electrode. In general, the pixel electrode is the main display area in the liquid crystal display. In other words, in the pixel structure, the layout area of the pixel electrode is one of the important factors affecting the aperture ratio, and in order to increase the displayable area of the liquid crystal display, To meet the high aperture ratio requirements, the pixel electrodes typically extend above the adjacent data lines. However, parasitic capacitance is easily generated due to the voltage coupling effect due to the overlap of the pixel electrode and the data line (Parasitic Capacitance), this parasitic capacitance is proportional to the overlap area between the pixel electrode and the data line, and inversely proportional to the distance between the pixel electrode and the data line, thus making the liquid crystal display susceptible to crosstalk.

In detail, FIG. 1A is a top view of a conventional thin film transistor array substrate, and FIG. 1B is a cross-sectional view taken along line AA' of FIG. 1A. As shown in FIG. 1A and FIG. 1B, the thin film transistor array substrate 100 includes a scan line 110, a data line 120, and a plurality of arrayed pixel structures 130, wherein the pixel structure 130 includes a thin film transistor 140 and a thin film transistor 140. Electrically connected pixel electrode 150. As shown in FIG. 1A and FIG. 1B, the pixel electrode 150 extends above the data line 120. The data line 120 and the pixel electrode 150 have only a single insulating layer 160. In other words, between the data line 120 and the pixel electrode 150. The distance is only about the thickness of the single insulating layer 160. Therefore, the parasitic capacitance generated between the data line 120 and the pixel electrode 150 is large, and the liquid crystal display is prone to crosstalk and affects display quality.

In order to reduce the crosstalk effect of the pixel structure in the above-mentioned thin film transistor array substrate, the designer can selectively reduce the area of the pixel electrode so that the pixel electrode does not overlap with the data line. However, reducing the area of the pixel electrode will greatly reduce the aperture ratio of the pixel structure, affecting the displayable area of the liquid crystal display. Therefore, how to properly design the structure between the pixel electrode and the data line in the pixel structure, so that the pixel structure can effectively improve the crosstalk phenomenon and maintain a certain degree of aperture ratio, which is the current layout of the thin film transistor array substrate. (Layout) is a problem to be overcome.

The invention provides a thin film transistor array substrate which can maintain display Shows the aperture ratio of the area and effectively reduces the crosstalk phenomenon.

The present invention provides a thin film transistor array substrate comprising a substrate and a plurality of scan lines, a plurality of data lines and a plurality of pixel structures disposed on the substrate. The scan line is composed of a first conductive layer. Each of the data lines includes a plurality of first wires and a plurality of second wires, wherein the first wires and the second wires are arranged in parallel with each other and connected in series, and the first wires and the second wires are alternately arranged with each other, and the second wires are crossed a scan line, the first wire is located between two adjacent scan lines, the first wire and the second wire are respectively composed of the first conductive layer and the second conductive layer, and the distance between the first conductive layer and the substrate is smaller than the second The distance between the conductive layer and the substrate. Each pixel structure includes a thin film transistor and a pixel electrode. The thin film transistor is electrically connected to the corresponding scan line and the corresponding second lead. The pixel electrode is electrically connected to the thin film transistor, and at least a portion of the pixel electrode extends over the adjacent first wire.

In an embodiment of the invention, the thin film transistor array substrate further includes a first insulating layer and a second insulating layer, wherein the first insulating layer covers the first conductive layer, and the second insulating layer covers the second conductive layer and the thin film Crystal. At this time, a laminate of the first insulating layer and the second insulating layer is provided between the pixel electrode and the corresponding first wire.

In an embodiment of the invention, the thin film transistor array substrate further includes a jumper layer, and the first insulating layer and the second insulating layer above the first conductive layer have a plurality of first contact windows to respectively expose the first a second insulating layer above the second wire, the second insulating layer having a plurality of second contact windows respectively exposing the two ends of each of the second wires, the jumper layer by each of the first contact windows and each Two contact windows electrically connected to each of the first wires and each of the second leads Between the lines, wherein the first wire and the second wire do not overlap on the projected area, and the composition of the jumper layer is the same as the composition of the pixel electrode.

In an embodiment of the invention, the first wire and the second wire are at least partially overlapped in the projection direction, and the first insulating layer located in the overlapping area of each of the first wires and the second wires has an opening, The second wire is connected to each of the first wires through the opening.

In an embodiment of the invention, each of the thin film transistors has a gate, a channel layer, a source, and a drain, and each gate is connected to a corresponding scan line, and each source is connected to a corresponding second wire, and each The bungee is connected to each pixel electrode. At this time, the gate is composed of the first conductive layer, and the source, the drain and the second wire are composed of the second conductive layer, and the channel layer is made of amorphous germanium.

In an embodiment of the invention, each of the thin film transistors has a semiconductor layer, and the semiconductor layer has a source region electrically connected to the second conductive line and a drain region electrically connected to the pixel electrode.

In an embodiment of the invention, the first wire and the second wire are not coplanar, and the width of the first wire is substantially equal to the width of the second wire.

In the thin film transistor array substrate of the present invention, the data lines are divided into first and second wires which are connected in series and are not coplanar, and are effectively reduced by increasing the distance between the first wires and the pixel electrodes. The parasitic capacitance between the data line and the pixel electrode maintains a certain degree of displayable area.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

First embodiment

2 is a schematic view of a thin film transistor array substrate according to an embodiment of the present invention, and FIGS. 3A and 3B are respectively schematic cross-sectional views corresponding to the A-A' and B-B' hatching lines of FIG. Referring to FIG. 2, FIG. 3A and FIG. 3B, the thin film transistor array substrate 200 is composed of a plurality of pixel structure arrays arranged on a substrate. For convenience of description, only two pixel structures are represented in the figure.

Referring to FIG. 2, FIG. 3A and FIG. 3B, the thin film transistor array substrate 200 is mainly composed of a substrate 210, a plurality of scanning lines 220, a plurality of data lines 230, and a plurality of pixel structures 240, and a plurality of scanning lines. 220. The plurality of data lines 230 and the plurality of pixel structures 240 are disposed on the substrate 210. The scan line 220 is composed of a first conductive layer M1. Each of the data lines 230 is mainly composed of a plurality of first wires 232 and second wires 234 which are serially connected and staggered, wherein the first wires 232 and the second wires 234 are respectively formed by the first conductive layer M1 and the second conductive layer. M2 is composed, and the first conductive layer M1 and the second conductive layer M2 belong to different film layers. In other words, the first conductive layer M1 and the second conductive layer M2 are not coplanar. In the present embodiment, the width of the first wire 232 is substantially equal to the width of the second wire 234. In addition, the first conductive layer M1 and the second conductive layer M2 may be selected from conductor materials of the same or different composition, such as aluminum, molybdenum, titanium, the above-mentioned nitrides, or any combination thereof, and the invention is not limited thereto.

As shown in FIG. 2, the second wire 234 spans the scan line 220, and the first wire 232 is located between two adjacent scan lines 220. Each pixel structure 240 includes a thin film transistor 250 and a pixel electrode 260, wherein the thin film transistor 250 is electrically connected to the corresponding scan line 220 and the corresponding second lead 234. The pixel electrode 260 is electrically connected to the thin film transistor 250, and the pixel electrode 260 portion extends over the adjacent first lead 232.

Continuing to refer to FIG. 2, FIG. 3A and FIG. 3B, it is worth noting that, in the thin film transistor array substrate 200 of the present invention, the area of the data line 230 spanning the scan line 220 is the second line 234. And the second conductive layer M2 is located above the first conductive layer M1 for transmitting the signal of the data line 230. Moreover, the present invention causes the data line 230 located between two adjacent scan lines 220 and mainly overlapping the pixel electrode 260 to be the first wire 232, and the first wire 232 is mainly located far from the pixel electrode 260. The first conductive layer M1 is configured such that the pixel electrode 260 and the data line 230 have a stack of the first insulating layer 270 and the second insulating layer 280, in other words, between the pixel electrode 260 and the data line 230. The distance between the first insulating layer 270 and the second insulating layer 280 is the sum of the thickness of the first insulating layer 270 and the second insulating layer 280. Therefore, the thin film transistor array substrate 200 of the present invention is elongated between the elongated pixel electrode 260 and the data line 230. The distance reduces the parasitic capacitance between the pixel electrode 260 and the data line 230, thereby effectively reducing the occurrence of crosstalk.

It is worth mentioning that in the present embodiment, the thin film transistor 250 belongs to a bottom gate type thin film transistor, as shown in FIG. Specifically, the thin film transistor 250 has a gate 252, a channel layer 254, a source 256, and a drain 258. Each gate 252 is connected to a corresponding scan line 220, and each source 256 is connected to a corresponding second wire 234. Each of the drain electrodes 258 is connected to each of the pixel electrodes 260. At this time, wherein the gate 252 is composed of the first conductive layer M1, The source 256, the drain 258 and the second wire 234 are composed of a second conductive layer M2, and the channel layer 254 is made of amorphous germanium. Also, as shown in FIG. 3B, the first insulating layer 270 covers the first conductive layer M1, and the second insulating layer 280 covers the second conductive layer M2 and the thin film transistor 250.

In order to clearly explain the relative positions of the members on the substrate, the fabrication process of the thin film transistor array substrate 200 will be briefly described below by taking the thin film transistor array substrate 200 of FIGS. 2, 3A, and 3B as an example. Please refer to FIG. 2, FIG. 3A and FIG. 3B at the same time. First, a first conductive layer M1 is deposited on the substrate 210, and then a patterning process of the first conductive layer M1 is performed to form a plurality of scan lines 220, a plurality of gates 252, and two adjacent scan lines on the substrate 210. The first wire 232 between 220. Next, a first insulating layer 270 is formed to cover the scan lines 220, the gates 252, and the first wires 232. Then, a patterning process of the second conductive layer M2 is performed on the substrate 210 to form a plurality of second wires 234, a plurality of source electrodes 256, and a plurality of drain electrodes 258 on the first insulating layer 270. Next, a second insulating layer 280 is formed to cover the plurality of second wires 234, the plurality of source electrodes 256, and the plurality of drain electrodes 258, and then the patterning process of the contact windows is performed to form in the first insulating layer 270. a first contact window H1 to expose portions of the respective first wires 232, and openings corresponding to the respective first contact windows H1 are formed in the second insulating layer 280 to expose portions of the respective first wires 232, and the second insulating layer 280 has a portion The two contact windows H2 expose portions of the respective second wires 234. Thereafter, a plurality of pixel electrodes 260 and a plurality of jumper layers 290 are formed on the second insulating layer 280, wherein each of the jumper layers 290 and the first wires 232 and the second via the first contact window H1 and the second contact window H2, respectively Two wires 234 Sexual connection.

As shown in FIG. 3A, for the upper pixel electrode 260, since the first wire 232 is lower than the second conductor 234 of FIG. 3B, it belongs to the lower layer of the first conductor layer M1, according to the parasitic capacitance value and the second The distance between the electrodes is inversely proportional to the relationship between the electrodes, and the region in the region of the data line 230 that mainly overlaps the pixel electrode 260 is planned to be the first wire 232 of the lower layer of the pixel structure, so that The overlapping area between the pixel electrode 260 and the data line 230 can be reduced without reducing the parasitic capacitance between the pixel electrode 260 and the data line 230, thereby effectively reducing the occurrence of crosstalk.

Based on the actual process yield considerations, as shown in FIG. 3B, in the embodiment, the first wire 232 and the second wire 234 do not overlap in the projection direction, but are electrically connected to the first layer by using the jumper layer 290. Between the wire 232 and the second wire 234. In detail, please refer to FIG. 2 and FIG. 3B simultaneously, the first insulating layer 270 and the second insulating layer 280 above the first wire 232 have a plurality of first contact windows H1 to respectively expose the first wires 232. The second insulating layer 280 above the second wire 234 has a plurality of second contact windows H2 to expose the two ends of the second wires 234 respectively. The jumper layer 290 passes through the first contact windows H1. And each of the second contact windows H2 is electrically connected between each of the first wires 232 and each of the second wires 234. In practice, the jumper layer 290 can be made of the same material as the pixel electrode 260. In other words, the jumper layer 290 and the pixel electrode 260 can be fabricated by the same mask process.

Figure 3C is another cross-sectional view taken along line BB' of Figure 2 in the first embodiment of the present invention; A schematic cross-sectional view of the implementation. Referring to FIG. 2 and FIG. 3C, the designer can also overlap the partial region of the first wire 232 with the second wire 234 based on the consideration of reducing the RC delay of the data line 230, and directly at the overlap. Pick up. In detail, the first wire 232 and the second wire 234 have at least partially overlapping regions in the projection direction, and the first insulating layer 270 located in the overlapping region has an opening 272, and the second wire 234 is opened by the opening 272 A wire 232 is directly connected. Therefore, the present invention does not limit the manner in which the first wire 232 and the second wire 234 are electrically connected.

Second embodiment

4 is a schematic view of a thin film transistor array substrate according to an embodiment of the present invention, and FIGS. 5A and 5B are respectively schematic cross-sectional views corresponding to the A-A' and B-B' hatching lines of FIG. 4. In order to simplify the description, portions similar to those shown in Figs. 2, 3A and 3B will not be described here. Compared with FIG. 2, FIG. 3A and FIG. 3B, the thin film transistor 350 in the thin film transistor array substrate 300 of the present embodiment belongs to a top gate type thin film transistor, and the top gate type thin film transistor comprises a single gate polycrystalline germanium thin film transistor. Double gate polysilicon thin film transistors or other transistors. In the present embodiment, the thin film transistor 350 is exemplified by a polycrystalline germanium thin film transistor, but is not limited thereto.

Figure 6 is a partial cross-sectional view of the thin film transistor of Figure 4 taken along line CC'. Referring to FIG. 6 , the thin film transistor 350 has a semiconductor layer 360 , and the semiconductor layer 360 has a source region 362 electrically connected to the second wire 234 and a drain region 364 electrically connected to the pixel electrode 260 . In the present embodiment, the composition of the semiconductor layer 360 is polysilicon. Of course, the thin film transistor 350 still has a gate 252. To clearly illustrate the relationship between the various components, Hereinafter, the fabrication process of the thin film transistor array substrate 300 will be briefly described using the thin film transistor array substrate 300 of FIGS. 4, 5A, and 5B as an example.

Please refer to FIG. 4, FIG. 5A, FIG. 5B and FIG. First, a patterning process of the semiconductor layer 360 is performed on the substrate 210, and the gate insulating layer 370 is covered on the semiconductor layer 360. Then, a patterning process of the first conductive layer M1 is performed on the gate insulating layer 370 to form a plurality of scan lines 220, a plurality of gates 252, and a first wire between the adjacent scan lines 220 on the substrate 210. 232. Moreover, an ion doping process is performed on the semiconductor layer 360 such that the doped regions of the semiconductor layer 360 form an extrinsic semiconductor to form a source region 362 and a drain region 364, respectively. Next, a first insulating layer 270 is formed to cover the scan lines 220, the gates 252, and the first wires 232, wherein the first insulating layer 270, as shown in FIG. 5B, has a first contact window H1 to be exposed. A portion of each of the first wires 232, and the first insulating layer 270 has a source contact window Hs and a drain contact window Hd exposing the source region 362 and the drain region 364, respectively.

Then, a patterning process of the second conductive layer M2 is performed on the substrate 210 to form a plurality of second wires 234, a plurality of source electrodes 256, and a plurality of drain electrodes 258 on the first insulating layer 270, wherein the source 256 passes through The source contact window Hs is connected to the source region 362, the drain 258 is connected to the drain region 364 through the drain contact window Hd, and the second wire 234 is connected to the source 256. Next, a second insulating layer 280 is formed to cover the plurality of second wires 234, the plurality of source electrodes 256, and the plurality of drain electrodes 258, wherein the second insulating layer 280 has openings corresponding to the respective first contact windows H1 to expose the first portions The part of the wire 232 The second insulating layer 280 has a second contact window H2 to expose portions of the respective second wires 234, and the second insulating layer 280 has a third contact window H3 to expose the drains 258. Thereafter, a plurality of pixel electrodes 260 and a plurality of jumper layers 290 are formed on the second insulating layer 280, wherein each jumper layer 290 is connected to the first wires 232 and the first via the first contact window H1 and the second contact window H2, respectively. The two wires 234 are electrically connected, and the pixel electrode 260 is connected to the drain 258 via the third contact window H3.

As described above, in the present embodiment, for the upper pixel electrode 260, the first wire 232 overlapping the data line 230 has the same total spacing of the two insulating layers, such as the first insulating layer. 270 and the second insulating layer 270 can also reduce the parasitic capacitance between the pixel electrode 260 and the data line 230 without reducing the area of the pixel electrode 260, thereby effectively reducing the occurrence of crosstalk.

In summary, the thin film transistor array substrate of the present invention appropriately divides the data line into the first wire and the second wire which are connected in series with each other in response to the position of the data line, and stretches between the pixel electrode and the first wire. Therefore, the parasitic capacitance between the pixel electrode and the data line can be effectively reduced. Therefore, those skilled in the art can extend the pixel electrode in the design of the pixel structure without being restricted by the parasitic capacitance. To the top of the data line, to increase the aperture ratio of the pixels, thereby increasing the display brightness of the liquid crystal display.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended patent application. Prevail.

100, 200, 300‧‧‧ Film Transistor Array Substrate

110, 220‧‧‧ scan lines

120, 230‧‧‧ data line

130, 240‧‧‧ pixel structure

140, 350‧‧‧ film transistor

150, 260‧‧‧ pixel electrodes

160‧‧‧Insulation

210‧‧‧Substrate

232‧‧‧First wire

234‧‧‧second wire

250‧‧‧film transistor

252‧‧‧ gate

254‧‧‧channel layer

256‧‧‧ source

258‧‧‧汲polar

270‧‧‧First insulation

272‧‧‧ openings

280‧‧‧Second insulation

290‧‧‧jumper layer

360‧‧‧Semiconductor layer

362‧‧‧ source area

364‧‧‧Bungee Area

370‧‧‧Brake insulation

H1‧‧‧ first contact window

H2‧‧‧Second contact window

H3‧‧‧ third contact window

Hs‧‧‧ source contact window

Hd‧‧‧汲 contact window

M1‧‧‧ first conductive layer

M2‧‧‧Second conductive layer

1A is a top plan view of a conventional thin film transistor array substrate.

Fig. 1B is a schematic cross-sectional view taken along line AA' of Fig. 1A.

2 is a schematic view of a thin film transistor array substrate according to an embodiment of the present invention.

3A and 3B are respectively schematic cross-sectional views corresponding to the A-A' and B-B' hatching lines of Fig. 2.

Fig. 3C is another schematic cross-sectional view taken along line BB' of Fig. 2.

4 is a schematic view of a thin film transistor array substrate according to an embodiment of the present invention.

5A and 5B are respectively schematic cross-sectional views corresponding to the A-A' and B-B' hatching lines in Fig. 4.

Figure 6 is a partial cross-sectional view of the thin film transistor of Figure 4 taken along line CC'.

200‧‧‧thin film array substrate

210‧‧‧Substrate

220‧‧‧ scan line

230‧‧‧Information line

232‧‧‧First wire

234‧‧‧second wire

240‧‧‧ pixel structure

250‧‧‧film transistor

252‧‧‧ gate

254‧‧‧channel layer

256‧‧‧ source

258‧‧‧汲polar

260‧‧‧ pixel electrodes

290‧‧‧jumper layer

H1‧‧‧ first contact window

H2‧‧‧Second contact window

M1‧‧‧ first conductive layer

M2‧‧‧Second conductive layer

Claims (9)

A thin film transistor array substrate comprises: a substrate; a plurality of scanning lines disposed on the substrate and composed of a first conductive layer; a plurality of data lines disposed on the substrate, each of the data lines comprising a plurality of a first wire and a plurality of second wires, wherein the first wires and the second wires are arranged in parallel with each other and connected in series, each of the second wires spanning each of the scan lines, and each of the first wires is located at two phases Between the adjacent scan lines, the first conductive lines and the second conductive lines are respectively composed of the first conductive layer and a second conductive layer, and the distance between the first conductive layer and the substrate is smaller than the second a distance between the conductive layer and the substrate; a plurality of pixel structures disposed on the substrate, each of the pixel structures comprising: a thin film transistor, corresponding to the scan lines and corresponding to the second wires And a pixel electrode electrically connected to the thin film transistor, at least a portion of the pixel electrode extending over the adjacent first wires; a first insulating layer; a second insulating layer, wherein The first insulating layer covers the first a conductive layer, the second insulating layer covering the second conductive layer and the thin film transistors; and a jumper layer, the first insulating layer and the second insulating layer above the first wires have a plurality of a first contact window to expose both ends of each of the first wires, and the second insulating layer above the second wires Having a plurality of second contact windows to respectively expose two ends of each of the second wires, the jumper layer being electrically connected to each of the first wires by each of the first contact windows and each of the second contact windows Between each of the second wires. The thin film transistor array substrate of claim 1, wherein the first insulating layer and the second insulating layer are laminated between the pixel electrodes and the corresponding first wires. . The thin film transistor array substrate of claim 1, wherein the first wires and the second wires do not overlap on a projected area. The thin film transistor array substrate of claim 1, wherein the jumper layer has the same composition as the pixel electrodes. The thin film transistor array substrate of claim 1, wherein the first wires and the second wires at least partially overlap on a projected area, and the first wires overlap each of the second wires The first insulating layer in the region has an opening, and each of the second wires is connected to each of the first wires through the opening. The thin film transistor array substrate of claim 1, wherein each of the thin film transistors has a gate, a channel layer, a source, and a drain, and each of the gates is connected to a corresponding scan line. Each of the sources is connected to a corresponding second wire, and each of the drains is connected to each of the pixel electrodes. The thin film transistor array substrate of claim 6, wherein the gates are composed of the first conductive layer, the sources, the drains, and the second wires are second The conductive layer is composed of a conductive layer. The thin film transistor array substrate of claim 1, wherein each of the thin film transistors has a semiconductor layer, and the semiconductor layer has a source region electrically connected to the second wire and a picture The drain region where the element electrode is electrically connected. The thin film transistor array substrate of claim 1, wherein the first wires and the second wires are not coplanar, and the width of the first wires is substantially equal to the width of the second wires .