TWI499020B - Method of forming semiconductor substrate - Google Patents

Description

Semiconductor substrate manufacturing method

The present invention relates to a method of fabricating a semiconductor substrate, and more particularly to a method of fabricating a semiconductor substrate that avoids excessive warpage of the semiconductor substrate.

The flip chip technology, which has the advantages of reducing the chip package area and shortening the signal transmission path, has been widely used in the field of chip packaging, for example, Direct Chip Attached (DCA), Chip Scale Package (Chip Scale Package, CSP) and multi-chip module (MCM) and other types of package modules, the industry is now widely using flip chip technology to achieve the purpose of reducing the chip package area.

In the flip chip packaging process, the difference in thermal expansion coefficient is the main cause of the decrease in reliability between the smaller wafer and the package substrate. If the difference between the thermal expansion coefficients of the small-sized wafer and the package substrate is very large, the bumps on the periphery of the wafer will not form a good bond with the corresponding contacts on the package substrate, and when the volume changes due to temperature changes, The bumps are peeled off from the package substrate. Moreover, if the degree of integration of the integrated circuit increases and the volume becomes smaller, the thermal expansion coefficient mismatch problem and the thermal stress and warpage phenomenon are generated. It will also become more serious and will eventually lead to failure of the reliability test.

In order to solve the above problem of the difference in thermal expansion coefficient, a semiconductor package 1 having a semiconductor substrate as an intermediate structure has been developed. As shown in FIG. 1, a splicing interposer 2 is added to a package base. The board 9 is interposed between a semiconductor wafer 8. Since the tantalum interposer 2 is close to the material of the semiconductor wafer 8, both have the same or similar thermal expansion coefficients, so that problems caused by mismatch in thermal expansion coefficients can be effectively avoided.

The surface of the conventional interposer 2 to which the semiconductor wafer 8 is attached is defined as a crystal plane, and the surface to which the package substrate 9 is attached is defined as an interposer. In detail, the method of the conventional cymbal interposer 2 as shown in Figs. 2A to 2D is as follows.

As shown in FIG. 2A, a plurality of through-silicon vias (TSVs) 200 are formed in a single wafer 20, and the wafers 20 have opposite crystal planes 20a and intermediate faces 20b'. The crystal plane 20a is used to bond the semiconductor wafer 8 , and the intermediate surface 20 b ′ is used to bond the package substrate 9 .

As shown in FIG. 2B, a redistribution layer (RDL) 22 is formed on the crystal plane 20a of the wafer 20, and a plurality of conductive elements 26 are formed to connect the semiconductor wafer 8 to the wafer. 20 on the crystal face 20a. The number of circuit layers t of the line redistribution structure 22 is three layers.

As shown in FIG. 2C, part of the material of the intermediate surface 20b' of the wafer 20 is removed so that the hole end of the conductive crucible 200 protrudes from the intermediate surface 20b.

As shown in FIG. 2D, an insulating layer 210 is formed on the interposer 20a of the wafer 20 such that the surface of the insulating layer 210 is flush with the hole end of the conductive crucible 200. Then, a circuit layer 21 is formed on the surface of the insulating layer 210 and the hole end of the conductive germanium through hole 200, so that the circuit layer 21 is connected and electrically connected by the plurality of conductive bumps 25 (as shown in FIG. 1). The package substrate 9.

In the conventional interposer 2, the contact (I/O) of the semiconductor wafer 8 A plurality of circuit redistribution layers are disposed on the crystal plane 20a, for example, at least three circuit layers t are electrically connected to the semiconductor wafer 8 and the conductive germanium via 200, and if a plurality of semiconductors are combined At the time of the wafer 8, an electrical connection between the semiconductor wafers 8 can be provided. For example, a single semiconductor wafer 8 has 1000 contacts. After the fan out design of the line redistribution structure 22 on the crystal plane 20a, only 800 contacts are connected to the conductive turns 200. The other 200 contacts are used for electrical interconnection between multiple semiconductor wafers.

Moreover, the line width and the line spacing of the package substrate 9 are much larger than the contact pitch of the semiconductor wafer 8. Therefore, the interposer 20b may not be provided with a line (or the number of routing layers s is smaller than the RDL of the crystal plane 20a). The wiring structure, such as a layer, is such that the conductive germanium via 200 is directly electrically connected to the contact pad of the package substrate 9 (or the conductive layer vial 21 and the package substrate 9 are electrically connected by the wiring layer 21 of the intermediate surface 20b).

However, in the method of manufacturing the intermediate board 2, the line redistribution structure 22 on the crystal plane 20a is first formed, and then the circuit layer 21 on the intermediate surface 20b' is formed, so that the number of circuit layers is already A large number of lines re-arrange the structure 22, so when the material of the intermediate surface 20b' of the substrate body 20 is removed, the warpage of the wafer 20 is greatly increased, resulting in difficulty in performing the intermediate surface 20b. a line process, and when the 矽 interposer 2 is completed, the warp of the 矽 interposer 2 is too large, as shown in FIG. 2D', causing the package substrate 9 and the semiconductor wafer 8 to be electrically connected to each other. As a result, the reliability test fails, and the package substrate 9 and the semiconductor wafer 8 cannot be attached.

Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for fabricating a semiconductor substrate, comprising: providing a substrate body having a plurality of conductive vias therein, and the substrate system defines a relative crystal plane and an intermediate surface; a line redistribution structure is disposed on the intermediate surface of the substrate body; and a second line redistribution structure is formed on the crystal plane of the substrate body, and the number of circuit layers of the first line redistribution structure is less than the second line The number of circuit layers of the redistribution structure.

In the above method, the substrate is a germanium-containing substrate, and the crystallized surface is used to bond the wafer, and the intermediate surface is used to bond the package substrate.

In the above method, the first line redistribution structure or the second line redistribution structure is electrically connected to the conductive via.

In the above manufacturing method, the crystal plane of the substrate body is leveled before the second line redistribution structure is formed.

In the above method, conductive bumps are formed on the first line redistribution structure.

It can be seen from the above that the semiconductor substrate of the present invention is produced by first fabricating the first line redistribution structure on the interposer surface, and then fabricating the second line redistribution structure on the crystal plane, because before the leveling process, The first line redistribution structure has a small number of circuit layers, so that the warpage of the substrate body is greatly reduced after the leveling process, so that the line on the crystal plane is facilitated compared with the prior art. a process, and when the semiconductor substrate is completed, the semiconductor The warpage range of the bulk substrate is an acceptable range, that is, the package substrate and the semiconductor wafer are not affected by the electrical connection effect, and thus the reliability test can be passed.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

3A to 3D are schematic cross-sectional views showing a method of manufacturing the semiconductor substrate 3 of the present invention.

As shown in FIG. 3A, a substrate body 30 having a plurality of conductive vias 300 is provided, and the substrate body 30 defines an opposite crystal plane 30a' and an intermediate surface 30b, wherein the crystal plane 30a' is used. To combine a semiconductor wafer (such as the semiconductor wafer 8 shown in FIG. 1), and the intermediate surface 30b It is used to bond a package substrate (such as package substrate 9 shown in Fig. 1).

In this embodiment, the substrate body 30 is a germanium-containing substrate, such as a wafer or an interposer, and the conductive via 300 is a through silicon via (TSV).

As shown in FIG. 3B, a first line redistribution layer (RDL) 31 is formed on the intermediate surface 30b of the substrate body 30.

In this embodiment, the first circuit redistribution structure 31 is formed by stacking at least one dielectric layer 310, the circuit layer 311 and the conductive blind vias 312, and the outermost circuit layer 311 is formed with solder balls. The conductive bumps 35 are bonded to the package substrate.

Moreover, the first line redistribution structure 31 is electrically connected to the conductive via 300 by the conductive via 312.

As shown in FIG. 3C, the crystal plane 30a of the substrate body 30 is leveled by a grinding method so that the crystal plane 30a is flush with the hole end of the conductive via 300.

As shown in FIG. 3D, a second line redistribution structure (RDL) 32 is formed on the crystal plane 30a of the substrate body 30, and the number of circuit layers s of the first circuit redistribution structure 31 is less than the first The number of circuit layers t of the two-line redistribution structure 32.

In this embodiment, the number of circuit layers s of the first circuit redistribution structure 31 is one layer, and the number of circuit layers t of the second circuit redistribution structure 32 is three layers.

Furthermore, the second line redistribution structure 32 is also composed of a plurality of dielectric layers 320, The circuit layer 321 is formed by laminating the conductive blind holes 322, and a plurality of conductive elements 36 such as solder balls are formed on the outermost circuit layer 321 to bond the semiconductor wafer.

Moreover, the second circuit redistribution structure 32 is electrically connected to the conductive via 300 by the conductive blind vias 322.

In summary, the semiconductor substrate 3 of the present invention is mainly formed by first fabricating the first line redistribution structure 31 on the intermediate surface 30b, and then fabricating the second line redistribution structure 32 on the crystal plane 30a. Since the first line redistribution structure 31 having a small number of circuit layers s is used in the leveling process, the warpage of the substrate body 30 after the leveling process is compared with the prior art. The circuit process on the crystal plane 30a is facilitated, and when the semiconductor substrate 3 is completed, the warpage range of the semiconductor substrate 3 is an acceptable range, that is, the package substrate and the package are not affected. The semiconductor wafer is electrically connected to it and thus can pass the reliability test.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1‧‧‧Semiconductor package

2‧‧‧矽Intermediary board

20‧‧‧ wafer

20a, 30a, 30a’‧‧‧ crystal face

20b, 20b’, 30b‧‧Intermediary

200‧‧‧ Conductive piercing

21,311,321‧‧‧ circuit layer

210‧‧‧Insulation

22‧‧‧Line redistribution structure

25,35‧‧‧Electrical bumps

26,36‧‧‧Conductive components

3‧‧‧Semiconductor substrate

30‧‧‧Substrate body

300‧‧‧Electrical perforation

31‧‧‧First line redistribution structure

310,320‧‧‧ dielectric layer

312,322‧‧‧conductive blind holes

32‧‧‧Second line redistribution structure

8‧‧‧Semiconductor wafer

9‧‧‧Package substrate

s, t‧‧‧ lines

1 is a schematic cross-sectional view of a conventional semiconductor package; FIGS. 2A to 2D are schematic cross-sectional views showing a method of manufacturing a conventional interposer; wherein the 2D' is a reduced view of the 2D; 3A to 3D are schematic cross-sectional views showing a method of fabricating the semiconductor substrate of the present invention.

30‧‧‧Substrate body

30a‧‧‧ crystal face

30b‧‧‧Intermediary

300‧‧‧Electrical perforation

31‧‧‧First line redistribution structure

35‧‧‧Electrical bumps

Claims (8)

A method for fabricating a semiconductor substrate, comprising: providing a substrate body having a plurality of conductive vias therein, wherein the substrate system defines a relative crystal plane and an intermediate surface; and forming a first line redistribution structure on the substrate surface of the substrate body And forming a second line redistribution structure on the crystal plane of the substrate body, and the number of circuit layers of the first line redistribution structure is less than the number of circuit layers of the second line redistribution structure. The method of fabricating a semiconductor substrate according to claim 1, wherein the substrate system is a germanium-containing substrate. The method of fabricating a semiconductor substrate according to claim 1, wherein the crystallographic surface is used to bond a wafer. The method of fabricating a semiconductor substrate according to claim 1, wherein the interposer is used to bond the package substrate. The method of fabricating a semiconductor substrate according to claim 1, wherein the first circuit redistribution structure electrically connects the conductive vias. The method of fabricating a semiconductor substrate according to claim 1, wherein the second circuit redistribution structure is electrically connected to the conductive via. The method for fabricating a semiconductor substrate according to claim 1, further comprising flattening a crystal plane of the substrate body before forming the second line redistribution structure. The method for fabricating a semiconductor substrate according to claim 1, further comprising forming a conductive bump on the first line redistribution structure.