TWI495037B - Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same - Google Patents

Description

Semiconductor device having reduced thickness, electronic product using the same, and method of manufacturing the same

Example embodiments relate to a semiconductor device, to an electronic product using the device, and to a method of fabricating the device. More particularly, the exemplary embodiments relate to a semiconductor device having a reduced thickness, an electronic product using the device, and a method of fabricating the device.

Recently, in order to meet the demand for smaller semiconductor wafers for electronic products and to require lower power consumption, research is being conducted to reduce the size of an element constituting the semiconductor wafers.

Accordingly, embodiments are directed to a semiconductor device, an electronic product using the device, and a method of fabricating the device that substantially overcome one or more disadvantages of the related art.

Accordingly, a feature of an exemplary embodiment provides a semiconductor device structure having a reduced thickness.

Another feature of an exemplary embodiment is to provide an electronic product comprising a semiconductor device structure having a reduced thickness.

Yet another feature of an exemplary embodiment is to provide a method of fabricating a semiconductor device having a reduced thickness.

At least one of the above and other features and advantages can be achieved by providing a semiconductor device including a semiconductor substrate having a first active region and a second active region. A first transistor is provided in the first active region of the semiconductor substrate. The first transistor includes a first impurity region And a first gate pattern. A second transistor is provided in the second active region of the semiconductor substrate. The second transistor includes a second impurity region and a second gate pattern. A first conductive pattern is formed on the first transistor. At least a portion of the first conductive pattern is disposed on an upper surface of one of the semiconductor substrates at the same distance from at least a portion of the second gate pattern.

The first transistor may include a conductive first gate pattern provided in a gate trench spanning the first active region, and provided in the first active region at both sides of the first gate pattern a first impurity region, and a first gate dielectric layer provided between the first gate pattern and the gate trench.

Further included may include an insulative first gate cap pattern enclosing the gate trench along with the first gate pattern. The first gate cap pattern can have a raised portion that is higher than the first active region above the upper surface of the substrate.

Further included can include a first contact structure configured to electrically connect one of the first impurity regions to the first conductive pattern.

The second transistor may include a second gate pattern spanning the second active region, a second gate dielectric layer provided between the second gate pattern and the active region, and a second gate provided A second impurity region located at both sides of the second gate pattern in the active region. Herein, the second gate pattern may include a first gate electrode and a second gate electrode, which are sequentially stacked, and the second gate electrode may be disposed at a level substantially the same as the first conductive pattern. At the office.

The semiconductor device may further include a cell contact structure electrically connected to one of the first impurity regions, and a cell contact structure provided The data storage component on it.

The data storage element can be disposed at a higher level than the first conductive pattern.

Further provided is a conductive buffer pattern provided between the unit contact structure and the data storage element.

The data storage component can comprise one of a data storage material layer of a volatile memory device and a data storage material layer of a non-volatile memory device.

The method further includes a second conductive pattern disposed at a higher level than the first conductive pattern, and a second configured to electrically connect one of the second impurity regions to the second conductive pattern Contact structure.

The unit contact structure and the second contact structure may have surfaces disposed at different levels. Alternatively, the unit contact structure and the second contact structure may have surfaces disposed at substantially the same level.

Further included may be a connection structure configured to electrically connect the first conductive pattern and the second conductive pattern.

According to another exemplary embodiment, an electronic product including a semiconductor wafer is provided. The semiconductor wafer of the electronic product includes a semiconductor substrate having a cell array region and a peripheral circuit region. A unit transistor including a first impurity region and a first gate pattern on the semiconductor substrate of the cell array region may be provided. a peripheral transistor including a second impurity region on the semiconductor substrate of the peripheral circuit region, and a first peripheral gate electrode and a first layer of the second impurity region sequentially stacked on the substrate Two peripheral gate electrodes. A unit in the array area of the unit can be provided At least a portion of the transistor is at a same distance from a top surface of the semiconductor substrate and at least a portion of the second peripheral gate electrode.

According to still another exemplary embodiment, a method of fabricating a semiconductor device capable of having a reduced thickness is provided. The method includes preparing a semiconductor substrate having a first active region and a second active region to form a first transistor, the first active region including a first gate pattern and a first impurity region, wherein the second active region Forming a second transistor including a second gate pattern and a second impurity region, and forming a first conductive pattern on the first transistor. At least a portion of the first conductive pattern is disposed at an same distance from an upper surface of the semiconductor substrate and at least a portion of the second gate pattern. The first conductive pattern may be formed when the second transistor is formed.

Forming the first and second transistors and the first conductive pattern may include forming a first impurity region in the first active region, forming a gate trench across the first active region, forming a gate trench Forming a gate conductive pattern in the second active region, forming a buffer insulating pattern on the first active region, forming a buffer insulating pattern and the gate conducting a first conductive layer of the pattern, and patterning the first conductive layer on the buffer insulating pattern, and the gate conductive pattern and the first conductive layer are sequentially stacked on the second active region for the first A conductive pattern may be formed on the buffer insulating pattern, and one of the first gate electrode and the second gate electrode may be sequentially formed on the second active region.

After forming the first gate pattern, further comprising forming a first gate cap pattern filling the gate trench along with the first gate pattern on the first gate pattern. The first gate cap pattern may have a protrusion at a higher level than the first active region.

The buffer insulating pattern may be formed after the gate conductive pattern is formed. Alternatively, the gate conductive pattern may be formed after the buffer insulating pattern is formed.

Before forming the first conductive pattern, further comprising forming a first contact structure configured to pass through the buffer insulating pattern and electrically connect to one of the first impurity regions. The first conductive structure can be electrically connected to the first conductive pattern.

The method further includes forming a first interlayer insulating layer on the substrate having the first conductive pattern, forming a one configured to pass through the first interlayer insulating layer, and electrically connecting to one of the first impurity regions The unit contact structure and a data storage element are formed on the unit contact structure.

Further included, when forming the cell contact structure, forming a perimeter contact structure configured to pass through the first interlayer insulating layer and electrically connected to one of the second impurity regions, and in the first layer A second conductive pattern electrically connected to the peripheral contact structure is formed on the insulating layer.

Further, the method further includes forming a buffer pattern electrically connected to the cell contact structure on the first interlayer insulating layer when the second conductive pattern is formed.

Meanwhile, the method further includes forming a second interlayer insulating layer on the first interlayer insulating layer, forming a structure to pass through the first interlayer insulating layer and the second interlayer insulating layer, and electrically connecting to the first layer One of the two impurity regions a second contact structure and a second conductive pattern formed on the second interlayer insulating layer.

According to still another exemplary embodiment, a method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having a first region and a second region. An insulating pattern is formed on the semiconductor substrate of the first region. A conductive pattern is formed on the semiconductor substrate of the second region. A conductive layer covering the conductive pattern and the insulating pattern is formed. The conductive layer and the conductive pattern are patterned to form an interconnect structure on the insulating pattern, and one of the first gate electrode and the second gate electrode are sequentially stacked on the semiconductor substrate of the second region.

Korean Patent Application No. 10-2007-0094725 filed on September 18, 2007, and No. 10-2008-0083457 filed on August 26, 2008 (in Korean Intellectual Property Office) The semiconductor device of reduced thickness, the electronic device using the device, and the method of manufacturing the device (Semiconductor Device Having Reduced Thickness, Electronic Product Employing the Same, and Methods of Fabricating the Same) are incorporated herein by reference in their entirety. in.

Example embodiments will now be described in more detail below with reference to the drawings; however, it will be construed in a different form and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention is disclosed to those skilled in the art.

In these figures, the layers and areas are enlarged for ease of clarity. Inch. It will also be understood that when a layer or element is referred to as being on another layer or substrate, it may be directly on another layer or substrate, or an intermediate layer may also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it may be directly below it, and one or more intermediate layers may also be present. In addition, it should also be understood that when a layer is referred to as "between" the "layer", it may be the only layer between the two layers, or one or more intermediate layers may be present. Throughout the drawings, the same reference numerals refer to the same elements.

As used herein, the expression "at least one", "one or more" and "and/or (or/or)" is an open expression of connection and transition. For example, expressing "at least one of A, B, and C", "at least one of "A, B, or C", "one or more of A, B, and C", "A, B, or One or more of C "and" A, B and/or C" include the following meanings: A alone; B alone; C alone; A and B; both A and C; B and C And A, B and C. Further, such expressions are open-ended unless explicitly stated to the contrary by the combination of the term "consisting of". For example, the expression "at least one of A, B, and C" may also include an nth member, where n is greater than 3, and the expression "at least one selected from the group consisting of free A, B, and C" It does not mean this.

As used herein, the term "a" and "an" are used in conjunction with the singular or plural terms.

A semiconductor device according to an example will now be explained in more detail below with reference to FIG. FIG. 1 illustrates a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment.

Referring to FIG. 1, a semiconductor device may include a semiconductor substrate 500, a semiconductor The first transistor AT1 and the second transistor AT2 on the body substrate 500 are located on the first transistor AT1 so that at least a portion thereof is at substantially the same height as a portion of the second gate pattern 540 of the second transistor AT2 ( For example, the first conductive pattern 539a is in a first direction (ie, the y-axis) above the upper surface 500a of the semiconductor substrate 500).

The semiconductor substrate 500 may have a first area A1, a second area A2, and an intermediate area B. The semiconductor substrate 500 can be a semiconductor wafer containing a semiconductor material such as germanium. The first area A1 may be a memory cell array area, and the second area A2 may be a peripheral circuit area. The intermediate region B may correspond to a predetermined region between a first device (eg, a unit transistor) on the first region A1 and a second device (eg, a peripheral transistor) on the second region A2. It should be noted that although the intermediate region B is illustrated as a separate region between the first region A1 and the second region A2 in FIG. 1, other configurations of the intermediate region B are also within the scope of the present invention, such as the intermediate region B. It may be disposed in a memory cell array region (eg, first region A1) or may be disposed in a peripheral circuit region (eg, second region A2).

An isolation region 503s defining the first active region 503a and the second active region 503b may be provided in the semiconductor substrate 500. The isolation region 503s can be a trench isolation layer. The isolation region 503s may define a first active region 503a within the first region A1, such as a unit active region, and may define a second active region 503b in the second region A2, such as a peripheral active region.

The first transistor AT1 may be provided in the first active region 503a. The first transistor AT1 may include first impurity regions 518a and 518b in the first active region 503a, a first channel region between the first impurity regions 518a and 518b, A first gate dielectric layer 521 and a first gate pattern 524. The first transistor AT1 may have a recessed channel, so that the first gate dielectric layer 521 and the first gate pattern 524 may be sequentially stacked in the gate trench 515 in the first channel region. The first gate pattern 524 can be a unit gate electrode.

More specifically, a gate trench 515 may be formed in the semiconductor substrate 500. The gate trench 515 may have a predetermined depth along a first direction (eg, in a downward direction from an upper surface 500a of the semiconductor substrate 500 along the y-axis) and may span the first active region 503a. The gate trench 515 can extend toward the isolation region 503s. The first gate pattern 524 can be provided in the gate trench 515 such that the first gate pattern 524 can extend across the first active region 503a and toward the isolation region 503a.

For example, the first gate pattern 524 can partially fill the gate trench 515 such that a first gate cap pattern 527 can fill the remaining portion of the gate trench 515. In other words, as illustrated in FIG. 1 , the first gate pattern 524 and the first gate cap pattern 527 may be sequentially stacked in the gate trench 515 so that one of the first gate cap patterns 527 is on the upper surface. It may be substantially horizontal (i.e., coplanar) with the upper surface 500a of the semiconductor substrate 500. The first gate cap pattern 527 may be formed of a layer of insulating material.

The first gate dielectric layer 521 can be inserted between the inner wall of the gate trench 515 and the first gate pattern 524. For example, the first gate dielectric layer 521 can be located on the entire inner wall of the gate trench 515. . The first impurity regions 518a and 518b may be provided in the upper region of the first active region 503a, that is, the upper surfaces of the first impurity regions 518a and 518b may be on the upper surface of the semiconductor substrate 500 at both sides of the gate trench 515. 500a is substantially horizontal, that is, the first gate in the gate trench 515 The capping pattern 527 may be located between the first impurity regions 518a and 518b.

The second transistor AT2 can be provided in the second active region 503b. The second transistor AT2 may include second impurity regions 548a and 548b in the second active region 503b, a second channel region between the second impurity regions 548a and 548b, a second gate dielectric layer 506a and a The second gate pattern 540. The second gate dielectric layer 506a and the second gate pattern 540 may be sequentially stacked on the second channel region. The second gate pattern 540 may include a lower gate electrode 509g and an upper gate electrode 539g stacked in sequence. An insulated second gate cap pattern 542g may be provided on the second gate pattern 540.

The lower gate electrode 509g and the upper gate electrode 539g may be formed of a substantially the same material or different materials. For example, the upper gate electrode 539g may be formed of a conductive material having a higher conductivity than the lower gate electrode 509g. For example, the lower gate electrode 509g may include a doped polysilicon layer, and the upper gate electrode 539g may include a metal material layer. , such as a tungsten layer. Considering the ohmic contact characteristics between a polysilicon layer and a metal material layer, a metal germanide layer can be inserted between the upper gate electrode 539g and the lower gate electrode 509g. In another example, the upper gate electrode 539g and the lower gate electrode 509g may be formed of a substantially identical conductive material.

The first conductive pattern 539a may be provided on the first transistor AT1 with a buffer insulating pattern 536 therebetween. The buffer insulation pattern 536 may be provided on the first region A1 and the intermediate region B of the semiconductor substrate 500 to cover the first transistor AT1 and the first gate cap pattern 527. The first conductive pattern 539a may be a linear structure provided on the buffer insulating pattern 536, such as a straight line shape. The first conductive pattern 539a may be defined as a unit bit line. At least a portion of the first conductive pattern 539a may be disposed in a first direction (eg, For example, the y-axis is at substantially the same height from at least a portion of the second gate pattern 540. For example, at least a portion of the first conductive pattern 539a can be disposed at substantially the same level from at least a portion of the upper gate electrode 539g, that is, at the same height above the upper surface 500a of the semiconductor substrate 500 along the y-axis. In another example, the lower surface of the first conductive pattern 539a may be substantially coplanar with the lower surface of the upper gate electrode 539g along the xz plane so as to be from each of the lower surface of the first conductive pattern 539a and the upper gate electrode 539g. The distance to, for example, the upper surface 500a of the semiconductor substrate 500 may be substantially equal. The first conductive pattern 539a may comprise a substantially identical conductive material and may be formed by a process substantially the same as the upper gate electrode 539g.

A first contact structure 538p can electrically connect one region 518a of the first impurity regions 518a and 518b to the first conductive pattern 539a. The first contact structure 538p may pass through the buffer insulation pattern 536.

A first insulating cap pattern 542a may be provided on the first conductive pattern 539a. A first insulating spacer 545a may be provided on sidewalls of the first conductive pattern 539a and the first insulating cap pattern 542a. A second insulating spacer 545g may be provided on the sidewalls of the second gate pattern 540 and the second gate cap pattern 542b. The first insulating spacer 545a and the second insulating spacer 545g may comprise a substantially identical layer of insulating material formed by the same process.

A first interlayer insulating layer 551 covering the entire surface of the first region A1 and the second region A2 and the intermediate region B of the semiconductor substrate 500 may be provided. The first interlayer insulating layer 551 may have a planarized upper surface disposed in a first direction (eg, the y-axis) than the upper surface of the first insulating capping pattern 542a and the second gate capping pattern 542g High level. Another option is the first layer The interlayer insulating layer 551 may have a planarized upper surface disposed at substantially the same level as the upper surface of the first insulating capping pattern 542a and the second gate capping pattern 542g, as illustrated in FIG. A second interlayer insulating layer 584 may be provided on the first interlayer insulating layer 551.

A second conductive pattern 575 can be provided on the second interlayer insulating layer 584. The second conductive pattern 575 can be electrically connected to the first conductive pattern 539a via a conductive connection structure 572a. The connection structure 572a can be interposed between the first conductive pattern 539a and the second conductive pattern 575, and can substantially pass through the second interlayer insulating layer 584 and the first insulating cap pattern 542a, as illustrated in FIG.

A second contact structure 572b interposed between one of the regions 548a of the second impurity regions 548a and 548b and the second conductive pattern 575 can electrically connect the region 548a of the second transistor AT2 to the second conductive pattern 575. The second contact structure 572b may include a contact structure 571a passing through the lower interlayer insulating layer 551 and a contact structure 571b passing through the second interlayer insulating layer 584. The lower contact structure 571a and the upper contact structure 571b may be formed of a conductive material layer formed by processes different from each other. Alternatively, the lower contact structure 571a and the upper contact structure 571b may be formed from a substantially identical layer of material formed by substantially the same process.

The semiconductor device can further include a data storage element 597 on the semiconductor substrate 500. The data storage component 597 can include first and second electrodes, and a layer of data storage material disposed between the first and second electrodes. The data storage element 597 can be disposed over a region of the first impurity regions 518a and 518b of the first transistor AT1 and can be electrically coupled to the region 518b via a cell contact structure 560, as illustrated in FIG. Unit contact structure 560 can The buffer insulating pattern 536 is passed through and through the first interlayer insulating layer 551. That is, the first transistor AT1 can be electrically connected to the first conductive pattern 539a via the first contact structure 538p and a first impurity region 518a, and electrically connected to the data storage via the cell contact structure 560 and another first impurity region 518b. Element 597.

The data storage component 597 can include a layer of data storage material such as a capacitor dielectric layer of a volatile memory device such as a DRAM, but is not limited thereto. For example, the data storage component 597 can comprise a layer of ferroelectric material composed of FeRAM, or a layer of data storage material composed of a non-volatile memory device, such as a phase change material layer composed of PRAM. The data storage element 597 can be located at a higher level than the first conductive pattern 539a, as illustrated in FIG. 1, so that the distance from the lower surface of a data storage element 597 to the upper surface 500a of the semiconductor substrate 500 along the y-axis can be It is larger than a distance from the upper surface of the first conductive pattern 539a to the upper surface 500a of the semiconductor substrate 500. At least a portion of the data storage element 597 can be disposed at a substantially identical or lower level than the second conductive pattern 575. For example, as further illustrated in FIG. 1, the lower portion of the data storage element 597 can pass through the second interlayer insulating layer 584.

The arrangement of the data storage element 597, the first conductive pattern 539a, and the upper gate electrode 539g as described above can minimize the distance between the data storage element 597 and the first transistor AT1 in the first direction (eg, the y-axis) In order that the total thickness of the semiconductor device measured in the first direction can be reduced. In other words, since the first conductive pattern 539a (ie, the cell bit line) between the data storage element 597 and the first transistor AT1 can be combined with a peripheral circuit region (ie, the second transistor) The upper gate electrode 539g of the body AT2) is disposed at a substantially same level, and the distance between the first conductive pattern 539a and the first active region 503a and the distance between the data storage element 597 and the first active region 503a are both minimize. Accordingly, the total thickness of the semiconductor device can be minimized, and a process margin for forming the cell contact structure 560 between the data storage element 597 and the first active region 503a can be increased.

A semiconductor device according to another exemplary embodiment will now be described below with reference to FIG. Referring to FIG. 2, a semiconductor device can include substantially the same components as the semiconductor device previously described with reference to FIG. Elements that are substantially identical will be designated as "corresponding to" elements of the previously described elements, and a detailed description thereof will not be repeated.

Referring to FIG. 2, a semiconductor device can include a semiconductor substrate 600 having a first region D1 and a second region D2, an intermediate region E, and a first region 603a and a second region 603b defined by an isolation region 603s. The semiconductor substrate 600 having the regions D1, D2, and E, and the active regions 603a and 603b defined by the isolation regions 603s, can be correspondingly defined by the regions A1, A2, and B previously defined with reference to FIG. 1, and defined by the isolation regions 503s. The semiconductor substrates 500 of the regions 503a and 503b are substantially the same.

As further illustrated in FIG. 2, the semiconductor device can include a first transistor DT1 and a second transistor DT2 on the semiconductor substrate 600. The first transistor DT1 may include first impurity regions 618a and 618b, a first gate dielectric layer 621, and a first gate pattern 624, which respectively correspond to the first impurity regions 518a and 518b of FIG. A gate dielectric layer 521 and a first gate pattern 524. The first gate pattern 624 can be provided in a gate trench 615 (corresponding to Figure 1 shows the gate trench 515). The first transistor DT1 can further include a first gate cap pattern 627 on the first gate pattern 624 in the gate trench 615. The first gate cap pattern 627 may extend over the upper surface 600a of the semiconductor substrate 600, that is, may have a surface disposed at a higher level than the upper surface of the first active region 603a. The first gate cap pattern 627 may be formed of an insulating material.

The second transistor DT2 may include second impurity regions 648a and 648b, a second gate dielectric layer 606a, and a second gate pattern 640, which respectively correspond to the second impurity regions 548a and 548b of FIG. The second gate dielectric layer 506a and the second gate pattern 540. The second gate pattern 640 may include a lower gate electrode 609g and an upper gate electrode 639g stacked in sequence. A second gate cap pattern 542g and a second insulating spacer 645g respectively corresponding to the second gate cap pattern 542g and a second insulating spacer 545g of FIG. 1 may be provided on the semiconductor substrate of the second region D2. 600 on.

A buffer insulating pattern 636 covering the isolation region 603s and the first impurity regions 618a and 618b may be provided on the first region D1 and the intermediate region E of the semiconductor substrate 600. The buffer insulation pattern 636 may be formed of an insulating material having an etch selectivity with respect to the first gate cap pattern 627. For example, when the first gate cap pattern 627 includes a tantalum nitride layer, the buffer insulating pattern 636 may include a hafnium oxide layer.

As further illustrated in FIG. 2, the semiconductor device can include a first conductive pattern 639a, a first insulating cap pattern 642a, a first insulating spacer 645a, and a first contact structure 638p, which respectively correspond to the previous reference. The first conductive pattern 539a, the first insulating cover pattern 542a, The first insulating spacer 545a and the first contact structure 538p. A first interlayer insulating layer 651 corresponding to the first interlayer insulating layer 551 of FIG. 1 may be provided on the first region D1 and the second region D2 of the semiconductor substrate 600 and the intermediate region E.

A cell contact structure 660 may be provided that passes through the first interlayer insulating layer 651 and the buffer insulating pattern 636 and is electrically connected to one of the first impurity regions 618a and 618b. A portion of the first gate cap pattern 627 that protrudes above the first impurity regions 618a and 618b can be disposed between the cell contact structure 660 and the first contact structure 638p, as illustrated in FIG. Therefore, the protrusion of the first gate cap pattern 627 can avoid a short circuit between the cell contact structure 660 and the first contact structure 638p. A portion of the first gate dielectric layer 621 can be disposed between the first gate cap pattern 627 and each of the cell contact structure 660 and the first contact structure 638p.

A second contact structure 672b may be provided that passes through the first interlayer insulating layer 651 and is electrically connected to one of the first impurity regions 648a and 648b. The second contact structure 672b can be provided at substantially the same level as the cell contact structure 660. For example, the second contact structure 672b and the upper surface of the cell contact structure 660 can be substantially coplanar, and the second contact structure 672b and the cell contact structure 660 The lower surface can be substantially coplanar along the xz plane. The second contact structure 672b and the cell contact structure 660 can comprise a substantially identical conductive material.

As further illustrated in FIG. 2, the semiconductor device further includes a conductive buffer pattern 675b and a second conductive pattern 675a on the first interlayer insulating layer 651. The conductive buffer pattern 675b may cover the cell contact structure 660, and the second conductive pattern 675a may cover the second contact structure 672b. Conduction buffer The pattern 675b and the second conductive pattern 675a may be spaced apart along the x-axis and may be disposed at substantially the same level. For example, the conductive buffer pattern 675b and the lower surface of the second conductive pattern 675a may be substantially coplanar along the xz plane. The conductive buffer pattern 675b and the second conductive pattern 675a may be formed of a substantially identical material.

A connection structure 672a can penetrate the first insulating cover pattern 642a to connect the first conductive pattern 639a with the second conductive pattern 675a. For example, the first conductive pattern 639a, the connection structure 672a, and the second conductive pattern 675a may be sequentially stacked, so that the connection structure 672a may be inserted between the first conductive pattern 639a and the second conductive pattern 675a, and may be electrically connected. The first conductive pattern 639a and the second conductive pattern 675a.

A second interlayer insulating layer 684 may be disposed on the first interlayer insulating layer 651 to surround the sidewalls of the conductive buffer pattern 675b and the second conductive pattern 675a. For example, the upper surfaces of the second interlayer insulating layer 684, the conductive buffer pattern 675b, and the second conductive pattern 675a may be substantially coplanar in the xz plane.

As further illustrated in FIG. 2, the semiconductor device can further include a data storage element 697 on the conductive buffer pattern 675b. Correspondingly, the data storage element 697 can be located at a higher level than the second conductive pattern 675a, that is, the lower surface of the data storage element 697 is spaced apart from the upper surface 600a of the semiconductor substrate 600 and the upper surface of the second conductive pattern 675a. Farther apart. The data storage component 697 can correspond to the data storage component 597 of FIG. 1 in terms of type and component.

A method of fabricating a semiconductor device in accordance with an exemplary embodiment will now be described with reference to FIGS. 3-19. 3 illustrates a plan view of a semiconductor device in accordance with an exemplary embodiment, and FIGS. 4A-12B illustrate an example according to an example. A cross-sectional view of a method of fabricating a semiconductor device, FIGS. 13A-17B illustrate a cross-sectional view of a method of fabricating a semiconductor device in accordance with another exemplary embodiment, and FIGS. 18A-19 illustrate a further implementation according to another example A cross-sectional view of a method of fabricating a semiconductor device.

It should be noted that FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A illustrate sequential cross-sectional views taken along line II' of FIG. 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B and 19 illustrate a cross-sectional view taken along line II-II' of FIG. In FIGS. 3-19, reference numeral C represents a first area, reference symbol M represents an intermediate area, and reference symbol P represents a second area.

First, a method of fabricating a semiconductor device in accordance with an exemplary embodiment will be described below with reference to FIGS. 3 and 4A-12B.

Referring to FIGS. 3 and 4A-4B, a semiconductor device can include a semiconductor substrate 1 having a first region C and a second region P, and an intermediate region M, and a first active region 3a defined by an isolation region 3s and The second active area 3b. The semiconductor substrate 1 having the regions C, P and M, and the active regions 3a and 3b defined by the isolation regions 3s may respectively correspond to the regions A1, A2 and B and the active regions defined by the isolation regions 503s as previously explained with reference to FIG. The semiconductor substrate 500 of 503a and 503b.

A preliminary impurity region (not shown) having a different conductivity type than the region C of the semiconductor substrate 1 may be formed in the first active region 3a. For example, when the first active region 3a is of a P type, impurity ions may be implanted into the first active region 3a so as to be shaped in the region above the first active region 3a. A preliminary impurity region of type N (not shown).

A dielectric layer 6 and a gate conductive layer 9 are sequentially stacked on the semiconductor substrate 1. The dielectric layer 6 can be formed to include at least one of a hafnium oxide layer and a high K dielectric. As used herein, a high K dielectric may comprise a dielectric material having a higher dielectric constant than a hafnium oxide layer. The gate conductive layer 9 may be formed of a layer of conductive material (eg, a polysilicon layer).

The gate conductive layer 9 and the dielectric layer 6 on the first region C may be patterned to expose predetermined portions of the first active region 3a and the isolation region 3s. Then, the exposed portions of the first active region 3a and the isolation region 3s may be etched to form a gate trench 15. The gate trench 15 may be formed to extend across the first active region 3a and toward the isolation region 3s. The gate trench 15 can have a line width that is less than the resolution limit of a lithographic process.

The gate trench 15 may be formed to span the first active region 3a within the preliminary impurity region. Therefore, the preliminary impurity regions can be divided into unit impurity regions separated from each other by the gate trenches 15, that is, the gate trenches 15 can define the cell source/drain regions 18a and 18b. For example, the preliminary impurity region can be divided into three unit impurity regions 18a and 18b by a pair of gate trenches 15. If three unit impurity regions are formed, one impurity region disposed between the pair of gate trenches 15 may be defined as a first unit impurity region 18a, and the remaining impurity regions may be defined as second impurity regions 18b. .

Referring to Figures 3, 5A-5B, a cell gate dielectric layer 21 having a cell gate trench 15 can be formed over the semiconductor device. The cell gate dielectric layer 21 may be formed to coat the inner wall of the cell gate trench 15 in the first active region 3a. The unit gate dielectric layer 21 can be formed to include a hafnium oxide layer and a high-k dielectric layer At least one of them.

A cell gate pattern 24 can be formed on the cell gate dielectric layer 21 within the cell gate trench 15. The cell gate pattern 24 can fill at least a portion of the gate trench 15. For example, the cell gate pattern 24 may partially fill the gate trench 15 so that the upper surface of the first active region 3a may be higher than the upper surface of the cell gate pattern 24 along the y-axis, that is, the first active region 3a. The upper surface is farther from the bottom of the gate trench 15 than from the upper surface of the cell gate pattern 24. The cell gate pattern 24 at a portion of the cross cell active region 3a may be defined as a cell gate electrode. The cell gate pattern 24 can be formed to include at least one of a metal layer, a metal nitride layer, a metal telluride layer, and a polysilicon layer. The cell source/drain region 18, the cell gate dielectric layer 21, and the cell gate pattern 24 may constitute unit transistors CT1 and CT2. That is, the unit transistors CT1 and CT2 may be buried channel array transistors (BCAT).

A cell gate cap pattern 27 filling the remaining portion of a gate trench 15 can be formed. The cell gate cap pattern 27 may be formed on the cell gate pattern 24 to include at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer.

A mask pattern 30 may be formed on the gate conductive layer 9 in the second region P such that a portion of the gate conductive layer 9 in the first region C and the intermediate region M may be exposed by the mask pattern 30. The mask pattern 30 can be a photoresist pattern. Alternatively, the mask pattern 30 may be formed of an insulating layer such as a hafnium oxide layer or a tantalum nitride layer.

Referring to FIGS. 3 and 6A-6B, the gate conductive layer 9 in the first region C and the intermediate region M may be etched into an etch mask using the mask pattern 30 to be in the second region. A gate conduction pattern 9a is formed in the domain P. It should be noted that in other embodiments, that is, an exemplary embodiment including a method of fabricating the first impurity regions 18a and 18b that is different from the previously described method, the gate conductive pattern 9a can be used on the substrate 1. An ion implantation process is performed to form first impurity regions, that is, cell source/drain regions 18a and 18b, in the cell active region 3a. It should be further noted that when etching the first region C, the intermediate region M, and the second region P, a portion of the dielectric layer 6, the cell gate dielectric layer 21, and the cell gate cap pattern 27 may be etched.

Once the gate conductive pattern 9a is formed, the mask pattern 30 can be removed. A stop layer 33 may be formed on a portion of the semiconductor substrate 1 from which the mask pattern 30 may be removed. The stop layer 33 may be formed of an insulating material having an etch selectivity with respect to the isolation region 3s. For example, when the isolation region 3s is formed of a tantalum oxide layer, the stop layer 33 may be formed of a tantalum nitride layer. The stop layer 33 can be conformally formed. The stop layer 33 may cover the isolation region 3s of the first region C and the cell transistors CT1 and CT2, and may cover the gate conduction pattern 9a in the second region P.

A buffer insulating layer (not shown) may be formed on the stop layer 33. The buffer insulating layer may be formed of a material layer having an etch selectivity with respect to the stop layer 33. For example, when the stop layer 33 is formed of a tantalum nitride layer, the buffer insulating layer may be formed of a tantalum oxide layer. The buffer insulating layer may be planarized to expose the upper surface of the stop layer 33 in the M region and the upper surface of the gate conductive pattern 9a in the second region P, so that the planarized buffer insulating pattern 36 may be formed in the first region On the stop layer 33 in C.

Referring to Figures 3 and 7A-7B, a cover can be formed on the buffer insulation pattern 36. Edge layer 37. The cap insulating layer 37 may be formed of an insulating material such as a hafnium oxide layer or a tantalum nitride layer. The cap insulating layer 37, the buffer insulating pattern 36, and the stop layer 33 may be patterned to form a bit line contact hole 36a exposing the first impurity region 18a. For example, the bit line contact hole 36a may be formed to expose the first cell impurity region 18a of the shared cell transistors CT1 and CT2.

A first conductive layer 38 may be formed on the semiconductor substrate 1 having the bit line contact holes 36a. The first conductive layer 38 can be formed to include at least one of a metal layer, a metal nitride layer, a metal telluride layer, and a poly germanium layer. For example, the first conductive layer 38 can be formed to include a Ti layer, a TiN layer, and a W layer, which are sequentially stacked. Herein, the W layer may fill the bit line contact hole 36a, and the sequentially stacked Ti and TiN layers may be interposed between the bit line contact hole 36a and one of the W walls to serve as a diffusion barrier layer.

A portion of the first conductive layer 38 in contact with the first impurity region 18a may be formed of a metal telluride. For example, a metal telluride layer may be formed on the first impurity region 18a, and a metal material layer may fill the bit line contact hole 36a to form the first conductive layer 38. In another example, the first and second electrodes may be sequentially disposed in the bit line contact hole 36a, followed by an annealing process of the metal layer, so that the metal of the first metal layer can react with the first impurity region 18a. A metal telluride layer is formed between the first conductive layer 38 and the first impurity region 18a.

Referring to Figures 3 and 8A-8B, the first conductive layer 38 can be processed to form a first contact structure, i.e., a one-bit line contact structure 38p, within the bit line contact hole 36a. For example, the first conductive layer 38 can be planarized by, for example, a chemical mechanical polishing (CMP) to expose the stop layer 33 in the second region P, followed by The stop layer 33 is etched. In another example, the first conductive layer 38 can be planarized to expose the gate conductive pattern 9a within the second region P. The cap layer 37 can be removed during the planarization process.

Next, a second conductive layer 39 covering the bit line contact structure 38p and the exposed gate conductive pattern 9a may be formed. The second conductive layer 39 can be formed to include at least one of a metal layer, a metal nitride layer, a metal telluride layer, and a poly germanium layer. In an exemplary embodiment, the second conductive layer 39 can be formed to include a conductive material different from the gate conductive pattern 9a. The second conductive layer 39 can be formed to include a layer of conductive material having a higher electrical conductivity than the gate conductive pattern 9a. For example, the gate conductive pattern 9a may be formed of a doped polysilicon layer, and the second conductive layer 39 may be formed to include a metal material layer, such as a tungsten layer. Herein, the ohmic contact characteristic between a metal material layer (for example, a tungsten layer) and the gate conductive pattern 9a is considered, and a portion of the second conductive layer 39 in contact with the gate conductive pattern 9a may be formed of a metal germanide layer. In another exemplary embodiment, the gate conductive pattern 9a and the second conductive layer 39 may be formed of a substantially identical layer of conductive material.

In some example embodiments, after the buffer insulating pattern 36 of FIGS. 7A and 7B is formed, or when the buffer insulating pattern 36 is formed, a process of exposing the gate conductive pattern 9a in the second region P may be performed. For example, the buffer insulating layer 36 may be planarized to expose the gate conductive pattern 9a such that the stop layer 33 in the second region P may be removed during the planarization process. In another example, after the buffer insulating layer 36 is planarized into the planarization stop layer 33 in the second region P using the stop layer 33, the stop layer in the second region P may be etched. 33, so that the buffer insulating pattern 36 and the stop layer 33 may be patterned to form the bit line contact hole 36a exposing the first impurity region 18a. A conductive layer filling the bit line contact hole 36a and covering the buffer insulating pattern 36 and the gate conductive pattern 9a may be formed, for example, a conductive layer made of the same material as the first conductive layer 38. Accordingly, the second conductive layer 39 and the bit line contact structure 38p can be formed to include the same material layer formed by the same process.

Referring to Figures 3 and 9A-9B, a mask layer can be formed on the second conductive layer 39. The mask layer may be formed to include at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer. The mask layer, the second conductive layer 39, and the gate conductive pattern 9a may be patterned so that one of the first conductive patterns 39a and the one-bit line cap pattern 42a may be sequentially formed on the first region C, and One of the first peripheral gate electrodes 9g, a second peripheral gate electrode 39g, and a peripheral capping pattern 42b may be formed to be sequentially stacked on the second region P. Accordingly, the first conductive pattern 39a and the second peripheral gate electrode 39g may be simultaneously formed and may be formed of the same material layer. Further, the first conductive pattern 39a and the second peripheral gate electrode 39g may be disposed substantially at the same level.

The first peripheral gate electrode 9g and the second peripheral gate electrode 39g may be defined as a peripheral gate pattern 40. The first conductive pattern 39a can be defined as a unit bit line. The peripheral gate pattern 40 and the first conductive pattern 39a may respectively correspond to the peripheral gate pattern 540 of FIG. 1 and the peripheral gate pattern 640 of FIG. 2 and the first conductive pattern 539a of FIG. 1 and the first conductive pattern 639a of FIG. . The cell bit line 39a may extend upward to the intermediate region M. The peripheral gate pattern 40 can be substantially linear and can extend over the isolation region 3s to span the perimeter active region 3b and define the perimeter active region 3b. In addition, a peripheral gate dielectric layer 6a can be mentioned Provided between the peripheral gate pattern 40 and the peripheral active region 3b.

A one-line spacer 45a may be formed on one of the sequentially stacked cell bit lines 39a and one of the bit line cap patterns 42a. A peripheral gate spacer 45g may be formed on the sidewalls of the peripheral gate pattern 40 and the peripheral gate cap pattern 42g which are sequentially stacked. The peripheral gate spacers 45g and the bit line spacers 45a may be formed to include at least one of a tantalum nitride layer, a hafnium oxynitride layer, and a hafnium oxide layer.

Impurity ions may be implanted into the peripheral active region 3b at both sides of the peripheral gate pattern 40 to be activated so that a peripheral impurity region, that is, a peripheral source/drain region 48, may be formed. Therefore, a peripheral transistor including a peripheral source/drain region 48, a peripheral gate dielectric layer 6a, a peripheral gate pattern 40, and a channel region in the peripheral active region 3b below the peripheral gate pattern 40 can be formed. PT1.

Referring to FIGS. 3, 10A and 10B, a first interlayer insulating layer 51 may be formed on the semiconductor substrate 1 having the cell bit line 39a and the peripheral transistor PT1. The first interlayer insulating layer 51 may be formed to have a substantially planarized upper surface. For example, an insulating material layer may be formed on the semiconductor substrate 1 having the cell bit line 39a and the peripheral transistor PT1, and a planarization process (eg, a CMP process) may be formed on the insulating material layer so as to be formed The first interlayer insulating layer 51 of the upper surface is planarized. The bit line capping pattern 42a and the peripheral gate capping pattern 42g may be used during the planarization process for forming the first interlayer insulating layer 51. Therefore, although the first interlayer insulating layer 51 may have a planarized upper surface as illustrated in FIG. 1, it is not limited thereto, and the first interlayer insulating layer 51 may have a planarized upper surface to expose the bit line. The upper surface of the cover pattern 42a and the peripheral gate cover pattern 42g.

In the first region C, the first interlayer insulating layer 51, the buffer insulating pattern 36, and the stop layer 33 may be sequentially patterned so that the first impurity region 18a and the second impurity region exposing the first region C may be formed. The cell of the second unit impurity region 18b in 18b contacts the hole 54.

In some embodiments, since the cell bit line 39a is disposed at substantially the same level from the second peripheral gate electrode 39g of the peripheral transistor PT2, the total thickness of the device does not increase due to the cell bit line 39a. Therefore, the cell contact hole 54 can be formed substantially by etching an insulating layer having a thickness formed by forming the peripheral transistor PT1. This process reduces the etching process time required to form the cell contact holes 54 and increases the etching process margin. Further, since the cell bit line 39a and the second peripheral gate electrode 39g can be simultaneously formed without any separate process for forming the cell bit line 39a, the total process time can be reduced.

A cell contact structure 60 filling the cell contact holes 54 can be formed. The cell contact structure 60 can be formed to include at least one of a metal layer, a metal nitride layer, a metal telluride layer, and a polysilicon layer. For example, the cell contact structure 60 can include a metal layer filling the cell contact holes 54 and can include a diffusion barrier layer interposed between the metal layer and the inner walls of the cell contact holes 54. Moreover, a portion exposed to the second unit impurity region 18b and exposed by the lower region of the unit contact structure 60 (i.e., the cell contact hole 54) may be formed of a metal germanide layer. For example, a metal telluride layer can be formed on the second cell impurity region 18b, and a conductive material layer filling the cell contact hole 54 can be formed so that the cell contact structure 60 can be formed. another The forming unit contact structure 60 may include performing an annealing process on a metal layer and a metal nitride layer to substantially cover the inner wall of the cell contact hole 54 and to make the metal element of the metal layer and the second cell impurity region 18b. The elemental element reacts to form a metal telluride layer.

Referring to FIGS. 3, 11A and 11B, a second interlayer insulating layer 63 may be formed on the first interlayer insulating layer 51. In the second region, a peripheral contact hole 66b passing through the first interlayer insulating layer 51 and the second interlayer insulating layer 63 and exposing at least one of the peripheral impurity regions 48 may be formed. Further, in the intermediate portion M, a connection via 66a penetrating through the second interlayer insulating layer 63 and the bit line cap pattern 42a and exposing a predetermined region of the cell bit line 39a may be formed.

A connection structure 75a filling the connection vias 66a may be formed, and a conductive peripheral contact structure 72b filling the peripheral contact holes 66b may be formed. The connection structure 75a and the peripheral contact structure 72b may be formed to include at least one of a metal layer, a metal nitride layer, a metal telluride layer, and a polysilicon layer.

The perimeter contact structure 72b can be formed to include a different conductive material than the cell contact structure 60. For example, when the cell contact structure 60 comprises a polysilicon layer, the perimeter contact structure 72b can comprise a layer of metallic material, such as tungsten.

A second conductive pattern 75 and an interconnect cap pattern 78 are sequentially stacked on the second interlayer insulating layer 63. The second conductive pattern 75 may cover the connection structure 75a and the peripheral contact structure 72b. The second conductive pattern 75 may be formed to include at least one of a metal layer, a metal nitride layer, and a polysilicon layer. The interconnect cap pattern 78 may be formed of an insulating metal layer, such as a tantalum nitride layer. The formation of the interconnect cap pattern 78 can be omitted.

In another exemplary embodiment, the second conductive pattern 75, the connection structure 75a, and the peripheral contact structure 72b may be formed substantially of a conductive material. For example, a conductive material layer filling the connection via hole 66a and the peripheral contact hole 66b and covering the second interlayer insulating layer 63 may be formed, and the conductive metal layer may be patterned to integrally form the second conductive pattern 75 and the connection structure. 75a and peripheral contact structure 72b.

The unit transistor CT1 and the peripheral transistor PT1 may be electrically connected to each other by the second conductive pattern 75. More specifically, one of the peripheral impurity region 48 of the peripheral transistor PT1 and the cell impurity region 18a of the unit transistors CT1 and CT2 can pass through the bit line contact structure 38p, the first conductive pattern 39a, the connection structure 75a, and the first The two conductive patterns 75 and the peripheral connection structure 72b are electrically connected to each other. An interconnect spacer 81 may be formed on sidewalls of the second conductive pattern 75 and the interconnect cap pattern 78.

Referring to FIGS. 3, 12A and 12B, a third interlayer insulating layer 84 may be formed on the semiconductor substrate having the second conductive pattern 75. The third interlayer insulating layer 84 may be planarized. An etch stop layer 87 may be formed on the third interlayer insulating layer 84.

A data storage element 97 may be formed which passes through the etch stop layer 87, the third interlayer insulating layer 84, and the second interlayer insulating layer 63, and is electrically connected to the cell contact structure 60 and projected to the etch stop layer 87 in the y-axis direction. Above. The data storage element 97 can include a first electrode 90, a second electrode 96, and a material storage material layer 93 between the first electrode 90 and the second electrode 96.

When a DRAM is used as an exemplary memory device, the material storage material layer 93 may comprise a DRAM cell capacitor dielectric material. However, this Exemplary embodiments of the inventive concept are not limited to DRAMs, and can be used in various semiconductor devices. Thus, depending on the device characteristics required for a data storage material layer 93, various data storage materials can be used, such as a PRAM phase change material layer or a FeRAM ferroelectric material layer.

Meanwhile, although the first electrode 90 is illustrated in a cylindrical shape as illustrated in FIG. 12A, the shape is not limited thereto and may be implemented in different shapes depending on the characteristics of a device. For example, the first electrode 90 can be formed in various shapes, such as a column or a plate.

Next, referring to Figures 3 and 13A through 16B, a method of fabricating a semiconductor device in accordance with another exemplary embodiment of the inventive concept will be described below.

Referring to Figures 3, 13A and 13B, a semiconductor substrate 100 having a first region C, a second region P and an intermediate region M can be prepared. The first active region 103a and the second active region 103b, an isolation region 103s, a dielectric layer 106, a gate conductive layer, and a gate trench can be formed in substantially the same manner as the methods of FIGS. 4 and 5. 115, unit impurity regions 118a and 118b, a cell gate dielectric layer 121, a cell gate pattern 124, a cell gate cap pattern 127, and unit transistors CT3 and CT4, respectively corresponding to the first active region 3a and second active region 3b, an isolation region 3s, a node layer 6, a gate conductive layer 9, a gate trench 15, a cell impurity region 18a and 18b, a cell gate dielectric layer 21, and a cell gate pattern 24 , a unit gate cap pattern 27, and unit transistors CT1 and CT2.

As illustrated in FIG. 13B, a mask pattern 130 may be formed on the gate conductive layer of the second region P, and the gate conductive layer may be etched to form a sustain The gate conductive pattern 109a on the second region P. In an exemplary embodiment of the inventive concept, the cell gate cap pattern 127 may maintain a portion protruding from the upper surface of the first active region 103a while forming the gate conductive pattern 109a. That is, the cell gate cap pattern 127 can maintain a protrusion filling the cell gate pattern 124 and the gate trench 115, and an upper surface thereof can be disposed on a surface of the first active region 103a along the y-axis. Higher level. At least a portion of the dielectric layer 106 and the unit gate dielectric layer 121 may be etched when the gate conductive pattern 109a is formed.

In other exemplary embodiments, an ion implantation process may be performed on the substrate 100, wherein the gate conductive pattern 109a is formed such that the impurity regions 118a and 118b may be formed in the first active region 103a.

Referring to Figures 3, 14A and 14B, the mask pattern can be removed (130 of Figure 13B). A stop layer 133 can then be conformally formed on the resulting structure. A buffer insulating layer may be formed on the stop layer 133. The buffer insulating layer may be planarized until the stop layer 133 or the gate conductive pattern 109a on the second region P is exposed so that a buffer insulating pattern 136 may be formed. When the stop layer 133 is held on the gate conductive pattern 109a while the buffer insulating pattern 136 is formed, the stop layer 133 on the gate conductive pattern 109a can be removed.

When the buffer insulating layer is planarized, for example, using CMP, the protrusion of the cell gate cap pattern 127 on a first region C can serve as a planarization stop layer. For example, when the cell gate cap pattern 127 is formed of a tantalum nitride layer and the buffer insulating layer is formed of a hafnium oxide layer, the cell gate cap pattern 127 can be used as a planarization stop layer. Therefore, the occurrence of swelling in the first region C when the planarization process is performed on the buffer insulating layer can be avoided. therefore, The buffer insulating pattern 136 may have a planarized upper surface in which the appearance of the swelling is significantly reduced.

Referring to FIGS. 3, 15A and 15B, the buffer insulating pattern 136 and an insulating material under the buffer insulating pattern 136 (eg, the stop layer 133 on the first active region 103a of the first region C) may be shaped to form an exposed portion. The bit line contact hole 136a of a unit impurity region 118a. A portion of the sidewall of the bit line contact hole 136a may be defined by a protrusion of the cell gate cap pattern 127. Therefore, in order to form the bit line contact hole 136a, the optical process margin when a photoresist pattern is formed on the buffer insulating pattern 136 can be increased.

A first conductive layer may be formed on the entire surface of the semiconductor substrate having the buffer insulating pattern 136. The first conductive layer portion defined by the bit line contact hole 136a may be defined as a first contact structure 138p.

A first wire cover pattern 142a and a peripheral cover pattern 142b may be formed on the first conductive layer, and the first conductive layer and the gate conductive pattern (109a of FIGS. 14A and 14B) may use a bit line cover pattern. The 142a and the peripheral gate cap pattern 142b are sequentially etched as an etch mask. As a result, a first conductive pattern (ie, a cell bit line 139a) may be formed on the first region C and the intermediate region M, and one of the first peripheral gate electrodes 109g and a second peripheral gate are sequentially stacked. The electrode 139g may be formed on the second region P. The first peripheral gate electrode 109g and the second peripheral gate electrode 139g may constitute a peripheral gate pattern 140. Accordingly, at least a portion of the cell bit line 139a can be formed to be disposed at a level that is substantially the same along at least a portion of the peripheral gate pattern 140 along the y-axis.

The cell bit line 139a may cover the upper surface of the bit line contact hole 136a. because Thus, the first contact structure 138a in the bit line contact hole 136a can be connected to the cell bit line 139a and can be formed of the same material. A peripheral gate dielectric layer 106a can be provided between the peripheral gate pattern 140 and the peripheral active region.

A one-line spacer 145a may be formed on the sidewalls of the cell bit line 139a and the bit line cap pattern 142a. A peripheral gate spacer 145g may be formed on the sidewalls of the peripheral gate pattern 140 and the peripheral gate cap pattern 142g.

Impurity ions may be implanted into the second active region 103b at both sides of the peripheral gate pattern 140 to be activated so that a peripheral impurity region, that is, a peripheral source/drain region 148 may be formed. Therefore, a peripheral transistor PT2 including a peripheral source/drain region 148, a peripheral gate dielectric layer 106a, a peripheral gate pattern 140, and a peripheral gate pattern 140 in the second active region 103b may be formed. Channel area.

Referring to FIGS. 3, 16A and 16B, a first interlayer insulating layer 151 may be formed on a substrate having a peripheral transistor PT2. The first interlayer insulating layer 151 may be formed to have a planarized upper surface. For example, an insulating material layer may be formed on the substrate having the peripheral transistor PT2, and a planarization process may be performed on the insulating material layer so that a first interlayer insulating layer having a planarized upper surface may be formed. 151. The planarization process can be performed using a CMP process using a bit line capping pattern 142a and a peripheral gate capping pattern 142g as a planarization stop layer.

In the first region C, a cell contact hole 154a that passes through the first interlayer insulating layer 151, the buffer insulating pattern 136, and the stop layer 133 and exposes the second cell impurity region 118b may be formed. A cell contact structure 160a filling the cell contact hole 154a may be formed.

In the second region P, a peripheral contact hole 154b passing through the first interlayer insulating layer 151 and exposing at least one of the peripheral impurity regions 148 may be formed. A peripheral contact structure filling the peripheral contact hole 154b may be formed. The unit and peripheral contact holes 154a and 154b can be formed simultaneously. Moreover, the unit and peripheral contact structures 160a and 160b can be formed simultaneously. Thus, the unit and perimeter contact structures 160a and 160b can be formed from the same conductive material.

Referring to FIGS. 3, 17A and 17B, in the intermediate portion M, a connection via 161 may be formed which passes through the bit line cap pattern 42s and exposes a predetermined region of a cell bit line 139a. A third conductive layer filling the connection via 161 may be formed, and the third conductive layer may be patterned so as to form a buffer pattern 175a covering the cell contact structure 160a and a cover connection via 161 and a peripheral contact structure 160b. Two conductive patterns 175b. The third conductive layer in the connection via 161 can be defined as a connection structure 175p. Therefore, the second conductive pattern 175b is connectable to the cell bit line 139a through the connection structure 175p, and is electrically connected to the peripheral transistor PT2, that is, one of the peripheral impurity regions 148, through the peripheral contact structure 160b.

In another exemplary embodiment of the inventive concept, the connection structure 175p and the peripheral contact structures 160a and 160b may be formed simultaneously.

In another exemplary embodiment, a damascene process may be used to form the buffer pattern 175a and the second conductive pattern 175b. For example, a second interlayer insulating layer 184 may be formed on the substrate having the unit and peripheral contact structures 160a and 160b, and a hole for forming the buffer pattern 175a and the second conductive pattern 175b in a damascene structure may be formed on the substrate. In the second interlayer insulating layer 184, a conductive material layer filling the holes may be formed, and the pass may be The conductive material layer is planarized so that a buffer pattern 175a and a second conductive pattern 175b defined in the holes can be formed.

An etch stop layer 187 covering the buffer pattern 175a and the second conductive pattern 175b may be formed. Then, the material storage element 197 electrically connected to the buffer pattern 175a may be formed on the buffer pattern 175a. The data storage component 197 can be used as a data storage unit for a volatile or non-volatile memory device.

Next, still another exemplary embodiment of the inventive concept will be described below with reference to FIGS. 18A, 18B, and 19.

Referring to Figures 3, 18A and 18B, a semiconductor substrate 200 having a first region C, a second region P and an intermediate region M can be prepared as illustrated in Figures 4A and 4B. An isolation region 203s defining the active regions 203a and 203b may be provided in the semiconductor substrate 200 using the same method as described in FIGS. 4A and 4B. A preliminary impurity region may be formed in the first active region 203a.

A stop layer 206 and a buffer insulating layer 209 may be sequentially formed on the semiconductor substrate 200. The stop layer 206 can include a layer of material having an etch selectivity with respect to the isolation region 203s. The buffer insulating layer 209 may be formed of a single layer formed of an insulating material. Alternatively, the buffer insulating layer 209 can be a plurality of layers having different etch selectivity (i.e., different material layers). For example, the buffer insulating layer 209 may be formed of a first material layer (eg, a hafnium oxide layer) and a second material layer (eg, a polysilicon layer or a tantalum nitride layer). A second material layer can be formed on the first material layer.

The buffer insulating layer 209 on the semiconductor substrate of the first region C may be patterned so as to form an opening exposing a predetermined region of the first active region 203a and the isolation region 203s. Further, the first exposed by the opening The active region 203a and the isolation region 203s may be etched so as to form a gate trench 215 illustrated in FIG. 18A. The preliminary impurity region may be divided by the gate trench 215 to form the first impurity region 218a and the second impurity region 218b.

A cell gate dielectric layer 221 and a cell gate pattern 224 may be sequentially formed in the cell gate trench 215 using the same method as in FIG. 5A. Therefore, the unit transistors CT5 and CT6 can be formed in the first active region 203a.

A cell gate cap pattern 227 may be formed which fills the remaining portion of the cell gate trench 215 and has a portion protruding from the upper surface of the first active region 203a. The cell gate cap pattern 227 may be formed to include at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer.

Meanwhile, when the buffer insulating layer 209 includes one of the first material layer and the second material layer stacked in sequence, the cell gate cap pattern 227 may be formed or the cell gate cap pattern 227 may be formed after the cell gate cap pattern 227 is formed. Two material layers.

Referring to FIGS. 3 and 19, the buffer insulating layer 209 and the stop layer 206 may be patterned to expose the second active region 203 of the second region P, and form a buffer insulating pattern 209a maintained on the first region P and the intermediate region M. . Thereafter, a gate dielectric layer 210 and a gate conductive pattern 211 are sequentially stacked on the substrate of the second region P.

The gate dielectric layer 210 and the gate conductive pattern 211 may correspond to the gate dielectric layers 6 and 106 and the gate conductive patterns 9a and 109a of FIGS. 6B and 14B, respectively, which are sequentially stacked in FIG. 6B and FIG. 14B. The two acting regions 3b and 103b. Although there is a method of forming the buffer insulating pattern 209a, the gate dielectric layer 210 and the gate conductive pattern 211 of FIG. 19 may be different from one for forming FIGS. 6B and 14B. The method of generating the buffer insulating patterns 36 and 136, the dielectric layers 6 and 106 and the gate conductive patterns 9a and 109a is similar. Therefore, the previously described elements such as the first conductive patterns 39a and 139a, the second conductive patterns 175b, and the data storage elements 97 and 197 may be formed with the buffer insulating pattern 209a, the gate dielectric layer 210, and the gate conductive pattern 211. On a semiconductor substrate.

Figure 20 schematically illustrates a product employing a semiconductor device in accordance with an exemplary embodiment of the inventive concept. Referring to Figure 20, a semiconductor wafer 710 employing a semiconductor device in accordance with the previously described exemplary embodiments can be provided. For example, an integrated circuit and a data storage unit can be formed on a solid semiconductor wafer having a plurality of wafer regions using methods according to the previously described exemplary embodiments. As described above, a semiconductor wafer in which an integrated circuit and a data storage unit are formed may be divided (eg, along the y-axis) to form a plurality of semiconductor wafers 710. The semiconductor wafer 710 can be formed as a single package. The semiconductor wafer 710 can be adapted to a variety of electronic products. The semiconductor wafer 710 can serve as a data storage medium. For example, semiconductor wafer 710 can be used as part of an electronic product 720 that requires a data storage medium such as a digital TV, a computer, a communication device, an electronic dictionary, or a portable memory device. For example, a packaged semiconductor wafer 710 can be mounted on a board or memory module that is suitable for use as part of the electronic product.

According to an exemplary embodiment of the inventive concept, although a first gate electrode and a second gate electrode are sequentially stacked on a peripheral circuit region, interconnections such as a cell bit line may be formed in a cell array region. on. Therefore, the The interconnects may be disposed substantially at the same level as the second gate electrode of the peripheral circuit region, that is, at the same height above the upper surface of the substrate along the y-axis. As a result, the total thickness of the device can be reduced.

The exemplified embodiments of the present invention have been disclosed herein, and are not intended to be limiting. Therefore, those skilled in the art should understand that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

1‧‧‧Semiconductor substrate

3s‧‧‧Isolated area

6‧‧‧Dielectric layer

9‧‧‧ gate conduction layer

15‧‧‧Ganjigou

18a‧‧‧Unit impurity area

18b‧‧‧Unit impurity area

21‧‧‧Unit gate dielectric layer

24, 124‧‧‧ unit gate pattern

27‧‧‧Unit gate cover pattern

30‧‧‧ mask pattern

33‧‧‧stop layer

36‧‧‧buffer insulation pattern

37‧‧‧ Cover insulation

38‧‧‧First Conductive Layer

38p‧‧‧ bit line contact structure

39, 139a‧‧ unit bit line

39a‧‧‧First conductive pattern

39g‧‧‧second perimeter gate electrode

40,140‧‧‧ peripheral gate pattern

42a‧‧‧ bit line cover pattern

42g‧‧‧ peripheral gate cover pattern

45a‧‧‧ bit line spacer

45g‧‧‧ perimeter gate spacer

48‧‧‧ Peripheral source/bungee area

51‧‧‧First interlayer insulation

54‧‧‧Unit contact hole

60‧‧‧Unit contact structure

63‧‧‧Second interlayer insulation

66a‧‧‧Connecting through hole

72b‧‧‧ Conductive peripheral contact structure

75a‧‧‧ Connection structure

78‧‧‧Interconnect cover pattern

81‧‧‧Interconnect spacers

84‧‧‧ Third interlayer insulation

87‧‧‧etch stop layer

90‧‧‧First electrode

93‧‧‧Data storage material layer

96‧‧‧second electrode

97‧‧‧Data storage components

100‧‧‧Semiconductor substrate

3a, 103a‧‧‧First action area

3b, 103b‧‧‧second area of action

106‧‧‧Dielectric layer

109a‧‧‧gate conduction pattern

115‧‧‧Ganjigou

118a‧‧‧Unit impurity area

118b‧‧‧ element impurity area

121‧‧‧Unit gate dielectric layer

127‧‧‧unit gate cap pattern

130‧‧‧ mask pattern

133‧‧‧stop layer

136‧‧‧buffer insulation pattern

138p‧‧‧first contact structure

142a‧‧‧ bit line cover pattern

142g‧‧‧ peripheral gate cover pattern

145a‧‧‧ bit line spacer

145g‧‧‧ peripheral gate spacers

148‧‧‧ Peripheral source/bungee area

75,75b‧‧‧second conductive pattern

151‧‧‧First interlayer insulation

154a‧‧‧unit contact hole

154b‧‧‧ peripheral contact hole

160a‧‧‧Unit contact structure

160b‧‧‧ Peripheral contact structure

175a‧‧‧buffer pattern

184‧‧‧Second interlayer insulation

187‧‧‧etch stop layer

197‧‧‧ data storage components

200‧‧‧Semiconductor substrate

203a‧‧‧Action area

203s‧‧‧Isolated area

206‧‧‧stop layer

209‧‧‧ Buffer insulation

209a‧‧‧buffer insulation pattern

210‧‧‧ gate dielectric layer

211‧‧‧ gate conduction pattern

215‧‧‧Unit gate trench

218a‧‧‧First impurity region

218b‧‧‧Second impurity area

221‧‧‧Unit gate dielectric layer

224‧‧‧unit gate pattern

227‧‧‧Unit gate cover pattern

500‧‧‧Semiconductor substrate

500a‧‧‧ upper surface

503s‧‧‧Isolated area

503a‧‧‧First action area

503b‧‧‧Action area

506a‧‧‧Second gate dielectric layer

509g‧‧‧ lower gate electrode

515‧‧ ‧ gate trench

518b‧‧‧First impurity region

518a‧‧‧First impurity region

521‧‧‧First gate dielectric layer

524‧‧‧first gate pattern

527‧‧‧First gate cover pattern

536‧‧‧ Buffer insulation pattern

536a‧‧‧buffer insulation pattern

538p‧‧‧First contact structure

539a‧‧‧First conductive pattern

539g‧‧‧Upper gate electrode

540‧‧‧Second gate pattern

542a‧‧‧First insulating cover pattern

542g‧‧‧second gate cover pattern

545a‧‧‧First Insulation Spacer

545g‧‧‧Second insulation spacer

548a‧‧‧located in the second impurity area

548b‧‧‧Second impurity area

551‧‧‧First interlayer insulation

560‧‧‧Unit contact structure

571a‧‧‧Contact structure

571b‧‧‧Upper contact structure

572a‧‧‧conductive connection structure

572b‧‧‧Second contact structure

575‧‧‧second conductive pattern

584‧‧‧Second interlayer insulation

597‧‧‧Data storage components

600a‧‧‧ upper surface

600‧‧‧Semiconductor substrate

603s‧‧‧Isolated area

603a‧‧‧Action area

603b‧‧‧Action area

606a‧‧‧Second gate dielectric layer

609g‧‧‧lower gate electrode

615‧‧‧Ganjigou

618b‧‧‧First impurity region

618a‧‧‧First impurity region

621‧‧‧First gate dielectric layer

624‧‧‧First Gate Pattern

627‧‧‧First gate cover pattern

636‧‧‧buffer insulation pattern

636a‧‧‧buffer insulation pattern

638p‧‧‧first contact structure

639a‧‧‧First conductive pattern

639g‧‧‧Upper gate electrode

640‧‧‧second gate pattern

642a‧‧‧First insulating cover pattern

642g‧‧‧second gate cover pattern

645a‧‧‧First insulation spacer

645g‧‧‧Second insulation spacer

648a‧‧‧First impurity area

648b‧‧‧Second impurity area

651‧‧‧First interlayer insulation

660‧‧‧Unit contact structure

672a‧‧‧Connection structure

672b‧‧‧Second contact structure

675b‧‧‧Transmission buffer pattern

675a‧‧‧second conductive pattern

684‧‧‧Second interlayer insulation

697‧‧‧Data storage components

710‧‧‧Semiconductor wafer

720‧‧‧Electronic products using semiconductor wafers

The above and other features and advantages of the present invention will become more apparent to those skilled in the <RTIgt; FIG. 2 illustrates a cross-sectional view of a semiconductor device in accordance with another exemplary embodiment; FIG. 3 illustrates a plan view of a semiconductor device in accordance with an exemplary embodiment; FIGS. 4A through 12B illustrate an exemplary implementation in accordance with an exemplary embodiment FIG. 13A to FIG. 17B are cross-sectional views showing successive stages in a method of fabricating a semiconductor device in accordance with another exemplary embodiment; FIGS. 18A and 18B are diagrams. And 19 illustrate cross-sectional views in sequential stages in a method of fabricating a semiconductor device in accordance with another exemplary embodiment; and FIG. 20 illustrates a semiconductor wafer and a semiconductor in accordance with an exemplary embodiment. Schematic diagram of electronic products.

500‧‧‧Semiconductor substrate

500a‧‧‧ upper surface

503s‧‧‧Isolated area

503a‧‧‧First action area

503b‧‧‧Action area

506a‧‧‧Second gate dielectric layer

509g‧‧‧ lower gate electrode

515‧‧ ‧ gate trench

518b‧‧‧First impurity region

518a‧‧‧First impurity region

521‧‧‧First gate dielectric layer

524‧‧‧first gate pattern

527‧‧‧First gate cover pattern

536‧‧‧ Buffer insulation pattern

536a‧‧‧buffer insulation pattern

538p‧‧‧First contact structure

539a‧‧‧First conductive pattern

539g‧‧‧Upper gate electrode

540‧‧‧Second gate pattern

542a‧‧‧First insulating cover pattern

542g‧‧‧second gate cover pattern

545a‧‧‧First Insulation Spacer

545g‧‧‧Second insulation spacer

548a‧‧‧located in the second impurity area

548b‧‧‧Second impurity area

551‧‧‧First interlayer insulation

560‧‧‧Unit contact structure

571a‧‧‧Contact structure

571b‧‧‧Upper contact structure

572a‧‧‧conductive connection structure

572b‧‧‧Second contact structure

575‧‧‧second conductive pattern

584‧‧‧Second interlayer insulation

597‧‧‧Data storage components

Claims (25)

A semiconductor device comprising: a semiconductor substrate having a first active region and a second active region; a first transistor located in the first active region of the semiconductor substrate, the first transistor comprising a plurality of An impurity region and a first gate pattern; a second transistor in the second active region of the semiconductor substrate, the second transistor comprising a plurality of second impurity regions and a second gate pattern; a first conductive pattern formed on the first transistor, wherein at least a portion of the first conductive pattern and at least a portion of the second gate pattern are disposed at the same distance from an upper surface of the semiconductor substrate; And an interconnect structure, the first conductive pattern is electrically connected to a corresponding one of the second impurity regions, wherein the interconnect structure comprises a second conductive pattern, the second conductive pattern is opposite to the upper conductive pattern The surface is higher than the at least a portion of the first conductive pattern and the second gate pattern. The device of claim 1, wherein the first transistor comprises: the first gate pattern is provided in a gate trench spanning the first active region; the first impurity region is located at the first An active region of the first gate pattern; and a first gate dielectric layer provided in the first gate pattern and the gate Between the extreme trenches. The device of claim 2, further comprising an insulative first gate cap pattern filling the gate trench together with the first gate pattern, wherein the first gate cap pattern has a protrusion The protrusion is farther from the upper surface of the semiconductor substrate than the first active region. The device of claim 1, further comprising a first contact structure configured to electrically connect one of the first impurity regions to the first conductive pattern. The device of claim 1, wherein the second transistor comprises: the second gate pattern spanning the second active region; a second gate dielectric layer provided in the second gate pattern and And a plurality of second impurity regions located at two sides of the second gate pattern in the second active region, wherein the second gate pattern comprises one of the first gate electrodes and one stacked in sequence a second gate electrode, and the second gate electrode is disposed above the upper surface of the semiconductor substrate at substantially the same height as the first conductive pattern. The device of claim 1, wherein the interconnect structure further comprises: a cell contact structure electrically coupled to one of the first impurity regions; and a data storage component located on the cell contact structure. The device of claim 6, wherein the data storage component is disposed at a level higher than the first conductive pattern. The device of claim 6 further comprising a conductive buffer pattern provided between the unit contact structure and the data storage element. The device of claim 6, wherein the data storage component comprises one of a data storage material layer of one of the volatile memory devices and one of the data storage material layers of one of the non-volatile memory devices. The device of claim 6, wherein the interconnect structure further comprises: a second contact structure configured to electrically connect one of the second impurity regions to the second conductive pattern. The device of claim 10, wherein the unit contact structure and the second contact structure have surfaces disposed at different levels from each other. The device of claim 10, wherein the unit contact structure and the second contact structure have surfaces disposed at substantially the same level. The device of claim 10, further comprising a connection structure configured to electrically connect the first conductive pattern and the second conductive pattern. An electronic product comprising a semiconductor wafer, the semiconductor wafer comprising: a semiconductor substrate having a cell array region and a peripheral circuit region; a unit transistor located on the semiconductor substrate of the cell array region, the cell The crystal includes a plurality of first impurity regions and a first gate pattern; a peripheral transistor located at the semiconductor region of the peripheral circuit region The peripheral transistor includes a plurality of second impurity regions and a first peripheral gate electrode and a second peripheral gate electrode sequentially stacked on the substrate between the second impurity regions; a cell bit line Provided on the unit cell of the cell array region, at least a portion of the cell bit line and at least a portion of the second peripheral gate electrode are disposed at the same distance from an upper surface of the semiconductor substrate; a wiring structure, wherein the cell bit line is electrically connected to a corresponding one of the second impurity regions, wherein the interconnect structure comprises a conductive pattern, the conductive pattern being higher than the cell bit with respect to the upper surface At least a portion of the line and the second peripheral gate electrode. A method of fabricating a semiconductor device, comprising: preparing a semiconductor substrate having a first active region and a second active region; forming a first transistor in the first active region, the first transistor comprising a first a gate pattern and a plurality of first impurity regions; a second transistor formed in the second active region, the second transistor comprising a second gate pattern and a plurality of second impurity regions; on the first transistor Forming a first conductive pattern, wherein at least a portion of the first conductive pattern and at least a portion of the second gate pattern are disposed at the same distance from an upper surface of the semiconductor substrate; and forming an interconnect structure The first conductive pattern is electrically connected to a corresponding one of the second impurity regions, wherein the interconnect structure comprises a second conductive pattern, the two conductive patterns being higher than the upper surface The at least a portion of the conductive pattern and the second gate pattern. The method of claim 15, wherein the forming the first and second transistors and the first conductive pattern comprises: forming the first impurity regions in the first active region; forming a gate across the first active region a drain trench; forming the first gate pattern filling at least a portion of the gate trench; forming a gate conductive pattern on the second active region; forming a buffer insulating pattern on the first active region; forming a first conductive layer covering the buffer insulating pattern and the gate conductive pattern; and patterning the first conductive layer on the buffer insulating pattern, and sequentially stacking the gate conductive pattern on the second active region And the first conductive layer to form the first conductive pattern on the buffer insulating pattern, and one of the first gate electrode and the second gate electrode are sequentially stacked on the second active region. The method of claim 16, after forming the first gate pattern, further comprising forming a first gate cap pattern to fill the gate together with the first gate pattern on the first gate pattern a trench, wherein the first gate cap pattern extends over the upper surface of the semiconductor substrate to be further than the first active region. The method of claim 16, wherein forming the buffer insulation pattern occurs after forming the gate conduction pattern. The method of claim 16, wherein the forming the gate conduction pattern occurs in a shape After the buffer insulation pattern. The method of claim 16, before forming the first conductive pattern, further comprising forming a first contact structure configured to pass through the buffer insulating pattern and electrically connect to the first impurities One of the regions, wherein the first conductive structure is electrically connected to the first conductive pattern. The method of claim 15, wherein the step of forming the interconnect structure comprises: forming a first interlayer insulating layer on the substrate having the first conductive pattern; forming a configuration to pass through the first An inter-layer insulating layer electrically connected to the cell contact structure of one of the first impurity regions; and a data storage element formed on the cell contact structure. The method of claim 21, further comprising: forming a perimeter contact structure when the cell contact structure is formed, the perimeter contact structure configured to pass through the first interlayer insulating layer and electrically connect to the second One of the impurity regions, wherein the second conductive pattern is formed on the first interlayer insulating layer. The method of claim 22, further comprising forming a buffer pattern electrically connected to the cell contact structure on the first interlayer insulating layer while forming the second conductive pattern. The method of claim 21, further comprising: forming a second interlayer insulating layer on the first interlayer insulating layer; forming a second contact structure configured to pass through The first interlayer insulating layer and the second interlayer insulating layer are electrically connected to one of the second impurity regions; and a second conductive pattern is formed on the second interlayer insulating layer. The method of claim 15, wherein forming the first conductive pattern occurs while forming the second gate pattern.