TWI489718B - Storage device and operating method thereof - Google Patents
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本發明係與電源保護電路有關,並且特別地,本發明是關於一種能夠防止突波電流並提高儲存裝置壽命之儲存裝置及其運作方法。The present invention relates to power protection circuits, and in particular, to a storage device capable of preventing surge currents and increasing the life of a storage device, and a method of operating the same.
近年來,由於個人電腦、手機、數位相機、數位攝影機以及個人數位助理等電子裝置日益普及,並且伴隨著數位影音多媒體的興起,使得包含記憶卡的儲存裝置成為大眾喜愛的電子商品。In recent years, electronic devices such as personal computers, mobile phones, digital cameras, digital cameras, and personal digital assistants have become increasingly popular, and with the rise of digital audio and video multimedia, storage devices including memory cards have become popular electronic products.
記憶卡是一種輕巧且方便攜帶的資料儲存裝置,隨著科技的進步及發展,並依據實際應用時的需求,市面上常見的記憶卡包含了數位安全卡(Secure Digital card,SD card)、迷你數位安全卡(mini SD card)、微型數位安全卡(micro SD card)、多媒體卡(Multi Media Card,MMC)及快閃記憶卡(Compact Flash card,CF card)等各式各樣的記憶卡。The memory card is a lightweight and portable data storage device. With the advancement and development of technology, and according to the needs of practical applications, the memory card commonly used in the market includes a digital security card (Secure Digital card, SD card), mini A variety of memory cards, such as a mini SD card, a micro SD card, a Multi Media Card (MMC), and a Compact Flash card (CF card).
請參見圖一,圖一係繪示傳統的儲存裝置1之功能方塊圖。如圖一所示,儲存裝置1包含輸入模組10、儲存模組12以及電阻元件R。Referring to FIG. 1, FIG. 1 is a functional block diagram of a conventional storage device 1. As shown in FIG. 1 , the storage device 1 includes an input module 10 , a storage module 12 , and a resistive element R .
於習知技藝中,儲存裝置1之輸入模組10可耦接至個人電腦、筆記型電腦等電子裝置;電阻元件R耦接於輸入模組10與儲存模組12之間。其中,電阻元件R係用以防止當傳統的儲存裝置1連接至電子裝置之瞬間,忽然產生過大的電流突波造成儲存裝置1的損壞。然而,單靠電阻元件R保護儲存裝置1之效果並不佳,並且當儲存裝置1正常運作時,由於電阻元件R仍會持續地消耗功率,導致不必要的損耗發生。In the prior art, the input module 10 of the storage device 1 can be coupled to an electronic device such as a personal computer or a notebook computer; the resistive component R is coupled between the input module 10 and the storage module 12. The resistor element R is used to prevent the damage of the storage device 1 caused by an excessive current surge when the conventional storage device 1 is connected to the electronic device. However, the effect of protecting the storage device 1 by the resistance element R alone is not good, and when the storage device 1 is operating normally, since the resistance element R continues to consume power, unnecessary loss occurs.
藉此,本發明提供一種儲存裝置及其運作方法,該儲存裝置利用保護模組有效降低突波電流並且正常使用時保護模組不會消耗功率,以解決上述之問題。Accordingly, the present invention provides a storage device and a method for operating the same, which utilizes a protection module to effectively reduce a surge current and protect the module from power consumption during normal use to solve the above problems.
因此,本發明之一範疇在於提供一種儲存裝置及其運作方法。儲存裝置利用保護模組產生延遲時間,使輸出訊號落後輸入訊號一延遲時間,進而達到保護儲存裝置之目的。藉此,本發明之儲存裝置與運作儲存裝置之方法可延長儲存裝置內電池的使用壽命以及避免遭受電流突波的影響。Accordingly, one aspect of the present invention is to provide a storage device and method of operation thereof. The storage device uses the protection module to generate a delay time, so that the output signal is delayed by the input signal for a delay time, thereby achieving the purpose of protecting the storage device. Thereby, the storage device and the method for operating the storage device of the present invention can prolong the service life of the battery in the storage device and avoid the influence of current surge.
根據本發明之一具體實施例為一種儲存裝置。於此實施例中,該儲存裝置包含輸入模組、保護模組以及儲存模組。當該儲存裝置耦接至電子裝置時,該輸入模組自電子裝置接收輸入訊號。保護模組係耦接至輸入模組,並係用以接收輸入訊號並產生輸出訊號。儲存模組係耦接至保護模組,並係用以接收輸出訊號,並根據輸出訊號使該儲存裝置作動。其中,保護模組係對輸入訊號進行延遲處理以產生輸出訊號,使得該輸出訊號與輸入訊號之間具有延遲時間的差異。A particular embodiment of the invention is a storage device. In this embodiment, the storage device includes an input module, a protection module, and a storage module. The input module receives an input signal from the electronic device when the storage device is coupled to the electronic device. The protection module is coupled to the input module and is configured to receive an input signal and generate an output signal. The storage module is coupled to the protection module and configured to receive the output signal and activate the storage device according to the output signal. The protection module delays the input signal to generate an output signal, so that there is a difference in delay time between the output signal and the input signal.
根據本發明之另一具體實施例為一種運作一儲存裝置之方法,該運作方法包含下列步驟:(a)當儲存裝置耦接至電子裝置時,儲存裝置自電子裝置接收輸入訊號;(b)對輸入訊號進行延遲處理以產生輸出訊號,其中輸出訊號與輸入訊號之間具有延遲時間之差異;(c)接收輸出訊號並根據輸出訊號使儲存裝置作動。Another embodiment of the present invention is a method of operating a storage device, the method comprising the steps of: (a) when the storage device is coupled to the electronic device, the storage device receives an input signal from the electronic device; (b) The input signal is delayed to generate an output signal, wherein the difference between the output signal and the input signal has a delay time; (c) receiving the output signal and causing the storage device to act according to the output signal.
綜上所述,本發明提供之儲存裝置及其運作方法係藉由保護模組將輸入訊號延遲一段時間,以確保儲存裝置與電子裝置已完整連接後,再供電至儲存裝置,避免儲存裝置遭受到瞬間的電流突波之影響而損壞。此外,本發明之儲存裝置在正常操作下,保護模組並不會造成額外的功率消耗。藉此,本發明之儲存裝置及其運作方法能夠延長儲存裝置內電池的使用壽命以及避免遭受電流突波的影響,以解決習知技術的種種問題。In summary, the storage device and the operation method thereof provided by the present invention delay the input signal by the protection module for a period of time to ensure that the storage device and the electronic device are completely connected, and then supply power to the storage device to avoid the storage device from being damaged. Damaged by the effects of instantaneous current surges. In addition, the protection device of the present invention does not cause additional power consumption under normal operation. Thereby, the storage device and the operation method thereof of the present invention can prolong the service life of the battery in the storage device and avoid the influence of current surge to solve various problems of the prior art.
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
請一併參照圖二A與二B,圖二A係繪示根據本發明之一具體實施例之儲存裝置3的功能方塊圖;圖二B係繪示圖二A中訊號之時序圖範例。實際上,儲存裝置3可以是CF(compact flash)卡裝置、MMC(multimedia memory card)卡裝置、SD(secure digital)卡裝置、SM(smart media)卡裝置、XD(extreme digital)卡裝置或MS(memory stick)卡裝置,但不以此為限。如圖二A所示,儲存裝置3包含輸入模組30、保護模組32、儲存模組34以及電池模組36。Referring to FIG. 2A and FIG. 2B together, FIG. 2A is a functional block diagram of a storage device 3 according to an embodiment of the present invention; and FIG. 2B is a diagram showing an example of a timing chart of the signal in FIG. In fact, the storage device 3 may be a CF (compact flash) card device, an MMC (multimedia memory card) card device, an SD (secure digital) card device, an SM (smart media) card device, an XD (extreme digital) card device, or an MS. (memory stick) card device, but not limited to this. As shown in FIG. 2A, the storage device 3 includes an input module 30, a protection module 32, a storage module 34, and a battery module 36.
當儲存裝置3透過其輸入模組30耦接至電子裝置4時,輸入模組30可從電子裝置3接收輸入訊號Si 。於實際應用中,輸入模組30可以是通用序列匯流排(Universal Synchronous Bus,USB),但不以此為限。並且,輸入訊號Si 通常是指由電子裝置(例如,個人電腦或筆記型電腦等裝置)提供之電壓訊號或電流訊號,可供應儲存裝置3所需之電力,但不以此為限。When the storage device 3 is coupled to the electronic device 4 through the input module 30, the input module 30 can receive the input signal S i from the electronic device 3. In practical applications, the input module 30 can be a Universal Synchronous Bus (USB), but is not limited thereto. Moreover, the input signal S i generally refers to a voltage signal or a current signal provided by an electronic device (for example, a device such as a personal computer or a notebook computer), and can supply the power required by the storage device 3, but is not limited thereto.
於此實施例中,保護模組32係耦接至輸入模組30,保護模組32係自輸入模組30接收輸入訊號Si 並根據輸入訊號Si 產生輸出訊號So 。值得注意的是,保護模組32係對於輸入訊號Si 進行延遲處理以產生輸出訊號So ,使得輸出訊號So 與輸入訊號Si 之間具有延遲時間(delay time)td 之差異。藉此,由於輸出訊號So 已較輸入訊號Si 延遲一段時間td ,故可確保儲存裝置3與電子裝置4已完整連接後,才供電至儲存裝置3,以避免儲存裝置3遭受到瞬間的電流突波之影響而損壞。In this embodiment, the protection module 32 is coupled to the input module 30. The protection module 32 receives the input signal S i from the input module 30 and generates an output signal S o according to the input signal S i . It should be noted that the protection module 32 performs delay processing on the input signal S i to generate the output signal S o such that the difference between the output signal S o and the input signal S i has a delay time t d . Therefore, since the output signal S o has been delayed by a period t d from the input signal S i , it can be ensured that the storage device 3 and the electronic device 4 are completely connected before being powered to the storage device 3 to avoid the storage device 3 being subjected to the instant. The current surge is affected by the damage.
實際應用中,當儲存裝置3耦接至電子裝置4的瞬間,很容易出現過大的電流突波(inrush current)現象。若無任何保護電路,將可能導致上述之各項裝置因為電流突波而損毀。再者,若保護電路上配置習知技術所述之被動元件,被動元件亦將在正常供電情況下持續消耗功率,導致後端模組無法獲得足夠之電力。接著,就本實施例中之保護模組32進行詳細說明。In practical applications, when the storage device 3 is coupled to the electronic device 4, an excessive inrush current phenomenon is likely to occur. Without any protection circuit, it may cause the above devices to be damaged due to current surges. Furthermore, if the passive component described in the prior art is disposed on the protection circuit, the passive component will continue to consume power under normal power supply conditions, resulting in insufficient power supply for the back-end module. Next, the protection module 32 in this embodiment will be described in detail.
本發明之保護模組32包含可程式邏輯元件(Complex Programmable Logic Device,CPLD)320、電阻元件R以及電容元件C。其中,可程式邏輯元件320包含第一邏輯單元3200、第二邏輯單元3202及第三邏輯單元3204;電阻元件R耦接至第一邏輯單元3200與第三邏輯單元3204之間;電容元件C耦接至電阻元件R與第二邏輯單元3202之間。The protection module 32 of the present invention includes a Complex Programmable Logic Device (CPLD) 320, a resistance element R, and a capacitance element C. The programmable logic element 320 includes a first logic unit 3200, a second logic unit 3202, and a third logic unit 3204; the resistive element R is coupled between the first logic unit 3200 and the third logic unit 3204; Connected between the resistive element R and the second logic unit 3202.
於此實施例中,如圖二A所示,第一邏輯單元3200(例如反(NOT)閘)耦接至輸入模組30,第一邏輯單元3200將輸入訊號Si 轉換成相反於輸入訊號Si 之第一訊號S1 (如圖二B所示)。第二邏輯單元3202可以是史密特觸發器,用以產生延遲(delay)訊號Sd ,但不以此為限。第三邏輯單元3204(例如及(AND)閘)耦接第一邏輯單元3200以及第二邏輯單元3202,第三邏輯單元3204係用以接收第一訊號S1 以及延遲訊號Sd 進而進行比較以產生輸出訊號So 至儲存模組34。In this embodiment, as shown in FIG. 2A, the first logic unit 3200 (eg, a NOT gate) is coupled to the input module 30, and the first logic unit 3200 converts the input signal S i to be opposite to the input signal. The first signal S 1 of S i (as shown in Figure 2B). The second logic unit 3202 can be a Schmitt trigger for generating a delay signal S d , but is not limited thereto. The third logic unit 3204 (for example, an AND gate) is coupled to the first logic unit 3200 and the second logic unit 3202. The third logic unit 3204 is configured to receive the first signal S 1 and the delay signal S d for comparison. generating an output signal S o to the storage module 34.
需特別說明的是,於保護模組32中,電阻與電容串聯電路將會根據訊號準位(第一訊號S1 )執行充電或放電之動作而產生第二訊號S2 。如圖二B所示,當電容元件C開始充電到完成充電所需的時間稱為延遲時間td ,並且延遲時間td 的長短需視電阻元件R與電容元件C選定之參數而定。接著,史密特觸發器再根據延遲時間td 的長短輸出延遲訊號Sd 至第三邏輯閘3204。It should be noted that, in the protection module 32, the resistor and capacitor series circuit will generate a second signal S 2 according to the signal level (the first signal S 1 ) to perform charging or discharging. Shown in Figure 2 B, when the element C starts charging the capacitor to the charging time required to complete the time delay referred to t d, and the length of the delay time t d is subject to the resistance element R and the capacitive element C selected parameter set. Then, the Schmitt trigger outputs the delay signal S d to the third logic gate 3204 according to the length of the delay time t d .
實際上,第一邏輯單元3200以及第三邏輯單元3204並不以上述之邏輯閘為限,舉例來說,假設第一邏輯單元3200不存在且第三邏輯閘3204是反及(NAND)閘,則其輸出訊號So 亦如同圖二B所示。In fact, the first logic unit 3200 and the third logic unit 3204 are not limited to the above-described logic gate. For example, it is assumed that the first logic unit 3200 does not exist and the third logic gate 3204 is a NAND gate. Then its output signal S o is also as shown in Figure 2B.
再者,由於延遲時間td 的產生使得儲存裝置3連接至電子裝置4之瞬間並不會供電,故可避免儲存裝置3之電池模組36的損耗。此外,這段延遲時間td 亦可確保儲存裝置3與電子裝置4完全連接後再行供電,以避免電流突波使得儲存裝置3損壞。於實際應用中,保護模組32亦可視為延遲開關。有別於傳統的儲存裝置,當儲存裝置3正常操作時,保護模組32並不會再消耗功率。Moreover, since the delay time t d is generated so that the storage device 3 is not connected to the electronic device 4 at the moment, power supply is not performed, so that the loss of the battery module 36 of the storage device 3 can be avoided. In addition, the delay time t d can also ensure that the storage device 3 is fully connected to the electronic device 4 and then supply power to avoid current surges to damage the storage device 3. In practical applications, the protection module 32 can also be regarded as a delay switch. Different from the traditional storage device, when the storage device 3 is operating normally, the protection module 32 does not consume power any more.
於此實施例中,儲存模組34耦接至保護模組32,儲存模組34係用以接收輸出訊號So ,並根據輸出訊號So 使儲存裝置3作動。其中,儲存模組34可用以儲存各種資料,並且儲存模組34可以與儲存裝置3分離放置或組裝於一體。實際上,儲存模組34可以是數位安全卡(Secure Digital card,SD card)、迷你數位安全卡(mini SD card)、微型數位安全卡(micro SD card)、多媒體卡(Multi Media Card,MMC)或快閃記憶卡(Compact Flash card,CF card)等。In this embodiment, the storage module 34 is coupled to the protection module 32. The storage module 34 is configured to receive the output signal S o and activate the storage device 3 according to the output signal S o . The storage module 34 can be used to store various materials, and the storage module 34 can be placed or assembled separately from the storage device 3. In fact, the storage module 34 can be a Secure Digital card (SD card), a mini SD card, a micro SD card, or a Multi Media Card (MMC). Or a flash memory card (Compact Flash card, CF card), etc.
電池模組36耦接至保護模組32與儲存模組34之間,當電池模組36執行充電時,電池模組36可以接收輸出訊號So 以儲存電力。當儲存裝置3與電子裝置4之間未連接時,電池模組36即可將儲存的電力提供給儲存裝置3(第三訊號S3 ),使其能順利運作,也讓使用者更便於使用儲存裝置3。The battery module 36 is coupled between the protection module 32 and the storage module 34. When the battery module 36 performs charging, the battery module 36 can receive the output signal S o to store power. When the storage device 3 and the electronic device 4 are not connected, the battery module 36 can supply the stored power to the storage device 3 (the third signal S 3 ), so that it can operate smoothly and make the user more convenient to use. Storage device 3.
請參照圖三,圖三係繪示本發明之另一具體實施例之儲存裝置3之運作方法的流程圖。如圖三所示,該運作方法包含下列步驟:首先,執行步驟S50,當儲存裝置3耦接至電子裝置4時,儲存裝置3自電子裝置4接收輸入訊號Si 。其中,輸入訊號Si 係指電壓訊號或電流訊號。Referring to FIG. 3, FIG. 3 is a flow chart showing a method of operating the storage device 3 according to another embodiment of the present invention. As shown in FIG. 3, the operation method includes the following steps. First, step S50 is performed. When the storage device 3 is coupled to the electronic device 4, the storage device 3 receives the input signal S i from the electronic device 4. The input signal S i refers to a voltage signal or a current signal.
接著,執行步驟S52,對輸入訊號Si 進行延遲處理以產生輸出訊號So ,其中輸出訊號So 與輸入訊號Si 之間具有延遲時間(delay time)td 之差異。Then, step S52 is performed to delay the input signal S i to generate an output signal S o , wherein the difference between the output signal S o and the input signal S i has a delay time t d .
值得注意的是,由於延遲時間td 的差異使得儲存裝置3耦接至電子裝置4的瞬間,並不會獲得所需電力,以避免瞬間產生的電流突波導致儲存裝置3損壞,同時亦能夠確保儲存裝置3與電子裝置4已完整連接。此外,當儲存裝置3與電子裝置4完整連接後再行供電,亦可減少電池的損耗。It should be noted that, due to the difference of the delay time t d , the storage device 3 is coupled to the electronic device 4 at an instant, and the required power is not obtained, so as to avoid the instantaneous current surge caused by the storage device 3, and at the same time It is ensured that the storage device 3 and the electronic device 4 are completely connected. In addition, when the storage device 3 is completely connected to the electronic device 4 and then powered, the battery loss can also be reduced.
最後,執行步驟S54,接收輸出訊號So 並根據輸出訊號So 趨動儲存裝置3。其中,儲存裝置3可包含電池模組36,輸出訊號So 可對電池模組36充電,當儲存裝置3未與電子裝置連接時,儲存裝置3仍可透過電池模組36提供所需之電力(第三訊號S3 )至儲存模組34,使得儲存裝置3仍可持續使用。Finally, step S54 is executed to receive the output signal S o and to activate the storage device 3 according to the output signal S o . The storage device 3 can include a battery module 36. The output signal S o can charge the battery module 36. When the storage device 3 is not connected to the electronic device, the storage device 3 can still provide the required power through the battery module 36. (Third signal S 3 ) to the storage module 34 so that the storage device 3 can still be used continuously.
請參照圖四,圖四係繪示圖三中之步驟S52的詳細流程圖。如圖四所述,於步驟S52中,首先,執行步驟S520,接收輸入訊號Si 並產生第一訊號S1 。於此實施例中,輸入訊號Si 係與第一訊號S1 反向,並且利用第一訊號S1 之準位變化對電阻與電容串聯電路執行充放電。接著,執行步驟S522,產生延遲(delay)訊號Sd ,並且延遲訊號Sd 的延遲時間係根據電容充電所需時間而定。最後,執行步驟S524,根據第一訊號S1 與延遲訊號Sd 比較後產生輸出訊號So ,以控制儲存模組34所需之電力。Please refer to FIG. 4 , which is a detailed flowchart of step S52 in FIG. 3 . As shown in FIG. 4, in step S52, first, step S520 is performed to receive the input signal S i and generate the first signal S 1 . In this embodiment, the input signal S i is opposite to the first signal S 1 , and the charge and discharge series circuit is charged and discharged by the level change of the first signal S 1 . Next, step S522 is executed to generate a delay signal S d , and the delay time of the delay signal S d is determined according to the time required for the capacitor to be charged. Finally, step S524 is executed to generate an output signal S o according to the first signal S 1 and the delay signal S d to control the power required by the storage module 34 .
綜上所述,本發明提供之儲存裝置及其運作方法係藉由保護模組將輸入訊號延遲一段時間,以確保儲存裝置與電子裝置已完整連接後,再供電至儲存裝置,避免儲存裝置由於遭受到瞬間的電流突波而損壞。此外,本發明之儲存裝置在正常操作情況下,保護模組並不會產生額外的功率消耗。藉此,本發明之儲存裝置及其運作方法可延長儲存裝置內電池的使用壽命以及減少遭受電流突波的影響,以解決習知技藝的種種問題。In summary, the storage device and the operation method thereof provided by the present invention delay the input signal by the protection module for a period of time to ensure that the storage device and the electronic device are completely connected, and then supply power to the storage device, thereby avoiding the storage device Suffering from an instantaneous current surge and damage. In addition, the protection device of the present invention does not generate additional power consumption under normal operating conditions. Thereby, the storage device of the present invention and the method of operating the same can prolong the service life of the battery in the storage device and reduce the influence of current surge to solve various problems of the prior art.
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.
S50~S54、S520~S524...流程步驟S50~S54, S520~S524. . . Process step
1、3...儲存裝置1, 3. . . Storage device
10、30...輸入模組10, 30. . . Input module
12、34...儲存裝置12, 34. . . Storage device
32...保護模組32. . . Protection module
320...可程式邏輯元件320. . . Programmable logic component
3200...第一邏輯單元3200. . . First logical unit
3202...第二邏輯單元3202. . . Second logical unit
3204...第三邏輯單元3204. . . Third logical unit
36...電池模組36. . . Battery module
34...儲存模組34. . . Storage module
4...電子裝置4. . . Electronic device
C...電容元件C. . . Capacitive component
R...電阻元件R. . . Resistance element
Si ...輸入訊號S i . . . Input signal
Sd ...延遲訊號S d . . . Delay signal
So ...輸出訊號S o . . . Output signal
S1 ...第一訊號S 1 . . . First signal
S2 ...第二訊號S 2 . . . Second signal
S3 ...第三訊號S 3 . . . Third signal
td ...延遲時間t d . . . delay
圖一係繪示傳統的儲存裝置之功能方塊圖。Figure 1 is a functional block diagram showing a conventional storage device.
圖二A係繪示根據本發明之一具體實施例之儲存裝置的功能方塊圖。Figure 2A is a functional block diagram of a storage device in accordance with an embodiment of the present invention.
圖二B係繪示圖二A中訊號的時序圖之一範例。Figure 2B is an example of a timing diagram of the signal in Figure 2A.
圖三係繪示本發明之另一具體實施例之儲存裝置運作方法的流程圖。FIG. 3 is a flow chart showing a method of operating a storage device according to another embodiment of the present invention.
圖四係繪示圖三中之步驟S52的詳細流程圖。FIG. 4 is a detailed flowchart of step S52 in FIG.
3...儲存裝置3. . . Storage device
30...輸入模組30. . . Input module
32...保護模組32. . . Protection module
320...可程式邏輯元件320. . . Programmable logic component
3200...第一邏輯單元3200. . . First logical unit
3202...第二邏輯單元3202. . . Second logical unit
3204...第三邏輯單元3204. . . Third logical unit
34...儲存模組34. . . Storage module
36...電池模組36. . . Battery module
4...電子裝置4. . . Electronic device
C...電容元件C. . . Capacitive component
R...電阻元件R. . . Resistance element
Si ...輸入訊號S i . . . Input signal
Sd ...延遲訊號S d . . . Delay signal
So ...輸出訊號S o . . . Output signal
S1 ...第一訊號S 1 . . . First signal
S2 ...第二訊號S 2 . . . Second signal
S3 ...第三訊號S 3 . . . Third signal
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Citations (5)
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TW550563B (en) * | 2002-02-01 | 2003-09-01 | Silicon Integrated Sys Corp | Memory data receiver and method |
TW200525349A (en) * | 2003-10-16 | 2005-08-01 | Intel Corp | Adaptive input/output buffer and methods thereof |
TW200608283A (en) * | 2004-05-20 | 2006-03-01 | Renesas Tech Corp | Nonvolatile memory apparatus |
TW200639633A (en) * | 2005-02-16 | 2006-11-16 | Sandisk Corp | Direct data file storage implementation techniques in flash memories |
TW200722998A (en) * | 2005-12-05 | 2007-06-16 | Via Tech Inc | Memory card detect circuit |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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TW550563B (en) * | 2002-02-01 | 2003-09-01 | Silicon Integrated Sys Corp | Memory data receiver and method |
TW200525349A (en) * | 2003-10-16 | 2005-08-01 | Intel Corp | Adaptive input/output buffer and methods thereof |
TW200608283A (en) * | 2004-05-20 | 2006-03-01 | Renesas Tech Corp | Nonvolatile memory apparatus |
TW200639633A (en) * | 2005-02-16 | 2006-11-16 | Sandisk Corp | Direct data file storage implementation techniques in flash memories |
TW200722998A (en) * | 2005-12-05 | 2007-06-16 | Via Tech Inc | Memory card detect circuit |
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