TWI488163B - Shift register, gate drive circuit using the register and display device using the register - Google Patents

Description

Shift register, gate drive circuit and display device using the shift register

The present invention relates to a shift register and a display device using the shift register, in particular, a scan signal output of an adjacent shift register can be stored by adjusting an input of the shift register. delay.

When the shift register is integrated and applied to the gate driving circuit, the gate driving circuit having the shift register will output a scanning signal having the delay, so that the scanning signal can be driven at different time points. Scan line.

In current implementations of shift register circuits, additional circuit components are typically required to allow time delays between adjacent shift registers (eg, NAND gates). The setting (as disclosed in U.S. Patent No. 8022920) allows the output of the shift register and the external signal to perform additional operations through the inverse gate, or utilizes a duty cycle of less than fifty percent. The pulse wave is used as the input of the shift register (as shown in US Patent Publication No. 20110291712). In the case of the publication 20110291712, three sets of time pulses less than fifty percent of the duty cycle are adopted, thereby achieving time delay. effect. Whether it is the need to use additional gates or time pulses of less than 50 percent of the duty cycle to achieve a time delay between shift registers, there is room for improvement in overall circuit design complexity.

The invention discloses a shift register. The shift register includes a first pull-up signal generator for receiving a start pulse (SP), a first time The pulse signal and an inverted first clock signal. The shift register also includes a first pull-down signal generator electrically connected to the first pull-up signal generator, and a first inverter electrically connected to the first pull-up signal generator and the first pull-down signal a second inverter is electrically connected to the first inverter and generates an output signal, and a second pull-up signal generator is electrically connected to the second inverter, and receives a second clock signal and An inverting second clock signal and generating a scan signal, and a second pull-down signal generator electrically connected to the second pull-up signal generator.

Another embodiment of the invention discloses a gate drive circuit. The gate drive circuit includes a first shift register and a second shift register. Each of the first shift register and the second shift register includes a first pull-up signal generator for receiving a start pulse (SP), a first clock signal, and a Invert the first clock signal. The first shift register and the second shift register also include a first pull-down signal generator electrically connected to the first pull-up signal generator, and a first inverter electrically connected to the first The pull signal generator is electrically connected to the first pull-down signal generator, the second inverter is electrically connected to the first inverter and generates an output signal, and the second pull-up signal generator is electrically connected to the second inverter. And receiving a second clock signal and an inverted second clock signal and generating a scan signal, and a second pull signal generator electrically connected to the second pull-up signal generator.

The invention further discloses that the display device comprises a gate driving circuit, and the gate driving circuit comprises a first shift register and a second shift register. The display device described above additionally includes a touch module controlled by the gate driving circuit. The gate drive circuit includes a first shift register and a second shift register. each A first shift register and a second shift register each include a first pull-up signal generator for receiving a start pulse (SP), a first clock signal, and a counter Phase first pulse signal. The first shift register and the second shift register also include a first pull-down signal generator electrically connected to the first pull-up signal generator, and a first inverter electrically connected to the first a pull-up signal generator and a first pull-down signal generator, a second inverter is electrically connected to the first inverter and generates an output signal, and a second pull-up signal generator is electrically connected to the second reverse And receiving a second clock signal and an inverted second clock signal and generating a scan signal, and a second pull-down signal generator is electrically connected to the second pull-up signal generator.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a circuit block diagram of a display device 100 according to an embodiment of the present invention. The display device 100 includes a pixel array 102 and a gate drive circuit 106. The pixel array 102 includes a plurality of scan lines 114-126 and complex Several data lines 128-136. The scan lines 114-126 described above are electrically coupled to the gate drive circuit 106. The gate driving circuit 106 is configured to output a plurality of scanning signals, and each of the scanning signals is respectively connected to one of the scanning lines 114-126 for driving the scanning lines 114-126 in a predetermined sequence. . When the scan lines 114-126 are driven, the signals located on the data lines 128-136 can be read.

The second figure is a circuit diagram of a shift register 200 in accordance with an embodiment of the present invention. The shift register 200 includes a first pull-up signal generator 202 for receiving a start pulse (SP) 204, a first clock signal (CK1) 206, and an inversion first. Clock signal (XCK1) 208. The shift register 200 further includes a first pull-down signal generator 212 and a first inverter 214, the first pull-up signal generator 202, the first pull-down signal generator 212, and the first inversion. The 214 are electrically connected to each other.

The shift register 200 further includes a second inverter 216 electrically coupled to the first inverter 214 and generating an output signal (OUT) 218. The shift register 200 further includes a second pull-up signal generator 222 electrically coupled to the second inverter 216 and a second pull-down signal generator 224 electrically coupled to the second pull-up signal generator 222.

The second pull-up signal generator 222 is configured to receive a second clock signal (CK2) 226 and an inverted second clock signal (XCK2) 228 and generate a scan signal (SCAN) 232. This scan signal 232 is used to output to one of the scan lines 114-126 shown in the first figure.

In addition, the first inverter 214 and the first pull-down signal generator 212 receive the The first clock signal 206 and the second pull signal generator 224 receive the second clock signal 226. The shift register 200 further includes a first capacitor 234, a second capacitor 236 and a third capacitor 238.

Please continue to see the second picture. Because of the relationship between the first inverter 214 and the second inverter 216, the output level of the output 242 of the first pull-up signal generator 202 is the same as the output signal 218 (for example, also at a high level). quasi). In addition, when the first clock signal 206 and the start pulse wave 204 are both at the respective first levels, the output 242 of the first pull-up signal generator 202 can therefore be located at one of its corresponding first levels. In one embodiment, the first clock signal 206 and the first level of the initial pulse wave 204 are at a high level, and the first level of the output 242 of the first pull-up signal generator 202 is a corresponding low level. quasi.

In order to achieve the above result, the first pull-up signal generator 202 includes a first transistor 244 and a second transistor 246 as the first clock signal 206 (connected to the gate of the first transistor 244). When the initial pulse 204 (connected to the drain of the first transistor 244) is at its high level, the first transistor 244 is turned on, so that the second transistor 246 is also turned on. . Since the drain of the second transistor 246 is connected to the inverted first clock signal 208 which is low level at this time, and the second transistor 246 is turned on, the first pull-up signal generator 202 is enabled. The output level of the output 242 (i.e., the source signal level of the second transistor 246) is located at a corresponding first level (in the present embodiment, the first level is a low level). When the output 242 of the first pull-up signal generator 202 is at the low level, the output signal 218 is located at a corresponding low level.

Conversely, when the first clock signal 206 and the starting pulse wave 204 are located at a corresponding second level (in this embodiment, the so-called low level), the first transistor 244 is turned off. However, the second transistor 246 is kept open by the first capacitor 234 connected to the source of the first transistor 244 and the gate of the second transistor 246, so that the output of the first pull-up signal generator 202 is output. 242 receives an inverted first clock signal 208 and becomes a high level (or corresponds to one of the second levels). The high level output 242 will cause the output signal 218 to be at the corresponding high level.

The second pull-up signal generator 222 includes a third transistor 248 and a fourth transistor 252. The gate of the third transistor 248 is coupled to the second clock signal 226 and the drain of the fourth transistor 252 is coupled to the inverted second clock signal 228.

The second clock signal 226 is a signal whose period is smaller than the first clock signal 206, and the second clock signal 226 may be set in the same manner as the first clock signal 206 in one cycle of the first clock signal 206. Keep at the first level, or both at different levels (one for the high level and the other for the low level). However, the first clock signal 206 and the second clock signal 226 are pulse waves with a duty cycle of 50%.

As described above, when the first clock signal 206 is at a low level, the output signal 218 is at its corresponding high level, and when the second clock signal 226 is also at its corresponding first level (here is The high level, which is a predetermined level of the second clock signal 226, the third transistor 248 is turned on, and the high level output signal 218 is stored in the third capacitor 238. The high level output signal 218 stored in the third capacitor 238 will change to the corresponding second level (in the present embodiment, the low level) in the second clock signal 226, so that the fourth transistor 252 is turned on, so that the scan is performed. Line 232 An inverted second clock signal 228 is received to become a high level.

The first pull-down signal generator 212 includes a fifth transistor 254, the gate of which is used to receive the first clock signal 206, and the second pull-down signal generator 224 includes the sixth transistor 255. The pole system receives the second clock signal 226.

The first inverter 214 includes a seventh transistor 256 and an eighth transistor 258, and the second inverter 216 includes a ninth transistor 262 and a tenth transistor 264.

The output signal 218 of the shift register 200 is output to the shift register of the next stage as the starting pulse of the next stage shift register. The first clock signal of the shift register of the next stage is the inverted first clock signal 208 input to the shift register 200, and the inverted first clock signal of the next stage shift register Then, it comes from the first clock signal 206 input to the shift register 200.

Please refer to the second figure at the same time. The third figure is a signal clock diagram according to an embodiment of the present invention. Taking the shift register 200 of the second figure as an example, the signal 302 in the third figure is the first clock signal 206 of the second figure, and the signal 304 of the third figure is the input to the first pull-up signal. The 202 (or the second transistor 246) inverts the first clock signal 208, and the signals 306 and 308 correspond to the second clock signal 226 and the inverted second clock signal 228, respectively. The signal 312 is a waveform indicating the start pulse 208 of the shift register 200 and the signal 314 is the output signal 218. At the same time, the signal 316 represents the scan signal 232 outputted by the shift register 200. Waveforms 318 and 322 are output signals and scan signals respectively representing the next stage shift register (or the shift register serially connected to shift register 200).

The output signal (signal 314) of one level and the output signal (signal 318) of the next stage In the architecture of the shift register 200 of the second figure, it is generated when the first clock signal (signal 302) is at its corresponding second level. Therefore, when the first clock signal of the next-stage shift register is equal to the inverted clock signal of the shift register of the previous stage, when the first clock signal of the previous shift register rises to the first When the bit is in time, the input to the first clock signal of the next stage (that is, the inverted first clock signal of the previous stage, and at this time becomes the second level), the output signal of the next stage shift register is This can be generated only by the output signal of the shift register in the upper stage, and the output signal of the next stage shift register is delayed by half the period of the first clock signal.

As described above, the generation of the scan signal of a certain stage of the shift register is determined based on the output signal of the same stage shift register and the level of the second clock signal in the circuit architecture of the second figure. Taking the third figure as an example, when the output signal is at its corresponding high level (that is, when an output signal is generated) and the second clock signal becomes a low level, the scan signal of the shift register is generated.

When there is no change in the input of the second clock signal, and there is a delay between the output signals of the adjacent serially connected shift registers, the delay of the output signal of the adjacent serial shift register is A delay in scanning signals between adjacent shift registers.

It can be seen from the signals 316 and 322 that there is a predetermined delay in the scanning signals outputted by the two consecutive serially connected shift registers, and the predetermined delay is equal to half of the second clock signal (such as the signal 306) in one embodiment. Cycles (or the length of time when the second clock signal is at the first level/second level).

Delaying the driving of the scanning signals of each adjacent scanning line can help ensure that when the Nth scanning line is driven, only the signal receiving line corresponding to the Nth scanning line is used. The material will be received, so that the probability of data interference on each other is reduced.

Please refer to the fourth figure. The fourth figure is a schematic diagram of signals electrically connected by a serially connected shift register according to an embodiment of the invention. Assume that the number of serially shifted shift registers is N (or, assuming that the number of scan lines that need to be driven is N), and the circuit of the shift register in the fourth figure is as shown in the second figure. .

These shift registers (S/R(1)-S/R(N)) are provided in the gate drive circuit 112 as in the first figure. The gate drive circuit 112 drives the scan lines 114-126 based on the scan signals of the shift registers. The output signal (OUT) of S/R(1) (or the output signal 218 of the shift register 200) is used as the starting pulse of the next stage shift register (S/R(2)) ( SP), and the output signal (OUT) of S/R(2) is used as the starting pulse of the next stage (S/R(3)).

In addition, in order to achieve the effect of delaying the scanning signals between the shift registers of each stage, the first clock signal (CK1) and the inverted first clock signal input to a shift register ( XCK1) is respectively connected to the inverted first clock signal and the first clock signal of the upper shift register. For example, the first clock signal (CK1) received by the shift register S/R(1) is input to the shift register S/R(2) to receive the inverted first clock. The position of the signal (for example, the signal 208 of the shift register 200), and the inverted first clock signal (XCK1) received by the shift register S/R (2) is set to input to The shift register S/R (3) is used to receive the position of the first clock signal (such as the signal 206 of the shift register 200). However, for the serial shift register S/R(1)-S/R(N), the input of the second clock signal and the inverted second clock signal is between the shift registers. It has not changed.

Therefore, the present invention does not require the use of an additional anti-gate, and only uses two sets of clock signals (and their inversions) with 50% duty cycle to achieve the result of delaying the output of the adjacent shift register. The implementation of the entire circuit design is relatively simple.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

100‧‧‧ display device

102‧‧‧ pixel array

106‧‧‧ gate drive circuit

114-126‧‧‧ scan line

128-136‧‧‧Information line

200‧‧‧Shift register

202‧‧‧First pull-up signal generator

204‧‧‧Starting pulse wave

206, 302‧‧‧ first clock signal

208, 304‧‧‧ Inverted first clock signal

212‧‧‧First pulldown signal generator

214‧‧‧First Inverter

216‧‧‧Second inverter

218, 314, 318‧‧‧ output signals

222‧‧‧Second pull-up signal generator

224‧‧‧Second pulldown signal generator

226, 306‧‧‧ second clock signal

228, 308‧‧‧ reverse second clock signal

232, 316, 322‧‧‧ scan signals

234‧‧‧first capacitor

236‧‧‧second capacitor

238‧‧‧ third capacitor

242‧‧‧First pull-up signal generator output

244‧‧‧First transistor

246‧‧‧second transistor

248‧‧‧ Third transistor

252‧‧‧4th transistor

254‧‧‧ fifth transistor

255‧‧‧ sixth transistor

256‧‧‧ seventh transistor

258‧‧‧ eighth transistor

262‧‧‧Ninth transistor

264‧‧‧10th transistor

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit block diagram of a display device in accordance with an embodiment of the present invention.

Figure 2 is a simplified circuit diagram of a shift register in accordance with one embodiment of the present invention.

Figure 3 is a signal clock diagram in accordance with an embodiment of the present invention.

4 is a schematic diagram of signals electrically connected by a serially connected shift register according to an embodiment of the invention.

200‧‧‧Shift register

202‧‧‧First pull-up signal generator

204‧‧‧Starting pulse wave

206‧‧‧First clock signal

208‧‧‧Inverted first clock signal

212‧‧‧First pulldown signal generator

214‧‧‧First Inverter

216‧‧‧Second inverter

218‧‧‧ output signal

222‧‧‧Second pull-up signal generator

224‧‧‧Second pulldown signal generator

226‧‧‧second clock signal

228‧‧‧Inverse second clock signal

232‧‧‧ scan signal

234‧‧‧first capacitor

236‧‧‧second capacitor

238‧‧‧ third capacitor

242‧‧‧First pull-up signal generator output

244‧‧‧First transistor

246‧‧‧second transistor

248‧‧‧ Third transistor

252‧‧‧4th transistor

254‧‧‧ fifth transistor

255‧‧‧ sixth transistor

256‧‧‧ seventh transistor

258‧‧‧ eighth transistor

262‧‧‧Ninth transistor

264‧‧‧10th transistor

Claims (30)

A shift register includes: a first pull-up signal generator for receiving a start pulse (SP), a first clock signal, and an inverted first clock signal; The first pull-down signal generator is electrically connected to the first pull-up signal generator; a first inverter is electrically connected to the first pull-up signal generator and the first pull-down signal generator; The phase device is electrically connected to the first inverter and generates an output signal; a second pull-up signal generator is electrically connected to the second inverter, and receives a second clock signal and an inverted second The clock signal generates a scan signal; and a second pull-down signal generator is electrically connected to the second pull-up signal generator. The shift register of claim 1, wherein the output level of one of the first pull-up signal generators is the same as the output signal, and the first pull-up signal generator includes a first power a gate, the gate of the first transistor is configured to receive the first clock signal, and one drain of the first transistor is configured to receive the initial pulse wave, the first The pull-up signal generator further includes a second transistor, one gate of the second transistor is electrically connected to one source of the first transistor, and one of the second transistors is used for the drain Receiving the inverted first clock signal. The shift register of claim 2, wherein the output level of the first pull-up signal generator is when the first clock signal and the start pulse wave are both at a first level The first level is in a corresponding one of the first level, wherein the output level is a signal level of a source of the second transistor of the first pull-up signal generator. The shift register of claim 3, wherein the first pull-up signal generator further comprises a capacitor connected to the source of the first transistor and the source of the second transistor. And maintaining a first level signal generated when the first clock signal and the starting pulse wave are both at their respective first levels. The shift register of claim 1, wherein when the second clock signal is at a predetermined level, the scan signal is at the same level as the output signal. The shift register of claim 1, wherein the second pull-up signal generator further includes a capacitor, the second pull-up signal generator includes a third transistor and a fourth transistor, the first One of the gates of the three transistors is configured to receive the second clock signal, and one of the fourth transistors is configured to receive the inverted second clock signal, and the capacitor is respectively connected to the third battery One source of the crystal, one of the gates of the fourth transistor, and one of the sources of the fourth transistor, and the capacitor is used to maintain the output signal and the second clock signal in one of their respective ones Another first quasi-signal generated by the first one on time. The shift register of the first item of claim 1, wherein one of the first clock signals is greater than one cycle of the second clock signal, and the output signal is used as the next stage of the shift register The starting pulse of the device. The shift register of item 1 of the claim, wherein the first pulldown generator package A fifth transistor is included, and one of the gates of the fifth transistor receives the first clock signal, and one of the fifth transistors is connected to the first pull-up signal generator, and the second pull-down is The signal generator includes a sixth transistor, one of the gates of the sixth transistor is configured to receive the second clock signal, and one of the sixth transistors is connected to the second pull-up signal Device. The shift register of claim 1, wherein the first inverter comprises a seventh transistor and an eighth transistor, and one of the seventh transistors receives the first clock signal One gate of the eighth transistor is connected to the first pull-up signal generator, and one source of the seventh transistor is connected to one of the drains of the eighth transistor. The shift register of claim 1, wherein the second inverter comprises a ninth transistor and a tenth transistor, and one of the ninth transistor and one of the tenth transistors a gate is connected to the first inverter, a source of the ninth transistor is connected to one of the tenth transistors, and the output signal is located at the source of the ninth transistor One of the drains of the tenth transistor. A gate driving circuit includes: a first shift register; and a second shift register; wherein the first shift register and the second shift register both include a first a pull-up signal generator for receiving a start pulse (SP), a first clock signal, and an inverted first clock signal, a first pull-down signal generator, and a first inverse The phase device is electrically connected to the first pull-up signal And a first pull-down signal generator, a second inverter is electrically connected to the first inverter and generates an output signal, and a second pull-up signal generator is electrically connected to the second inverter Receiving a second clock signal and an inverting second clock signal and generating a scan signal, and a second pull-down signal generator electrically connected to the second pull-up signal generator; wherein the second shift The initial pulse wave of the register is the output signal of the second inverter in the first shift register, and one cycle of the first clock signal is greater than one of the second clock signals The period, and the scan signal output by the first shift register and the scan signal output by the second shift register have a delay. The gate driving circuit of claim 11, wherein the delay is one of the first level time lengths of the second clock signal. The gate driving circuit of claim 11, wherein an output of the first pull-up signal generator is at the same level as the output signal, and the first pull-up signal generator includes a first transistor, a gate of the first transistor is configured to receive the first clock signal, and a drain of the first transistor is configured to receive the initial pulse wave, the first pull-up signal The generator further includes a second transistor, one of the gates of the second transistor is electrically connected to a source of the first transistor, and one of the second transistors is used to receive the Invert the first clock signal. The gate driving circuit of claim 13, wherein the first pull-up signal is generated when the first clock signal and the initial pulse wave are both at a first level The output of the device is located at a corresponding one of the first levels, wherein the output level refers to a signal level of a source of the second transistor of the first pull-up signal generator. The gate driving circuit of claim 14, wherein the first pull-up signal generator further comprises a capacitor respectively connected to the source of the first transistor and the gate of the second transistor, And maintaining a first level signal generated when the first clock signal and the starting pulse wave are both at their respective first levels. The gate driving circuit of claim 11, wherein when the second clock signal is at a predetermined level, the scanning signal is at the same level as the output signal. The gate driving circuit of claim 11, wherein the second pull-up signal generator further comprises a capacitor, the second pull-up signal generator comprises a third transistor and a fourth transistor, the third One gate of the transistor is configured to receive the second clock signal, and one of the fourth transistors is configured to receive the inverted second clock signal, and the capacitor is respectively connected to the third transistor a source, a gate of the fourth transistor, and a source of the fourth transistor, and the capacitor is configured to maintain the output signal and the second clock signal in a respective one of the respective Another first quasi-signal generated by a punctuality. The gate driving circuit of claim 11, wherein the first pull-down signal generator comprises a fifth transistor, and one of the fifth transistors receives the first clock signal, the fifth power One of the crystals of the crystal is connected to the first pull-up signal generator, the second pull-down signal generator includes a sixth transistor, and one of the gates of the sixth transistor is used to receive the second clock signal And one of the sixth transistors is connected to the second pull-up signal generator. The gate driving circuit of claim 11, wherein the first inverter comprises a seventh transistor and an eighth transistor, and a gate of the seventh transistor receives the first clock signal, One gate of the eighth transistor is connected to the first pull-up signal generator, and one source of the seventh transistor is connected to one of the drains of the eighth transistor. The gate driving circuit of claim 11, wherein the second inverter comprises a ninth transistor and a tenth transistor, and one of the ninth transistor and one of the tenth transistors a pole is connected to the first inverter, a source of the ninth transistor is connected to one of the tenth poles of the tenth transistor, and the output signal is located at the source of the ninth transistor One of the drains of the tenth transistor. A display device includes: a display module; and a gate driving circuit coupled to the display module; wherein the gate driving circuit includes a first shift register and a second shift register; The first shift register and the second shift register each include a first pull-up signal generator for receiving a start pulse (SP), a first clock signal, and An inverting first clock signal, a first pull-down signal generator, a first inverter electrically connected to the first pull-up signal generator and the first pull-down signal generator, and a second inversion The device is electrically connected to the first inverter and generates an output signal, and a second pull-up signal generator is electrically connected to the second inverter system to receive a second time And a second pull-down signal generator is electrically connected to the second pull-up signal generator; wherein the second shift register is started The pulse wave is the output signal of the second inverter in the first shift register, one cycle of the first clock signal is greater than one cycle of the second clock signal, and the first shift The scan signal of the bit buffer and the scan signal of the second shift register have a delay. The display device of claim 21, wherein the delay is one of the first level time lengths of the second clock signal. The display device of claim 21, wherein the output of one of the first pull-up signal generators is at the same level as the output signal, and the first pull-up signal generator comprises a first transistor, the first A gate of the transistor is configured to receive the first clock signal, and one drain of the first transistor is used to receive the initial pulse wave, and the first pull-up signal generator In addition, a second transistor is included, one of the gates of the second transistor is electrically connected to one source of the first transistor, and one of the second transistors is used to receive the reverse phase The first clock signal. The display device of claim 23, wherein when the first clock signal and the initial pulse wave are both at a first level, the output of the first pull-up signal generator is located in a corresponding one of The first level, wherein the output level refers to a signal level of a source of the second transistor of the first pull-up signal generator. The display device of claim 24, wherein the first pull-up signal generator further comprises two capacitors respectively connected to the source of the first transistor and the gate of the second transistor for maintaining One of the first level signals generated when the first clock signal and the initial pulse wave are both at their respective first levels. The display device of claim 21, wherein when the second clock signal is at a predetermined level, the scan signal is at the same level as the output signal. The display device of claim 21, wherein the second pull-up signal generator further comprises a capacitor, the second pull-up signal generator comprising a third transistor and a fourth transistor, the third transistor One gate is configured to receive the second clock signal, and one of the fourth transistors is configured to receive the inverted second clock signal, and the capacitor is respectively connected to one of the third transistors a source, a gate of the fourth transistor, and a source of the fourth transistor, and the capacitor is configured to keep the output signal and the second clock signal in a first position Another first quasi-signal generated on time. The display device of claim 21, wherein the first pull-down signal generator comprises a fifth transistor, and one of the fifth transistors receives the first clock signal, the fifth transistor a first pull-up signal generator is connected to the first pull-up signal generator, the second pull-down signal generator includes a sixth transistor, and one of the gates of the sixth transistor is configured to receive the second clock signal, and One of the sixth transistors is connected to the second pull-up signal generator. The display device of claim 21, wherein the first inverter comprises a seventh transistor and an eighth transistor, and the gate of the seventh transistor receives the first a clock signal, one gate of the eighth transistor is connected to the first pull-up signal generator, and one source of the seventh transistor is connected to one of the drains of the eighth transistor. The display device of claim 21, wherein the second inverter comprises a ninth transistor and a tenth transistor, and one of the ninth transistor and one of the tenth transistor Connected to the first inverter, one source of the ninth transistor is connected to one of the tenth transistors, and the output signal is located at the source and the tenth of the ninth transistor One of the drains of the transistor.