TWI476898B - Semiconductor structure and manufacturing method of the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure for a memory device and a method of fabricating the same.

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. However, as the size of the memory device is reduced, the feature size of the memory unit is also reduced, which tends to cause a decrease in the reliability of the memory device. Therefore, designers are all committed to developing research to improve the reliability of memory devices.

The present invention relates to a semiconductor structure and a method of fabricating the same, which can be applied to a memory device. Each of the conductive damascene structures of the semiconductor structure is independently formed on both sides of the stacked structure in a damascene manner such that the conductive damascene structures are completely spaced apart from each other, and there is no residual conductive material between the conductive damascene structures. The insulation between the conductive mosaic structures has good insulation, thereby improving the reliability of the memory device.

According to an aspect of the invention, a semiconductor structure is proposed. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure is formed on a substrate, and the stacked structure includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The first conductive block is formed on the stacked structure, and the first conductive layer and the second conductive layer are respectively formed on both sidewalls of the stacked structure. The conductive damascene structure is formed on both sides of the stacked structure, and each of the first conductive blocks is electrically connected to each of the conductive damascene structures via the first conductive layers and the second conductive layers.

According to another aspect of the present invention, a method of fabricating a semiconductor structure is proposed. The manufacturing method of the semiconductor structure comprises: forming a stacked structure on a substrate, comprising forming a plurality of conductive strips and a plurality of insulating strips, the conductive strips and the insulating strips are interlaced; forming a plurality of first conductive blocks on the stack Structurally forming a plurality of first conductive layers and a plurality of second conductive layers on both sidewalls of the stacked structure; and forming a plurality of conductive damascene structures on both sides of the stacked structure, wherein each of the first conductive layers The block is electrically connected to each of the conductive damascene structures via the first conductive strips and the second conductive strips.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. Each of the conductive damascene structures of the semiconductor structure are independently formed on both sides of the stacked structure in a damascene manner such that the conductive damascene structures are completely spaced apart from each other, and there is no residual conductive material between the conductive damascene structures, and each of the conductive damascene structures has Good insulation, which improves the reliability of the memory device. However, the detailed structure and process steps set forth in the examples are for illustrative purposes only and are not intended to limit the scope of the invention. These steps are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation.

1A is a schematic top view of a semiconductor structure according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line 1B-1B' of FIG. 1A, and FIG. 1C to FIG. A schematic cross-sectional view of the section line 1C-1C'.

Please refer to Figures 1A~1B. The semiconductor structure 100 includes a substrate 110, a stacked structure 120, a plurality of first conductive blocks 141, a plurality of first conductive layers 131 and a plurality of second conductive layers 133, and a plurality of conductive damascene structures. The stacked structure 120 is formed on the substrate 110. The stacked structure 120 includes a plurality of conductive strips 121 and a plurality of insulating strips 123. The conductive strips 121 and the insulating strips 123 are interlaced. The first conductive block 141 is formed on the stacked structure 120, and the first conductive layer 131 and the second conductive layer 133 are respectively formed on the two sidewalls 120a of the stacked structure 120. The conductive damascene structure 150 is formed on both sides of the stacked structure 120 , and the first conductive block 141 is electrically connected to the conductive damascene structure 150 via the first conductive layer 131 and the second conductive layer 133 .

In one embodiment, as shown in FIG. 1A, the semiconductor structure 100 may further include an insulating structure 160 formed between the conductive damascene structures 150. In an embodiment, as shown in FIG. 1B , the semiconductor structure 100 may include a plurality of stacked structures 120 , and the insulating structures 160 are also formed between the stacked structures 120 . In an embodiment, the extending direction D1 of the conductive damascene structure 150 is, for example, perpendicular to the extending direction D2 of the stacked structure 120. In the embodiment, the material of the insulating structure 160 includes, for example, an oxide.

In one embodiment, the semiconductor structure 100 is a 3D memory device. As shown in FIGS. 1A-1B, the stacked structure 120 is, for example, a bit line, and the conductive mosaic structure 150 is, for example, The main structure of the word line applies an operating voltage via the first conductive layer 131 and the second conductive layer 133. Conventionally, after forming a whole metal layer, the metal layer is etched to form separate word lines. However, the metal material remaining between the word lines may be short-circuited due to the complete etching, so that the memory device cannot operate. . In contrast, in the embodiment of the present invention, the conductive damascene structures 150 are independently formed on both sides of the stacked structure 120 in a damascene manner, so that the conductive damascene structures 150 are completely spaced apart from each other, such that In addition, there is no residual conductive material between the inlaid word lines, and it can have good insulation, which can ensure the memory device works well and improve the reliability of the memory device.

In one embodiment, as shown in FIG. 1B , the semiconductor structure 100 may further include a dielectric layer 170 formed on the stacked structure 120 and the conductive damascene structure 150 . In an embodiment, the semiconductor structure 100 may further include an etch barrier layer 173 disposed between the dielectric layer 170 and the stacked structure 120, for example. In the embodiment, the material of the dielectric layer 170 includes, for example, a metal oxide. The material of the etch barrier layer 173 includes, for example, a metal nitride. However, in practical applications, the materials are also appropriately selected depending on the application, and the materials are not limit.

In one embodiment, as shown in FIG. 1B, the semiconductor structure 100 may further include a memory material layer 180 formed on both sidewalls 120a of the stacked structure 120. In an embodiment, the memory material layer 180 is formed, for example, between the first conductive layer 131 and the stacked structure 120 and between the second conductive layer 133 and the stacked structure 120. In the embodiment, as shown in FIG. 1B, the memory material layer 180 is formed on the substrate 110. In another embodiment, the memory material layer 180 may also be formed only on the sidewalls 120a of the stacked structure 120 without being formed on the substrate 110 (not shown). In an embodiment, the memory material layer 180 may have a multi-layer structure, such as an ONO composite layer or an ONONO composite layer or a BE-SONOS composite layer, or an ONO structure including, for example, a stack of yttrium oxide and tantalum nitride.

In one embodiment, as shown in FIG. 1B, the semiconductor structure 100 may further include an oxide layer 115 formed between the stacked structure 120 and the substrate 110.

Please refer to Figure 1C. The semiconductor structure 100 may further include a second conductive block 143, a third conductive layer 135, and a fourth conductive layer 137. The second conductive block 143 is formed on the stacked structure 120, and the third conductive layer 135 and the fourth conductive layer 137 are respectively formed on the two sidewalls 120a of the stacked structure 120, the second conductive block 143 and the third conductive layer 135 and the fourth conductive layer Layer 137 is electrically connected. In the embodiment, as shown in FIG. 1A, the second conductive block 143, the third conductive layer 135, and the fourth conductive layer 137 are located at the end of the semiconductor structure 100, for example. In the embodiment, the first conductive block 141 and the second conductive block 143 have the same material, for example, and the first conductive layer 131, the second conductive layer 133, the third conductive layer 135, and the fourth conductive layer 137 have the same material, for example. In the embodiment, the material of the substrate 110, the conductive blocks 141 and 143, and the conductive layers 131, 133, 135, and 137 include a germanium-containing material, such as a polysilicon, but in practical applications, the materials are also appropriately selected depending on the application state, and Not limited to the aforementioned materials.

In one embodiment, the semiconductor structure 100 is a three-dimensional memory device. As shown in FIG. 1D, the second conductive block 143 is, for example, a string select line (SSL).

In one embodiment, as shown in FIG. 1C, the semiconductor structure 100 may further include an insulating damascene structure 190 formed on both sides of the second conductive block 143, and the insulating damascene structure 190 is connected, for example. And a second conductive block 143. In the embodiment, as shown in FIG. 1C, the insulating damascene structure 190 covers, for example, the third conductive layer 135 and the fourth conductive layer 137. In an embodiment, the extending direction D3 of the insulating damascene structure 190 is, for example, parallel to the extending direction D1 of the conductive damascene structure 150.

In an embodiment, please refer to FIG. 1D. The semiconductor structure 100 may further include a contact hole 175 formed in the dielectric layer 170 and electrically connected to the second conductive block 143. In the embodiment, as shown in FIG. 1D, the contact hole 175 is electrically connected to the second conductive block 143 through the etch barrier layer 173.

The following is a method of fabricating a semiconductor structure of the embodiments, which are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation. Please refer to Figures 2A to 21. 2A through 21 are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

Referring to FIGS. 2A-2B (FIG. 2B is a cross-sectional view along section line 2B-2B' of FIG. 2A), a stacked structure 120 is formed on the substrate 110. The manufacturing method of forming the stacked structure 120 includes, for example, forming a plurality of conductive strips 121 and a plurality of insulating strips 123, and the conductive strips 121 and the insulating strips 123 are interlaced. In one embodiment, as shown in FIGS. 2A-2B, a plurality of stacked structures 120 may also be formed on the substrate 110.

Next, as shown in FIGS. 2A to 11E, a plurality of first conductive blocks 143 are formed on the stacked structure 120, and a plurality of first conductive layers 131 and a plurality of second conductive layers 133 are respectively formed on both sidewalls of the stacked structure 120. On 120a. The manufacturing method of forming the first conductive bumps 143, the first conductive layer 131, and the second conductive layer 133 includes, for example, the following steps.

As shown in FIGS. 2A-2B, a conductive material layer 140 is formed on the stacked structure 120. In an embodiment, an oxide layer 115 may also be formed between the stacked structure 120 and the substrate 110.

As shown in Figs. 3A to 3B (Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A), a memory material coating layer 180a is formed on the stacked structure 120. In an embodiment, the memory material coating layer 180a completely covers the stacked structure 120, the conductive material layer 140, and the substrate 110. The memory material coating layer 180a includes a charge trapping material such as an ONO composite layer or an ONONO composite layer or a BE-SONOS composite layer, or an ONO structure including, for example, a stack of yttrium oxide and tantalum nitride.

As shown in Figs. 4A-4B (Fig. 4B is a cross-sectional view taken along line 4B-4B' of Fig. 4A), a sacrificial layer 210 is formed on the substrate 110. In an embodiment, the sacrificial layer 210 surrounds the stack structure 120 and the memory material coating layer 180a and exposes at least a portion of the conductive material layer 140 and the memory material coating layer 180a. In an embodiment, the sacrificial layer 210 includes, for example, pure carbon, a carbon-containing oxide, a bottom antireflective coating (BARC), or a silicon rich bulk (SHB). The sacrificial layer 210 may also be, for example, a disposable film whose material includes a carbon like organic material, which is easy to coat and easy to remove. The sacrificial layer 210 may be formed by coating and then performing an etch back process, and the etch back process has high selectivity to the memory material coating layer 180a.

As shown in FIGS. 5A-5B (FIG. 5B is a cross-sectional view along section line 5B-5B' of FIG. 5A), the memory material coating layer 180a is etched to expose the conductive material layer 140 to form a memory material layer. 180 is on the two sidewalls 120a of the stacked structure 120. In an embodiment, for example, the memory material coating layer 180a exposed outside the sacrificial layer 210 is etched, and the top of the memory material layer 180 formed after etching is substantially flush with the upper surface of the sacrificial layer 210. In an embodiment, the memory material layer 180 is formed, for example, between the sacrificial layer 210 and the stacked structure 120.

As shown in Figs. 6A to 6B (Fig. 6B is a schematic cross-sectional view taken along line 6B-6B' of Fig. 6A), the sacrificial layer 210 is removed to expose the memory material layer 180. In an embodiment, a portion of the memory material layer 180 on the substrate 110 may also be removed such that the memory material layer 180 is only located on the sidewalls 120a of the stacked structure 120 (not shown).

As shown in Figs. 7A-7B (Fig. 7B is a cross-sectional view taken along line 7B-7B' of Fig. 7A), a conductive material layer 130 is formed on the stacked structure 120 and the conductive material layer 140. In an embodiment, the conductive material layer 130 completely covers the conductive material layer 140 and the memory material layer 180. The conductive material layer 130 is, for example, a highly doped polysilicon or a conformal conductive film.

As shown in Figs. 8A-8B (Fig. 8B is a cross-sectional view taken along line 8B-8B' of Fig. 8A), the conductive material layer 130 is etched to expose a portion of the conductive material layer 140. In an embodiment, the layer of conductive material 130 covers the layer of memory material 180 and surrounds the stacked structure 120.

As shown in Figs. 9A to 9B (Fig. 9B is a schematic cross-sectional view taken along line 9B-9B' of Fig. 9A), a sacrificial layer 220 is formed on the substrate 110. In an embodiment, the sacrificial layer 220 surrounds the stacked structure 120 and covers the conductive material layer 130 on the sidewall 120a, exposing the upper surface 140a of the conductive material layer 140. The method of fabricating the sacrificial layer 220 includes, for example, forming a sacrificial coating to completely cover the conductive material layer 130, the conductive material layer 140, and the substrate 110, and planarizing the sacrificial coating to expose the upper surface 140a of the conductive material layer 140. In an embodiment, the sacrificial coating is planarized, for example, by chemical mechanical polishing (CMP). In the embodiment, the material of the sacrificial layer 220 includes, for example, silicon nitride (SiN).

As shown in FIGS. 10A-10E (Fig. 10B-10E respectively show a cross-sectional view along section line 10B-10B' to section line 10E-10E' of Fig. 10A), the sacrificial layer 220 is patterned to form a plurality of The strip-shaped sacrificial layer 220a, the extending direction D4 of the sacrificial strip 220a is, for example, perpendicular to the extending direction D2 of the stacked structure 120. In an embodiment, the manufacturing method of forming the plurality of strip sacrificial layers 220a includes, for example, disposing a plurality of strip photoresists PR1 on the sacrificial layer 220, and etching the sacrificial layer 220 according to the pattern of the strip photoresists PR1 to form a strip sacrificial layer. Layer 220a. In the embodiment, a plurality of strip-shaped photoresists PR1 are disposed, for example, in a self-aligned double patterning (SADP) manner. In the embodiment, the position of the strip sacrificial layer 220a is the predetermined formation position of the conductive damascene structure in the subsequent process.

As shown in Figures 11A to 11E (Fig. 11B to 11E respectively show a cross-sectional view taken along section line 11B-11B' to section line 11E-11E' of Fig. 11A), the removal is not covered by the strip photoresist PR1. The conductive material layer 140 in the region is formed on the stacked structure 120 by forming a plurality of first conductive bumps 141 and a second conductive bumps 143. In the embodiment, the conductive material layer 130 in the region not covered by the strip photoresist PR1 is also removed to form a plurality of first conductive layers 131 and a plurality of second conductive layers 133 on the sidewalls 120a of the stacked structure 120. . In the embodiment, each of the first conductive blocks 141 is spaced apart from each other, and each of the first conductive layers 131 is spaced apart from each other, and each of the second conductive layers 133 is spaced apart from each other. In the embodiment, each of the first conductive blocks 141 is adjacent to the corresponding first conductive layer 131 and the second conductive layer 133, and each of the first conductive layers 131 and the respective second conductive layers 133 are adjacent to the corresponding strip-shaped sacrificial layer 220a. In the embodiment, the first conductive block 141 is electrically connected to the first conductive layer 131 and the second conductive layer 133.

As shown in FIGS. 11A-11E, the conductive material layer 140 and the conductive material layer 130 in the region not covered by the strip photoresist PR1 are removed, and a second conductive block 143 is formed on the stacked structure 120 and a third. The conductive layer 135 and a fourth conductive layer 137 (not shown) are on the sidewalls 120a of the stacked structure 120. In the embodiment, the first conductive block 141 and the second conductive block 143 are spaced apart, the first conductive layer 131 and the third conductive layer 135 are spaced apart, and the second conductive layer 133 and the fourth conductive layer 137 are spaced apart. In an embodiment, the third conductive layer 135 and the fourth conductive layer 137 are adjacent to the corresponding strip sacrificial layer 220a. In the embodiment, the second conductive block 143 is electrically connected to the third conductive layer 135 and the fourth conductive layer 137.

Next, as shown in Figs. 12A to 12E (Fig. 12B to Fig. 12E are schematic cross-sectional views taken along line 12B-12B' of Fig. 12A to section line 12E-12E', respectively, the strip photoresist PR1 is removed.

Next, as shown in FIGS. 13A-13E (Fig. 13B-13E respectively show a cross-sectional view along the section line 13B-13B' to the section line 13E-13E' of Fig. 13A), an insulating structure 160 may also be formed. Between the sacrificial layers 220a (that is, between the conductive damascene structures formed in subsequent processes). In an embodiment, the insulating structure 160 is also formed between the plurality of stacked structures 120. In an embodiment, the manufacturing method for forming the insulating structure 160 includes, for example, forming an insulating material layer on the stacked structure 120, the first conductive block 141, the second conductive block 143, and the strip sacrificial layer 220a, and planarizing the insulating material layer to expose The first conductive block 141, the second conductive block 143, and the strip sacrificial layer 220a are formed. In an embodiment, the layer of insulating material is planarized, for example, by chemical mechanical polishing (CMP).

Next, as shown in Figs. 14A to 14E (Fig. 14B to Fig. 14E respectively show a cross-sectional view taken along line 14B-14B' to section line 14E-14E' of Fig. 14A), a cap layer may also be formed. The second conductive block 143, the third conductive layer 135, the fourth conductive layer 137, and the strip-shaped sacrificial layer 220a disposed adjacent to the three. In an embodiment, the manufacturing method of forming the shielding layer 230 includes: forming a masking material layer covering the first conductive block 141, the second conductive block 143, the first conductive layer 131, the second conductive layer 133, and the third conductive layer 135, a fourth conductive layer 137 and a strip sacrificial layer 220a, and a portion of the masking material that removes the second conductive bump 143, the third conductive layer 135, the fourth conductive layer 137, and the strip sacrificial layer 220a disposed adjacent to the three Floor. In the embodiment, the material of the shielding layer 230 includes, for example, an oxide.

Next, as shown in Figs. 15A to 16E, a plurality of conductive damascene structures 150 are formed on both sides of the stacked structure 120. Each of the first conductive blocks 141 is electrically connected to each of the conductive damascene structures 150 via the first conductive strips 131 and the second conductive strips 133 . The manufacturing method of forming the conductive damascene structures 150 on both sides of the stacked structure 120 includes, for example, the following steps.

As shown in FIGS. 15A-15E (Fig. 15B-15E respectively show a cross-sectional view of the section line 15B-15B' to the section line 15E-15E' along the 15A diagram), a plurality of grooves T are formed in the stack structure 120. On both sides. In the embodiment, the extending direction D5 of the groove T is, for example, perpendicular to the extending direction D2 of the stacked structure 120. In an embodiment, the manufacturing method of forming the recess T includes, for example, removing the strip sacrificial layer 220a that is not covered by the shielding layer 230. In the embodiment, the strip sacrificial layer 220a is removed by etching, for example, and the strip sacrificial layer 220a covered by the shielding layer 230 is not removed.

As shown in Figs. 16A to 16E (Fig. 16B to Fig. 16E are respectively sectional views of the section line 16B-16B' to the section line 16E-16E' along the 16A), and the conductive material is filled in the groove T, To form a conductive damascene structure 150. In an embodiment, the conductive damascene structure 150 is formed in the spaced apart trenches T, thus providing good insulation between the conductive damascene structures 150. That is, the respective conductive damascene structures 150 are independently embedded in the spaced apart grooves T and spaced apart from each other, so that there is no residual conductive material between the respective conductive damascene structures 150, and good insulation is possible. Sex, which in turn improves the reliability of the subsequently completed device.

Next, as shown in Figs. 17A to 17E (Fig. 17B to Fig. 17E are schematic cross-sectional views taken along line 17B-17B' of Fig. 17A to section line 17E-17E', respectively, the mask layer 230 is removed.

Next, as shown in Figs. 18A to 19F, an insulating damascene structure 190 may be formed on both sides of the second conductive block 143. The insulating damascene structure 190 is adjacent to the second conductive block 143. The manufacturing method of forming the insulating damascene structure 190 on both sides of the second conductive block 143 includes, for example, the following steps.

As shown in Figs. 18A to 18E (Fig. 18B to Fig. 18E respectively show a cross-sectional view of the section line 18B-18B' to the section line 18E-18E' along the 18AA), the groove T' is formed in the second conductive block. On both sides of 143. In the embodiment, the extending direction D6 of the groove T' is, for example, perpendicular to the extending direction D2 of the stacked structure 120. In an embodiment, the manufacturing method of forming the recess T' includes, for example, removing the strip sacrificial layer 220a originally covered by the shielding layer 230, that is, removing the adjacent adjacent to the second conductive block 143, the third conductive layer 135, and the fourth The strip layer sacrificial layer 220a is provided by the conductive layer 137. In the embodiment, the strip sacrificial layer 220a is removed, for example, by etching.

As shown in Figures 19A to 19F (Fig. 19B to 19F respectively show a cross-sectional view of the section line 19B-19B' to the section line 19F-19F' along the line 19A), filling the insulating material in the groove T' To form an insulating damascene structure 190.

Next, as shown in FIGS. 20A-20F (Fig. 20B-20F respectively show a cross-sectional view of the section line 20B-20B' to the section line 20F-20F' along the 20AA), the dielectric layer 170 may also be formed. On the stack structure 120. In the embodiment, the dielectric layer 170 is also formed on the conductive damascene structure 150 and the insulating damascene structure 190. In an embodiment, an etch stop layer 173 may also be formed between the dielectric layer 170 and the stacked structure 120.

Next, as shown in FIG. 21, a contact hole 175 may also be formed in the dielectric layer 170. In the embodiment, the contact hole 175 is electrically connected to the second conductive block 143.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Semiconductor structure

110. . . Base

115. . . Oxide layer

120. . . Stack structure

120a. . . Side wall

121. . . Conductive strip

123. . . Insulation strip

130, 140. . . Conductive material layer

131. . . First conductive layer

133. . . Second conductive layer

135. . . Third conductive layer

137. . . Fourth conductive layer

140a. . . Upper surface

141. . . First conductive block

143. . . Second conductive block

150. . . Conductive mosaic structure

160. . . Insulation structure

170. . . Dielectric layer

173. . . Etch barrier

175. . . Contact hole

180. . . Memory material layer

180a. . . Memory coating layer

190. . . Insulated mosaic structure

210, 220. . . Sacrificial layer

220a. . . Strip sacrificial layer

230. . . Masking layer

1B-1B'~1C-1C', 2B-2B', 3B-3B', 4B-4B', 5B-5B', 6B-6B', 7B-7B', 8B-8B', 9B-9B', 10B-10B'~10E-10E', 11B-11B'~11E-11E', 12B-12B'~12E-12E', 13B-13B'~13E-13E', 14B-14B'~14E-14E', 15B-15B'~15E-15E', 16B-16B'-16E-16E', 17B-17B'~17E-17E', 18B-18B'~18E-18E', 19B-19B'~19F-19F', 20B-20B'~20F-20F'. . . Section line

D1~D6. . . Extension direction

PR1. . . Strip photoresist

T, T’. . . Groove

1A is a top plan view of a semiconductor structure in accordance with an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line 1B-1B' of Fig. 1.

Fig. 1C to Fig. 1D are schematic cross-sectional views taken along line 1C-1C' of Fig. 1.

2A through 21 are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

100. . . Semiconductor structure

120. . . Stack structure

131. . . First conductive layer

133. . . Second conductive layer

141. . . First conductive block

150. . . Conductive mosaic structure

160. . . Insulation structure

190. . . Insulated mosaic structure

1B-1B’~1C-1C’. . . Section line

D1~D3. . . Extension direction

Claims (10)

A semiconductor structure comprising:
a stacked structure formed on a substrate, wherein the stacked structure includes a plurality of conductive strips and a plurality of insulating strips, the conductive strips being interlaced with the insulating strips;
a plurality of first conductive blocks formed on the stacked structure;
a plurality of first conductive layers and a plurality of second conductive layers are respectively formed on the two sidewalls of the stacked structure; and a plurality of conductive damascene structures are formed on both sides of the stacked structure, wherein each of the A conductive block is electrically connected to each of the conductive damascene structures via each of the first conductive layer and each of the second conductive layers. The semiconductor structure of claim 1, further comprising a memory material layer formed on the two sidewalls of the stacked structure, wherein the memory material layer is formed on the first conductive layer and the stacked structure And between the second conductive layers and the stacked structure. For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a second conductive block is formed on the stacked structure; and a third conductive layer and a fourth conductive layer are respectively formed on the two sidewalls of the stacked structure, wherein the second conductive block and the third conductive layer And electrically connected to the fourth conductive layer. The semiconductor structure of claim 3, further comprising an insulating damascene structure formed on both sides of the second conductive block, the insulating damascene structure being connected to the second conductive block. A method of fabricating a semiconductor structure, comprising:
Forming a stacked structure on a substrate, comprising forming a plurality of conductive strips and a plurality of insulating strips, the conductive strips being interlaced with the insulating strips;
Forming a plurality of first conductive blocks on the stacked structure;
Forming a plurality of first conductive layers and a plurality of second conductive layers on both sidewalls of the stacked structure; and forming a plurality of conductive damascene structures on opposite sides of the stacked structure, wherein each of the first conductive layers The block is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips. The method for manufacturing a semiconductor structure according to claim 5, further comprising:
Forming a memory material layer on the two sidewalls of the stacked structure, wherein the memory material layer is formed between the first conductive layer and the stacked structure and between the second conductive layer and the stacked structure. The method for manufacturing a semiconductor structure according to claim 5, further comprising:
Forming a second conductive block on the stacked structure; and forming a third conductive layer and a fourth conductive layer on the two sidewalls of the stacked structure, wherein the second conductive block and the third conductive layer and the The fourth conductive layer is electrically connected. The method for manufacturing a semiconductor structure according to claim 7, further comprising:
An insulating damascene structure is formed on both sides of the second conductive block, and the insulating damascene structure is adjacent to the second conductive block. The manufacturing method of the semiconductor structure of claim 5, wherein the step of separately forming the first conductive layer and the second conductive layer on the two sidewalls of the stacked structure comprises:
Forming a conductive material layer on the stacked structure and the first conductive blocks; and etching the conductive material layer to expose the first conductive blocks and forming the first conductive layers and the second conductive layers The two side walls of the stack structure. The manufacturing method of the semiconductor structure of claim 5, wherein the forming the conductive mosaic structures on the two sides of the stacked structure comprises:
Forming a plurality of grooves on the two sides of the stacked structure, wherein the grooves extend in a direction perpendicular to the extending direction of the stacked structure; and filling a conductive material in the grooves to form the conductive Mosaic structure.