TWI476743B - Shift register - Google Patents

Description

Shift register

The present invention relates to a shift register, and more particularly to a shift register that varies voltage according to a threshold temperature.

With the development of panel technology, the use of array on-board driver technology (Gate on Panel, or GOP for short) has become more and more popular. The display panel often uses a shift register to generate a gate pulse to drive the pixels. However, the driving transistor in the shift register can work normally under normal operating conditions, but when the ambient temperature is high or low, leakage current, ripple, and the like are likely to occur.

Please refer to Fig. 1, which is a schematic diagram of the on-current of the transistor corresponding to the change in voltage across the ambient temperature. It should be noted that in this figure, the magnitude of the current value is expressed in logarithm (log), so each scale on the vertical axis represents an order of magnitude change in current value.

The curve indicated by the dotted line in the figure represents the relationship between the gate voltage of the transistor and the source voltage difference (Vgs) and the leakage current of the driving transistor at a temperature of 80 degrees Celsius. The curve on the right side and the thicker in the figure represents the relationship between the leakage current and the gate voltage and source voltage difference Vgs of the driving transistor when the ambient temperature is 25 degrees Celsius.

In addition, as can be seen from Fig. 1, when the gate and source voltage difference Vgs of the driving transistor is V volts, the driving transistor should be in a closed state, but actually exists between the source and the drain. Leakage current.

When the gate and source voltage difference of the driving transistor is Vgs=0 volts, if the ambient temperature = 80 degrees, the leakage current flowing through the driving transistor is 1.8e-9 amps; compared to the ambient temperature = 25 degrees, the flow The leakage current of the driven transistor is 3.3e-10 amps. It can be seen that the influence of the ambient temperature has a great influence on the leakage current.

When there is leakage current in the display circuit, the stability of the display panel is quite susceptible. In particular, because the shift register uses the output signals of the front and back stages, the leakage current affects the circuit operation. That is, even if the voltage between the gate and the drain of the driving transistor remains unchanged, the leakage current of the driving transistor is more serious at a higher temperature.

Furthermore, when the driving transistor is operated in the linear region, the current formula for turning on the driving transistor can be expressed as:

According to this formula, when the temperature becomes high, the mobility of electrons is enhanced, and at this time, the on-current Id becomes large. At a low temperature, since the drift characteristic of electrons becomes small, the conduction current Id becomes small.

However, for the display panel, its output signal out_n is transmitted to the back end for use. Therefore, when the driving transistor is operated at a low temperature, due to the small on-current relationship, it is relatively susceptible to signal reversal, resulting in a weak output current generated by the shift register located in the subsequent stage, so that the display screen is displayed. Cannot be displayed normally.

It can be seen that the design of the shift register used in the display is still not ideal, and it may cause an abnormal operation due to the influence of the ambient temperature when the screen is displayed. Therefore, how to provide a stable operation of the shift register under different temperature environments becomes an important problem to be solved.

The present invention relates to a shift register comprising: a driving transistor comprising a gate, a drain receiving a clock signal, and a source generating an output signal; a pull-up unit electrically connected to the The gate receives the action signal, and when the action signal is activated, turns on the driving transistor; a first pull-down unit is electrically connected to the gate, receives the stop signal and a first low voltage, and the stop signal In operation, the first low voltage is provided to turn off the driving transistor; a second pull-down unit is electrically connected to the drain, and receives the stop signal and a second low voltage, wherein when the driving transistor is turned off The output signal is the second low voltage; when the driving transistor is turned on, the clock signal is used as the output signal, and the first low voltage is less than or equal to the second low voltage, wherein, when an ambient temperature When the temperature is greater than a first threshold temperature, the difference between the first low voltage and the second low voltage is increased.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Please refer to FIG. 2A, which is a schematic diagram of a circuit structure of a shift register according to the present invention. The shift register 20 is used to receive the action signal (out_n-2) output by the previous stage shift register and the stop signal (out_n+2) output by the subsequent stage shift register.

Of course, the action signal (out_n-2) and the stop signal (out_n+2) here are assumed for the sake of illustration. The action signal (out_n-2) is assumed to be generated by the shift register of the upper stage, and the stop signal (out_n+2) is assumed to be generated by the shift register of the lower stage. However, in practical applications, the sources of the action signal and the stop signal are not limited thereto.

In the preferred embodiment, the shift register 20 includes a drive transistor TFT1, a pull-up unit 201, a first pull-down unit 203, and a second pull-down unit 205.

The following briefly describes the relationship between the components and signals in the shift register 20, and the influence of each signal on each other is described in the description of FIG. 2B.

The gate of the driving transistor TFT1 determines whether or not to turn on the driving transistor TFT1 according to the control of the pull-up unit 201 and the first pull-down unit 203. The drain of the driving transistor TFT1 is used to receive the clock signal CLK. The source of the driving transistor TFT1 generates an output signal (out_n) according to whether or not the driving transistor TFT1 is turned on and driven. Further, between the gate and the source of the driving transistor TFT1, there is a coupling capacitor C.

First, the pull-up unit 201 is electrically connected to the gate of the driving transistor TFT1, and is used to receive an action signal (out_n-2) output by the pre-stage shift register. When the action signal (out_n-2) is activated, the driving transistor TFT1 is turned on.

The shift register 20 contemplated in accordance with the present invention includes two pull down units. The first pull-down unit 203 is electrically connected to the first low voltage VGL_GOP, the second pull-down unit 205 is electrically connected to the second low voltage VGL_AA, and the first low voltage VGL_GOP is less than or equal to the second low voltage VGL_AA. In addition, the voltage difference between the first low voltage VGL_GOP and the second low voltage VGL_AA is adjusted according to the ambient temperature, and the voltage levels of the first low voltage VGL_GOP and the second low voltage VGL_AA are both lower than a ground voltage ( GND).

In addition to being connected to the first low voltage VGL_GOP, the first pull-down unit 203 is also electrically connected to the gate of the driving transistor TFT1. The first pull-down unit 203 is used to receive the stop signal (out_n+2) output by the subsequent stage shift register. When the signal action (out_n+2) is stopped, the first low voltage VGL_GOP is supplied to turn off the driving transistor TFT1.

The second pull-down unit 205 is electrically connected to the drain of the driving transistor TFT1 and the second low voltage VGL_AA, and the second pull-down unit 205 also receives the stop signal (out_n+2) output by the subsequent stage shift register.

When the driving transistor TFT1 is turned off, the output signal generated by the driving transistor TFT1 at the source is the second low voltage VGL_AA; when the driving transistor TFT1 is turned on, the drain and the source are turned on, and thus the time when the drain is received The pulse signal CLK is used as an output signal.

Please refer to FIG. 2B, which is a waveform diagram of an action signal, a stop signal, a gate voltage, an output signal, and a clock signal in a shift register according to the present invention. For convenience of explanation, the following is discussed in the following three periods: the first period T1, the second period T2, and the third period T3. In addition, the first low voltage VGL_GOP here is assumed to be -13 volts, and the second low voltage VGL_AA is assumed to be -7 volts.

First, in the first period T1, the pull-up unit 201 receives the action signal (out_n-2) supplied from the shift register of the previous stage. The action signal (out_n-2) rises from a low level (-7 volts) to a high level (30 volts) during the first period T1. The gate voltage of the driving transistor TFT1 (ie, the P point voltage VP) is transmitted through the pull-up unit 201, and is raised from the first low voltage VGL_GOP to the level of the action signal (out_n-2) in the first period T1. That is, 30 volts.

As a result, since the gate voltage of the driving transistor TFT1 is 30 volts, the driving transistor TFT1 will be turned on during the first period T1. Since the drain of the driving transistor TFT1 is electrically connected to the clock signal CLK, when the driving transistor TFT1 is turned on during the first period T1, the clock signal CLK is transmitted to the source of the driving transistor TFT1. Therefore, the output signal (out_n) generated by the source of the driving voltage TFT1 is affected by the clock signal CLK.

Since the clock signal CLK is at a low level (corresponding to the first low voltage VGL_GOP) before the first period T1, the output signal (out_n) will be pulled down from the original -7 volts to -12 volts during the first period T1. . The reason why the output signal (out_n) at this time is between the first low voltage VGL_GOP (-13 volts) and the second low voltage VGL_AA (-7 volts) is because the output signal (out_n) is at the first position. The low voltage VGL_GOP is between the second low voltage VGL_AA.

Second, the clock signal CLK rises from a low level to a high level during the second period T2. Since the driving transistor TFT1 is continuously turned on, the output signal rises to 30V. Due to the coupling capacitor C, the gate voltage will further increase from 30 volts to 60 volts. That is, when the clock signal CLK is input to the driving transistor TFT1, the gate of the driving transistor TFT1 causes the gate voltage to rise again due to the coupling capacitance C.

In other words, the driving transistor TFT1 is also in an on state during the second period T2. By driving the transistor TFT1 on, the clock signal CLK is transmitted to the source of the driving transistor TFT1. Since the clock signal CLK is at a high level in the second period T2, the voltage of the output signal (out_n) is increased by the influence of the clock signal CLK. Of course, this output signal (out_n) can be used as the stop signal of the pre-stage shift register and as the action signal of the post-stage shift register.

In the third period T3, the first pull-down unit 203 and the second pull-down unit 205 both receive the stop signal (out_n+2) transmitted by the shift register of the subsequent stage, that is, the shift register of the subsequent stage. The resulting output signal.

When the stop signal (out_n+2) is transmitted to the first pull-down unit 203, the gate voltage of the driving transistor TFT1 is pulled down to the first low voltage VGL_GOP through the first pull-down unit 203. As can be seen from the waveform diagram, the voltage of the gate voltage of the driving transistor TFT1 during the third period T3 is -13 volts.

Since the gate voltage of the driving transistor TFT1 is the first low voltage, the driving transistor TFT1 is in the off state in the third period T3.

When the stop signal (out_n+2) is transmitted to the second pull-down unit 205, the output signal (out_n) will be turned on to the second low voltage through the second pull-down unit 205. As can be seen from the waveform diagram, the voltage of the output signal (out_n) is -7 volts during the third period T3.

Furthermore, the first low voltage VGL_GOP not only affects the voltage of the clock signal CLK, but also further affects the voltage variation of the gate and the output signal. If the voltage level of the first low voltage VGL_GOP is lowered, it will affect the low potential of the clock signal CLK. When the clock signal is switched between the high level and the low level, the gate voltage affected by the coupling capacitor C also increases, and the conduction current of the driving transistor TFT1 also increases.

When the negative voltage of the clock signal CLK is supplied to the output signal (out_n), the voltage of the output signal (out_n) is actually a value between the first low voltage VGL_GOP and the second low voltage VGL_AA. Therefore, if the first low voltage VGL_GOP and the second low voltage VGL_AA are simultaneously pulled down together, the voltage of the output signal (out_n) can be lowered lower.

Therefore, in addition to lowering the voltage of the first low voltage VGL_GOP alone, the voltage of the second low voltage VGL_AA can also be lowered at a low temperature. This is because when the voltage value of the second low voltage VGL_AA of the source becomes large, the voltage of the gate is also increased by the coupling effect of the capacitance. Therefore, if the first low voltage VGL_GOP can be simultaneously lowered with the second low voltage VGL_AA, the current value of the driving transistor TFT1 can be more affected.

In other words, at a low temperature, one of the first low voltage VGL_GOP or the second low voltage VGL_AA may be selected to be lowered, or the voltage level of the first low voltage VGL_GOP and the second low voltage VGL_AA may be lowered together.

At high temperatures, the turn-on or turn-off of the drive transistor is determined by the gate-to-source voltage difference VGS(off). Referring to Fig. 1, it can be known that if the gate and the gate voltage are negatively biased, the driving transistor will have a low leakage current. Therefore, the present invention proposes a method of changing the gate and the gate bias for the case of high temperature. Since the falling of the first low voltage VGL_GOP can provide a larger Vgs bias and provide a larger on-current, the present invention provides a first low voltage VGL_GOP having a lower voltage for the driving transistor at a low temperature. Practice.

Hereinafter, the first low voltage VGL_GOP and the second low voltage VGL_AA of different levels are provided according to the concept of the present invention when the ambient temperature is different, using FIGS. 3A to 3D. It should be noted that in each of the patterns of the 3A to 3D diagrams, VI, V2, and V3 represent different negative voltage levels, and the first preset temperature T1, the second preset temperature T2, and the third preset are used. The temperature T3 and the fourth preset temperature T4 represent different ambient temperatures. For example, the first preset temperature T1 is -10 degrees, and the second preset temperature T2 is 0 degrees.

The relationship between the voltage levels used is as follows: V1>V2>V3; and the relationship of the preset temperature is: T1<T2<T3<T4. Of course, the selection of these parameters representing the voltage level and the ambient temperature, including the number and the value, can be changed according to the needs of the application.

As can be seen from the following preferred embodiments, as the temperature increases, the magnitude of the difference between the second low voltage VGL_AA and the first low voltage VGL_GOP also increases.

Please refer to FIG. 3A, which is a schematic diagram of adjusting the low voltage used by the pull-down unit in response to temperature changes in accordance with a first preferred embodiment of the present invention.

In the preferred embodiment, the first low voltage VGL_GOP which remains unchanged is taken as an example. For the voltage level of the second low voltage VGL_AA, three different voltage levels (V1, V2, V3) are provided in response to changes in temperature.

When the ambient temperature is lower than the first preset temperature T1, the generated second low voltage VGL_AA is V3 volt; when the ambient temperature is between the second preset temperature T2 and the third preset temperature T3, V2 volt is provided. The second low voltage VGL_AA; when the ambient temperature is higher than T4, the voltage level of the second low voltage VGL_AA provided is V1 volt.

As described above, when the relationship between the voltage level of the first low voltage VGL_GOP and the second low voltage VGL_AA in FIG. 3A is further explored, it can be seen that since the first low voltage VGL_GOP remains unchanged, the second low voltage The voltage level criterion of VGL_AA is divided into three intervals as the ambient temperature changes.

That is, the first low voltage VGL_GOP when the ambient temperature is less than the first preset temperature T1 is V3 volts, and the first low voltage VGL_GOP of the ambient temperature between the second preset temperature T2 and the third preset temperature T3 is V2 volts. The first low voltage VGL_GOP when the ambient temperature is greater than the fourth preset temperature T4 is V1 volt.

When the first low voltage VGL_GOP and the second low voltage VGL_AA provided by the circuit have the characteristics of this pattern, the VGS reverse bias is more negative at high temperatures, and the gate level is higher at low temperatures. High characteristics.

Please refer to FIG. 3B, which is a schematic diagram of adjusting the low voltage used by the pull-down unit in response to temperature changes in accordance with a second preferred embodiment of the present invention.

In the preferred embodiment, it is assumed that the voltage levels of the first low voltage VGL_GOP and the second low voltage VGL_AA are maintained at a low temperature and a normal temperature; when the ambient temperature is at a high temperature, the voltage level of the second low voltage VGL_AA The quasi-rise rises while the voltage level of the first low voltage VGL_GOP drops.

When the ambient temperature is less than T2, the voltage levels of the second low voltage VGL_AA and the first low voltage VGL_GOP are both maintained at V2 volts.

Further, when the ambient temperature is higher than the second preset temperature T2, a second low voltage VGL_AA of V1 volts and a first low voltage VGL_GOP of V3 volts are provided.

That is, when the ambient temperature is between 0 degrees and the second preset temperature T2, the voltage levels of the first low voltage VGL_GOP and the second low voltage VGL_AA are both consistent, and the voltage levels of the two are also equal; In addition, when the ambient temperature is greater than the second preset temperature T2, the voltage difference amplitude of the first low voltage VGL_GOP and the second low voltage VGL_AA is V1-V3.

When the first low voltage VGL_GOP and the second low voltage VGL_AA provided by the bias generating circuit have the characteristics of the pattern, the shift register has a degree of increasing the VGS reverse bias of the driving transistor TFT1 at a high temperature. And the characteristics of more power saving at normal temperature.

Referring to Figure 3C, which is a schematic diagram of the low voltage required to adjust the pull-down unit in response to temperature changes in accordance with a third preferred embodiment of the present invention. In the preferred embodiment, the voltage level of the second low voltage VGL_AA varies substantially as in Figure 3A, except that the selection of the threshold temperature is changed.

When the ambient temperature is lower than T1, the generated second low voltage VGL_AA is V3 volt; when the ambient temperature is between the second preset temperature T2 and the third preset temperature T3, the second low voltage of V2 volt is provided. VGL_AA; when the ambient temperature is higher than the fourth preset temperature T4, the voltage level of the second low voltage VGL_AA provided is V1 volt.

In FIG. 3C, the voltage level of the first low voltage VGL_GOP is maintained at a voltage level of V3 volts in a low temperature, normal temperature state, but when the ambient temperature is higher than the fourth preset temperature T4, the first low voltage VGL_GOP The voltage level criterion is reduced to V4.

Observing the difference between the second low voltage VGL_AA and the first low voltage VGL_GOP in FIG. 3C, it can be seen that when the ambient temperature is less than the first preset temperature T1, the second low voltage VGL_AA is equal to the voltage of the first low voltage VGL_GOP; When the ambient temperature is between the second preset temperature T2 and the third preset temperature T3, the voltage difference between the second low voltage VGL_AA and the first low voltage VGL_GOP is V2-V3; when the ambient temperature is higher than the fourth pre- When the temperature T4 is set, the voltage difference between the second low voltage VGL_AA and the first low voltage VGL_GOP is V1 - V4.

When the first low voltage VGL_GOP and the second low voltage VGL_AA provided by the circuit have the characteristics of this pattern, the VGS reverse bias is more negative at a high temperature, and the gate has a higher level. Characteristics.

Please refer to FIG. 3D, which is a schematic diagram of the low voltage required to adjust the pull-down unit in response to temperature changes in accordance with a fourth preferred embodiment of the present invention. In the preferred embodiment, the second low voltage VGL_AA provides three possible voltage levels (V4, V2, V1) depending on the ambient temperature.

When the ambient temperature is lower than the first preset temperature T1, the generated second low voltage VGL_AA is V4 volt; when the ambient temperature is between the second preset temperature T2 and the third preset temperature T3, V2 volt is provided. The second low voltage VGL_AA; and when the ambient temperature is higher than the fourth preset temperature T4, the voltage level of the second low voltage VGL_AA provided is V1 volt.

On the other hand, the voltage of the first low voltage VGL_GOP is also maintained at the voltage level of V4 when the ambient temperature is less than T1, but the first low voltage VGL_GOP of the voltage level of V4 is provided when the ambient temperature is higher than T2.

As described above, when the relationship between the voltage level of the second low voltage VGL_AA and the first low voltage VGL_GOP in the 3D picture is further explored, it can be seen that the difference between the first low voltage VGL_GOP and the second low voltage VGL_AA It changes as the temperature changes.

That is, when the ambient temperature is less than T1, the voltage difference between the second low voltage VGL_AA and the first low voltage VGL_GOP is 0 volt; when the ambient temperature is between the second preset temperature T2 and the third preset temperature T3, The difference between the second low voltage VGL_AA and the first low voltage VGL_GOP is (V2-V3); and when the ambient temperature is greater than the fourth preset temperature T4, between the second low voltage VGL_AA and the first low voltage VGL_GOP The difference is (V1-V3).

In short, when the method of the 3D is used, the magnitude of the difference between the voltage level of the second low voltage VGL_AA and the first low voltage VGL_GOP will also increase as the ambient temperature increases. When the first low voltage VGL_GOP and the second low voltage VGL_AA provided by the circuit have the characteristics of this pattern, the VGS reverse bias voltage of the driving transistor is more negative in a high temperature environment, and in a low temperature environment, the gate is Extremely high level of characteristics.

According to the description of FIGS. 3A-3D, the concept proposed by the present invention can be summarized as: increasing the difference between the first low voltage VGL_GOP and the second low voltage VGL_AA when the ambient temperature is greater than the first threshold temperature Th; When the ambient temperature is less than the second threshold temperature T1, the difference between the first low voltage VGL_GOP and the second low voltage VGL_AA is decreased. Here, the first threshold temperature Th is higher than the second threshold temperature T1, and the manner of changing the voltage difference can be adjusted according to different combinations.

When the ambient temperature is greater than the first threshold temperature Th, the method of increasing the difference between the first low voltage VGL_GOP and the second low voltage VGL_AA does not need to be defined. The following are several possible combinations: when the ambient temperature is greater than the first When the threshold temperature Th is reached, the level of the second low voltage VGL_AA is maintained, but the level of the first low voltage VGL_GOP is lowered; when the ambient temperature is greater than the first threshold temperature Th, the level of the first low voltage VGL_GOP is maintained, However, the level of the second low voltage VGL_AA is raised; or when the ambient temperature is greater than the first threshold temperature Th, the level of the first low voltage VGL_GOP is lowered, and the level of the second low voltage VGL_AA is raised.

Similarly, when the ambient temperature is less than the second threshold temperature T1, the method of reducing the difference between the first low voltage VGL_GOP and the second low voltage VGL_AA does not need to be limited, and several possible combinations are as follows: When the ambient temperature is less than the second threshold temperature T1, the level of the first low voltage VGL_GOP is maintained, but the level of the second low voltage VGL_AA is lowered; when the ambient temperature is less than the second threshold temperature T1, the first low voltage is simultaneously decreased The level of VGL_GOP and the second low voltage VGL_AA, wherein the second low voltage VGL_AA has a larger drop. Alternatively, when the ambient temperature is less than the second threshold temperature T1, the first low voltage VGL_GOP is raised and the level of the second low voltage VGL_AA is lowered.

Of course, the selection of the first threshold temperature Th and the second threshold temperature T1 can be adjusted by means of circuit design, and the temperature threshold can be set. The change of the first low voltage VGL_GOP and the second low voltage VGL_AA at a high temperature can slow down the degree of aging of the driving transistor T1 at a high temperature.

In order to provide the first low voltage VGL_GOP and the second low voltage VGL_AA having the above characteristics, the present invention is explained by using a bias generating circuit using a thermistor resistance (TSR).

In order to simplify the description, R(T) will be used to represent the resistance values of various types of thermistors, and when the object to be generated is the first low voltage VGL_GOP and the second low voltage VGL_AA, when the thermistor is selected, It may be a thermistor having a positive temperature coefficient (PTC), a negative temperature coefficient (NTC), and a critical temperature coefficient (CTC).

See Figure 4, which is a schematic diagram of the circuit architecture that controls the change in output voltage.

The current source provides a reference current Iref (eg, 5 mA), and the resistance value of the resistor R3 is known (eg, 1 k ohm), so the voltage supplied to the buffer 315 is Iref*R3 (eg, 5 volts). That is, the buffer 315 will derive an upper voltage limit based on the reference current Iref and the resistance value R3 of the thermistor.

The purpose of providing the clamping circuit 312 is to maintain the voltage value of the node VC at a lowest voltage level (e.g., 1.2 volts), i.e., to provide a lower voltage limit.

According to the aforementioned upper voltage limit and lower voltage limit, the voltage received by the negative input terminal of the amplifier 316 ranges from 1.2 to 5 volts. The magnification provided by amplifier 316 is then passed, for example, 5 times. Since the product of the voltage range and the amplification is negative, it can be concluded that the voltage supplied to the bias control circuit 311 is between -6 and -25 volts.

When the thermistor R(T) is affected by the temperature and changes its resistance value, it will affect the output of the comparator. At this time, the comparator 314 will change the current value of the reference current Iref through the constant current source controller 313. For example, the reference current Iref output from the constant current source is increased from 5 mA to 6 mA, and the maximum bias voltage that the bias generating unit 30 can provide is: 6 mA * 1 K * ( - 5 ) = -30 volts.

Through the bias generating unit 30 of FIG. 4, the bias voltage outputted by the bias control circuit 311 can generate biases of different levels in response to changes in temperature. The level of this bias is between the amplification factor of the amplifier and the upper voltage limit, and the product of the amplification factor and the lower voltage limit. Therefore, the circuit of the bias generating unit 30 can be used to implement the foregoing preferred embodiment to change the voltage levels of the first low voltage VGL_GOP and the second low voltage VGL_AA depending on the ambient temperature.

As described above, since the application of the second low voltage VGL_AA tends to increase the voltage when the temperature is high, a PTC type thermistor whose resistance value becomes larger as the temperature increases can be selected. Because the characteristic of the PTC thermistor is that the resistance value increases with increasing temperature, the voltage value across the PTC thermistor increases as the resistance increases as the current remains fixed.

On the other hand, since the application of the first low voltage VGL_GOP tends to provide a lower resistance when the temperature is high, an NTC type thermistor can be selected as R(T). Since the characteristics of the NTC thermistor are such that the resistance value decreases as the temperature increases, the voltage across the NTC thermistor decreases as the resistance decreases as the current remains fixed.

According to the foregoing description, the present invention not only improves the leakage current phenomenon of the shift register in a high temperature environment, but also allows the shift register to provide a relatively stable driving current in a low temperature environment.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

201. . . Pull-up unit

203. . . First pull down unit

205. . . Second pull down unit

311. . . Bias control circuit

312. . . Clamp circuit

313. . . Constant current source controller

314. . . Comparators

315. . . buffer

316. . . Amplifier

30. . . Bias generating unit

Figure 1, which is a schematic diagram of the on-current of the transistor corresponding to the change in voltage across the ambient temperature.

FIG. 2A is a schematic diagram showing a circuit structure of a shift register according to the present invention.

FIG. 2B is a waveform diagram of an action signal, a stop signal, a gate voltage, an output signal, and a clock signal in a shift register according to the present invention.

Figure 3A is a schematic illustration of the low voltage used to adjust the pull-down unit in response to temperature changes in accordance with a first preferred embodiment of the present invention.

FIG. 3B is a schematic diagram of adjusting the low voltage used by the pull-down unit in response to temperature changes in accordance with a second preferred embodiment of the present invention.

Figure 3C is a schematic diagram of the low voltage used to adjust the pull-down unit in response to temperature changes in accordance with a third preferred embodiment of the present invention.

FIG. 3D is a schematic diagram of adjusting the low voltage used by the pull-down unit in response to temperature changes in accordance with a fourth preferred embodiment of the present invention.

Figure 4 is a schematic diagram of a circuit architecture that controls the change in output voltage.

Claims (15)

A shift register includes: a driving transistor comprising a gate, a drain receiving a clock signal, and a source generating an output signal; a pull-up unit electrically connected to the gate and receiving a An action signal, when the action signal is activated, turning on the driving transistor; a first pull-down unit electrically connected to the gate, receiving a stop signal and a first low voltage, and when the stop signal is activated, providing the a first low voltage to turn off the driving transistor; a second pull-down unit electrically connected to the drain, receiving the stop signal and a second low voltage, wherein the output signal is when the driving transistor is turned off Is the second low voltage; when the driving transistor is turned on, the clock signal is used as the output signal, and the first low voltage is less than or equal to the second low voltage, wherein when an ambient temperature is greater than a first When the temperature is limited, the difference between the first low voltage and the second low voltage is increased. The shift register according to claim 1, wherein when the ambient temperature is greater than the first threshold temperature, the level of the first low voltage is lowered, and the second low voltage level is maintained. . The shift register according to claim 1, wherein when the ambient temperature is greater than the first threshold temperature, the level of the first low voltage is maintained, and the level of the second low voltage is raised. . The shift register according to claim 1, wherein when the ambient temperature is greater than the first threshold temperature, the level of the first low voltage is lowered, and the level of the second low voltage is raised. . The shift register according to claim 1, wherein when the ambient temperature is greater than the first threshold temperature, the first low voltage and the second low voltage are raised, and the first The voltage rise of the low voltage is less than the voltage increase of the second low voltage. The shift register of claim 1, wherein when the ambient temperature is less than a second threshold temperature, the difference between the first low voltage and the second low voltage is reduced, wherein The first threshold temperature is higher than the second threshold temperature. The shift register according to claim 6, wherein when the ambient temperature is less than the second threshold temperature, the level of the first low voltage is maintained, and the level of the second low voltage is lowered. . The shift register according to claim 6, wherein when the ambient temperature is less than the second threshold temperature, the first low voltage and the second low voltage are lowered, and the first The voltage drop of the low voltage is less than the voltage drop of the second low voltage. The shift register of claim 6, wherein when the ambient temperature is less than the second threshold temperature, the first low voltage is raised and the second low voltage level is lowered. The shift register of claim 1, wherein the first low voltage and the second low voltage are provided by a bias generating unit. The shift register of claim 10, wherein the bias generating unit comprises a thermistor. The shift register according to claim 11, wherein the thermistor is a thermistor having a positive temperature coefficient, a thermistor having a negative temperature coefficient, and a thermistor having a critical temperature. The shift register according to claim 11, wherein the bias generating unit further comprises: a current source electrically connected to the thermistor, which provides a reference current; a buffer, an electrical connection The thermistor is configured to obtain an upper voltage limit according to the reference current and the resistance value of the thermistor; a clamping circuit electrically connected to the buffer, which provides a lower voltage limit; an amplifier, an electrical connection The buffer is provided with a magnification; and a bias control circuit is electrically connected to the amplifier and outputs a bias voltage, wherein the bias level is between the amplification factor and the upper voltage limit. And the ratio between the magnification and the lower voltage limit. The shift register according to claim 12, wherein the bias generating unit further comprises: a comparator electrically connected to the buffer; and a constant current source controller electrically connected to the comparator and The current source, wherein the constant current source controller adjusts the current value of the reference current due to the output of the comparator. The shift register of claim 1, wherein the first low voltage and the second low voltage are both lower than a ground voltage.