TWI462107B - Electronics system, memory and method for providing the same - Google Patents

Description

Electronic system, memory and method of providing same

The present invention relates to a memory storage unit, particularly a programmable resistor element of a memory array.

A programmable resistive element generally means that the resistive state of the component can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a One-Time Programmable (OTP) component (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP component. When a high current flows through the OTP component via the open programming selector, the OTP component will be programmed to be fired in a high or low resistance state (depending on whether it is a fuse or an antifuse).

Electrical fuses are a common type of OTP, and such programmable resistive elements can be polycrystalline germanium, germanium polysilicon, germanium, thermally isolated active regions, metals, metal alloys, or combinations thereof. The metal can be aluminum, copper or other transition metal. The most commonly used electrical fuse is a deuterated polysilicon, which is made of a complementary MOS transistor gate for internal connections. The electrical fuse can also be one or more contacts or layer invias, rather than an internal connection of small segments. High current can burn contacts or layers indirectly to a high resistance state. The electrical fuse can be an anti-fuse, where the high voltage reduces the resistance rather than increasing the resistance . The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The antifuse can also be coupled to the CMOS body by a CMOS gate that contains a gate oxide layer as an insulator.

Figure 1 shows a conventional programmable resistive memory storage unit. The memory cell 10 includes a resistive element 11 and an N-type MOS transistor (NMOS) programming selector 12. The resistive element 11 is coupled at one end to the drain of the NMOS and at the other end to a positive voltage V+. The gate of NMOS 12 is coupled to select signal SEL and the source is coupled to a negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed to turn on the NMOS 12 by raising the program select signal SEL. One of the most common resistive components is deuterated polysilicon, which is the same material used in the fabrication of MOS gates at the same time. The area of the NMOS programming selector 12 needs to be large enough to allow the required programming current to last for a few microseconds. The programming current for deuterated polysilicon is typically from a few milliamps (for a fuse of about 40 nanometers in width) to 20 milliamps (for a fuse of about 0.6 micrometers in width). Therefore, an electrical fuse storage unit using a deuterated polysilicon tends to have a large area.

The programmable resistive element can be a reversible resistive element that can be reprogrammed and reversibly programmable to a digital logic value of "0" or "1". The programmable resistive element can be fabricated from a phase change material such as germanium (Ge), germanium (Sb), and germanium (Te), Ge2Sb2Te5 (GST-225) or including the constituent indium (In), tin (Sn), or selenium ( Se) GeSbTe type material. The phase change material can be programmed to an amorphous high resistance state or a crystalline low resistance state via a high voltage short pulse or a low voltage long pulse. The reversible resistance element may be a resistive random access memory (resistive memory RRAM), and the memory unit is made of a metal oxide between metal or metal alloy electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt). Or made of titanium nitride/titanium oxide/yttria/titanium nitride (TiN/TiOx/HfO2/TiN). The reversible change of the resistance state is via electricity The polarity, intensity, and duration of a pulse or current pulse that produces or destroys the conductive filament. Another programmable resistive element like Resistive Random Access Memory (RRAM) is Conductive Bridge Random Access Memory (CBRAM). This memory is based on electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrode may be an oxidizable anode and an inert cathode, and the electrolyte may be a silver- or copper-containing chalcogenide glass such as strontium selenide (GeSe) or selenium sulphide (GeS). The reversible change in resistance state is the generation or elimination of a conductive bridge via the polarity, intensity and duration of the voltage or current pulse.

Figure 2a shows a cross-sectional view of a conventional bipolar transistor 22. The bipolar transistor 22 includes a P+ active region 23, an N shallow well 24, an N+ active region 27, a P-type substrate 25, and a shallow trench isolation (STI) 26 for isolating components. P+ active region 23 and N+ active region 27 are coupled to N-well 24, which is the P and N terminals of the emitter and base diodes of bipolar transistor 22, while P-type substrate 25 is the collector of bipolar transistor 22. . Such a memory cell requires N shallow wells 24 to be shallower than shallow trench isolations 26 to properly isolate each memory cell, thus requiring 3-4 more photomasks than standard CMOS logic processes, making it more expensive to fabricate.

Figure 2b shows a programmable resistive element of another phase change memory (PCM). The phase change memory material has a phase change film 21' and a diode 22' programming selector. The phase change film 21' is coupled between the diode anode 22' and the positive voltage V+. The cathode 22' of the diode is coupled to a negative voltage V-. Applying the appropriate voltage between V+ and V- for an appropriate period of time, the phase change film 21' can be programmed to a high or low resistance state, depending on voltage and duration. See "Kwang-Jin Lee et al., "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," International Solid-State Circuit Conference, 2007, pp. 472-273". Figure 2c shows an example of a programming selector using a diode as a phase change memory (PCM) memory cell. Although this technique can reduce the PCM memory cell size to only 6.8 F2 (F represents features) Size), the diodes require very complex manufacturing processes, such as selective epitaxial growth (SEG). As a result, the application of embedded PCM will become very expensive.

Figures 3a and 3b show that the magnetic memory (MRAM) memory cell 210 is magnetically parallel (or state 0) and magnetic anti-parallel (or state 1) via current direction. The MRAM memory cell 210 is comprised of a magnetic tunnel junction (MTJ) 211 and an NMOS programming selector 218. The magnetic tunnel junction 211 has a multi-layered ferromagnetic or antiferromagnetic stack with a metal oxide such as Al2O3 or MgO as an insulator between multiple layers. The magnetic tunnel junction 211 includes a free stack layer 212 and a fixed stack layer 213. The programming selector CMOS 218 is turned on and an appropriate current is applied to the magnetic tunnel junction 211, and the freely stacked layers 212 can be arranged in magnetic parallel or magnetic anti-parallel to the fixed stacked layer 213, depending on whether the current flows out or flows into the fixed stacked layer 213. . Therefore, the magnetic state can be programmed, and the state result can be determined by the resistance value to determine the low resistance of the magnetic parallel state or the high resistance of the magnetic anti-parallel state. The state 0 or 1 resistance values are approximately 5 kΩ or 10 KΩ, respectively, and the programming current is approximately +/- 100-200 mA. An example of programming an MRAM memory cell is described in "2Mb Spin-Transfer Torque RAM with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read," International Solid-State Circuit Conference, 2007, pp. 480-481.

It is an object of the present invention to provide a programmable resistive element memory cell that uses a diode as a programming selector, and a programmable resistive component can be fabricated using a standard CMOS logic process. To reduce the size and cost of the storage unit.

Therefore, the present invention provides a memory comprising: a plurality of memory storage units, the at least one memory storage unit comprising: a memory element having a first end and a second end, the first end being coupled to the first supply voltage line; and a The first diode includes at least a first end and a second end, wherein the first end has a first type of doping, the second end has a second type of doping, the first dipole a first end is coupled to the second end of the memory element; a second diode includes at least a first end and a second end, wherein the first end has a first type of doping, the second end Having a second type of doping, the second end of the second diode being coupled to the second end of the memory element, wherein the second end of the first diode is coupled to a second a supply voltage line, wherein the first end of the second diode is coupled to the second or a third supply voltage line, wherein the memory element is configured to be programmable to a different logic state via application of a voltage to The first, second, and/or third supply voltage lines to turn on the first diode The second diode is turned off to a logic state, or the second diode is turned on to cut the first diode to another logic state.

Therefore, the present invention provides a memory comprising: a plurality of memory storage units, at least one memory storage unit comprising: a memory element having a first end and a second end, the first end being coupled to a first supply voltage line; The first diode includes at least a first end and a second end, wherein the first end has a first type of doping and the second end has a second type of doping, the first dipole a first end is coupled to the second end of the memory element; a second diode includes at least a first end and a second end, wherein the first end has a first type of doping, the second end Having a second type of doping, the second end of the second diode being coupled to the second end of the memory element, wherein the second end of the first diode and the second diode The first end is coupled to a first a power supply voltage line, wherein the memory element is configured to be programmable to a different logic state, by applying a voltage to the first and second supply voltage lines, thereby turning the first diode off and cutting the second The diode goes to a logic state, or turns on the second diode to cut the first diode to another logic state.

Accordingly, the present invention provides an electronic system comprising: a processor; and a memory operatively coupled to the processor, the memory comprising at least a plurality of memory storage units for providing data storage, each memory storage unit comprising: a memory The component has a first end and a second end, the first end is coupled to a first supply voltage line; and a first diode includes at least a first end and a second end, wherein the first end has a a first type doping, the second end having a second type doping, the first end of the first diode being coupled to the second end of the memory element, the first diode The second end is coupled to the second power voltage line; the second body includes at least a first end and a second end, wherein the first end has a first type of doping, and the second end has a first a second type of doping, the second end of the second diode being coupled to the second end of the memory element, and the first end of the second diode being coupled to the second or third Supply voltage line; wherein the memory element is configured to be programmable to different logic a state, by applying a voltage to the first, second, and/or third power voltage lines, thereby turning on the first diode to cut the second diode to a logic state, or turning on the second The polar body cuts off the first diode to another logic state.

Accordingly, the present invention provides a method of providing a memory comprising: providing a plurality of memory storage units, at least one memory storage unit comprising at least (i) a memory element having a first end and a second end, the first end being coupled to a first power supply voltage line; and (ii) a first diode comprising at least a first end and a second end, the first end having a first type of doping and the second end having a second type of doping The first of the first diode One end is coupled to the second end of the memory element and the second end of the first diode is coupled to a second supply voltage line; (iii) a second diode includes at least a first end and a second end having a first type of doping, the second end having a second type of doping, the first end providing a first end of the diode, and the second end providing a diode a second end, the second end of the second diode is coupled to the second end of the memory element and the first end of the second diode is coupled to the second or a third power source a voltage line; and wherein the memory element is configured to be programmable to a different logic state, by applying a voltage to the first, second, and/or third supply voltage lines to turn the first diode off The second diode is turned to a logic state, or the second diode is turned on to cut the first diode to another logic state.

[知知]

10‧‧‧ storage unit

11‧‧‧Resistive components

12‧‧‧ NMOS programming selector

20,20'‧‧‧Programmable Resistive Components

21, 21‧‧‧ phase change film

22‧‧‧Bipolar transistor

23‧‧‧P+ emitter

27‧‧‧N type base

25‧‧‧

22'‧‧‧ Diode

210‧‧‧ storage unit

211‧‧‧Magnetic tunnel junction

218‧‧‧ NMOS programming selector

212‧‧‧Free stacking layer

213‧‧‧Fixed stacking layer

[this invention]

30‧‧‧Memory memory unit

30a‧‧‧ memory components

32a, 32b‧‧‧ diode

32,32’,32”‧‧‧dipole

33,33’,33”‧‧‧P+ active zone

34,34’,34”‧‧‧N Well

37,37’,37”‧‧N+ active zone

36,36’‧‧‧Shallow trench isolation

31', 31" ‧ ‧ active area

39’‧‧‧ gate

39"‧‧‧ Telluride barrier

35,35’,35”‧‧‧ base

45‧‧‧Connected diode

31-1, 31-2, 31-3‧‧‧ islands

39-1, 39-2, 39-3‧‧‧ MOS gate

40-1‧‧‧矽区

40-2‧‧‧矽区

33-1, 2, 3, ‧‧‧P+ active zone

37-1, 2, 3‧‧‧N+ active zone

38'‧‧‧P+ implant layer

310,310’‧‧‧MRAM storage unit

311,311’‧‧‧MTJ

317,318,317',318'‧‧‧Connected diode

312,312'‧‧‧Free stacking layer

313,313'‧‧‧ fixed stack

321,320,321'320’‧‧‧N Well

315,316,315’,316’‧‧‧P+ active zone

314,319,314’,319’‧‧‧N+ active zone

330,330’‧‧‧STI

310-00, 310-01, 310-10, 310-11‧‧‧ storage unit

317-00‧‧‧Programming 1 diode

318-00‧‧‧Programming 0 diode

100‧‧‧Programmable Resistor Memory

101‧‧‧Array

110‧‧‧ memory storage unit

111‧‧‧Resistive components

112‧‧‧Programming 0 diode

113‧‧‧Programming 1 diode

BLR0 175-0‧‧‧ reference bit line

150-i‧‧‧ character line driver

BLj 170-j‧‧‧ bit line

LWLNi 154-i‧‧‧ local word line

WLPi 153-i‧‧‧ character line

LWLNi, LWLPi‧‧‧ local word line

120-0j, 125‧‧‧Y-write-0 channel gate

121-j, 126‧‧‧Y-write-1 channel gate

140‧‧‧Sense amplifier

160,161‧‧‧ input

130-j, 135‧‧‧Y-read channel gate

S700-S760, S800-S870‧‧‧ steps

700‧‧‧Processor System

740‧‧‧ memory

744‧‧‧Programmable resistance element

742‧‧‧Memory Cell Array

710‧‧‧Central Processing Unit

715‧‧‧Common bus

720‧‧‧Input and output unit

730‧‧‧ Hard disk drive

750‧‧‧DVD

740‧‧‧ memory

760‧‧‧Other memory

Figure 1 shows a circuit diagram of a conventional programmable resistive memory cell.

Figure 2a shows a circuit diagram of another conventional programmable resistive element for phase change memory (PCM) that uses a bipolar transistor as a programming selector.

Figure 2b shows a circuit diagram of another conventional phase change memory (PCM) memory cell that employs a diode as a programming selector.

Figures 3a and 3b show schematic diagrams of magnetic directions for programming a conventional magnetic memory (MRAM) memory cell in parallel (or state 0) and anti-parallel (or state 1) via current direction.

Figure 4 shows a block diagram comprising a memory storage unit using at least one diode in accordance with the present invention.

Figure 5a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by shallow trench isolation (STI) and when the selector is programmed.

Figure 5b shows a cross section of a junction diode. According to this embodiment, the diode is dummy The CMOS gate is used to isolate the anode and cathode, and when programming the selector.

Figure 5c shows a cross section of a junction diode. According to this embodiment, the diode is separated from the anode and cathode by a deuteration barrier (SBL) and when the selector is programmed.

Figure 6a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by a dummy CMOS gate in an insulating germanium (SOI) technique and when the selector is programmed.

Figure 6b shows a cross section of a junction diode. According to this embodiment, the diode is insulated with a dummy CMOS gate in a fin field effect transistor (FINFET) technique to isolate the anode and cathode, and when programming the selector.

Figure 7 shows a circuit diagram of an MRAM memory cell of an embodiment employing at least one diode as a program selector.

Figure 8a shows a top view of an MRAM cell. According to this embodiment, a magnetic tunnel junction (MTJ) is used as a resistive element and a P+/N well diode of a standard CMOS process is used as a program selector.

Figure 8b shows a top view of another MRAM memory cell. According to this embodiment, a magnetic tunnel junction (MTJ) is used as a resistive element and a P+/N well diode of a shallow well CMOS process is used as a program selector.

Figure 9a shows a schematic diagram of an embodiment of a three-terminal 2X2 MRAM memory cell array that uses a diode as a programming selector. Moreover, according to this embodiment, the condition that the upper right memory cell is programmed is one.

Figure 9b shows another embodiment status list for programming a memory cell on the upper right side of a 2X2 MRAM memory cell array to a condition of one.

Figure 10a shows a schematic diagram of an embodiment of a three-terminal 2X2 MRAM memory cell array using junction diodes as a programming selector. Moreover, according to this embodiment, the condition that the upper right memory cell is 0 is programmed.

Figure 10b shows another embodiment status list for programming a memory cell on the upper right side of a 2X2 MRAM memory cell array to zero.

Figures 11a and 11b show a schematic diagram of an embodiment in which the upper right memory cell is programmed to 1 and 0, respectively, in a two-terminal 2X2 MRAM memory cell array.

Figure 12a shows a schematic diagram of a portion of a programmable resistive memory. According to this embodiment, the MRAM array is composed of three endpoint memory cells.

Figure 12b shows a schematic diagram of another embodiment in which a portion of the MRAM memory is formed by a two-terminal MRAM memory cell.

Figure 13a depicts a flow diagram of a method for programming a programmable resistive memory.

Figure 13b depicts a flow diagram of a method for reading a programmable resistive memory.

Figure 14 shows a schematic diagram of an embodiment of a system of processors.

In an embodiment of the invention, the P+/N well junction diode acts as a programming selector for the programmable resistive element. This diode can include P+ and N+ active regions in the N well. Since the P+ and N+ active regions and the N-well are both off-the-shelf standard CMOS logic processes, these components can be fabricated in an efficient and cost-effective manner without the need for additional masks or process steps to save cost. This programmable resistive element can be included in an electronic system.

4 is a block diagram of a memory storage unit 30 using at least one diode in accordance with an embodiment. In particular, memory unit 30 includes a memory element 30a and diodes 32a, 32b. The memory element 30a can be coupled between the anode of the diode 32a and the voltage V. The cathode of diode 32a can be coupled to a negative voltage V-. Memory element 30a can be coupled between the cathode of diode 32b and voltage V. The anode of diode 32b can be coupled to a positive voltage V+. In one embodiment, the memory storage unit 30 can be a magnetic memory (MRAM) storage device. A unit containing a memory element 30a that is a magnetic tunnel junction (MTJ). The diode 32a or 32b can be used as a programmed 0 or 1 selector. The diode can be constructed using a standard CMOS process P+/N well of a P-type substrate. The P+ and N+ active regions as the diode anode and cathode are the source or drain of the CMOS component. Well N is a CMOS well used to embed PMOS components. Alternatively, the diode can be constructed using an N+/P well in a P-well CMOS process using an N-type substrate. Memory element 30a and diode 32a or 32b are interchangeable between supply voltages V and V+/V-. By applying an appropriate voltage (between V+ and V-) over a suitable period of time, memory element 30a can be programmed to be high by turning on a diode and cutting off the other diode. Or a low resistance state, so the program memory storage unit 30 can store data values (eg, bits of data). The diode 32a or 32b may be a junction diode. The P+ and N+ active regions of the junction diode can be isolated using a dummy CMOS gate, shallow trench isolation (STI), local oxidation (LOCOS) or germanium blocking layer (SBL). If no germanide is near the boundary of the first and second active regions, the first and second active regions may be butted together or doped with a low dose active region to separate the two active regions.

A magnetic tunnel junction (MTJ) memory cell can serve as an example to illustrate the key implementation concepts. Figure 5a shows a cross section of a diode 32 in which a shallow trench isolated P+/N well diode is used as a programming selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37, which respectively constitute the P and N terminals of the diode 32, are the source or drain of the PMOS and NMOS in a standard CMOS logic process. The N+ active region 37 is coupled to an N-well 34 that embeds a PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as the MTJ, can be coupled to the P+ region 33 at one end and to the high voltage supply V+ at the other end. In order to program such a programmable resistive component, a high voltage is applied to V+, a low voltage or ground potential is applied to N+ zone 37. Therefore, a high current flows through the fuse element and the diode 32 to program the resistance element.

Figure 5b shows a cross-sectional view of another junction diode 32' embodiment as a programming selector and isolated by a dummy CMOS gate. Shallow trench isolation 36' provides isolation of other active regions. The active region 31' is defined by a shallow trench isolation 36'. Here, the N+ and P+ active regions 37' and 33' are further defined by a mixture of a dummy CMOS gate 39', a P+ implant layer 38', and an N+ implant layer (complementary to the P+ implant layer 38'), respectively. N and P terminals of the diode 32'. The diode 32' is fabricated like a PMOS-like component comprising 37', 39', 33', 34' as the source, gate, drain and N well, whereas the source 37' is covered with an N+ implant. The layer is replaced by a P+ implant layer 38' covered by a true PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage for the purpose of isolation between the P+ active region 33' and the N+ active region 37' during fabrication. The N+ active region 37' is coupled to the N-well 34', which is a body embedded in the PMOS in a standard CMOS logic process. The P substrate 35' is a matrix of P-type germanium. The resistive element (not shown in Figure 5b, such as MTJ) may be coupled to the P+ region 33' at one end and to the high voltage power supply V+ at the other end. To program such a programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the fuse element and the diode 32' to program the resistance element. This embodiment has an ideal small size and low resistance.

A cross-section of another embodiment, shown in Figure 5c, in which the junction diode 32" is isolated by a telluride barrier (SBL) 39" and serves as a programming selector. Figure 5c is similar to Figure 5b, however the dummy CMOS gate 39' in Figure 5b is replaced by a telluride barrier layer 39" in Figure 5c to prevent the growth of germanide on top of the active region 31". Without a dummy CMOS gate or germanium blocking layer, the N+ and P+ active regions will be shorted by the germanium on the surface of the active region 31.

Figure 6a shows a cross section of another embodiment in which the junction diode 32" acts as a programming selector and employs a technique of insulating germanium (SOI). In SOI technology, the substrate 35" is like cerium oxide or An insulator of similar material, the insulator comprising a thin layer of tantalum grown on top. All NMOS and PMOS are in the well, separated from each other and the substrate 35 by germanium dioxide or similar materials. One piece of active region 31" via dummy CMOS gate 39", P+ implant layer 38" The mixing with the N+ implant layer (complementary to the P+ implant layer 38) is divided into an N+ active region 37", a P+ active region 33" and a body 34". Therefore, the N+ active region 37" and the P+ active region 33" respectively constitute the N terminal and the P terminal of the junction diode 32". The N+ active region 37" and the P+ active region 33" can respectively be combined with the NMOS and the standard CMOS logic process. The source or drain of the PMOS is the same. Similarly, the dummy CMOS gate 39 "can be the same as the CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39' can be biased at a fixed voltage for the purpose of isolation between the P+ active region 33" and the N+ active region 37" during fabrication. The N+ active region 37" is coupled to a low voltage V- and N well 34 that is embedded in the PMOS body in a standard CMOS logic process. The resistive component (not shown in Figure 6a), such as the MTJ, can be coupled to one end. The P+ active region 33' and the other end are coupled to a high voltage power supply V+. To program such an electrical fuse memory cell, high and low voltages are applied to V+ and V-, respectively, and a large current is conducted through the MTJ and the junction diode. Body 32" to program the resistive element. Other embodiments of CMOS isolation techniques, such as shallow trench isolation, dummy CMOS gates or germanium blocking layers on one to four sides or on either side, can be readily applied to corresponding CMOS SOI technologies.

Figure 6b shows a cross-sectional view of another junction diode 45 embodiment using a finned field effect transistor (FinFET) technology programming selector. FinFET is a basic multi-gate transistor with a fin (FIN). FinFET technology is similar to traditional CMOS, but has a high thin island, which is raised on the germanium substrate to serve as a CMOS component. main body. The body is like a traditional CMOS, divided into source, drain and polysilicon or non-aluminum metal gates. The main difference is that in FinFET technology, the body of the MOS device is lifted onto the substrate, and the height of the island is the width of the channel, although the direction of current flow is still parallel to the surface of the crucible. Figure 6b shows an example of a FinFET technique in which the germanium substrate 35 is an epitaxial layer built on top of an SOI insulating layer or other high resistance germanium substrate. The ruthenium substrate 35 can be etched into several tall rectangular island regions 31-1, 31-2, and 31-3. Through the growth of the appropriate gate oxide layer, the island regions 31-1, 31-2, ie, 31-3, can cover both sides of the raised island region with MOS gates 39-1, 39-2, and 39-3, respectively. And define the source and drain regions. The source and drain regions are formed in the island regions 31-1, 31-2, and 31-3, and then filled with germanium, such as filled in the filled regions 40-1 and 40-2, so that the combined source and drain regions are large. It is enough to put down the joint. In Fig. 6b, the filled regions of 40-1 and 40-2 are only used to illustrate and reveal the cross section, for example, the filled regions may be filled to the surfaces of the island regions 31-1, 31-2, and 31-3. In this embodiment, the active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by the P+ implant layer 38 and the N+ implant layer (complementary to the P+ implant layer 38) to form the junction two. The P and N terminals of the body 45, rather than the PMOS like a conventional FinFET, are all covered by the P+ implant layer 38. The N+ active regions 37-1, 2, 3 are coupled to a low voltage power supply V-. The resistive element (not shown in Figure 6b), such as the MTJ, is coupled at one end to the P+ active regions 33-1, 2, 3 and at the other end to the high voltage supply V+. In order to program such an electrical fuse, high and low voltages are applied to V+ and V-, respectively, to conduct a large current through the resistive element and junction diode 45 to program the resistive element. Other embodiments of CMOS body technology isolation, such as shallow trench isolation, dummy CMOS gates, or germanium blocking layers, can be readily applied to the corresponding FinFET technology.

FIG. 7 shows an embodiment of a magnetic memory (MRAM) memory cell 310 that uses diodes 317 and 318 as programming selectors. According to this embodiment, the MRAM storage unit 310 In FIG. 7, there is a three-terminal MRAM memory cell and has a magnetic tunnel junction (MTJ) 311 including a free stack layer 312, a fixed stack layer 313 and a dielectric film therebetween, and two diodes 317 and 318. Free stack layer 312 is coupled to supply voltage V and coupled to fixed stack layer 313 via a dielectric film such as aluminum oxide (Al 2 O 3 ) or magnesium oxide (MgO). The N terminal of diode 317 is coupled to fixed stack layer 313 and the P terminal is coupled to V+ to program (logic) 1. The P terminal of diode 318 is coupled to fixed stack layer 313 and the N terminal is coupled to V- to program (logic) zero. If the V+ voltage is above V, current flows from V+ to V to program MTJ 311 to state 1. Similarly, if the V-voltage is below V, current flows from V to V- to program MTJ 311 into state 0. During the programming process, the other diode should be in the cutoff zone. At the time of reading, both V+ and V- can be set to 0V and the resistance between nodes V and V+/V- can be sensed to determine that the magnetic tunnel junction 311 is in state 0 or 1.

Figure 8a shows a cross-sectional view of an example of an MRAM memory cell 310 that includes an MTJ 311 and junction diodes 317 and 318 as programming selectors. According to this embodiment, the MTJ 311 has a free stack layer 312, a fixed stack layer 313, and a dielectric therebetween to form a magnetic tunnel junction. Diode 317 is used to program 1 and diode 318 is used to program 0. The diodes 317 and 318 have P+ and N+ active regions in the N wells 321 and 320, respectively, which can be used to embed PMOS in a standard CMOS process. The diode 317 has a P+ active region 315 and an N+ active region 314 to form the P and N terminals of the diode 1 of the programming 1. Similarly, diode 318 has P+ active region 316 and N+ active region 319 to form the P and N terminals of diode 0 of programming 0. The P and N terminals of diodes 317 and 318 shown in Figure 8a are isolated by STI 330. It is known to those skilled in the art that different isolation methods (such as a dummy MOS gate or SBL) can also be applied.

The free stacking layer 312 of the MTJ 311 can be coupled to the supply voltage V, the N of the diode 318 The terminal can be coupled to the supply voltage V- and the P terminal of the diode 317 can be coupled to another supply V+. In Figure 8a, Program 1 can be achieved by applying a high voltage (i.e., 2V) to V+ and V- while maintaining V at ground or 0V. For programming 1, current flows from diode 317 through MTJ 311, while diode 318 is in an off state. Similarly, programming 0 can be achieved by applying a high voltage (ie, 2V) to V and maintaining V+ and V-ground. In this case, current flows from the MTJ 311 through the diode 318, while the diode 317 is in the off state.

Figure 8b shows a cross-sectional view of another embodiment of an MRAM memory cell 310'. According to this embodiment, it includes MTJ 311' and junction diodes 317' and 318' as programming selectors. The MTJ 311' has a free stacking layer 312', a fixed stack layer 313' and a dielectric therebetween to form a magnetic tunnel junction. Diode 317' is used to program 1 and diode 318' is used to program 0. The diodes 317' and 318' have P+ and N+ active regions in the N wells 321 ' and 320', respectively, which must be fabricated in shallow wells that are additionally treated. Although more processing steps are required, the memory cell size can be smaller. The diode 317' has a P+ active region 315' and an N+ active region 314' to form the P and N terminals of the programming 1 diode 317'. Similarly, diode 318' has P+ active region 316' and N+ active region 319' to form the P and N terminals of programming 0 diode 318'. The STI 330' is used to isolate different active zones.

The free stacking layer 312' of the MTJ 311' can be coupled to the supply voltage V, the N terminal of the diode 318' can be coupled to the supply voltage V-, and the P terminal of the diode 317' can be coupled to the supply voltage V+ . Programming 1 in Figure 11b can be achieved by applying a high voltage (i.e., 2V) to V+ and V- while maintaining V ground or 0V. For programming 1, current flows through diode 317' via MTJ 311', while diode 318' is in an off state. Similarly, programming 0 can be done by applying a high voltage (ie 2V) to V and keeping V+ and V- grounding are achieved. In this case, current will flow from the MTJ 311' through the diode 318' while the diode 317' is in the off state.

Figure 9a shows an embodiment of a three-terminal 2X2 MRAM memory cell array that uses diodes 317 and 318 as programming selectors and displays programming conditions for one memory cell. The storage units 310-00, 310-01, 310-10, and 310-11 constitute a two-dimensional array. The memory unit 310-00 has an MTJ 311-00, a programming 1 diode 317-00 and a programming 0 diode 318-00. One end of the MTJ 311-00 is coupled to the supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to a supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to a supply voltage V-. Other memory units 310-01, 310-10, and 310-11 have similar couplings. The voltage V at the same row of memory cells 310-00 and 310-10 is connected to bit line 0 (BL0). The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to the bit line 1 (BL1). The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same column are connected to the word lines WL0P and WL0N, respectively. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to the word lines WL1P and WL1N, respectively. In order to write 1 to memory cell 310-01, WL0P is set to a high voltage, BL1 is set to a low voltage, and other BL and WL are set at the appropriate voltage, as shown in Figure 9a, to make other programming 1 and programming 0 Polar body disability. The thick black line in Figure 9a shows the direction of current flow.

Figure 9b shows another embodiment illustrating another condition for programming memory cell 310-01 in a 2X2 MRAM memory cell array to one. For example, BL1 and WL0P are respectively set to a low voltage and a high voltage to program the memory cell 310-01 to 1. If BL0 is set to a high voltage in Condition 1, WL0N and WL1N may be high voltage or floating, and WL1P may be low voltage or floating. The high and low voltages of MRAM in today's technology are approximately: High voltage 2-3V and low voltage 0. If BL0 is floating in Condition 2, WL0N and WL1N can be high voltage, low voltage, or floating, and WL1P can be low voltage or floating. In practice, floating nodes are typically coupled to a fixed voltage via very weak components to prevent leakage. In the embodiment shown in Figure 9a programmed to 1 condition, there are no floating nodes.

Figure 10a shows an embodiment of a three-terminal 2X2 MRAM memory cell array including MTJ 311 and junction diodes 317 and 318 as programming selectors, and a condition that the programming memory cell is zero. These memory cells 310-00, 310-01, 310-10, and 310-11 form a two-dimensional array. The memory unit 310-00 has an MTJ 311-00, a programming 1 diode 317-00, and a programming 0 diode 318-00. One end of the MTJ 311-00 is coupled to the supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to a supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to a supply voltage V-. Other memory units 310-01, 310-10, and 310-11 have similar couplings. The voltage V of the memory cells 310-00 and 310-10 in the same row is connected to the bit line BL0. The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to BL1. The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same column are connected to the word lines WL0P and WL0N, respectively. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to the word lines WL1P and WL1N, respectively. As shown in FIG. 10a, in order to write 0 to the memory cell 310-01, WL0N is set to a low voltage, BL1 is set to a high voltage, and other BLs and WLs are set at appropriate voltages to enable other programming 1 and programming 0 Polar body depletion. The thick black line in Figure 10a shows the direction of current flow.

Figure 10b shows another embodiment illustrating the condition of programming memory cell 310-01 in a three-terminal 2X2 MRAM memory cell array to zero. For example, set BL1 and WL0N respectively. The low voltage and high voltage can be programmed to zero for memory cell 310-01. In Condition 1, if BL0 is set to a low voltage, WL0P and WL1P may be low voltage or floating, and WL1N may be high voltage or floating. The high and low voltages of MRAM in today's technology are approximately: high voltage 2-3V and low voltage 0. In Condition 2, if BL0 is floating, WL0P and WL1P can be high voltage, low voltage, or floating, and WL1N can be high voltage or floating. In practice, floating nodes are typically coupled to a fixed voltage via very weak components to prevent leakage. Figure 10a shows an embodiment programmed to a 0 condition without any floating nodes.

The 2x2 MRAM array memory cells shown in Figures 9a, 9b, 10a, and 10b are three-terminal memory cells, i.e., the memory cells have V, V+, and V-nodes. However, if the programming voltage VDDP is less than twice the diode threshold voltage Vd (ie, VDDP<2*Vd), the V+ and V-nodes of the same memory cell can be connected together as a double-ended memory cell. Since Vd is about 0.6-0.7V at room temperature, such a double-ended memory cell can operate normally if the programming voltage is lower than 1.2V. This is a common voltage configuration of MRAM arrays in advanced CMOS technology with a supply voltage of approximately 1.0V. Figures 11a and 11b show circuit diagrams for programming 1 and 0, respectively, in a 2X2 MRAM array with two ends.

Figures 11a and 11b show examples of programming 1 and 0, respectively, in a 2X2 array with MRAM memory cells at both ends. These memory cells 310-00, 310-01, 310-10, and 310-11 form a two-dimensional array. The memory unit 310-00 has an MTJ 311-00, a programming diode 317-00 and a programming 0 diode 318-00. One end of the MTJ 311-00 is coupled to the supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to a supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to another supply voltage V-. If the VDDP<2*Vd condition is met, the voltages V+ and V- can be connected together at the memory cell level. its His storage units 310-01, 310-10, and 310-11 have similar couplings. The voltage V at the same row of memory cells 310-00 and 310-10 is connected to BL0. The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to BL1. The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same column are connected to WL0. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to WL1.

In order to write 1 to memory cell 310-01, WL0 is set to a high voltage, BL1 is set to a low voltage, and other BL and WL are set at the appropriate voltage, as shown in Figure 11a to make other programming 1 and programming 0 dipoles Body can be removed. The thick black line in Figure 11a shows the direction of current flow. To write 0 to memory location 310-01, WL0 is set to a low voltage, BL1 is set to a high voltage, and other BL and WL are set to the appropriate voltage, as shown in Figure 11b, to enable other programming 1 and programming 0 Polar body depletion. The thick black line in Figure 11b shows the direction of current flow.

As shown in Figures 9a-11b, an example of constructing an MRAM memory cell in a 2x2 array is for illustrative purposes only. Those skilled in the art can arbitrarily change the number of rows or columns of memory cells in a memory, and the rows and columns are interchangeable.

The magnetic parallelism or magnetic anti-parallel of magnetic memory (MRAM) memory cells may change the stability of the memory cells over time. However, most applications require data retention for 10 years and from an operating temperature of 0 to 85 ° C or -40 to 125 ° C. In order to maintain the stability of the memory cell over the life of the component and over such a wide temperature range, the magnetic memory can be periodically read out and then written back to the same memory cell, which is an update mechanism. The update cycle can be quite long, such as more than one second (eg, minutes, hours, days, weeks, or even months). The update mechanism can be generated internally by the memory or externally from the memory. Long-term update cycle to maintain the stability of the memory cell, can also be applied to other emerging memory, such as resistive memory (RRAM), conductive bridge random access Memory (CBRAM) and phase change memory (PCM).

According to another embodiment, a programmable resistive element can be used to create a memory. Figure 12a shows a portion of a programmable resistive memory 100, an array 101 of n-terminal MRAM memory cells 110 of n columns x (m + 1) rows and n pairs of word line drivers 150-i and 151-i (i =0,1,...,n-1) constructed. The memory array 101 has m normal lines and a reference line sharing a sense amplifier for differential sensing. Each of the memory storage units 110 has a resistive element 111 coupled to the P terminal of a programming 0 diode 112 and the N terminal of a programming 1 diode 113. Program 0 diode 112 and programming 1 diode 113 are used as programming selectors. Each of the resistive elements 111 in the same row of those memory storage units 110 is also coupled to one bit line BLj 170-j (j = 0, 1, .. m-1) or reference bit line BLR0 175-0. The memory cells are coupled to a word line WLNi 152-i at the N-terminal of the diode 112 at the same column 110, via local word line LWLNi 154-i (i=0, 1, ..., N-1). The P terminal of the diode 113 of the same column of the memory cells is coupled to a word line WLPi 153-i via the local word line LWLPi 155-i (i = 0, 1, ..., n-1) . Each word line WLNi or WLPi is coupled to at least one local word line LWLNi or LWLPi (i = 0, 1, ..., n-1), respectively. The LWLNi 154-i and LWLPi 155-i are typically constructed of a high-resistance material (such as N-well or polysilicon) and connected to the memory cell, and via conductive contacts or layer indirect points, buffers or post-decoders, respectively. 172-i or 173-i (i = 0, 1, ..., n-1) is coupled to WLNi or WLPi (eg, low resistance metal WLNi or WLPi). When a diode is used as the programming selector, a buffer 172-i or a post decoder 173-i may be necessary because of the current flowing through WLNi or WLPi; especially in some embodiments when one WLNi or WLPi drives multiple Memory cells are used for simultaneous programming and reading. Word lines WLNi and WLPi are driven by word line drivers 150-i and 151-i, respectively. For editing And read, its power supply voltage vddi can be switched between different voltages. Each BLj 170-j or BLR0 175-0 is coupled to a supply voltage VDDP via a Y-write-0 channel gate 120-j or 125 to program a 0, where each BLj 170-j or BLR0 175-0 respectively It is selected by YS0WBj (j=0,1,..,m-1) or YS0WRB0. Y-write-0 channel gate 120-j (j = 0, 1, ..., m-1) or 125 may be constructed with PMOS; however, NMOS, diode or bipolar components may also be implemented in some embodiments use. Similarly, each BLj 170-j or BLR0 175-0 is programmed via a Y-write-1 channel gate 121-j or 126 to a supply voltage of 0V, where each BLj 170-j or BLR0 175 -0 is selected by YS1Wj (j = 0, 1, .., m-1) or YS1WR0, respectively. The Y-write-1 channel gate 121-j or 126 can be constructed with NMOS, although PMOS, diode or bipolar components can also be used in some embodiments. Each BL or BLR0 is coupled to data line DLj or reference data line DLR0 via a Y-read channel gate 130-j or 135, respectively, by YSRj (j = 0, 1, .., m-1) or YSRR0 Select. In the portion of the memory array 101, m normal data lines DLj (j = 0, 1, ..., m-1) are connected to an input terminal 160 of a sense amplifier 140. The reference data line DLR0 provides the other input 161 of the sense amplifier 140, however a multiplexer is generally not required in the reference section. The output of sense amplifier 140 is Q0.

To program a 0 to a memory cell, as shown in Figure 10a or 10b, the particular WLNi, WLPi, and BLj are selected by the word line drivers 150-i, 151-i and the Y-pass channel gates 120-j are separated by YS0WBj, respectively. Select, where i = 0, 1, .., n-1 and j = 0, 1, ..., m-1, and other word lines and bit lines are also appropriately set. A high voltage is applied to VDDP. In some examples, the reference memory cell can be programmed to zero by setting the appropriate voltage to WLRNi 158-i, WLRPi 159-i and YS0WRB0, where i= 0,1,...,n-1. To program a 1 to a memory cell, as shown in Figure 9a or 9b, the particular WLNi, WLPi and BLj are selected by the word line drivers 150-i, 151-i, and the Y-pass channel gates 121-j are YS1WBj. Select, where i = 0, 1.. n-1 and j = 0, 1, ..., m-1, and other word lines and bit lines are also appropriately set. In some embodiments, the reference memory cell can be programmed to one by setting the appropriate voltage to WLRNi 158-i, WLRPi 159-i and YS1WR0 (i = 0, 1, ..., n-1). To read a memory location, data row 160 can be opened by opening specific WLNi, WLPi and YSRj (where i = 0, 1, ..., n-1, and j = 0, 1, ..., m-1) Is selected, and a reference data line DLR0 161 can be turned on by a particular reference memory cell, coupled to sense amplifier 140 to sense and compare the difference in resistance between 160 and DLR 161 and ground, while making all YS0WBj, YS0WRB0, YS1Wj and YS1WR0 are disabled, where j=0, 1, ..., m-1.

Figure 12b shows another embodiment of a MRAM memory cell with two endpoints to form an MRAM memory. According to this embodiment, the VDDP voltage difference between the high and low states must be less than twice the diode threshold voltage Vd, that is, VDDP < 2 * Vd. As shown in Fig. 12b, the two word lines WLNi 152-i and WLPi 153-i of each column originally in Fig. 12a can be combined into a word line driver WLNi 152-i, where i = 0, 1, ..., N-1. Further, as shown in Fig. 12b, the local word lines LWLNi 154-i and LWLP 155-i of each column originally in Fig. 12a can be merged into a local word line LWLNi 154-i, where i = 0, 1, ... , n-1. Further, the two word line drivers 150-i and 151-i in Fig. 12a can be combined into one, i.e., word line driver 150-i. The BL group and the WLN group of unselected memory cells are arranged with appropriate programming conditions of 1 and 0, as shown in Figures 11a and 11b, respectively. Since half of the word lines, local word lines and word line drivers can be removed in this embodiment, the area of the memory cells and memory can be Significantly reduced.

Figures 13a and 13b show flow diagram embodiments depicting a programmable resistive memory programming method S700 and a read method S800, respectively. Methods S700 and S800 describe the programming and reading of the programmable resistive memory 100 as shown in Figures 12a and 12b in the case of a programmable resistive memory. In addition, although it is a step process, it is known to those skilled in the art that at least some of the steps may be performed in a different order, including simultaneous or skipping.

Figure 13a depicts a flow diagram of a programming method S700 in a programmable resistive memory. According to this embodiment, in a first step S710, an appropriate power supply selector is selected to apply a high voltage power supply to the word line and bit line drivers. In a second step S720, the data to be programmed is analyzed in the control logic (not shown in Figures 12a and 12b), depending on what type of programmable resistive element. For MRAM, the direction in which current flows through the MTJ is more important than the duration. The control logic determines the appropriate power selector for the word line and bit line and initiates a control signal to ensure that the current flows through the desired direction for the desired amount of time. In a third step S730, a column (group) of memory cells is selected, so the opposite local word lines can be turned on. In a fourth step S740, the sense amplifier is deactivated to save power and prevent interference to the programmed operation. In a fifth step S750, a row (group) of memory cells can be selected and the corresponding Y-write channel gate can be opened to couple the selected bit line to a supply voltage. At the last step S760, the programmed conduction operation is completed in the established conduction path to drive the required current for a period of time. For most programmable resistor memories, this conduction path is made by a high voltage power supply through the selected bit line, the resistive element, the diode as the programming selector, and the NMOS pull-down element of the local word line driver to ground. Especially for programming 1 to an MRAM, the conduction path is by a high voltage power supply, through the PMOS pull-up component of the local word line driver, as a diode of the programming selector, the resistive element, Select the bit line to ground.

Figure 13b depicts a flow diagram of a programmable resistive memory read method S800 in accordance with an embodiment. In a first step S810, a suitable power selector is provided to select the supply voltage to the local word line driver, sense amplifier and other circuitry. In a second step S820, all Y-write channel gates, such as bit line programming selectors, can be turned off. In a third step S830, the desired local word line driver (group) can be selected such that the diodes (groups) as programming selectors (groups) have a conductive path to ground. In a fourth step S840, the sense amplifier (group) and the input signal ready for sensing are activated. In a fifth step S850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step S860, the desired Y-read pass gate is selected such that the desired bit line is coupled to an input of the sense amplifier. A conduction path is then established, from the bit line (group) to the desired resistive element of the memory cell, as a diode (group) of the programming selector (group) and a pull-down element of the local word line driver (group) to Ground. The same applies to the reference branch. At the last step S870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.

FIG. 14 shows a processor system 700 in accordance with another embodiment. In accordance with this embodiment, processor system 700 can include a programmable resistive element 744 in memory cell array 742 in memory 740. Processor system 700 can, for example, belong to a computer system. The computer system can include a central processing unit (CPU) 710 that communicates with various memory and peripheral devices via a common bus 715, such as input and output unit 720, hard disk drive 730, optical disk 750, memory 740, and other memory 760. . The other memory 760 is a conventional memory such as static memory (SRAM), dynamic memory (DRAM) or flash memory, usually via a memory controller. The central processing unit 710 communicates. Central processing unit 710 is typically a microprocessor, digital signal processor, or other programmable digital logic element. Memory 740 is preferably constructed in an integrated circuit that includes a memory array 742 having at least programmable resistive elements 744. Typically, memory 740 contacts central processing unit 710 via a memory controller. If desired, the memory 740 can be combined with a processor (e.g., central processing unit 710) in a monolithic integrated circuit.

The invention may be implemented in part or in whole on an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistive element can be a fuse, an anti-fuse or an emerging non-volatile memory. The fuse may be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a metal fuse, a contact fuse, or a layer indirect fuse. The antifuse may be a gate oxide breakdown antifuse, a dielectric contact therebetween or a layer indirect antifuse. Emerging non-volatile memory devices can be magnetic memory (MRAM), phase change memory (PCM), conductive bridge random access memory (CBRAM) or resistive random access memory (RRAM). Although the programming mechanisms are different, their logic states can be distinguished by different resistance values.

The above description and drawings are merely illustrative of implementations that are believed to be illustrative of the features and advantages of the invention. Specific process conditions, structural modifications and alternatives can be achieved without departing from the spirit and scope of the invention.

30‧‧‧Memory memory unit

30a‧‧‧ memory components

32a, 32b‧‧‧ diode

Claims (15)

A memory comprising: a plurality of memory storage units, at least one memory storage unit comprising: a memory element having a first end and a second end, the first end being coupled to the first supply voltage line; and a first diode The body includes at least a first end and a second end, wherein the first end has a first type doping, the second end has a second type doping, and the first end of the first dipole is Coupled to the second end of the memory element; a second diode includes at least a first end and a second end, wherein the first end has a first type doping and the second end has a second end Doping, the second end of the second diode is coupled to the second end of the memory element; wherein the second end of the first diode is coupled to a second supply voltage line; Wherein the first end of the second diode is coupled to the second or a third supply voltage line; wherein the memory element is configured to be programmable to a different logic state, via applying a voltage to the first a second and/or third supply voltage line to turn on the first diode and cut the first The diode is switched to a logic state, or the second diode is turned on to cut the first diode to another logic state. The memory of claim 1, wherein the memory element is a magnetic tunnel junction (MTJ) consisting of a fixed stack of multi-layered ferromagnetic or antiferromagnetic stacks, and multi-layer ferromagnetic or A freely stacked layer of antiferromagnetic stacks with insulators between the two stacked layers. The memory of claim 2, wherein the memory element is an elliptical magnetic tunnel junction (MTJ) on the surface of the crucible. The memory of claim 2, wherein the memory element is a magnetic tunnel junction (MTJ) and the first or second supply voltage line is inclined to an elliptical shape on the surface of the crucible. The memory of claim 1, wherein the memory element is a metal oxide between a metal or metal alloy electrode and an electrode. The memory of claim 1, wherein the memory element is a solid electrolyte membrane between the electrode and the electrode. The memory of claim 1, wherein at least one of the diodes is a junction diode, and the first and second active regions are present in the well as both ends of the diode. The memory of claim 1, wherein at least one of the diodes is a junction diode, and the first and second active regions are present in the well as the ends of the diode, and the well in which the well is located It is used to manufacture metal oxide semiconductor (CMOS) components. The memory of claim 1, wherein at least one of the diodes is a junction diode, and two active regions are used as two ends of the diode and separated by a dummy MOS gate. The memory of claim 1, wherein at least one of the diodes is a junction diode, and two active regions are used as two ends of the diode, and are separated by a shallow trench. The memory of claim 1, wherein at least one of the diodes is a junction diode, and the two active regions are both ends of the diode and separated by a telluride barrier layer. A memory comprising: a plurality of memory storage units, at least one memory storage unit comprising: A memory component has a first end and a second end, the first end being coupled to a first supply voltage line; and a first diode comprising at least a first end and a second end, wherein the first end Having a first type of doping, the second end having a second type of doping, the first end of the first diode being coupled to the second end of the memory element; and the second diode comprising at least a first end and a second end, wherein the first end has a first type doping, the second end has a second type doping, and the second end of the second dipole is coupled to the The second end of the memory element; wherein the second end of the first diode and the first end of the second diode are coupled to a second supply voltage line; wherein the memory element is configured to Programmable to different logic states, by applying a voltage to the first and second supply voltage lines, thereby turning on the first diode to cut the second diode to a logic state, or turning on the second The diode cuts off the first diode to another logic state. An electronic system comprising: a processor; and a memory operatively coupled to the processor, the memory comprising at least a plurality of memory storage units for providing data storage, each memory storage unit comprising: a memory component having a first And the first end is coupled to a first supply voltage line; and the first diode includes at least a first end and a second end, wherein the first end has a first type of doping Miscellaneous, the second end has a second type of doping, the first end of the first diode is coupled to the second end of the memory element, and the second end of the first diode is Coupled to a second supply voltage line; a second diode includes at least a first end and a second end, wherein the first end has a first type doping, the second end having a second type of doping, the second end of the second diode being coupled to the second end of the memory element, and the second diode The first end is coupled to the second or a third supply voltage line; wherein the memory element is configured to be programmable to a different logic state, via applying a voltage to the first, second, and/or third power source And a voltage line, thereby turning on the first diode to cut off the second diode to a logic state, or turning on the second diode to cut the first diode to another logic state. The electronic system of claim 13, wherein the electronic system is configured to periodically read the contents of each storage unit and write back the content. A method of providing a memory, comprising: providing a plurality of memory storage units, at least one memory storage unit comprising at least (i) a memory component having a first end and a second end, the first end being coupled to a first power source a voltage line; and (ii) a first diode comprising at least a first end and a second end, the first end having a first type of doping and the second end having a second type of doping, the first The first end of the diode is coupled to the second end of the memory element and the second end of the first diode is coupled to a second supply voltage line; (iii) a second diode Having at least a first end having a first type of doping, the second end having a second type of doping, the first end providing a first end of the diode, a second end providing a second end of the diode, the second end of the second diode being coupled to the second end of the memory element and the first end of the second diode being coupled to the second end a second or a third supply voltage line; and wherein the memory element is configured to be programmable to a different logic state via an applied voltage The first, second, and/or third power voltage lines, thereby turning on the first diode to cut off the second diode to a logic state, or turning on the second diode to cut off The first diode is in another logic state.