TWI459510B - Array substrate of flat display panel - Google Patents

Description

Array substrate of flat display panel

The invention relates to an array substrate, in particular to an array substrate of a flat display panel.

A flat display panel, such as a liquid crystal display (LCD) panel, an organic light emitting diode display (OLED display) panel, or a plasma display panel (PDP) Field emission display (FED) panels, etc., have become the mainstream display products on the market due to their thin thickness. A problem that the display panel generally encounters is that the resistance of the connecting wires located in the peripheral area and for transmitting the scanning signal or the data signal is uneven, resulting in poor signal transmission quality.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams of an array substrate of a conventional flat display panel. As shown in FIG. 1 , the array substrate of the conventional flat display panel comprises a substrate 10 , a plurality of signal lines 16 , a plurality of connecting wires 18 and a plurality of driving chips 20 . The substrate 10 includes a display area 12 and a peripheral area 14. The signal line 16 is disposed in the display area 12 of the substrate 10. The connecting wires 18 are disposed in the peripheral region 14 of the substrate 10, and one end of each connecting wire 18 is electrically connected to the signal line 16 respectively, and the other end of each connecting wire 18 is electrically connected to the driving chip 20. Thereby, the driving chip 20 can transmit the driving signal to the respective signal lines 16 via the connecting wires 18. As can be seen from FIG. 1, the connecting wires 18 electrically connected to the driving chips 20 have a left-right symmetric distribution, that is, the center position of each driving chip 20 has the same pitch between the connecting wires 18 which are the farthest from the electrical connection. t, therefore, the wiring resistance of each of the driving wafers 20 exhibits a uniform and regular distribution. However, as shown in FIG. 2, if it is limited by the design of the display panel, the connecting wires 18 electrically connected to the partial driving wafers 20' cannot have a left-right symmetric distribution due to insufficient layout area, that is, the center of the driving wafer 20'. The distance between the position c and the connecting wire 18 which is the farthest from the electrical connection is not equal to t1 and t2. As can be seen from FIG. 2, the spacing t1 is greater than the spacing t2, so the wiring resistance distribution of the driving chip 20' and the driving wafer 20' are The difference is large, so that the transmission quality of the driving signal is not good, and the block unevenness corresponding to the position of the driving wafer 20' is generated on the display.

One of the main objects of the present invention is to provide an array substrate of a display panel to solve the problem that the difference in wiring resistance value is excessively affected and the display quality is affected by the asymmetrically arranged driving wafer.

To achieve the above objective, the present invention provides an array substrate of a display panel, comprising: a substrate, a plurality of signal lines, a plurality of first connecting wires, a plurality of second connecting wires, at least one first driving chip, and at least one Two drive wafers. The substrate includes a display area and a peripheral area. The signal line is disposed in the display area of the substrate. The first connecting wire is disposed in a peripheral area of the substrate, and one end of each of the first connecting wires is electrically connected to a part of the signal line. The second connecting wire is disposed in a peripheral area of the substrate, and one end of each of the second connecting wires is electrically connected to a part of the signal line. With each second connection The signal line of the portion to which one end of the wire is connected is different from the signal line of the portion connected to one end of each of the first connecting wires. The first connecting wire and the second connecting wire are respectively defined by patterned metal layers having different layers of similar sheet resistance, and a portion of the first connecting wire and a portion of the second connecting wire partially overlap in a vertical projection direction And the first connecting wire and the second connecting wire are separated by an insulating layer to form electrical insulation. The first driving chip is electrically connected to the other end of each of the first connecting wires. The second driving chip is electrically connected to the other end of each of the second connecting wires.

In addition, the present invention provides an array substrate of a display panel, comprising a substrate, a plurality of signal lines, a plurality of first connecting wires, a plurality of second connecting wires, at least one first driving wafer and at least one second driving wafer. The substrate includes a display area and a peripheral area. The signal lines are disposed in the display area of the substrate, and the signal lines are arranged in parallel with each other. The first connecting wire is disposed in a peripheral area of the substrate, and one end of each of the first connecting wires is electrically connected to a part of the signal line. The second connecting wire is disposed in a peripheral area of the substrate, and one end of each of the second connecting wires is electrically connected to a part of the signal line. The signal line connecting the portion connected to one end of each of the second connecting wires is different from the signal line connecting the portion connected to one end of each of the first connecting wires. The number of first connecting wires is not equal to the number of second connecting wires. The first driving chip is electrically connected to the other end of each of the first connecting wires. The second driving chip is electrically connected to the other end of each of the second connecting wires.

In the array substrate of the display panel of the present invention, the first connecting wires and the second connecting wires are defined by patterned metal layers having different layers of similar sheet resistances. The number of connecting wires for electrically connecting the driving chips can be changed, so that the problem that the wiring resistance difference is excessively caused by the asymmetrically arranged driving chips can be avoided.

Please refer to Figures 3A and 3B. 3A is a schematic view showing an array substrate of a flat display panel according to a first embodiment of the present invention, and FIG. 3B is a partially enlarged schematic view showing an array substrate of the flat display panel of FIG. 3A. As shown in FIG. 3A, the array substrate 30 of the flat display panel of the present embodiment includes a substrate 31, a plurality of first connecting wires 38a, a plurality of second connecting wires 38b, at least one first driving wafer 40a, and at least one The second driving wafer 40b and the at least one third driving wafer 44. The substrate 31 includes a display area 32 and a peripheral area 34. The strip signal line 36 is disposed in the display area 32 of the substrate 31. The first connecting wire 38a is disposed in the peripheral region 34 of the substrate 31, and one end of each of the first connecting wires 38a is electrically connected to a part of the signal line 36. The second connecting wire 38b is disposed in the peripheral region 34 of the substrate 31, and one end of each of the second connecting wires 38b is electrically connected to a portion of the signal line 36. The first driving wafer 40a is electrically connected to the other end of each of the first connecting wires 38a. The second driving chip 40b is electrically connected to the other end of each of the second connecting wires 38b. In this embodiment, the first driving wafer 40a and the second driving wafer 40b may be, for example, a chip on film (COF), but not limited thereto.

As shown in Fig. 3B, the first connecting wire 38a and a portion of the second connecting wire 38b partially overlap in a vertical projection direction. The first connecting wire 38a and the second connecting wire 38b are respectively formed by patterned metal layers of different layers, for example, the first connecting wire 38a is composed of a first A metal layer M1 is defined, and the second connecting wire 38b is defined by a second metal layer M2, and the first metal layer M1 and the second metal layer M2 preferably have similar sheet resistance, but not Limited. In addition, the signal line 36 can be defined by the second metal layer M2 as well as the second connecting wire 38b, but is not limited thereto. For example, the signal line 36 can also be defined by the first metal layer M1 as the first connecting wire 38a. In this embodiment, since the signal line 36 and the first connecting wire 38a are different layers of wires, the first connecting wire 38a is electrically connected to the corresponding signal line 36 through the plurality of switching elements 42.

As can be seen from the above, the present embodiment defines the first connecting wire 38a and the second connecting wire 38b by using patterned metal layers having different layers and having similar chip resistances, so that the first connecting wire 38a and the portion of the second connecting wire 38b are in one Partially overlapping in the vertical projection direction. The overlapping wiring design in the vertical space can overcome the limitation of the insufficient layout area, and the first connecting wires 38a electrically connected to the first driving chips 40a have a left-right symmetric distribution, that is, the center of each of the first driving wafers 40a. The first connecting wire 38a, which is the farthest from the electrical connection, has an equal spacing S, and the second connecting wire 38b electrically connected to each of the second driving chips 40b has a left-right symmetric distribution, that is, each second driving chip. The second connecting wire 38b, which is located at the center position C of 40b and is the farthest from the electrical connection, also has an equal spacing S. Therefore, the wiring resistance values of the respective first driving wafers 40a and the respective second driving wafers 40b exhibit a uniform and regular distribution.

Please refer to FIG. 3A. In this embodiment, the signal line 36 in the display area 32 is, for example, the data line DL, and the first driving chip 40a and the second driving chip 40b are source driving wafers, and the third driving wafer 44 is used. Drive the wafer for the gate. Third driver chip The 44 series is electrically connected to one end of a plurality of connecting wires (not shown), and the other end of the connecting wires is electrically connected to each scanning line (not shown). In the present embodiment, the third driving wafer 44 is disposed within the peripheral region 34 of the substrate 31, which may have a design of a gate driver on array (GOA), but is not limited thereto.

Please refer to FIG. 4, which is a schematic diagram of an array substrate of a flat display panel according to another embodiment of the first embodiment of the present invention. For the sake of clarity, the differences between the different embodiments of the first embodiment of the present invention will be described, and the same reference numerals will be used to refer to the same elements. As shown in Fig. 4, in the present embodiment, the signal line 36 of the array substrate 30' of the flat display panel is the scanning line GL. The first drive wafer 36a and the second drive wafer 36b are gate drive wafers, and the third drive wafer 44 is a source drive wafer. The first connecting wire 38a and the second connecting wire 38b are respectively defined by patterned metal layers of different layers (refer to FIG. 3B), and are electrically connected to the respective signal lines 36. The arrangement of the first connecting wire 38a and the second connecting wire 38b and the effect thereof are the same as the foregoing embodiments, and will not be described again. In the array substrate of the flat display panel of the first embodiment of the present invention, the first connecting wire 38a and the second connecting wire 38b defined by the patterned metal layers of different layers can be used for electrically connecting the source driving chip and the data line. Or electrically connecting the gate driving the wafer and the scanning line, or simultaneously electrically connecting the source driving chip and the data line and electrically connecting the gate driving chip and the scanning line.

Please refer to FIG. 5, which is a schematic diagram of an array substrate of a flat display panel according to a second embodiment of the present invention. As shown in FIG. 5, the array of flat display panels of this embodiment The substrate 50 includes a substrate 51, a plurality of signal lines 56, a plurality of first connecting wires 58a, a plurality of second connecting wires 58b, at least one first driving wafer 60a, at least one second driving wafer 60b, and at least a third driving Wafer 62. The substrate 51 includes a display area 52 and a peripheral area 54. The signal lines 56 are disposed in the display area 52 of the substrate 51, and the signal lines 56 are arranged in parallel with each other. The first connecting wire 58a is disposed in the peripheral region 54 of the substrate 51, and one end of each of the first connecting wires 58a is electrically connected to a part of the signal line 56. The second connecting wire 58b is disposed in the peripheral region 54 of the substrate 51, and one end of each of the second connecting wires 58b is electrically connected to a portion of the signal line 56. It is to be noted that the number of the first connecting wires 58a is not equal to the number of the second connecting wires 58b.

In this embodiment, the first driving wafer 60a is electrically connected to the first connecting wire 58a, the second driving wafer 60b is electrically connected to the second connecting wire 58b, and the number of the first connecting wires 58a is different from the second. The number of connecting wires 58b. In the case that the layout area is insufficient, the design of the embodiment can still have the first connecting wire 58a electrically connected to the first driving wafer 60a and the second connecting wire 58b electrically connected to the second driving wafer 60b. The symmetrical distribution, that is, the central position C of each of the first driving wafers 60a and the first connecting wires 58a which are electrically connected to each other have an equal spacing S1, and the central position C of each of the second driving wafers 60b is electrically connected thereto. The farthest second connecting wires 58b also have an equal spacing S2.

Referring to FIG. 5, in the present embodiment, the signal line 56 in the display area 52 is, for example, the data line DL. The first driving wafer 60a and the second driving wafer 60b are sources The wafer is driven while the third driver wafer 62 is a gate drive wafer. The third driving chip 62 is electrically connected to one end of a plurality of connecting wires (not shown), and the other end of the connecting wires is electrically connected to each scanning line (not shown). In the present embodiment, the third driving chip 62 is disposed within the peripheral region 54 of the substrate 51 and has a design of a gate driver on array (GOA), but is not limited thereto.

Next, please refer to FIG. 6. FIG. 6 is a schematic diagram of an array substrate of a flat display panel according to another embodiment of the second embodiment of the present invention. For the sake of clarity, the differences between the different embodiments of the first embodiment of the present invention will be described, and the same reference numerals will be used to refer to the same elements. As shown in FIG. 6, in this embodiment, the signal line 56 of the array substrate 50' of the flat display panel is, for example, the scanning line GL, and the first driving wafer 60a and the second driving wafer 60b are gate driving wafers. The third drive wafer 62 is a source drive wafer. The first driving wafer 60a and the second driving wafer 60b are electrically connected to the first connecting wire 58a and the second connecting wire 58b, respectively, and the number of the first connecting wires 58a is not equal to the number of the second connecting wires 58b. With the above configuration, the first connecting wires 58a electrically connected to the first driving wafer 60a and the second connecting wires 58b electrically connected to the second driving wafer 60b can have a distribution of left and right symmetry. In the array substrate of the flat display panel of the second embodiment of the present invention, the first connecting wires 58a and the second connecting wires 58b can be used for electrically connecting the data lines in the display region 52 of the substrate 51 or electrically connecting the substrate 51. The scan lines in the display area 52 are also used to electrically connect the data lines and the scan lines in the display area 52 of the substrate 51.

In summary, the array substrate of the flat display panel of the present invention has a design in which the connecting wires defined by the patterned metal layers having different layers of similar chip resistance are partially overlapped in the vertical projection direction, or the respective driving is changed. The number of connecting wires electrically connected to the wafer can make the connecting wires electrically connected to the driving chips be symmetrically distributed, so as to solve the problem that the driving chip of the asymmetric configuration causes the difference in wiring resistance to be excessively large and affects the display quality.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Substrate

12‧‧‧Display area

14‧‧‧The surrounding area

16‧‧‧Signal line

18‧‧‧Connecting wires

20,20’‧‧‧ drive chip

c‧‧‧Drive wafer center position

t, t1, t2‧‧‧ spacing

31‧‧‧Substrate

32‧‧‧Display area

34‧‧‧The surrounding area

36‧‧‧Signal line

38a‧‧‧First connecting wire

38b‧‧‧Second connecting wire

40a‧‧‧First driver chip

40b‧‧‧second driver chip

42‧‧‧Transfer components

44‧‧‧ gate drive chip

51‧‧‧Substrate

52‧‧‧Display area

54‧‧‧ surrounding area

56‧‧‧Signal line

58a‧‧‧First connecting wire

58b‧‧‧Second connecting wire

60a‧‧‧First driver chip

60b‧‧‧second driver chip

62‧‧‧Gate drive chip

C‧‧‧Center position of the drive chip

S, S1, S2‧‧‧ spacing

M1‧‧‧ first metal layer

M2‧‧‧ second metal layer

DL‧‧‧ data line

GL‧‧‧ scan line

30,30'‧‧‧ Array substrate for flat display panel

50, 50' ‧ ‧ Array substrate for flat display panel

1 and 2 are schematic views of an array substrate of a conventional flat display panel.

3A is a schematic view of an array substrate of a flat display panel according to a first embodiment of the present invention.

FIG. 3B is a partially enlarged schematic view showing the array substrate of the flat display panel of FIG. 3A.

4 is a schematic view of an array substrate of a flat display panel according to another embodiment of the first embodiment of the present invention.

Fig. 5 is a schematic view showing an array substrate of a flat display panel according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram of an array substrate of a flat display panel according to another embodiment of the second embodiment of the present invention.

31. . . Substrate

32. . . Display area

34. . . Surrounding area

36. . . Signal line

38a. . . First connecting wire

38b. . . Second connecting wire

40a. . . First driver chip

40b. . . Second driver chip

44. . . Gate driver chip

C. . . Drive the center of the wafer

S. . . spacing

30. . . Array substrate of flat display panel

DL. . . Data line

Claims (9)

An array substrate of a flat display panel includes: a substrate including a display area and a peripheral area; a plurality of signal lines disposed in the display area of the substrate; and a plurality of first connecting wires disposed on the substrate One end of each of the first connecting wires is electrically connected to a portion of the signal lines; a plurality of second connecting wires are disposed in the peripheral region of the substrate, and each of the second connecting wires is disposed in the peripheral region One of the end portions is electrically connected to the portion of the signal lines, wherein the signal lines of the portion connected to one end of each of the second connecting wires are different from the portions connected to the one end of each of the first connecting wires. The first connecting wires and the second connecting wires are respectively defined by patterned metal layers having different layers of sheet resistance, and the first connecting wires and portions of the first connecting wires are partially defined by the patterned connecting metal layers The second connecting wires are partially overlapped in a vertical projection direction, and the first connecting wires and the second connecting wires are electrically insulated by an insulating layer; A first driving chip, electrically connected to the other end of each of the wires of the first connector; wafer and at least a second drive, connected to the other end of each of the second electrically conductive wire connection. The array substrate of the flat display panel of claim 1, wherein the signal lines comprise a plurality of scan lines. The array substrate of the flat display panel according to claim 1, wherein the The equal signal line includes a plurality of data lines. The array substrate of the flat display panel of claim 1, further comprising a plurality of switching elements, wherein the signal lines and the first connecting wires are defined by patterned metal layers of different layers, And each of the first connecting wires is electrically connected to the corresponding signal line through the switching component. An array substrate of a flat display panel, comprising: a substrate comprising a display area and a peripheral area; a plurality of signal lines disposed in the display area of the substrate, wherein the signal lines are arranged in parallel with each other; a connecting wire is disposed in the peripheral region of the substrate, and one end of each of the first connecting wires is electrically connected to a portion of the signal lines; and a plurality of second connecting wires are disposed on the periphery of the substrate One end of each of the second connecting wires is electrically connected to a portion of the signal lines, wherein the signal lines of the portion connected to one end of each of the second connecting wires are different from the foregoing The signal lines of the portion of the first connecting wire connected to one end, the number of the first connecting wires is not equal to the number of the second connecting wires; at least one first driving chip, and the other of the first connecting wires One end is electrically connected; and at least one second driving chip is electrically connected to the other end of each of the second connecting wires. The array substrate of the flat display panel of claim 5, wherein the first connecting wires have a left-right symmetric distribution. The array substrate of the flat display panel of claim 5, wherein the second connecting wires have a left-right symmetric distribution. The array substrate of the flat display panel of claim 5, wherein the signal lines comprise a plurality of scan lines, and the first drive wafers and the second drive wafers are gate drive wafers. The array substrate of the flat display panel of claim 5, wherein the signal lines comprise a plurality of data lines, and the first driving wafers and the second driving wafers are source driving wafers.