Claims (17)
一種薄膜電晶體，包括：一源極；一汲極，該汲極與該源極間隔設置；一半導體層，該半導體層與該源極和汲極電連接；以及一閘極，該閘極通過一絕緣層與該半導體層、源極及汲極絕緣設置，其改良在於，所述半導體層包括一奈米碳管薄膜，該奈米碳管薄膜包含複數個通過凡得瓦力首尾相連且擇優取向排列的奈米碳管，至少部分奈米碳管的排列方向沿源極到汲極延伸。
A thin film transistor comprising: a source; a drain, the drain is spaced apart from the source; a semiconductor layer electrically connected to the source and the drain; and a gate, the gate The insulating layer is insulated from the semiconductor layer, the source and the drain. The improvement is that the semiconductor layer comprises a carbon nanotube film, and the carbon nanotube film comprises a plurality of ends connected by van der Waals force and Preferably, the arrangement of the carbon nanotubes, at least part of the arrangement of the carbon nanotubes extends along the source to the drain.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述奈米碳管為半導體性的奈米碳管。
The thin film transistor according to claim 1, wherein the carbon nanotube is a semiconducting carbon nanotube.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述奈米碳管為單壁或雙壁奈米碳管，且該奈米碳管的直徑小於10奈米。
The thin film transistor according to claim 1, wherein the carbon nanotube is a single-wall or double-walled carbon nanotube, and the diameter of the carbon nanotube is less than 10 nm.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述奈米碳管薄膜進一步包括複數個首尾相連的奈米碳管束片段，每個奈米碳管束片段具有大致相等的長度且每個奈米碳管束片段由複數個相互平行的奈米碳管束構成，奈米碳管束片段兩端通過凡得瓦力相互連接。
The thin film transistor according to claim 1, wherein the carbon nanotube film further comprises a plurality of end-to-end carbon nanotube bundle segments, each of the carbon nanotube bundle segments having substantially the same length and each The carbon nanotube bundle segments are composed of a plurality of mutually parallel carbon nanotube bundles, and the carbon nanotube bundle segments are connected to each other by van der Waals force.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述奈米碳管薄膜的厚度為0.5奈米~100微米。
The thin film transistor according to claim 1, wherein the carbon nanotube film has a thickness of from 0.5 nm to 100 μm.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述絕緣層的材料為氮化矽、氧化矽、苯並環丁烯、聚酯或丙烯酸樹脂。
The thin film transistor according to claim 1, wherein the insulating layer is made of tantalum nitride, hafnium oxide, benzocyclobutene, polyester or acrylic resin.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述薄膜電晶體的閘極、源極及汲極的材料為金屬、合金、導電聚合物或導電性奈米碳管。
The thin film transistor according to claim 1, wherein the material of the gate, the source and the drain of the thin film transistor is a metal, an alloy, a conductive polymer or a conductive carbon nanotube.
如申請專利範圍第7項所述的薄膜電晶體，其中，所述薄膜電晶體的閘極、源極及汲極的材料為鋁、銅、鎢、鉬、金、銫、鈀或其合金。
The thin film transistor according to claim 7, wherein the material of the gate, the source and the drain of the thin film transistor is aluminum, copper, tungsten, molybdenum, gold, rhodium, palladium or an alloy thereof.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述絕緣層設置於閘極與半導體層之間。
The thin film transistor according to claim 1, wherein the insulating layer is disposed between the gate and the semiconductor layer.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述源極及汲極間隔設置於所述半導體層表面。
The thin film transistor according to claim 1, wherein the source and the drain are spaced apart from each other on a surface of the semiconductor layer.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述薄膜電晶體設置於一絕緣基板表面，所述半導體層設置於該絕緣基板表面，所述源極及汲極間隔設置於所述半導體層表面，所述絕緣層設置於該半導體層表面，所述閘極設置於絕緣層表面，並通過該絕緣層與源極、汲極及半導體層電絕緣。
The thin film transistor according to claim 1, wherein the thin film transistor is disposed on a surface of the insulating substrate, the semiconductor layer is disposed on the surface of the insulating substrate, and the source and the drain are disposed at intervals The surface of the semiconductor layer is disposed on the surface of the semiconductor layer, and the gate is disposed on the surface of the insulating layer, and is electrically insulated from the source, the drain, and the semiconductor layer by the insulating layer.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述薄膜電晶體設置於一絕緣基板表面，所述閘極設置於該絕緣基板表面，所述絕緣層設置於閘極表面，所述半導體層設置於該絕緣層表面，並通過所述絕緣層與閘極電絕緣，所述源極、汲極間隔設置於該半導體層表面，並通過該絕緣層與閘極電絕緣。
The thin film transistor according to claim 1, wherein the thin film transistor is disposed on a surface of an insulating substrate, the gate is disposed on a surface of the insulating substrate, and the insulating layer is disposed on a surface of the gate. The semiconductor layer is disposed on the surface of the insulating layer and electrically insulated from the gate by the insulating layer. The source and the drain are spaced apart from the surface of the semiconductor layer, and are electrically insulated from the gate by the insulating layer.
如申請專利範圍第11項或第12項所述的薄膜電晶體，其中，所述絕緣基板的材料為玻璃、石英、陶瓷、金剛石、塑膠或樹脂。
The thin film transistor according to claim 11 or 12, wherein the insulating substrate is made of glass, quartz, ceramic, diamond, plastic or resin.
如申請專利範圍第11項或第12所述的薄膜電晶體，其中
，所述源極、汲極與閘極設置於半導體層的同一面。
A thin film transistor according to claim 11 or 12, wherein
The source, the drain, and the gate are disposed on the same side of the semiconductor layer.
如申請專利範圍第11項或第12所述的薄膜電晶體，其中，所述源極、汲極與閘極設置於半導體層的不同面，半導體層設置於源極、汲極與閘極之間。
The thin film transistor according to claim 11 or 12, wherein the source, the drain and the gate are disposed on different faces of the semiconductor layer, and the semiconductor layer is disposed on the source, the drain and the gate between.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述薄膜電晶體的半導體層進一步包括一通道，該通道為所述半導體層位於所述源極和汲極之間的區域，該通道及半導體層的長度為1微米~100微米，寬度為1微米~1毫米，厚度為0.5奈米~100微米。
The thin film transistor of claim 1, wherein the semiconductor layer of the thin film transistor further comprises a channel, wherein the channel is a region between the source and the drain of the semiconductor layer, The channel and the semiconductor layer have a length of 1 micrometer to 100 micrometers, a width of 1 micrometer to 1 millimeter, and a thickness of 0.5 nm to 100 micrometers.
如申請專利範圍第1項所述的薄膜電晶體，其中，所述薄膜電晶體的載子移動率為10~1500cm2/V-1s-1，開關電流比為1×102~1×107。
The thin film transistor according to claim 1, wherein the film transistor has a carrier mobility of 10 to 1500 cm 2 /V -1 s -1 and a switching current ratio of 1 × 10 2 to 1 × 107.