TWI454901B - Microprocessor, method of operating microprocessor and computer program product - Google Patents

Description

Microprocessor, method of operating microprocessor, and computer program product

The present invention relates to power management of microprocessors, and more particularly to power management of multi-core microprocessors.

U.S. Patent Application Publication No. 12/403,195 (CNTR. 2 475), which issued on March 12, 2009, discloses an adaptive power regulation feature for providing when a time interval T is below a maximum power consumption P. User best performance. The P and T values are typically specified by the manufacturer of the system incorporating a microprocessor that includes adaptive power regulation characteristics. The microprocessor knows that it can operate on a frequency Xp that does not exceed PW watts (in one embodiment, the frequency of the operating point Xp corresponds to a P state, as P0). However, on most sub-intervals of T (this is a time division), the microprocessor calculates the average power consumption A for the most recent T time and compares A and P. If A is sufficiently lower than P (i.e., the microprocessor has a power "evaluation value"), the microprocessor can operate at a frequency higher than Xp.

The dual core on a single microprocessor component introduces power regulation characteristics or power evaluation values. This is because the system manufacturer imposes P and T requirements on the microprocessor component base rather than on each core. However, the independent core may consume different powers at a given time interval T. First, the operating system independently changes the operating points of each core (such as the P state and the C state) such that the core consumes different power. Furthermore, the software workload may not be the same on both cores. In addition, independent cores may reach their time division intervals at different points in time. For the whole, the P and T requirements must still satisfy the microprocessor components.

The present invention provides a microprocessor for operating in a system having one of the memories. The microprocessor includes a complex processing core, wherein each processing core of the processing core is configured to calculate a first value when a power event is detected, wherein the first value represents a processing core in a time interval of a power event The energy value consumed, wherein the length of the time interval is a predetermined time value; one or a plurality of second values are read from the memory, wherein the second value represents the energy value consumed by the other of the processing cores in the time interval And wherein the second value has been previously calculated by the other of the processing cores and written to the memory; and the operating frequency of the processing core is adjusted according to the first value and the second value.

The present invention provides a method of operating a microprocessor, comprising a complex processing core in a system having a memory, wherein the memory is accessible by the processing core, the method comprising: when detecting a power event occurs, by The processing core processing core calculates a first value, wherein the first value represents the energy value consumed by the processing core in one of the time intervals of the power event, wherein the length of the time interval is a predetermined time value; Reading one or a plurality of second values, wherein the second value represents an energy value consumed by the other of the processing cores in the time interval, wherein the second value has been previously calculated and written by the other of the processing cores Entering into the memory; and adjusting the operating frequency of the processing core according to the first value or the second value by the processing core.

The present invention provides a computer program product in which at least one computer readable storage medium is embedded. The computer program product includes a computer readable code embedded in a computer readable storage medium. Embedding a computer readable code in a computer readable storage medium for designating a microprocessor for operating in a system having a memory, the computer readable code including a code specifying a plurality of processing cores, wherein the plurality of processing Each processing core of the core is configured to: when a power event is detected, calculate a first value, wherein the first value represents an energy value consumed by the processing core in one of the time intervals of the power event, wherein the time interval is The length is a predetermined time value; one or a plurality of second values are read from the memory, wherein the second value represents an energy value consumed by the other of the processing cores in the time interval, wherein the second value has been previously The other of the processing cores calculates and writes to the memory; and adjusts the operating frequency of the processing core based on the first value and the second value.

The invention provides a microprocessor comprising an input and a complex processing core. The input is used to receive an indicator of the instantaneous power level exerted by the external power source on the microprocessor. Each processing core of the complex processing core is configured to: receive an indicator from the input end and determine an energy value consumed by the microprocessor in a previous period, wherein the previous period is a predetermined length of time; and the operation processing core is higher than one A frequency of a given frequency in response to the energy value consumed by the microprocessor determined in the previous period being less than a predetermined energy value.

The present invention provides a method of operating a microprocessor comprising receiving, by a microprocessor on an input, an indicator of the instantaneous power level applied to the microprocessor by an external power source; Determining, according to the indicator, the energy value consumed by the microprocessor in the previous period, wherein the period is a predetermined length of time; and operating the processing core at a frequency higher than a predetermined frequency in response to the micro-processing determined in the previous period The energy consumed by the device is lower than a predetermined energy value.

The present invention provides a computer program product in which at least one computer readable storage medium is embedded. The computer program product includes a computer readable code embedded in a computer readable storage medium for designating a microprocessor for operation in a system having a memory. The computer readable code includes a first code and a second code. The first code specifies an input for receiving an indicator of the instantaneous power level applied to the microprocessor by an external power source. a second code designating a complex processing core, wherein each processing core is configured to: receive an indicator from the input end and determine an energy value consumed by the microprocessor in the previous period, wherein the period is a predetermined length of time; and the operation processing The core is at a frequency above a predetermined frequency in response to the energy value consumed by the microprocessor determined in the previous period being lower than a predetermined energy value.

The present invention provides a microprocessor including a complex processing core, wherein each processing core is configured to: in each case of the connection, determine the energy value consumed by the microprocessor in a cycle prior to the current situation, wherein The period is a predetermined length of time; and the operation processing core is at a frequency higher than a predetermined frequency in response to the determination that the energy value consumed by the microprocessor is lower than a predetermined energy value in a period before the current situation. Wherein, the microprocessor is configured to cause all of the processing cores to operate simultaneously at a frequency above a predetermined frequency until one of the processing cores determines that the microprocessor has consumed more energy than a predetermined energy value in a period prior to the current situation.

The present invention provides a method of operating a microprocessor comprising: processing a core by each complex: in the case of each connection, determining the energy value consumed by the microprocessor in a cycle prior to the current situation, wherein the cycle For a predetermined length of time; and the operation processing core is at a frequency higher than a predetermined frequency in response to the period before the current situation, the energy value consumed by the microprocessor is lower than a predetermined energy value. Wherein, the microprocessor is configured to cause all of the processing cores to operate simultaneously at a frequency above a predetermined frequency until one of the processing cores determines that the microprocessor has consumed more energy than a predetermined energy value in a period prior to the current situation.

The invention provides a computer program product, wherein at least one computer readable storage medium is embedded in a computer device, and the computer program product comprises a computer readable program code embedded in the computer readable storage medium for designating a microprocessor for Operates in a system with one memory. The computer readable code includes a code for specifying a complex processing core, wherein each processing core is configured to: in the case of each connection, determine the energy value consumed by the microprocessor in a cycle before the current situation, Wherein the period is a predetermined length of time; and the operation processing core is at a frequency higher than a predetermined frequency in response to the period before the current situation, the energy value consumed by the microprocessor is lower than a predetermined energy value Wherein, the microprocessor can cause all of the processing cores to operate simultaneously at a higher frequency than the predetermined frequency until one of the processing cores determines that the microprocessor has consumed more energy than the predetermined energy value in the period prior to the current situation.

An embodiment of performing a power credit feature on a multi-core component is described below. According to an embodiment, the core shares information such that one of the cores can perform a power credit operation on the entire component. When a core determines that the required component-wide power credit is not available, the core transitions to a lower power P state to ensure that the component-wide P and T can be satisfied. Carefully, the core operates at or below Xp to ensure that the package-wide P and T are met, where Xp is the core of the microprocessor at which the specified time value T can be consumed by the microprocessor. For a frequency above a given energy value, the predetermined energy value is the product of P watts and T seconds, and Xp is the highest frequency that the system software requires for the core operation, and in some systems is typically the P state P0.

In one embodiment, the two cores share power credit information through the memory. In one embodiment, the area in the SMM memory is used. The BIOS writes the base address of the region to the MSR of each core. Each time the core experiences an event in a given list (such as frequency/voltage conversion, entry/exit sleep state, timer update average core power, etc.), the power credit information is updated to the shared memory region.

1 is a block diagram of a computer system 100 in accordance with the present invention. Computer system 100 includes a dual core microprocessor component 102 that includes power credit characteristics. Component 102 includes two cores: core 0 104A and core 1 104B. Although the embodiment of FIG. 1 includes two cores, embodiments of the present invention may also apply multi-core power credit characteristics.

In addition to the dual core microprocessor assembly 102, the computer system 100 further includes a voltage regulation module 108 (VRM) coupled to the component 102. The voltage regulation module 108 provides power to the component 102 via the VCORE signal 156. The component 102 provides a VID signal 158 to the voltage regulation module 108 for controlling the voltage level. The voltage level provides the VCORE signal 156 to the component 102 for the voltage regulation module 108.

The computer system 100 also includes a memory 106 coupled to the component 102 by a processor bus 154. In general, a memory controller (not shown), such as the north bridge of the chipset, is placed between the memory 106 and the processor bus 154. A system area such as a BIOS or an operating system is configured as a power information sharing area (PISA) 138 by the system software. The power information sharing area 138 includes power information 132A shared by core 0 104A to core 1 104B, and power information 132B shared by core 1 104B to core 0 104A. Each core 104 power information 132 includes a dynamic energy 114 value that is representative of the dynamic energy value consumed by each of the nearest time interval T cores 104, and a value of the leakage energy 116 that is used to represent the T core at the most recent time interval. The value of the leakage energy consumed by each of 104. In one embodiment, each core 104 power information 132 also includes a dynamic power constant that is used to calculate the respective dynamic energy of the core 104, as described below. Advantageously, the power information sharing area 138 provides a method for the dual cores 104 to communicate power information to each other to implement power evaluation value characteristics in a multi-core manner. As described in detail below, no communication power is required between the dual cores 104 via the signal wires. News.

Each core 104 includes a phase locked loop (PLL) 126 for providing core clock signals to the core 104 circuitry. Each core 104 also includes a temperature sensor 128 for sensing the temperature of the core 104. In one embodiment, the temperature of the core 104 can be read from the temperature sensor 128 by the microcode 127 of the core 104.

The core 104 also includes a bus timing timer 122 coupled to the receiving bus timing signal 146. The bus timing signal 146 is provided by the processor bus 154 coupled to the component 102. When bus bar 146 and core 104 actively enable bus timer timer 122, bus clock timer 122 times, causing bus clock timer 122 to continue tracking time in core 104 in this state. . The bus timing timer 122 is clocked at the rate of the bus timing signal 146. In this manner, bus clock 146 provides a common source, and each core 104 can track time through bus clock timer 122. In detail, each core 104 designs a bus timing timer 122 for power credit purposes to provide a periodic interrupt to the core 104. More precisely, the time interval T (e.g., one second) is divided into equal length bins (e.g., the number of bins 128), and the core 104 programs the bus clock timer 122 to interrupt each minute. The interval of the grid, or the length of the division or the length of the division. In one embodiment, processor bus 154 includes STPCLK and SLP signals for the Pentium processor bus. In one embodiment, the bus timing timer 122 begins to operate after the SLP is asserted.

Each core 104 also includes a resident timer 124 that is timed even when the core 104 clock is not used to hold the resident timer 124 for a time. In one embodiment, the resident timer 124 is driven by the self-excited oscillator, and the resident timer 124 continues to count even when the core 104 clock is stopped. In one embodiment, because the self-excited oscillator will change between the two cores 104, each core 104 will correct its resident timer 124 to the value of the bus timing 146 at an initial time.

Each core 104 also includes a power evaluation value register 129 for maintaining information used by each core 104 to perform power evaluation value characteristics. The power evaluation values are discussed below, for example, maximum power consumption P value; time interval T value; multiple constants associated with power calculations (e.g., dynamic power constants of core 104 that have been generated by component 102) Decision); the base address of the power information sharing area 138; the number of divisions; the temperature limit that is not conducive to the power evaluation value of the core 104; and the dynamic power factor used to calculate the dynamic energy consumption. Some power evaluation values may be written to the power evaluation value register 129 by system software, and some power evaluation values may be written into the power during manufacture, such as through fuses and/or hardwired values. The evaluation value register 129. Some power evaluation value registers 129 may be specific mode memories (MSRs) of the core 104.

2 is a block diagram of a power information sharing area 138 in the memory 106 of the computer system 100 of FIG. According to an embodiment, the core 104 is an x86 architecture core to support System Management Mode (SMM). If the processor can properly execute an application on an x86 processor, the processor is an x86 architecture processor. If an application can get predictable results, it shows that the application is executed correctly. In detail, core 104 executes the x86 instruction set and instructions containing the x86 user scratchpad set. As shown in FIG. 2, according to an embodiment, the system software (e.g., operating system, BIOS) allocates a portion of the SMM memory space 202 to the power information sharing area 138, which is an SMM memory space 202 that is not used by other functions. . Therefore, the system software design power evaluation value register 129 has the base address of the power information sharing area 138. In other embodiments, a portion of the system software configuration memory 106 space is provided to the power information sharing region 138 (which portion is not already in use by other software programs), and the base address to power evaluation value register of the power information sharing region 138 is used. 129 for programming.

3 is an operational flow diagram of the assembly 102 in accordance with the first embodiment of the present invention, and the flow begins in step 302.

In step 302, core 104 is reset. The core 104 can reset the core 104 by power-on, a reset bit determination of the component 102, or a software reset. The flow then proceeds to step 304.

In step 304, each core 104 corrects its resident timer 124, that is, each core 104 determines the cycle period of the resident timer 124 (to determine the number of bus clocking points for each resident timer 124). . As described above, the resident timer 124 can be driven by the self-excited oscillator, resulting in a very small variation in the cycle period of the resident timer 124 between the individual integrated circuits. Thus, each core 104 corrects its resident timer 124 based on the frequency of the bus timing 146. In detail, each core 104 determines the number of cycles of the bus 126 that occurs due to each cycle of the resident timer 124. In one embodiment, the microcode 127 is operated in response to a reset of the core 104, which simultaneously activates the resident timer 124 and the bus timing timer 122 and programs it to one of the bus cycle 146 cycles. An interrupt is formed after a predetermined number. When the bus timing timer 122 is interrupted, the microcode 127 reads the value of the resident timer 124 to determine the number of cycles that occur on the resident timer 124, and the number of cycles by the resident timer 124 will be the bus time. The predetermined number of cycles of the timer 122 is divided by the cycle of the resident timer 124 to determine the number of bus cycle 146 cycles that occur due to each cycle of the resident timer 124. The process ends at step 304.

Fig. 4 is a flow chart showing the operation of the computer system 100 according to Fig. 1 of the present invention. Flow begins at step 402.

In step 402, the system software writes one or more power evaluation value registers 129 to an initial power evaluation value characteristic. As described above, the write can specify a data value associated with the power evaluation value. In one embodiment, the write to power evaluation value register 129 can initiate the microcode 127 of FIG. The flow then proceeds to step 404.

In step 404, the microcode 127 generates and initializes the initial structure in response to the initialization in step 402. That is, the microcode 127 produces a grid structure that includes the loops of the items. The number of items corresponds to the number of time intervals of the time interval T. Each item is used to store information about the power consumption in the corresponding compartment. In one embodiment, each of the bins stores the dynamic energy value and the leakage energy value consumed by the core 104 during the time of the bin. In one embodiment, the microcode 127 initializes each bin by a predetermined value of dynamic energy and leakage energy. In one embodiment, the microcode 127 generates a partition structure in the private random access memory of the core 104. The user instruction cannot access the private random access memory, and only the microcode 127 can perform the random access memory. access. The microcode 127 dynamically updates the cell structure and performs power evaluation value characteristics using the cell structure. The flow then proceeds to step 406.

In step 406, the microcode 127 initially has a variable relating to the power evaluation value characteristic, the variable being stored in the private random access memory. Most of the variables are read from the power credit register 129, and the remaining variables are calculated. For example, the time of the division is obtained by dividing the time interval T by the number of divisions. Other parameters obtained include (but the invention is not limited thereto): time-interval leakage and dynamic energy of the most recently calculated core 104; time-interval total energy of the most recently calculated core 104; time of the recently updated partition structure; threshold If the time interval energy of the component 102 is lower than the threshold, the core 104 determines to operate at an operating point higher than Xp (in one embodiment, there are two frequencies higher than the Xp and the two-phase different threshold); the threshold if the system The software recently requested the threshold, the core 104 determines the operating point above Xp; the dynamic energy factor; the index of the binning item; the temperature of the core 104 of the last sample; the voltage of the last core 104; the last core 104 The frequency. The core 104 also determines its dynamic energy constant, which is the value of the product of the frequency and the square of the voltage, used to calculate the dynamic energy consumption of the core 104. In one embodiment, the microcode 127 calculates the dynamic power constant as an information function in the power evaluation value register 129. In one embodiment, to reduce the amount of computational effort, core 104 maintains dynamic and leakage energy values separately in the binning item, time interval, and power information sharing area 138. In detail, this value is a converted value, and the dynamic energy value is not added to the dynamic power constant. However, when the final component spacing energy value is calculated in the sub-program W (see Figure 9), the dynamic power constant is only multiplied by the spacing dynamic energy. In this embodiment, core 104 also writes dynamic power constant values to power information sharing area 138 at an initial time. Then proceed to step 412.

In step 412, the microcode 127 sets the bus timing timer 122 and activates the bus timing timer 122 to generate an interrupt after a divided time has occurred. Each time the bus timing timer 122 interrupt occurs, the microcode 127 redesigns the bus timing timer 122 to generate an interrupt when the time of the division occurs. In addition, each time the core 104 is started from a sleep state in which the core 104 clock is not operational, the microcode 127 redesigns the bus timing timer 122 to generate an interrupt when the time of the division occurs. The process ends at step 412.

Figure 5 is a flow chart showing the operation of the computer system 100 according to the first embodiment of the present invention. Figure 5 includes Figures 5A and 5B. Figure 5A includes steps 502 through 539, and Figure 5B includes steps 542 through 588. Flow begins at step 502.

In step 502, a power event occurs at core 104. The power event includes a core 104 clock frequency update, an interrupt to the bus schedule timer 122, the core 104 goes to sleep, the core 104 starts from the bus schedule timer 122 sleep state, or the core 104 boots from the resident timer 124 sleep state. . In an embodiment, the power event causes the microcode 127. The flow then proceeds to step 504.

In decision step 504, the microcode 127 determines whether to update the core 104 clock frequency, and the reason that the microcode 127 updates the core 104 clock frequency includes (but the invention is not limited thereto) the system software requires changing the P state or temperature event of the core 104. For example, if the temperature of the core 104 is higher or lower than a predetermined threshold. If the core 104 updates the clock frequency, the flow proceeds to step 522, otherwise the flow proceeds to step 506.

In decision step 506, the microcode 127 determines if the bus timing timer 122 has generated an interrupt. If the bus timing timer 122 generates an interrupt, the flow proceeds to step 528, otherwise the flow proceeds to step 508.

In step 508, the microcode 127 determines if the core 104 is in a sleep state. Entering the sleep state means that the core 104 no longer executes user instructions. In an embodiment, the sleep state may correspond to a well-known C state. For example, core 104 is in a suspended state, such as a C1C state, in response to a temperature adjustment event or executing a HALT instruction or a MWAIT instruction. Furthermore, the computer system 100 chipset asserts the STPCLK signal on the processor bus 154 to request that the SLP signal be asserted to stop the core 104 clock as C2. Until the SLP is asserted, the core 104 clock is still active and the bus clock timer 122 is still operating. Then, once the SLP is asserted, as C3, the bus schedule timer 122 will no longer function and the core 104 must rely on the resident timer 124 to determine the sleep time of the core 104. In addition, core 104 can reduce sleep power consumption by turning off phase-locked loop 126 as C4. Finally, core 104 can reduce sleep power consumption by stopping some or all of the cache memory and interrupting power as C5. It is worth noting that the core 104 consumes less power in the sleep state than in the operational state, and takes into account the power credit characteristics when calculating the energy consumption of the total component 102 at the most recent time interval. The system software may require the core 104 and/or component 102 to change to a dormant state, or the core 104 may change itself. If the core 104 is about to sleep, the flow proceeds to step 534, otherwise; the flow proceeds to step 512.

In step 512, during the period in which the bus timer 122 is still operating, the microcode 127 determines whether the core 104 is activated from the sleep state (the sleep state of the bus timer) so that the microcode 127 can update the bin. Structure and spacing energy values. If the core 104 is initiated from the sleep state of the bus schedule timer 122, the flow proceeds to step 538, otherwise, the flow proceeds to step 514.

In decision step 514, during the period in which bus clock timer 122 is no longer operational, microcode 127 determines whether core 104 is booted from a sleep state (sleep state of the resident timer) such that microcode 127 is no longer updated. The bin structure and the pitch energy value, and the core 104 must rely on the resident timer 124 to determine the sleep time of the core 104. If the core 104 is initiated from the sleep state of the resident timer 124, the flow proceeds to step 542, otherwise the flow ends at step 514.

In step 522, a subroutine is called, here referred to as subprogram Z. The subprogram Z will be described in detail in Fig. 6. The return is obtained from the subprogram Z and the flow proceeds to step 524.

In step 524, a subroutine is called, here referred to as subprogram X. The subroutine X will be described in detail in Fig. 8. A return is obtained from the subroutine X and the process ends with step 524.

In step 528, the secondary program Z is called. The return is obtained from the subprogram Z and the flow proceeds to step 532.

In step 532, a subroutine is called, here referred to as subprogram Y. The subroutine Y will be described in detail in Fig. 10. The process ends at step 532.

In step 534, a program is called. The reward is obtained and the flow proceeds to step 536.

In step 536, the microcode 127 puts the core 104 into a sleep state. The process ends at step 536.

In step 538, the subprogram Z is called. The return is obtained from the subprogram Z and the flow proceeds to step 539.

In step 538, the secondary program Y is called. The process ends at step 539.

In step 542, the microcode 127 reads the resident timer 124 and calculates the sleep time (TSLP). In one embodiment, the microcode 127 cycles through the bus 146 to calculate the sleep time. The flow proceeds to step 544.

In step 544, the microcode 127 calculates the time remaining for the bin, using the time of the bin minus the time of the last update of the bin, which is used as the variable of the microcode 127. The flow then proceeds to step 546.

In step 546, the microcode 127 determines in step 544 whether the calculated sleep time is greater than the time interval. If the sleep time is greater than the time interval, the flow proceeds to step 548, otherwise the flow proceeds to step 564.

In step 548, the microcode 127 calculates the leakage energy consumed by the core 104 when the core 104 is in a sleep state. The leakage energy is calculated as a function of the temperature of the core 104 provided by the temperature sensor 128 and the operating voltage. The flow then proceeds to step 552.

In step 552, the microcode 127 sets the dynamic energy consumed when the core 104 is in the sleep state to zero because the core 104 clock is not operating. The flow then proceeds to step 554.

In step 554, the microcode 127 writes the core spacing leakage energy and dynamic energy calculated in steps 548 and 552 to the area of the power information 132. The area of the power information 132 is related to the core 104 of the power information sharing area 138. . The flow then proceeds to step 556.

In step 556, the microcode 127 is calculated in the time of the division. When the core 104 sleeps, the dynamic energy consumed is divided by the core spacing dynamic energy by the number of divisions to obtain dynamic energy. The flow then proceeds to step 558.

In step 558, the microcode 127 calculates the leakage energy consumed when the core 104 is dormant in the time of the division, and divides the core spacing leakage energy by the number of divisions to obtain the leakage energy. The flow then proceeds to step 562.

In step 562, the microcode 127 fills the grid dynamic energy and the grid leakage energy calculated in steps 556 and 558 into all of the bin items in the queue. The flow then proceeds to step 562.

In step 564, the microcode 127 determines if the sleep time is less than the time remaining in the current bin. If the sleep time is less than the remaining time of the previous division, the flow proceeds to step 566, and if not, the flow proceeds to step 572.

In step 566, the microcode 127 sets the dynamic power factor to zero such that the dynamic energy calculated in step 712 is zero. The flow then proceeds to step 568.

In step 568, a subroutine is called, here referred to as subprogram V, wherein the subprogram V is called with a time parameter which is the sum of the last update time and the sleep time of the time division. The subroutine V is described in detail in Fig. 7. The process ends with the subprogram V.

In step 572, the microcode 127 determines if the sleep time is greater than the time of the bin. If the sleep time is greater than the time division time, the flow proceeds to step 574, otherwise, the flow proceeds to step 584.

In step 574, the microcode 127 sets the dynamic power factor to zero such that the dynamic energy calculated in step 712 is zero. The flow then proceeds to step 576.

In step 576, the subroutine V is called with a time parameter equal to the time of the time division. The reward is then obtained from the subroutine V and the flow proceeds to step 578.

In step 578, the secondary program Y is called. Get the reward and proceed to step 582.

In step 582, the sleep time is subtracted from the time division by the time division time. Advantageously, the loop from steps 572 to 582 and the steps 584 to 588 grasp the possibility that the core 104 is in a dormant state, which is a time when the core clock does not operate for multiple time divisions and it must be calculated The process of separating the structures in the update time. The flow then proceeds to step 572.

In step 584, the microcode 127 sets the dynamic power factor to zero such that the dynamic energy calculated in step 712 is zero. The flow then proceeds to step 586.

In step 586, the subroutine V is called with a time parameter equal to the time of the time division. The reward is then obtained from the subroutine V and the flow proceeds to step 588.

In step 588, the sub-program Y is called and the flow ends at step 588.

Fig. 6 is a flowchart showing the operation of the subprogram Z by the computer system 100 according to Fig. 1 of the present invention. The flow begins in step 602.

In step 602, the microcode 127 sets the dynamic power factor based on whether the core 104 is in an operational state or a particular sleep state. The dynamic power factor of the operational state is 1, and since the power consumed by the general core 104 in each successive low sleep state is low, each successive low sleep state has a smaller dynamic power factor. For example, the dynamic power factor of the C1 state is the fraction of the dynamic power factor of the operating state, such that the product thus calculated in step 712 can also be the same as the operating state, due to the dynamic power constant in the C1 state, The voltage and frequency can be the same as the operational state, while the core 104 can consume lower power because it can be suspended by the execution of the instruction. Additionally, in an embodiment, step 708 can incorporate a leakage power factor. For example, in the C4 state, the leakage power factor of the C4 state is less than the leakage power factor of the C3 state, since the core 104 consumes less power due to the deactivation of the phase locked loop 126, and in the C5 state, C5 The leakage power factor of the state is less than the leakage power factor of the C4 state, since the core 104 consumes less power due to the de-energization of the voltage of the cache memory. The flow proceeds to step 604.

In step 604, the microcode 127 reads the value of the bus timing timer 122 to determine how long the core 104 has been operating since the current division time. The flow proceeds to step 606.

In step 606, the value of the secondary program V and the bus timing timer 122 read in step 604 are called. The process ends at step 606.

Fig. 7 is a flow chart showing the operation of the subroutine V by the computer system 100 according to Fig. 1 of the present invention. The process begins in step 702.

In step 702, the microcode 127 begins with the current bin (the last update TLUP) and calculates the time based on the value of the timer input to the subroutine V, which may be in step 604 of FIG. The value from the bus timing timer 122 is read or passed through the values in steps 568, 576 or 586 of FIG. The flow proceeds to step 706.

In step 706, the microcode 127 reads the temperature sensor 128 to obtain the current temperature. Flow proceeds to step 708.

In step 708, the microcode 127 calculates the leakage energy consumed in the last update (TLUP) based on the voltage and the current temperature. The flow proceeds to step 712.

In step 712, the microcode 127 calculates the product of the dynamic energy consumed by the core 104 as the last update (TLUP), its frequency, the dynamic power constant, the dynamic power factor, and its voltage squared in the last update (TLUP). In one embodiment, the microcode 127 calculates an average of the new and old voltages and an average of the new and old frequencies to perform the above calculations. In most cases, such as when a bus clock timer 122 is interrupted, the old voltage and frequency will be the same as the new voltage and frequency, such that the average of the new and old voltages and the average of the new and old frequencies are the same as the current values. In addition, in the case of frequency and / or voltage changes, the average of the new and old voltages and the new and old average will be different from the current values. The flow proceeds to step 716.

In step 716, the microcode 127 increases the leakage energy of the current bin by the leakage energy calculated at step 708. Additionally, the microcode 127 increases the current divisional dynamic energy by the dynamic energy calculated at step 712. The value of the self-power information sharing area 138 is in the oldest (initial) division, and the number of divisions is relatively large (in one embodiment, the number of divisions is 128), and the inaccurate voltage in the value can be attributed to time. The quantization of the spacing (T) is generally relatively small (nearly 1%). Flow proceeds to step 718.

In step 718, the microcode 127 adds the leakage energy of the current time interval to the core 104 by the leakage energy calculated in step 708. Additionally, and the microcode 127 increases the dynamic energy of the current time interval to the core 104 by the dynamic energy calculated in step 712. The flow proceeds to step 722.

In step 722, the microcode 127 writes the leakage energy and the dynamic energy to the power information sharing region 138 to the core 104 calculated in step 718. The process ends at step 722.

Figure 8 is a flow chart showing the operation of the sub-program X in accordance with the computer system 100 of Figure 1 of the present invention. The flow begins in step 802.

In step 802, the microcode 127 determines whether the requested frequency is the same as the power evaluation value characteristic trigger frequency. If the required frequency is the same as the power evaluation value characteristic trigger frequency, the flow proceeds to step 804; otherwise, the flow proceeds to step 803.

In step 803, the microcode 127 controls the voltage regulation module 108 and the core 104 phase locked loop 126, causing the core 104 to operate in the desired P-state. In one embodiment, a comparator compares the VID signal 158 output of the two cores 104, and when the VID signals 158 output of the two cores 104 are different, one of the larger ones is selected. The process ends at step 803.

In step 804, the microcode 127 obtains the temperature of the core 104 from the temperature sensor 128 and determines if the temperature of the core 104 is greater than a predetermined temperature threshold. In an embodiment, the temperature threshold is determined by the power rating 129. When the temperature of the core 104 is higher than the predetermined temperature threshold, the flow proceeds to step 803; otherwise, the flow proceeds to step 806.

At step 806, a program W is called. For a detailed description of the subprogram W, refer to the description of Fig. 9. The process receives a return from the subroutine W, which returns the energy consumed by the component 102 in the latest time interval, or the value of the component time interval energy (PIE) (ie, the return of the subprogram W is the component time interval energy). The flow proceeds to step 808.

In step 808, the microcode 127 determines if the component time interval energy received in step 806 is greater than a predetermined energy threshold. The established energy threshold is slightly less than the product of the maximum power consumption (P) and the time interval (T). In another embodiment, the microprocessor 100 circuit that consumes a lot of power outside the core 104 can reduce the predetermined energy threshold, such as a shared cache memory; or the subprogram W can include component time interval energy. The energy consumed by the circuitry of the microprocessor 100 external to the core 104 is calculated. In an embodiment, the predetermined energy threshold is provided by the power evaluation value register 129. If the component time interval energy is greater than the predetermined energy threshold, the flow proceeds to step 803; otherwise, the flow proceeds to step 812.

In step 812, the microcode 127 advantageously controls the voltage regulation module 108 and the core 104 phase locked loop 126 to cause the core 104 to operate at an operating point above Xp. The process ends at 812.

Fig. 9 is a flow chart showing the operation of the subroutine W in the computer system 100 according to Fig. 1 of the present invention. The flow begins in step 902.

In step 902, the microcode 127 reads the time interval dynamic energy and the time interval leakage energy of the other of the cores 104 from the power information sharing area 138. It should be noted that in embodiments with more than two cores 104, the microcode 127 can read the value of the time interval dynamic energy and the time interval leakage energy to the other of each core, and in steps 904 and 908 below. The time interval dynamic energy and the time interval leakage energy are used in the calculation flow to calculate the time interval energy of the component 102. The flow proceeds to step 904.

At step 904, the microcode 127 uses the value obtained in step 902 to add the leakage energy of the other of the core 104 and the dynamic energy of the other of the cores 104 as the time interval energy. The flow proceeds to step 906.

In step 906, the microcode 127 adds the leakage energy of the core 104 and the dynamic energy of the core 104 as the time interval energy of the core 104. The flow proceeds to step 908.

At step 908, the microcode 127 adds the time interval energy calculated by the other of the core 104 in step 904 and the time interval energy calculated by the core 104 in step 906 as the time interval energy of the component 102. The flow proceeds to step 912.

In step 912, the microcode 127 reports the time interval energy calculated by the component 102 in step 908. The process ends at step 912.

Fig. 10 is a flow chart showing the operation of the subprogram Y by the computer system 100 according to Fig. 1 of the present invention. The process begins in step 1002.

In step 1002, the microcode 127 restarts the bus timing timer 122. That is, the microcode 127 programs the bus timing timer 122 to operate other binning times and generate an interrupt to the core 104. The flow proceeds to step 1004.

In step 1004, the microcode 127 obtains the temperature of the core 104 from the temperature sensor 128 and determines if the temperature of the core 104 is above a predetermined temperature threshold. If the temperature of the core 104 is above a predetermined temperature threshold, the flow proceeds to step 1024; otherwise, the flow proceeds to step 1006.

In step 1006, the subroutine is called. The flow from the subroutine W reports the energy (component time interval energy) consumed by the calculated component 102 in the most recent time interval. The flow proceeds to step 1008.

In step 1008, the microcode 127 determines if the component time interval energy received in step 1006 is greater than a predetermined energy threshold. If the component time interval energy is greater than the predetermined energy threshold, the flow proceeds to step 1024; otherwise, the flow proceeds to step 1014.

In step 1014, the microcode 127 advantageously controls the voltage regulation module 108 and the phase locked loop 126 of the core 104 to cause the core 104 to operate above the operating point Xp. In one embodiment, a comparator compares the VID signal 158 outputs of the two cores 104, and when the VID signals 158 outputs of the two cores 104 are different, one of the larger ones is selected. The flow proceeds to step 1016.

In step 1016, the microcode 127 reduces the time interval leakage energy to the core 104 by the specific leakage energy of the oldest binning item in the queue. Thus, the current time interval leakage energy for the core 104 can be more efficiently computed by the operation of step 718 of FIG. 7 and step 1016 of FIG. 10 as compared to summing all of the divisional leakage energy. Similarly, the microcode 127 reduces the current time interval dynamic energy to the core 104 by the specific dynamic energy of the oldest binning item in the queue. The flow proceeds to step 1018.

At step 1018, the microcode 127 writes the leakage energy and dynamic energy calculated in step 1016 to the core 104 to the power information sharing region 138. The flow proceeds to step 1022.

In step 1022, the microcode 127 clears the oldest cell in the queue so that the oldest cell becomes the most recent cell or the current cell. The process ends at step 1022.

In step 1024, the microcode 127 controls the voltage regulation module 108 and the phase locked loop 126 of the core 104 to cause the core 104 to operate at a previous operating point, such as Xp or below. The flow proceeds to step 1016.

As can be seen from the above description, advantageously, all cores can operate above Xp as long as sufficient power evaluation values are accumulated (for example, all cores 104 in a time period determine that the component time interval energy does not exceed a predetermined energy threshold). The frequency. The present invention is superior to multi-core processors that operate on one or more cores at a raised frequency based solely on a coarse index, as this approach does not enable all core operations at an elevated frequency, so anyway One of the multiple cores will be dormant.

11 is a block diagram of a computer system 100 including a dual core microprocessor assembly 102 in accordance with another embodiment of the present invention, including a power evaluation value characteristic. The computer system 100 shown in FIG. 11 is similar to the computer system 100 shown in FIG. 1, and includes a component 102 coupled to the memory 106 and the voltage regulation module 108 via a bus bar 154, and the component 102 includes two cores 104A. /104B. In addition, the energy consumption of the component 102 device of the computer system of Fig. 11 has been determined (due to the power evaluation value characteristic) as a computer system different from that of Fig. 1. The core 104 in the computer system 11 shown in Fig. 1 calculates its power consumption (energy consumption rate) based on various inputs (such as voltage, frequency, and temperature) to calculate the energy consumption in the time interval, the computer shown in Fig. 11. The system 100 includes circuitry external to the component 102 that provides an instantaneous power consumption indicator VINSTPWR signal 1154, and the core 104 uses the instantaneous power consumption indicator VINSTPWR signal 1154 to calculate the energy consumption over the time interval. In addition, each core 104 includes an energy monitor 1144 that samples the VINSTPWR signal 1154 signal and accumulates the energy value consumed by the VCORE signal 156 signal each time the energy monitor 1144 reads the signal. The accumulated energy can be read by the microcode 127 as the value of the PKGENERGY signal 1162.

The circuitry external to component 102 includes a resistor (R) coupled in series with the output of VRM 108 to VCORE signal 156 and an amplifier 1102 (DIFF. AMP.) across the two ends of resistor (R) to produce a VINTTCUR Signal 1152. The VINSTCUR signal 1152 is an analog voltage signal whose value is proportional to the instantaneous current supplied to the component 102 via the VCORE signal 156. A class multiplier 1104 (MUL) also receives the VCORE signal 156 and multiplies it by the VINSTCUR signal 1152 to generate the VINSTPWR signal 1154. The VINSTPWR signal 1154 is an analog voltage whose value is proportional to the instantaneous power supplied to the component 102 via the VCORE signal 156. The energy monitor 1144 converts the VINSTPWR signal 1154 into a digital signal PKGENERGY signal 1162 in each core 104. The energy monitor 1144 includes a status register, and the microcode 127 can read the value of the PKGENERGY signal 1162 from the status register. PKGENERGY signal 1162 indicates the energy value provided to VCORE signal 156 since the last read of energy monitor 1144. Thus, each time the microcode 127 reads the value of the PKGENERGY signal 1162 from the energy monitor 1144, the energy monitor 1144 resets the energy value to 0 and begins to accumulate a new energy value consumed by the component 102 until the next microcode. 127 reads the value of PKGENERGY signal 1162. The energy monitor 1144 converts the analog voltage value of the VINSTPWR signal 1154 to the instantaneous power value supplied to the component 102 by dividing by the value of the resistor R (and multiplying by a fractional constant when the parallel amplifier is amplified by the VINTTCUR signal 1152). .

Figure 12 is a flow chart showing the operation of the computer system 100 in accordance with the eleventh embodiment of the present invention. The flow of Figure 12 is similar to Figure 4. Additionally, in FIG. 12, the flow proceeds from step 412 to a new step 1216.

In step 1216, the microcode 127 of each core 104 writes the value of the respective energy monitor 1144 to the control register to set and initiate the energy consumption of the energy monitor 1144 accumulation component 102. The process ends at step 1216.

Figure 13 is a flow chart showing the operation of the computer system 100 in accordance with the eleventh embodiment of the present invention. The flow of Figure 13 is similar to Figure 5B. In addition, the difference of the flow of FIG. 13 and FIG. 5B will be described in detail below.

Figure 13 does not show steps 566, 574 and 584, so the flow begins directly from the branch "YES" of steps 564 to 568; the flow begins directly from the branch "YES" of steps 572 to 576; The branch "Yes" from step 576 to step 586 is started. In addition, FIG. 13 replaces steps 548, 552, 556, and 562 of the original FIG. 5 with steps 1348, 1352, 1356, and 1362. Finally, steps 554 and 558 are not depicted in FIG. 13 but are not substituted; therefore, the flow proceeds directly from step 1352 to step 1356 and from step 1356 directly to step 1362.

If, in step 546, the microcode 127 determines that the sleep time calculated in step 544 is greater than the time interval, the flow proceeds to a new step 1348.

In step 1348, the microcode 127 reads the value of the PKGENERGY signal 1162 from the energy monitor 1144. The flow proceeds to a new step 1352.

In step 1352, the microcode 127 is in the time interval, and when the core 104 is in the sleep state, the component consumed by the component 102 is calculated based on the value of the PKGENERGY signal 1162 obtained in step 1348 and the sleep time obtained in step 542. Time interval energy (component time interval energy). In one embodiment, the values of the time interval and the sleep time are in units of one of the bus time clocks 146, and the component time interval energy value is calculated as the PKGENERGY value, and the fractional molecular system is the time interval and the denominator. For sleep time. Flow proceeds from step 1352 to step 1356.

In step 1356, when the time of the core 104 is in a dormant state, the microcode 127 divides the component time interval energy determined in step 1352 by the quotient of the number of divisions as the partition component 102. The energy consumed. The flow proceeds from step 1356 to 1356 to step 1362.

In step 1362, the microcode 127 fills in the energy of the bin component 102 calculated in step 1356 into all of the binned items in the queue. The process ends at step 1362.

Figure 14 is a flow chart showing the operation of the subprogram Z by the computer system 100 according to Fig. 11 of the present invention. Figure 14 is the same as Figure 6, except that the 14th does not include step 602, so the flow begins at step 604. Therefore, another embodiment shown in Fig. 14 does not use the dynamic power factor of the embodiment of Fig. 1. Since the actual instantaneous power value is provided to the core 104 via the VINSTPWR signal 1154, this embodiment does not require a dynamic power factor.

Fig. 15 is a flow chart showing the operation of the subroutine V by the computer system 100 according to Fig. 11 of the present invention. Flow begins in step 702, which is similar to step 702 shown in FIG. The flow proceeds to step 1512.

In step 1512, the microcode 127 reads the value of the PKGENERGY signal 1162 from the energy monitor 1144 to determine the energy value consumed by the component 102 in the last update. The flow proceeds to step 1516.

At step 1516, the microcode 127 reduces the current binning energy by the value of the PKGENERGY signal 1162 obtained in step 1512. Advantageously, since the number of divisions is relatively large (in one embodiment, the number of divisions is 128), the inaccurate voltage in the value can be attributed to the fact that the quantization of the time interval (T) is generally relatively small (nearly 1). %). The flow proceeds to step 1518.

In step 1518, the microcode 127 reduces the component time interval energy by the value of the PKGENERGY signal 1162 obtained in step 1512. The process ends at step 1518.

Figure 16 is a flow chart showing the operation of the subroutine X by the computer system 100 in accordance with the eleventh embodiment of the present invention. Fig. 16 is the same as Fig. 8, except that Fig. 16 does not include step 806; therefore, the flow starts directly from the branch "No" of steps 804 to 808. Therefore, another embodiment shown in Fig. 16 does not require the calculation of the component time interval energy of the embodiment as in Fig. 1. This is because the component time interval energy is maintained by the PKGENERGY signal 1162 at each time read from the energy monitor 1144. Furthermore, it is worth noting that another embodiment as shown in FIG. 11 does not require a subroutine W because the component time interval energy is maintained by the PKGENERGY signal 1162 read from each time of the energy monitor 1144. .

Figure 17 is a flow chart showing the operation of the subprogram Y in accordance with the computer system 100 of Fig. 1 of the present invention. Fig. 17 is similar to Fig. 10 except for the following differences.

Figure 17 does not include step 1006; therefore, the flow begins directly from the branch "No" of steps 1004 through 1008. Therefore, another embodiment shown in Fig. 17 does not require the calculation of the component time interval energy of the embodiment as in Fig. 1. This is because the component time interval energy is maintained by the PKGENERGY signal 1162 at each time read from the energy monitor 1144.

In addition, step 1016 of FIG. 10 is replaced by step 1716 shown in FIG. 17, so that the flow proceeds directly from steps 1014 and 1024 to step 1716.

In step 1716, the microcode 127 reduces the component time interval energy by the particular energy of the oldest binning item in the queue. Therefore, the component time interval energy can be more efficiently calculated by the operation of step 1716 in step 1518 of FIG. 15 and FIG. 17 as compared to the sum of all the energy of the division. Figure 7 does not include step 1018; therefore, the flow proceeds directly from step 1716 to step 1022.

Figure 18 is a block diagram of a computer system 100 including a dual core microprocessor assembly 102 in accordance with another embodiment of the present invention including a power evaluation value characteristic. The computer system 100 shown in Fig. 18 is similar to the computer system 100 shown in Fig. 11. In addition, the computer system 100 shown in Fig. 18 does not include the analog multiplier 1104 of Fig. 4. Instead, the energy monitor 1144 performs the work of the analog multiplier. Therefore, the energy monitor 1144 receives each VINVTCUR signal 1152 and the VCORE signal 156.

The various advantageous effects of the present embodiment will be described in detail below. First, one of the enabling cores is the core of making two matches with another core to transmit power information, and directly locating the signal line between the two cores so that the two cores can communicate with each other. In addition, another advantage of the present embodiment is that the cores can communicate with each other via the memory, so there is no need to manufacture a matching complex core, but it is necessary to separately manufacture and then package. Thus, the implementation of the present invention may have a higher yield than the method of manufacturing a matching core.

Secondly, the core of the embodiment uses memory for communication of power information. Compared with the core of direct communication through the signal line, the scale of this embodiment can be better than two cores, due to the number of signal lines. It will increase exponentially based on the number of cores.

Third, an advantage of embodiments of the power evaluation value feature is that it allows a user/system with a good temperature environment/solution to enjoy the user/system without other good temperature environments/solutions. Extra high performance.

Fourth, some instructions (for example, transcendental function instructions or modulo multiply instructions with extremely large operands) may have relatively long execution times, possibly A time or a time between time T. According to the embodiment of the present invention, a core can determine whether the necessary power evaluation value is a component of the current project and according to the performance of the adjustment itself, the embodiment of the present invention can be operated properly under a long command at the time. The event, even if other cores are unable to respond to the interruption of their bus timing timer.

Fifth, as previously mentioned, all cores can operate at frequencies above Xp with sufficient power evaluation values.

While the embodiments of the present invention have been described in terms of the objects, features and advantages thereof, other embodiments are also contemplated by the present invention. For example, although the instantaneous power indicator of the embodiment of the present invention is provided by the external circuitry of the components of the multi-core architecture shown in Figures 11 and 18, a single core component is also within the scope of the present invention. Furthermore, although the present invention has shown that the values represented by dynamics and leakage energy are maintained separately, it is contemplated in other embodiments to maintain a single representative energy value. In addition, in other embodiments, the signal VINSTPWR signal 1154 or the signal VINTTCUR signal 1152 is provided directly to the component 102 by the voltage regulation module 108 or by a power supply. Finally, while embodiments of the present invention have illustrated that power evaluation value characteristics are heavily used for microcode, other embodiments also consider the use of power evaluation value characteristics in large numbers for hardware logic or a combination of microcode and hardware logic.

Various embodiments of the invention have been described herein, but those skilled in the art should understand that these embodiments are only by way of example and not limitation. Variations in form and detail may be made by those skilled in the art without departing from the spirit of the invention. For example, the software can enable the functions, fabrication, modeling, simulation, description, and/or testing of the apparatus and method described in the embodiments of the present invention, and can also be through a general programming language (C, C++), Hardware Description Languages (HDL) (including Verilog HDL, VHDL, etc.), or other available programming languages. The software can be configured on any known computer usable medium such as tape, semiconductor, disk, or optical disc (eg CD-ROM, DVD-ROM, etc.), internet, wired, wireless, or other communication medium. Among the transmission methods. The apparatus and method embodiments of the present invention can be included in a semiconductor intellectual property core, such as a microprocessor core (implemented in HDL), and converted into hardware of an integrated circuit product. Furthermore, the apparatus and method of the present invention are implemented by a combination of a hardware and a soft body. Therefore, the invention should not be limited to the disclosed embodiments, but is defined by the scope of the appended claims. In particular, the present invention can be implemented in a microprocessor device for use in a general purpose computer. In the following, the present invention is not limited to the scope of the present invention, and any one of ordinary skill in the art can make a slight difference without departing from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims.

100. . . computer system

108. . . Voltage regulation module

158. . . VID signal

156. . . VCORE signal

104A. . . Core 0

104B. . . Core 1

102. . . Component

129. . . Power evaluation value register

126. . . Phase-locked loop

128. . . Temperature sensor

127. . . Microcode

124. . . Resident timer

122. . . Bus timing timer

146. . . Bus time

154. . . Busbar

106. . . Memory

138. . . Power Information Sharing Area (PISA)

132A, 132B. . . Power information

114. . . Dynamic energy

116. . . Leakage energy

202. . . SMM memory space

1102. . . Amplifier

1152. . . VINSTCUR signal

1104. . . Analog multiplier

1154. . . VINSTPWR signal

1144. . . Energy monitor

1162. . . PKGENERGY signal

1 is a block diagram of a computer system described in the present invention;

Figure 2 is a block diagram of a power information sharing area in the memory of the computer system of Figure 1;

Figure 3 is a flow chart showing the operation of the assembly according to Figure 1 of the present invention;

Figure 4 is a flow chart showing the operation of the computer system according to the first embodiment of the present invention;

5A and 5B are flowcharts of operations performed by the computer system according to the first embodiment of the present invention;

Figure 6 is a flow chart showing the operation of the sub-program Z in accordance with the computer system of Figure 1 of the present invention;

Figure 7 is a flow chart showing the operation of the sub-program V in accordance with the computer system of Figure 1 of the present invention;

Figure 8 is a flow chart showing the operation of the sub-program X in accordance with the computer system of Figure 1 of the present invention;

Figure 9 is a flow chart showing the operation of the sub-program W in accordance with the computer system of Figure 1 of the present invention;

Figure 10 is a flow chart showing the operation of the sub-program Y in accordance with the computer system of Figure 1 of the present invention;

Figure 11 is a block diagram of a computer system including a dual core microprocessor assembly in accordance with another embodiment of the present invention;

Figure 12 is a flow chart showing the operation of the computer system according to the eleventh embodiment of the present invention;

Figure 13 is a flow chart showing the operation of the computer system according to the eleventh embodiment of the present invention;

Figure 14 is a flow chart showing the operation of the sub-program Z in accordance with the computer system of Figure 11 of the present invention;

Figure 15 is a flow chart showing the operation of the sub-program V in accordance with the computer system of Figure 11 of the present invention;

Figure 16 is a flow chart showing the operation of the sub-program X in accordance with the computer system of Figure 11 of the present invention;

Figure 17 is a flow chart showing the operation of the sub-program Y in accordance with the computer system of Figure 1 of the present invention;

Figure 18 is a block diagram of a computer system 100 including a dual core microprocessor assembly in accordance with another embodiment of the present invention.

100. . . computer system

108. . . Voltage regulation module

158. . . VID signal

156. . . VCORE signal

104A. . . Core 0

104B. . . Core 1

102. . . Component

129. . . Power evaluation value register

126. . . Phase-locked loop

128. . . Temperature sensor

127. . . Microcode

124. . . Resident timer

122. . . Bus timing timer

146. . . Bus time

154. . . Busbar

106. . . Memory

138. . . Power Information Sharing Area (PISA)

132A. . . Power information

132B. . . Power information

114. . . Dynamic energy

116. . . Leakage energy

Claims (36)

A microprocessor for operating in a system having a memory, the microprocessor comprising: a complex processing core, wherein each processing core of the processing core is configured to: operate at an adjustable operating frequency; When a power event occurs, a first value is calculated, wherein the first value represents an energy value consumed by the processing core in a time interval of the power event, wherein the length of the time interval is a predetermined time value Reading one or more second values from the memory, wherein the or the second value represents an energy value consumed by the other of the processing cores in the time interval, wherein the second or second The value has been previously calculated and written to the memory by the other of the processing cores; and the operating frequency of the processing core is adjusted based on the first value and the second value. The microprocessor of claim 1, wherein each processing core sets the operation of the processing core only when the predetermined condition exists according to the first value and the second value. The frequency is higher than a predetermined frequency to adjust the operating frequency. The microprocessor of claim 2, wherein the predetermined frequency is such that the processing core of the microprocessor can maintain operation if the microprocessor consumes no more than a predetermined energy value. At one of the established time values. The microprocessor of claim 2, wherein the predetermined frequency is a maximum frequency at which the system software can request one of the processing core operations. The microprocessor of claim 2, wherein each processing core further comprises: calculating a third value by using the first value and the second value, wherein the third value represents The amount of energy consumed by the microprocessor during this time interval. The microprocessor of claim 5, wherein if the third value is less than a fourth value, the predetermined condition is established according to the first value and the second value, wherein the length is In any time interval of the predetermined time value, the fourth value represents a predetermined maximum value of one of the allowable consumptions of the microprocessor in the system. The microprocessor of claim 2, wherein if the sum of the first value and the second value is less than a fourth value, according to the first value and the second or second The established condition of the value is established, wherein in any of the time intervals having a length of the predetermined time value, the fourth value represents a predetermined maximum value of one of the allowable consumptions of the processing cores in the system. The microprocessor of claim 2, wherein, if the predetermined condition is not satisfied, each processing core is further configured to set the operating frequency of the processing core at the predetermined frequency or lower than the predetermined frequency. Adjust the frequency of this operation. The microprocessor of claim 1, wherein each processing core is further configured to: write the first value to the memory to provide the processing core Others use it. The microprocessor of claim 1, wherein the first value and the second value comprise a dynamic energy component and a leakage energy component. The microprocessor of claim 1, wherein each processing core is configured to read the second value or the second value from a location in the memory, and further comprising: Before the second value is read from the memory, an address of the location in the memory is received. The microprocessor of claim 11, wherein each processing core is configured to receive the address of the location in response to the system software writing the address to the processing core. The microprocessor of claim 11, wherein the address of the location of the memory is stored in a system management mode (SMM) area of the memory. The microprocessor of claim 1, wherein each processing core comprises microcode for calculating the first value, reading the second value or the second value, and adjusting the operating frequency. The microprocessor of claim 1, wherein the power event comprises an event from a list comprising: a timer from a timer for indicating a period of time exceeding a predetermined time period, and a method for causing the processing core to sleep It is required that the processing core resumes operation from the sleep state and a request to update the operating frequency of the processing core. The microprocessor of claim 15, wherein the predetermined time period is less than two orders of magnitude of the predetermined time value. The microprocessor of claim 15, wherein the sleep state comprises a state in which a clock signal is removed from a majority of the processing core. A method of operating a microprocessor, comprising a plurality of processing cores in a system having a memory, each of the processing cores being operative to adjust an operating frequency, wherein the memory is accessible by the processing cores, The method includes: when detecting a power event, calculating a first value by the processing core, wherein the first value represents an energy value consumed by the processing core in a time interval of the power event, wherein The length of the time interval is a predetermined time value; the processing core reads one or more second values from the memory, wherein the second value or the second values represent the processing cores in the time interval The energy value consumed by the other, wherein the or the second value has been previously calculated by the other of the processing cores and written to the memory; and the processing core is based on the first value and the The second values adjust the operating frequency of the processing core. The method of operating a microprocessor according to claim 18, wherein the operating frequency of the processing core is set only when the predetermined condition exists according to the first value and the second value. Higher than a predetermined frequency to adjust the operating frequency. The method of operating a microprocessor according to claim 19, wherein the predetermined frequency is such that the processing core of the microprocessor is performed when the microprocessor consumes no more than a predetermined energy value. The frequency of operation at one of the established time values can be maintained. The method of operating a microprocessor of claim 19, wherein the predetermined frequency is a maximum frequency at which the system software can request one of the processing core operations. The method of operating a microprocessor according to claim 19, further comprising: calculating, by the processing core, the third value by using the first value and the second value, wherein the third value is about Represents the amount of energy consumed by the microprocessor during this time interval. The method of operating a microprocessor according to claim 22, wherein if the third value is less than a fourth value, the predetermined condition is established according to the first value and the second value, wherein In any time interval having a length of the predetermined time value, the fourth value represents a predetermined maximum value of one of the allowable consumptions of the microprocessor in the system. The method of operating a microprocessor according to claim 22, wherein if the sum of the first value and the second value is less than a fourth value, according to the first value and the The predetermined condition of the second value is established, wherein in any of the time intervals having the length of the predetermined time value, the fourth value represents a predetermined maximum value of one of the allowable consumptions of the processing cores in the system. The method for operating a microprocessor according to claim 19, wherein if the predetermined condition is not satisfied, the operation is adjusted by setting the operating frequency of the processing core at the predetermined frequency or lower than the predetermined frequency. frequency. The method for operating a microprocessor as described in claim 18, further comprising: The first value is written to the memory by the processing core to provide for use by the other of the processing cores. The method of operating a microprocessor of claim 18, wherein the first value and the second value comprise a dynamic energy component and a leakage energy component. The method of operating a microprocessor of claim 18, wherein the reading the second value from the memory comprises reading the second value from a location in the memory And further comprising: receiving, by the processing core, an address of the location in the memory before the second value is read from the memory. A method of operating a microprocessor as claimed in claim 28, wherein the address of the location is received in response to the system software writing the address to the processing core. The method of operating a microprocessor according to claim 28, wherein the address of the location of the memory is stored in a system management mode (SMM) area of the memory. The method of operating a microprocessor of claim 18, wherein the computing, reading, and adjusting are performed by the microcode of the processing core. The method of operating a microprocessor of claim 18, wherein the power event comprises an event from a list comprising: a timer from a timer to indicate an indicator for more than a predetermined period of time, and a method for causing the processing The core sleep requirement, the processing core returns from the sleep state operation, and a request to update the operating frequency of the processing core. The method of operating a microprocessor of claim 32, wherein the predetermined time period is less than two orders of magnitude of the predetermined time value. The method of operating a microprocessor according to claim 32, wherein the sleep state comprises a state in which a clock signal is removed from a majority of the processing core. A computer program product embedding at least one non-volatile computer readable storage medium in a computer device, the computer program product comprising: embedding a computer readable program code in the computer readable storage medium to specify a micro The processor is configured to operate in a system having a memory, the computer readable code comprising: a code specifying a complex processing core, wherein each processing core of the complex processing core is configured to: operate on one of an adjustable operation Frequency; when a power event is detected, calculating a first value, wherein the first value represents an energy value consumed by the processing core in a time interval of the power event, wherein the length of the time interval is one a predetermined time value; reading one or more second values from the memory, wherein the or the second value represents an energy value consumed by the other of the processing cores in the time interval, wherein the or Waiting for the second value to be previously calculated by the other of the processing cores and written to the memory; and adjusting the processing core based on the first value and the second value The operating frequency. The computer program product of claim 35, wherein the at least non-volatile computer readable storage medium is a compact disc, a magnetic tape, or other magnetic, optical, or electronic storage medium and a network. Cable, wireless or other non-volatile communication media.