TWI442707B - Clock generating device - Google Patents

Description

Clock generating device

The present invention relates to a clock generating apparatus, and more particularly to a clock generating apparatus in which an oscillation frequency is not affected by temperature.

In the circuit design rule, the clock signal is usually designed to control the timing of the signals processed by each circuit to prevent malfunction due to signal unsynchronization. For example, the application of the clock signal may include a start trigger, a reset setting, a reference signal, and the like. Therefore, in IC design, the clock signal is usually required as the basis for the action. At this time, a crystal, an oscillator, or a clock generating device is usually provided outside the IC as a source of the clock signal.

In addition, due to the development of technology, the density of electronic components in ICs is also increasing. Therefore, when some precision electronic devices operate, a large amount of heat is generated inside, which causes the internal temperature to increase. At this time, if the clock generating device is affected by the internal temperature and the oscillation frequency of the clock signal is changed, the operation of the precision electronic device may be affected, thereby causing unpredictable consequences. Therefore, if the clock generating device is less affected by temperature, the operation of the precision electronic device is less affected by temperature.

The present invention provides a clock generating apparatus whose oscillation frequency of a clock signal is not affected by temperature.

The invention provides a clock generating device comprising a fixed current generating unit, a control circuit and a charge pump circuit. The fixed current generating unit is configured to generate a current. A control circuit has a first end and a second end. The first end is connected to the fixed current generating unit for receiving the current of the first part, and the second end of the control circuit is for outputting the clock signal. The charge pump circuit is coupled to the second end of the control circuit, and between the fixed current generating unit and the first end of the control circuit, and the charge pump circuit receives the second portion of the current, the reference voltage, and the clock signal. Wherein, when the current value of the first portion is not zero, the frequency of the clock signal changes due to the current of the first portion. When the current value of the first part is zero, the frequency of the clock signal is a fixed value, and the current of the second part is equal to the current.

In an embodiment of the invention, the control circuit includes an integration circuit and a voltage controlled oscillator. The integrating circuit is configured to receive the current of the first portion and generate a control voltage. The voltage controlled oscillator is coupled to the integrating circuit to generate a clock signal having a frequency according to the control voltage.

In an embodiment of the invention, the current generated by the fixed current generating unit is a current of a zero temperature coefficient.

In an embodiment of the invention, the fixed current generating unit includes a positive temperature coefficient circuit and a negative temperature coefficient circuit, and the absolute value of the temperature coefficient of the positive temperature coefficient circuit and the absolute value of the temperature coefficient of the negative temperature coefficient circuit the same.

The invention also provides a clock generation device comprising a first node, a current generating unit, an integrating circuit, a voltage controlled oscillator and a charge pump circuit. The electric current generating unit is configured to generate a fixed current having a zero temperature coefficient to the first node. The integrating circuit is coupled to the first node for outputting a control voltage based on the current received from the first node. The voltage controlled oscillator is connected to the integrating circuit to output a clock signal according to the control voltage. The charge pump circuit receives a reference voltage and connects the first node and the voltage controlled oscillator to receive the sink current from the first node according to the reference voltage and the pulse signal. Wherein, when the current pulse generating device is stable, the sinking current is equal to the fixed current.

In an embodiment of the invention, the current generating unit includes a zero temperature coefficient current generating circuit and a mirror current unit. A zero temperature coefficient current generating circuit is used to output a bias voltage. The mirror current unit is connected to a zero temperature coefficient current generating circuit that outputs a fixed current according to the bias voltage.

In an embodiment of the invention, the mirror current unit includes at least one first P-type field effect transistor, the gate of the first P-type field effect transistor receives the bias voltage and receives a system at the first source/汲 terminal Voltage and output a fixed current at the second source/汲 terminal.

In an embodiment of the invention, the zero temperature coefficient current generating circuit includes a second P-type field effect transistor, a third P-type field effect transistor, a first operational amplifier, a first PNP dual carrier transistor, and a first A two-PNP bipolar transistor, a first resistor, a second resistor, and a third resistor. The second P-type field effect transistor receives the system voltage. The first source/汲 terminal of the third P-type field effect transistor receives the system voltage, and its gate is connected to the gate of the second P-type field effect transistor. The first operational amplifier is configured to output a bias voltage, and the output end of the first operational amplifier is connected to the gate of the second P-type field effect transistor, wherein the negative input terminal and the positive input terminal of the first operational amplifier are respectively connected to the second P The field effect transistor is connected to the second source/汲 terminal of the third P-type field effect transistor. The emitter of the first PNP bipolar transistor is connected to the second source/汲 terminal of the second P-type field effect transistor, and the collector and the base of the first PNP bipolar transistor are connected to a ground. The collector and base of the second PNP bipolar transistor are connected to the ground. The first resistor is coupled between the second source/deuterium terminal of the second P-type field effect transistor and the ground. The second resistor is coupled between the second source/汲 terminal of the third P-type field effect transistor and the emitter of the second PNP bipolar transistor. The third resistor is connected between the second source/汲 terminal of the third P-type field effect transistor and the ground.

In an embodiment of the invention, the voltage controlled oscillator is an LC voltage controlled oscillator, an RC voltage controlled oscillator or a transistor voltage controlled oscillator.

In an embodiment of the invention, the charge pump circuit includes a second operational amplifier, a third operational amplifier, a first capacitor, a first switch, a second switch, a third switch, and a fourth switch. The positive input of the second operational amplifier is connected to the reference voltage, and the negative input of the second operational amplifier is connected to the output of the second operational amplifier. The positive input of the third operational amplifier is connected to the first node to receive the sink current, and the negative input of the third operational amplifier is connected to the output of the third operational amplifier. The first switch is coupled between the first end of the first capacitor and the output of the second operational amplifier. The second switch is coupled between the first end of the first capacitor and the first voltage. The third switch is coupled between the second end of the first capacitor and the output of the third operational amplifier. The fourth switch is coupled between the second end of the first capacitor and the positive input of the third operational amplifier. Wherein, when the first switch and the third switch are turned on when the clock signal is at the first level, and the second switch and the fourth switch are turned on when the clock signal is at the second level, the first level is different from the second level .

In an embodiment of the invention, the first voltage is a ground terminal.

In an embodiment of the invention, the first voltage is a system voltage.

In an embodiment of the invention, the frequency of the clock signal is proportional to the voltage level of the control voltage.

In an embodiment of the invention, the magnitude of the current sinking current is proportional to the voltage level of the reference voltage and the frequency of the pulse signal.

Based on the above, the clock generating device of the present invention, when stabilized, the fixed current of the current generating unit is equal to the sink current received by the charge pump circuit, and the integrating circuit provides a stable control voltage to stabilize the frequency of the clock signal. . Thereby, since the fixed current is not affected by the temperature, the frequency of the clock signal is not affected by the temperature.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a system diagram of a clock generation device in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the clock generating apparatus 100 includes a first node A, a current generating unit 110, an integrating circuit 120, a voltage controlled oscillator 130, and a charge pump circuit 140. The voltage controlled oscillator is, for example, LC voltage controlled oscillator, RC voltage controlled oscillator, transistor voltage controlled oscillator or other type of voltage controlled oscillator. The current generating unit 110 is configured to output a fixed current If that is not affected by temperature (equivalent to having a zero temperature coefficient) to the first node A.

The integrating circuit 120 is connected to the first node A for outputting the control voltage Vctrl according to the current received from the first node A. The voltage controlled oscillator 130 is connected to the integrating circuit 120 to output the clock signal CLK in accordance with the control voltage Vctrl. The charge pump circuit 140 receives the reference voltage VR and connects the first node A and the voltage controlled oscillator 130 to receive the sink current Is from the first node A according to the reference voltage VR and the pulse signal CLK. When the pulse generating device 100 is stable, the sinking current Is will be equal to the fixed current If. The integrating circuit 120 and the voltage controlled oscillator 130 can be regarded as a control circuit, and the integrating circuit 120 can serve as a first end of the control circuit to receive current from the first node A, and the output of the voltage controlled oscillator 130 can be used as The second end of the control circuit outputs a clock signal CLK.

Further, when the pulse generating device 100 starts operating, the current generating unit 110 supplies the fixed current If to the first node A, and the current flowing from the first node A to the integrating circuit 120 (ie, the first portion of the fixed current If) The portion of the sink current Is (i.e., the fixed current If of the second portion) is subtracted for the fixed current If, and the integrating circuit 120 outputs the control voltage Vctrl in accordance with the received current. The voltage controlled oscillator 130 determines the frequency of the clock signal CLK according to the voltage level of the control voltage Vctrl, wherein the frequency of the clock signal CLK is proportional to the voltage level of the control voltage Vctrl. The charge pump circuit 140 determines the magnitude of the received sink current Is according to the frequency of the reference voltage VR and the pulse signal CLK, wherein the current of the sink current Is is proportional to the voltage level of the reference voltage VR and the frequency of the pulse signal CLK.

According to the above, when the pulse generation device 100 is not stabilized, the sink current Is may be smaller or larger than the fixed current If, and the current received by the integration circuit 120 from the first node A is not zero. When the sink current Is is smaller than the fixed current If, the voltage level of the control voltage Vctrl rises, and the frequency of the clock signal CLK rises, so that the sink current Is rises. When the sink current Is is greater than the fixed current If, the voltage level of the control voltage Vctrl drops, and the frequency of the clock signal CLK decreases, so that the sink current Is decreases. Thereby, when the clock generating device 100 is stable, the sinking current Is converges to be equal to the fixed current If, that is, the current received by the integrating circuit 120 from the first node A is zero, so that the voltage level of the control voltage Vctrl is zero. The frequency of the timely pulse signal CLK will remain fixed. Also, since the fixed current If is not affected by the temperature, the frequency of the clock signal CLK is not affected by the temperature.

On the other hand, if the current of the fixed current If is set to a higher current, the current of the sinking current Is will be increased synchronously, so that the frequency of the clock signal CLK is also increased; if the fixed current If When the current is set to a lower current, the current of the sinking current Is is stabilized at the same time, so that the frequency of the clock signal CLK is also lowered. In other words, the frequency of the clock signal CLK is proportional to the magnitude of the current of the fixed current If.

In addition, since the current of the sink current Is is controlled by the frequency of the clock signal CLK, the sink current Is will be converged from high to equal to the fixed current If or from low to equal to the fixed current If is determined by the frequency of the clock signal CLK. The direction of convergence. In other words, when the circuit structure of the voltage controlled oscillator 130 causes the frequency of the clock signal CLK to converge from high to a stable frequency, the sink current Is will converge from high to equal to the fixed current If; when the voltage of the voltage controlled oscillator 130 When the structure causes the frequency of the clock signal CLK to converge from a low to a stable frequency, the sink current Is will converge from low to equal to the fixed current If.

2 is a schematic diagram of the system of the current generating unit of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the present embodiment, the current generating unit 110' includes a zero temperature coefficient current generating circuit 210 and a mirror current unit 220. In this embodiment, the mirror current unit 220 is at least one P-type field effect transistor PM1. The zero temperature coefficient current generating circuit 210 is for outputting a bias voltage Vb that varies with temperature. The mirror current unit 220 is connected to the zero temperature coefficient current generating circuit 210 to output a fixed current If in accordance with the bias voltage Vb. In other words, the gate of each P-type field effect transistor PM1 receives the bias voltage Vb, and the source of each P-type field effect transistor PM1 (ie, the first source/汲 terminal) receives the system voltage VDD, and these P-type fields The drain of the effect transistor PM1 (ie, the second source/汲 terminal) outputs a fixed current If.

Further, since the gates of each of the P-type field effect transistors PM1 receive the bias voltage Vb, the drain current Id1 of each of the P-type field effect transistors PM1 will be the same. The fixed current If is the sum of the drain current Id1 of each P-type field effect transistor PM1, that is, the fixed current If is the drain current Id1 of each P-type field effect transistor PM1 multiplied by the P-type field effect power. The number of crystals PM1. Moreover, since the bias voltage Vb changes the gate voltage of the P-type field effect transistor PM1 with temperature, the gate current Id1 affected by the temperature of the P-type field effect transistor PM1 is maintained by the change of the gate voltage thereof. Change (ie, not affected by temperature), so the fixed current If is also unaffected by temperature.

3 is a circuit diagram of a zero temperature coefficient current generating circuit according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3, in the embodiment, the zero temperature coefficient current generating circuit 210 includes P-type field effect transistors PM2, PM3, operational amplifiers OP1, PNP bipolar transistors PBT1, PBT2, and resistors R1, R2. , R3. The source of the P-type field effect transistor PM2 receives the system voltage VDD. The source of the P-type field effect transistor PM3 receives the system voltage VDD, and the gate of the P-type field effect transistor PM3 is connected to the gate of the P-type field effect transistor PM2. The output terminal of the operational amplifier OP1 is connected to the gates of the P-type field effect transistors PM2 and PM3 and outputs the bias voltage Vb. The negative input terminal of the operational amplifier OP1 is connected to the drain of the P-type field effect transistor PM2, and the positive input terminal of the operational amplifier OP1. Connect the drain of the P-type field effect transistor PM3.

The emitter of the PNP bipolar transistor PBT1 is connected to the drain of the P-type field effect transistor PM2, and the collector and base of the PNP bipolar transistor are connected to the ground. The collector and base of the PNP bipolar transistor PBT2 are connected to the ground. The resistor R1 is connected between the drain of the P-type field effect transistor PM2 and the ground. The resistor R2 is connected between the drain of the P-type field effect transistor PM3 and the emitter of the PNP bipolar transistor PBT2. The resistor R3 is connected between the drain of the P-type field effect transistor PM3 and the ground.

According to the circuit operation, the connection relationship between the P-type field effect transistors PM2 and PM3 is the same current mirror, and the gate of the P-type field effect transistor PM1 receives the bias voltage Vb outputted by the operational amplifier OP1, so the P-type field effect transistor The circuit operation of PM1 and PM2 and PM3 will also be equivalent to the current mirror. That is, the drain current of the P-type field effect transistor PM2 is Id2=the gate current of the P-type field effect transistor PM3 is Id3=P type field effect transistor PM1 The fixed current of the bungee output is If. Further, the drain current Id3 = the current Ir1 flowing through the resistor R2 + the current Ir2 flowing through the resistor R3. Furthermore, since Ir1 is a positive temperature coefficient (PTAT) current and Ir2 is a negative temperature coefficient (CTAT) current, the drain current Id3 synthesized by the currents Ir1 and Ir2 can be regarded as a temperature-independent current, resulting in a drain The current Id2 and the fixed current If can be regarded as temperature independent currents.

4 is a circuit diagram of the current generating unit of FIG. 1 according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 4, in the present embodiment, the current generating unit 110" includes impedance units 410 and 420. The impedance unit 410 is connected to the system voltage VDD, and the impedance unit 420 is connected in series to the impedance unit 410 and outputs a fixed current If. Therefore, the impedance value of the impedance unit 410 has a positive temperature coefficient, that is, the higher the temperature, the higher the impedance value of the impedance unit 410, and the lower the temperature, the lower the impedance value of the impedance unit 410, and the impedance value of the impedance unit 420. There is a low temperature coefficient. Therefore, the fixed current If outputted by the impedance unit 420 is mutually compensated by the temperature coefficients of the impedance units 410 and 420, so that the fixed current If is not affected by the temperature, wherein the impedance unit 410 can be regarded as a positive The temperature coefficient circuit, the impedance unit 420 can be regarded as a negative temperature coefficient circuit, and, in an optimum state, the absolute value of the temperature coefficient of the impedance unit 410 is similar or even the same as the absolute value of the temperature coefficient of the impedance unit 420.

Further, the impedance unit 410 may include a resistor R4 connected between the system voltage VDD and the impedance unit 420. The impedance unit 420 may include a PNP bipolar transistor PBT3, an emitter connection impedance unit 410 of the PNP bipolar transistor PBT3, and a base of the PNP bipolar transistor PBT3 connected to the collector of the PNP bipolar transistor PBT3. And the collector of the PNP bipolar transistor PBT3 is connected to the first node A to output a fixed current If. In the present embodiment, the impedance unit 410 having a positive temperature coefficient is realized through the resistor R4, and the impedance unit 420 having a negative temperature coefficient is realized through the P/N interface of the emitter and the base in the PNP bipolar transistor PBT3, but It is not limited to this in other embodiments, and can be designed by a person skilled in the art.

FIG. 5 is a circuit diagram of the current generating unit of FIG. 1 according to still another embodiment of the present invention. Referring to FIG. 1, FIG. 4 and FIG. 5, in the present embodiment, the current generating unit 110''' includes a P-type field effect transistor PM4, at least one P-type field effect transistor PM5, and impedance units 510 and 520. The impedance units 510 and 520 operate similarly to the impedance units 410 and 420, and the impedance unit 510 includes a resistor R4. The impedance unit 520 includes a PNP bipolar transistor PBT4, and the difference is that the impedance unit 520 is connected to the impedance unit. Between 510 and ground.

According to the above, due to the different temperature coefficients of the impedance units 510 and 520, the drain current Id4 of the P-type field effect transistor PM4 can be regarded as a current that is not affected by temperature, and under the action of the current mirror, the P-type field effect power The drain current Id5 of the crystal PM5 can also be regarded as a current that is not affected by temperature. The fixed current If is the number of times the drain current Id5 of each P-type field effect transistor PM5 is multiplied by the P-type field effect transistor PM5.

6 is a circuit diagram of the integration circuit of FIG. 1 in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 6, in the embodiment, the integration circuit 120 includes a resistor R6 and a capacitor C1. The resistor R6 is connected between the first node A and the voltage controlled oscillator 130, and outputs a control voltage Vctrl. The capacitor C1 is connected between the voltage controlled oscillator 130 and the ground. Here, when current flows into the integrating circuit 120, the capacitor C1 is charged so that the control voltage Vctrl rises; when the current flows out of the integrating circuit 120, the capacitor C1 is discharged so that the control voltage Vctrl is lowered.

FIG. 7 is a circuit diagram of the charge pump circuit of FIG. 1 according to an embodiment of the invention. Referring to FIG. 7, in the present embodiment, the charge pump circuit 140 includes operational amplifiers OP2, OP3, switches SW1, SW2, SW3, SW4 and a capacitor C2. The positive input terminal of the operational amplifier OP2 is connected to the reference voltage VR, and the negative input terminal of the operational amplifier OP2 is connected to the output terminal of the operational amplifier OP2. The positive input terminal of the operational amplifier OP3 is connected to the first node A to receive the sink current Is, and the negative input terminal of the operational amplifier OP3 is connected to the output terminal of the operational amplifier OP3.

The switch SW1 is connected between the first terminal C2a of the capacitor C2 and the output terminal of the operational amplifier OP2. The switch SW2 is connected between the first end C2a of the capacitor C2 and the ground (ie, the first voltage). The switch SW3 is connected between the second terminal C2b of the capacitor C2 and the output terminal of the operational amplifier OP3. The switch SW4 is connected between the second terminal C2b of the capacitor C2 and the positive input terminal of the operational amplifier OP3. Here, it is assumed that the switches SW1 and SW3 are turned on when the clock signal CLK is at the high voltage level (ie, the first level), and the switches SW2 and SW4 are turned on when the clock signal CLK is at the low voltage level (ie, the second level). However, other embodiments of the invention are not limited. In addition, in other embodiments, the switch SW2 may also be connected between the first end C2a of the capacitor C2 and the system voltage VDD.

When the clock signal CLK is at a high voltage level, the voltage level of the first terminal C2a of the capacitor C2 is equal to the reference voltage VR, and the voltage level of the second terminal C2b of the capacitor C2 is equal to the voltage of the first node A; When the signal CLK is at the low voltage level, the voltage level of the first terminal C2a of the capacitor C2 is equal to the ground terminal, and the sink current Is flows into the second terminal C2b of the capacitor C2 to charge the capacitor C2. According to the above, the relationship is as follows:

Is=Q _C2 ×F _CLK

Q _C2 = C _C2 × (GND-VR) = -C _C2 × VR

Is=-C _C2 ×VR×F _CLK

Where Q _C2 is the charge amount of the capacitor C2, F _{CLK is} the frequency of the clock signal CLK, GND is the ground terminal, and C _C2 is the capacitance value of the capacitor C2.

In summary, the clock generating device of the embodiment of the present invention, when the current is stable, the fixed current of the current generating unit is equal to the sink current received by the charge pump circuit, and the integrating circuit provides a stable control voltage to make the clock. The frequency of the signal remains stable. Thereby, since the fixed current is not affected by the temperature, the frequency of the clock signal is not affected by the temperature.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Clock generating device

110, 110', 110", 110'''... current generating unit

120. . . Integral circuit

130. . . Voltage controlled oscillator

140. . . Charge pump circuit

210. . . Zero temperature coefficient current generating circuit

220. . . Mirror current unit

410, 420, 510, 520. . . Impedance unit

A. . . First node

C1, C2. . . capacitance

C2a. . . First end

C2b. . . Second end

CLK. . . Clock signal

PM1~PM5. . . P-type field effect transistor

Id1~Id5. . . Bungee current

If. . . Fixed current

Ir1, Ir2. . . Current

Is. . . Sink current

OP1~OP3. . . Operational Amplifier

PBT1~PBT4. . . PNP bipolar transistor

R1~R6. . . resistance

SW1~SW4. . . switch

Vctrl. . . Control voltage

VDD. . . System voltage

Vb. . . bias

VR. . . Reference voltage

1 is a system diagram of a clock generation device in accordance with an embodiment of the present invention.

2 is a schematic diagram of the system of the current generating unit of FIG. 1 according to an embodiment of the invention.

3 is a circuit diagram of a zero temperature coefficient current generating circuit according to an embodiment of the invention.

4 is a circuit diagram of the current generating unit of FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of the current generating unit of FIG. 1 according to still another embodiment of the present invention.

6 is a circuit diagram of the integration circuit of FIG. 1 in accordance with an embodiment of the present invention.

FIG. 7 is a circuit diagram of the charge pump circuit of FIG. 1 according to an embodiment of the invention.

100. . . Clock generating device

110. . . Current generating unit

120. . . Integral circuit

130. . . Voltage controlled oscillator

140. . . Charge pump circuit

A. . . First node

CLK. . . Clock signal

If. . . Fixed current

Is. . . Sink current

Vctrl. . . Control voltage

VR. . . Reference voltage

Claims (14)

A clock generating device includes: a fixed current generating unit for generating a current; a control circuit having a first end and a second end, the first end being connected to the fixed current generating unit for receiving a first portion of the current, a second end of the control circuit for outputting a clock signal; and a charge pump circuit coupled to the second end of the control circuit, and the fixed current generating unit and the control circuit Between the first ends, the charge pump circuit receives a second portion of the current, a reference voltage, and the clock signal; wherein, when the current value of the first portion is not zero, the The frequency of one of the clock signals is changed by the current of the first portion; when the current value of the first portion is zero, the frequency of the clock signal is a fixed value, and the second portion This current is equal to this current. The clock generating device of claim 1, wherein the control circuit comprises: an integrating circuit for receiving the current of the first portion and generating a control voltage; and a voltage controlled oscillator Connected to the integration circuit to generate the clock signal having the frequency according to the control voltage. The clock generating device of claim 1, wherein the current generated by the fixed current generating unit is a current of a zero temperature coefficient. The clock generating device of claim 1, wherein the fixed current generating unit comprises a positive temperature coefficient circuit and a negative temperature coefficient circuit, and an absolute value of a temperature coefficient of the positive temperature coefficient circuit and the The absolute value of the temperature coefficient of the negative temperature coefficient circuit is the same. A clock generating device includes: a first node; a current generating unit configured to generate a fixed current having a zero temperature coefficient to the first node; and an integrating circuit connected to the first node, The method is configured to output a control voltage according to the current received from the first node; a voltage controlled oscillator connected to the integrating circuit to output a clock signal according to the control voltage; and a charge pump circuit to receive a reference voltage, and Connecting the first node and the voltage controlled oscillator to receive a sink current from the first node according to the reference voltage and the clock signal, wherein the sink current is equal to the fixed current when the clock generating device is stable. The clock generating device of claim 5, wherein the current generating unit comprises: a zero temperature coefficient current generating circuit for outputting a bias voltage; and a mirror current unit for connecting the zero temperature coefficient current generating The circuit outputs the fixed current according to the bias voltage. The clock generating device of claim 6, wherein the mirror current unit comprises at least one first P-type field effect transistor, the gate of the first P-type field effect transistor receiving the bias voltage and The first source/汲 terminal receives a system voltage and outputs the fixed current at a second source/汲 terminal. The clock generating device of claim 6, wherein the zero temperature coefficient current generating circuit comprises: a second P-type field effect transistor, wherein the first source/汲 terminal receives the system voltage; a P-type field effect transistor, the first source/汲 terminal receives the system voltage, and the gate is connected to the gate of the second P-type field effect transistor; a first operational amplifier is used to output the bias voltage And the output end of the first operational amplifier is connected to the gate of the second P-type field effect transistor, wherein the negative input terminal and the positive input terminal of the first operational amplifier are respectively connected to the second P-type field effect transistor And a second source/汲 terminal of the third P-type field effect transistor; a first PNP bipolar transistor, the emitter of the first PNP bipolar transistor is connected to the second P-type field effect a second source/汲 terminal of the crystal, the collector and the base of the first PNP bipolar transistor being connected to a ground; a second PNP bipolar transistor, the set of the second PNP bipolar transistor a pole and a base connected to the ground; a first resistor connected to the second source/汲 of the second P-type field effect transistor Between the end and the ground; a second resistor connected between the second source/汲 terminal of the third P-type field effect transistor and the emitter of the second PNP bipolar transistor; And a three resistor connected between the second source/deuterium terminal of the third P-type field effect transistor and the ground. The clock generating device of claim 5, wherein the voltage controlled oscillator is an LC voltage controlled oscillator, an RC voltage controlled oscillator or a transistor voltage controlled oscillator. The clock generating device of claim 5, wherein the charge pump circuit comprises: a second operational amplifier, a positive input terminal of the second operational amplifier is connected to the reference voltage, and the second operational amplifier is negative The input terminal is connected to the output end of the second operational amplifier; a third operational amplifier, the positive input terminal of the third operational amplifier is connected to the first node to receive the sink current, and the negative input terminal of the third operational amplifier is connected to the first An output of the third operational amplifier; a first capacitor; a first switch coupled between the first end of the first capacitor and the output of the second operational amplifier; and a second switch coupled to the first capacitor Between the first end and a first voltage; a third switch coupled between the second end of the first capacitor and the output of the third operational amplifier; and a fourth switch coupled to the first Between the second end of the capacitor and the positive input of the third operational amplifier; wherein the first switch and the third switch are turned on when the clock signal is at a first level, the second switch Four open When the clock signal is at a second level, the first level is different from the second level. The clock generating device of claim 10, wherein the first voltage is a ground. The clock generating device of claim 10, wherein the first voltage is a system voltage. The clock generating device of claim 5, wherein the frequency of the clock signal is proportional to a voltage level of the control voltage. The clock generating device of claim 5, wherein the current of the sinking current is proportional to a voltage level of the reference voltage and a frequency of the clock signal.