TWI308785B - Chip structure and method for fabricating the same - Google Patents

Description

1308785

[Description of the Invention] [Technical Field] The present invention has a wafer structure and a manufacturing method thereof, and particularly relates to a method for simplifying a process step, a wafer structure, and a corresponding method thereof Wafer [prior art]

A method for improving the performance of a semiconductor device is generally to reduce the cost per die (die) by reducing the geometry of the integrated circuit = 'the above results, while improving the performance of some aspects of the semiconductor device. The metal connection (metal c〇nnecti〇n) between the integrated circuit and other circuits or between the integrated circuit and the system components becomes relatively important, and with the further miniaturization of the integrated circuits, for line performance The negative impact also increases. When the parasitic capacitance and resistance of the metal interconnects increase, it will mean a decrease in the performance of the wafer. Among them, the most concern is the voltage drop (v〇itage drop) between the power bus and the ground bus (the floating 1111 (1 buses), and the resistance and capacitance delay of the key signal path (RC delay) In order to reduce the resistance, if a wide metal wire is used, the parasitic capacitance of these wide metal wires will increase. To solve this problem, a low-resistance metal (such as copper) is used as a wire, and a low dielectric constant is used. The dielectric material of (1〇w_k) is between the signal lines. From the point of view of the history of 1C connection metal, the aluminum sputter has become the mainstream of ic connection metal materials since the 1960s. The film aluminum covers the whole film by sputtering. The wafer's next process is to pattern aluminum metal in a yellow lithography process and a dry or wet etch process. In terms of cost and sputtering stress considerations, it is difficult and costly to produce a metal circuit with a thickness of more than 2 μm. Expensive. In about 1995, Damascene became another metal that can be used for ic bonding. In the case of damascene copper, after patterning the insulating layer, it can be shaped by electroplating. The copper layer and by chemical mechanical polishing (CMP) can remove the copper layer outside the opening of the insulating layer. The copper metal wire is formed in the opening of the insulating layer. The electric clock is thick on the whole wafer and the gold is 6 1308785. 'And the thickness of the inlaid copper (Damaseene) is usually determined by the insulating layer two, so the insulating layer - like oxide, due to stress and cost ^: method provides too thick thickness 'that is to form a thickness of more than 2 division The copper metal connection is technically difficult and costly. - US Patent Publication No. 5,212, 4G3 (9) - Bowl) discloses a method of forming a line connection, in which the inside and outside of the towel are connected In the circuit substrate on the circuit board, the design of the logic circuit depends on the length of the line connection.

U.S. Patent No. 5,501,006 (Gehman, Jr. et al.) discloses an integrated circuit and a line-based structure that aligns with the Wei edge layer, and the pin that can be used to make the contacts of the wafer and the substrate The contacts are electrically connected. U.S. Patent No. 5,554,907 (Jacobs) discloses an integrated semiconductor structure that allows a manufacturer to convert a thin layer of thin layers onto a support substrate wafer to integrate circuitry external to the wafer. A multi-layered wire structure is disclosed in U.S. Patent Publication No. 5,1,6,461 (Volfsonetal.) by means of a TAB structure and utilizing a dielectric layer and a metal layer of a p〇lyimide. Made on the wafer. U.S. Patent No. 5,635,767 (Wenzeletal.) discloses a method of reducing the resistance of a resistive capacitor by providing a PBGA structure in which a plurality of layers of metal are separated. U.S. Patent No. 5,686,764 (Fulcher) discloses a flip-chip substrate by The power line is configured separately from the input and output leads to reduce the resistor and capacitor sluggish effects. Silicon Processing for the VLSI Era (Vol. 2, pp. 214-217, Lattice Press, Sunset Beach, CA c. 1990) by Stanley Wolf discusses the use of polyamines as intermetallic dielectric materials in the 1980s. . However, since polyamines have many disadvantages, polyamidoguanidine has not been used for this purpose since then. SUMMARY OF THE INVENTION 1308785 is in this context. The object of the present invention is to improve the performance of an integrated circuit. Furthermore, another object of the present invention is to reduce the voltage drop caused by the line impedance of the power bus of the connection ic and adjacent circuits or circuit components. Further, another object of the present invention is to reduce the impedance of the power bus of the high current 1 〇 component. Furthermore, another object of the present invention is to reduce the impedance of the IC metal connection line of the low voltage IC device. Furthermore, another object of the present invention is to reduce the impedance and load of the IC metal connection line of the low power IC component.

Further, another object of the present invention is to reduce the RC delay constant of the path of the high-performance integrated circuit (IC) device. Furthermore, another object of the present invention is to promote the use of ic components that reduce volume and increase current density. Furthermore, another object of the present invention is to promote and enhance the application of low resistance conductive gold. Furthermore, another object of the present invention is to promote and enhance low-capacitance conductive metals. Again, another object of the present invention is to provide high performance by increasing the number of input/output (1/0) connections (pincount). IC components. Furthermore, a further object of the present invention is to simplify wafer assembly by reducing the need for a new distribution of 1/〇 wafer connections. Furthermore, another object of the present invention is to facilitate the connection of high performance IC components to the ground bus. ..., 'again' The purpose of the present invention is to facilitate the connection of high performance IC components to clock distribution networks. Furthermore, 'the purpose of the invention is to use the less expensive process equipment' or to use the less clean room requirements of the clean room, the cost of the 8 1308785 is low, and above Both are compared to sub-micron manufacturing requirements. Further, another object of the present invention is to drive and stimulate the design of a systemized wafer, since the present invention can provide a functional circuit that is easy to manufacture and low in cost to connect long distances. The purpose is to automatically wrap the connection line over the preset length by the winding software of the operation _, ie, according to the connection line of the & Thick polymer dielectric layer and layer

It is on the protective layer of the finished wafer. Thick dielectric layer; gold road based cyclobutene (BCB), its thickness exceeds 3 microns. Thick and wide main 嶋 '__ domain metal layer ^ (clock distribution networks), ^ key job m redistribution input / output seam user ^ = capacitance product value under the protective layer of fine metal structure Further, the present invention provides a top metal structure of a rr performance structure for a germanium performance integrated circuit. The integrated circuit includes the semiconductor 4 in the substrate. The thin film metal structure includes the fine metal inner i-line connecting member. n Read + conductor The connection pad of the fine metal inside. The area is much larger than the thickness of the film and the thickness of the metal structure under the protective layer. The structure can make the value of the resistance and capacitance of the structure, for example, much less than 7^== layer metal. Resistor capacitance product value. 9 1308785 of the 4 m metal structure under the I layer is to make the above and other objects, the following and the gamma energy of the present invention easier to understand, and the following is a detailed description of the preferred embodiment, and the following is a detailed description. [Embodiment] The present invention discloses a circuit structure in which an integrated metal layer and a polymerized germanium are formed on a protective layer of a conventional ic, and a reconfigured connecting metal layer uses a wide and thick gold f line, so Reduce the resistance and capacitance delay. Alternatively, the thick and wide metal lines on the protective layer can be electrically connected to the separated two-electrode, exposed to the opening σ of the protective layer. Alternatively, the thick metal layer on the protective layer may be a sensing element, a capacitive element or a resistive element. The eyeglass diagram of the present invention is illustrated with reference to the accompanying drawings. The semiconductor substrate 1 is, for example, a germanium substrate, a germanium substrate or a gallium arsenide substrate, which is doped with pentavalent or triplet ions, such as boron ions or scale ions, to form a plurality of electronic components in the semiconductor, the surface layer of the bottom 1 As shown in the element layer 2 in FIG. 1, the electronic components are, for example, metal oxide semiconductors, transistors, multi-resistance elements, and poly-to-poly capacitors using polymorphs as electrodes. The bus layer 3 on the element layer 2 is formed by an inter-deposited thin film metal layer and a thin film dielectric layer. In general, the inter-metal thin film dielectric layer material includes niobium-containing oxides, such as chemical vapor deposited oxidized oxide, chemical vapor deposited TEOS oxide, spin-on-glass (S0G), fluorine. The glass (FSG) and the oxide deposited by the high-density plasma, the thin film dielectric layer may also be a composite layer structure or a single layer structure composed of the above-mentioned partial materials. The thickness of the film line layer is, for example, between 1, 〇〇〇 micron and 1 〇, 〇〇〇 micron. The thin film circuit layer is generally formed by sputtering aluminum or aluminum alloy, and the splashed aluminum or aluminum δ gold is patterned to form a fine metal circuit. In one embodiment, for example, an aluminum-copper alloy using less than 5% by weight of copper. As a thin metal line under the protective layer. In aluminum private, the metal layer such as lyon is formed on the dielectric layer such as cerium oxide, and then the metal layer is patterned by lithography, 1308785 small ^ 2 using a chemical vapor deposition method to form an additional dielectric layer such as cerium oxide or a dielectric constant type on the metal layer, after which the lithographic etching can be utilized to form a dielectric layer. A plurality of openings may be formed on the other dielectric layer. The second process is performed on the lower layer of the metal layer, and the subsequent processes are repeated in sequence according to the sequence. In addition, the thin film wiring layer metal lines can also be formed. In the inlaid copper process, copper is protected by an adhesion/obstruction layer beneath the copper layer and copper to prevent the migration of copper ions from affecting its footprint. In the inlaid copper process towel, the type of paste chemical vapor deposition is used to form a dielectric layer with a dielectric constant of less than 2.5 or a dielectric layer of less than 2.5.

If ^ + ^ layer of the genus layer ' can be formed by means of a surface such as m ! Guanghua Qin Zhi adhesion / barrier layer on the dielectric layer and the opening of the dielectric layer, the formation of vapor deposition is such as On the adhesion/barrier layer of copper, m 2 in the layer occupied by copper and the opening in the opening of the dielectric layer, and the weight percentage of the medium copper is, for example, greater than 95%, and then the mechanical r (CMP) Way to remove the bit outside the opening of the dielectric layer

Fooo^muo^ is used to make the thickness of the photoresist layer, and the thickness of the photoresist layer is used to operate the pad. The metal connection point provides Ic connection = for example, 疋 connection (bond connection. The connection circuit layer is electrically connected to the external circuit. 1308785 The Warranty 4 layer is placed on the 1C connection structure and has a plurality of openings, exposed/out of the 1C connection structure on the top layer to provide electrical connection points. In the current technology, the 'protective layer is usually used. Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to deposit oxides and nitrides. When the protective layer 4 is formed, a PECVD oxide having a thickness of about 5 μm can be deposited first. Then, a nitride having a thickness greater than 〇3 μm, preferably ο. μm is formed. The protective layer 4 described above is important to protect the thin film wiring layer and the thin film dielectric in the wiring layer 3 of the component 2 and the 1C. The layer is protected from moisture and the destruction of transition metals such as gold, silver, copper, etc., and foreign ion contaminants such as sodium ions (ion c〇ntaminati〇n). For protection purposes, the thickness of the nitride layer of the protective layer 4 is typically greater than 0.3 microns and is therefore formed by a sub-micron process (forming an integrated circuit with thin lines). The protective layer 4 between the IC wiring layer 3 and the protective layer 80 formed by the tens or micron (greater than 1 micron) (tens_mjcr〇n) process (forming a thick and wide metal interconnect structure) is of critical importance By the protection of the protective layer 4, when forming the back cover 80, a relatively inexpensive process can be made to make a thick and wide metal interconnect and a thick polymer layer, and a dust-free grade can be used. Room to manufacture. The thickness of the protective layer 4 is, for example, greater than 0.35 micrometers, and the protective layer may be formed of oxynitride, phosphosilicate glass (PSG), and borax in addition to being formed of β PECVD oxide and PECVD nitride. A borophosphosilicate glass (BSG), a borophosphosilicate glass (BPSG) or a composite layer of at least one of the above materials is formed. In one embodiment, the protective layer 4 comprises a layer of a ruthenium compound and a layer of a oxon compound, wherein the layer of the ruthenium compound is on the ruthenium compound layer, and the thickness of the nitridene compound layer is, for example, 0.2 μm. Between 1.2 microns, the oxygen oxide compound layer is, for example, between 0.1 microns and 0.8 microns. In general, the protective layer 4 includes the topmost layer of the ruthenium compound and the topmost ruthenium compound layer in the wafer structure that has been fabricated in 12 1308785 and the protective layer 4 is included in the topmost layer of the fabricated wafer structure. An insulating layer formed by & vapor deposition. The plurality of openings θ located in the protective layer 4 expose the opening of the topmost thin film wiring layer in the wiring layer 3, and the opening in the protective layer may be between 0.1 μm and 25 μm. n Using a selective deposition process as described below, a thick and wide metal line of the back cover layer 8 can be formed on the protective layer 4. The thick and wide metal line formed by this technique = the resistance-capacitor product value is much smaller than the bit The resistance-capacitance product value of the fine gold road of the IC film circuit layer under the protective layer. , ,, ''

FIG. 1b is a cross-sectional view of a semiconductor wafer according to an embodiment of the present invention. A semiconductor substrate 10 has a transistor or an electronic component formed of other materials such as polysilicon. A thin film dielectric layer 12 is formed on the surface of the semiconductor substrate 1 and covers these electronic components. The source (S〇urce) and the drain (Drain) diffusion layer 120 are in the semiconductor substrate, and the gate 119 is located in the thin film dielectric layer 12, so that the channel can be formed on the semiconductor substrate 1 under the gate 119. The inside of the crucible is located between the source (s〇urce) and the drain diffusion layer 120. A plurality of layers of metal/dielectric layer 14 are disposed on the thin film dielectric layer 12, wherein the patterned metal layer in the metal/dielectric layer 14 is formed, for example, by the aforementioned sputtering aluminum process or inlaid copper process. The dielectric layer in layer 14 is, for example, an oxonium compound formed by chemical vapor deposition. For example, the metal layer formed by the foregoing aluminum plating or inlaid copper process is tied to the metal/dielectric layer 14 of the top layer, and the protective layer 18 is positioned on the metal layer, and the opening is located in the protective layer 18. The electrical pads 16 of the metal layer are exposed. The structure and use of the protective layer 18 herein can be referred to the structure and use of the protective layer 4 in Fig. 1a, and will not be described herein. After the formation of the protective layer 18, the previously formed semiconductor element such as M?s and the metal/dielectric layer 14 can be protected from damage by moisture, transition metal or foreign ion contaminants. Therefore, a relatively inexpensive process can be made to make thick and wide metal interconnects and a thick polymer layer formed on the protective layer 18, and can be fabricated in a clean room of a lower clean 13 1308785 clarity class, such as in Grade 1 or more clean room manufacturing, where Class 100 is defined as more than 100 particles exceeding α5 microns per cubic foot of environment. After the protective layer 18 is formed, a thick polymer layer 20 may be deposited on the protective layer 18. The material used to form the monolayer 20 is, for example, Hitachi-Dupont Polyurethane HD2732 or 2734 (p〇lyimide, PI), or Asahi Polyimine Ls_, 1-83005^ or 8124. Another material can also be used to form the polymer layer 2〇, which is BenzoCycloButene (BCB), the manufacturer is D〇w Chemical, for example, and the phenylcyclobutene is gradually substituted. The trend of amines. Materials such as polyarylene arylene, porous dielectric materials or elastomers may also be the material of the polymer layer 20. An epoxy group-containing material such as photosensitive epoxy resin su_8 (manufacturer Sotec Microsystems) can also be used as the material of the polymer layer. The deposition of the polymer layer 20 can be formed by spin coating (eg ) 〇 〇 ) ting) and hardening (egg), as described below: in spin coating a polymer such as a photosensitive polyimide. After the film (4) 18 and the electrical pad 16, the polymer film can be patterned by lithography to form an opening in the polymer film, and the electrical pad 16 is exposed, and then the polymer is polymerized. The film was placed in a vacuum environment or under a nitrogen atmosphere and used in a period of Celsius for a 4 hour hardening process. Alternatively, it may be other impurities. After spin coating, such as a non-inductive hetero-imine film on the tilting layer 18 and the electrical pad 16, the polymer may be placed in the vacuum ring. Brother or nitrogen atmosphere, and using the conditions of Celsius, for 4 hours of hardening process 'then can be patterned _ lithographic side of the polymer film' to form an opening in the polymer film, and exposed electricity Sex pad 16. To obtain a thicker polymer layer 2〇', the spin coating step can be repeated to form a further polymer-polymerized polymer layer formed in the previous layer to achieve the desired thickness, of which the second layer = 14 1308785 The film of the film is, for example, a photosensitive polyimide, which can then be micro-formed to form an opening in the polymer layer of the multilayer and expose the electrical pad 16 Then, the multilayer polymer film is placed in a vacuum environment or a nitrogen atmosphere, and subjected to a 4 hour hardening process using a condition of 380 degrees Celsius, so that a thick polymer layer having a multilayer polymer film can be formed.

On the protective layer 18. Alternatively, if a thicker polymer layer 2 is to be obtained, the step of spin coating may be used to repeatedly form another polymer film on the previously formed polymer film until the laminated polymer film is laminated. Achieving a desired thickness, wherein the laminated polymer film is, for example, a non-photosensitive polyimine, and the multilayer polymer film is placed in a vacuum or nitrogen atmosphere and is used at 38 Torr. The condition of 'degree of 4' hardening process, then the side of the lithography side can be used to pattern the multilayer polymer fine 'by forming a shape in the multilayer polymer film' and exposing the electrical pad 16 Thus, a thick polymer layer 20 having a multilayer polymer film is formed on the protective layer 18.

In addition, the polymer layer 20 can also be formed on the protective layer 18 by screen printing. When the polymer layer 2 is printed, an area can be left unprinted to form an opening, thereby exposing the electricity. The pad 16 can eliminate the lithography or micro-steps, wherein the polymer layer material is, for example, poly-imine, then (10) the polymer layer 2G is placed in a vacuum or nitrogen atmosphere. And use a condition of Celsius to perform a 4 hour hardening process. Alternatively, the polymer layer 2 can also be formed by heat-pressing a dry film having an opening in the protective layer. Thus, the polymer layer having an opening pattern can be directly formed on the protective layer is. The opening in the polymer layer 20 exposes the electrical pads 16, so that the steps of silk or micro-secret can be saved. Alternatively, the polymer layer % can also be used to make the film on the protective layer 18, and then use the side process to form the dry mouth after the hot pressing, which exposes the mat. 16, it can save the steps of silk shadow or micro-carried.

1308785 In another embodiment, 'in terms of the conditions for hardening the polyimide, it is not limited to the above technique', it may be hardened under the condition that the temperature is below 320 degrees Celsius' or it may be at a temperature of Celsius. Under conditions of 320 degrees or more, a hardening process of less than 4 minutes is performed, even a hardening process of less than 20 minutes. The thickness of the polymer layer 20 after the curing process can exceed 2 microns, such as between 2 microns and 150 microns, depending on the electrical design requirements. The thickness of the polymer layer 20 is 2 to 500 times thicker than the thickness of the thin film dielectric layer or the thin film metal layer of the metal/dielectric layer 14. After the hardening step, the sidewalls of the openings in the polymer layer 2〇 will assume an oblique pattern. The angle between the sidewalls and the horizontal plane is, for example, 45 degrees or more, and is substantially between 50 degrees and 60 degrees. Between degrees; or, the angle of inclination of the side wall can also be as small as 20 degrees. At this time, the opening in the polymer layer 20 may be in a semi-conical pattern. Referring to FIG. 1b, the maximum lateral dimension of the opening 27 in the polymer layer 20 is greater than the maximum lateral dimension of the opening 17 in the protective layer 18, wherein the maximum lateral dimension of the opening 17 of the protective layer 18 is, for example, 01 micron. Between 5 〇 micrometers, preferably in the case of between 0.5 micrometers and 20 micrometers, and the maximum lateral dimension of the electrical pads 16 is between 〇 1 micrometer and 50 micrometers, In preferred cases, for example, between 0.5 microns and 20 microns. The maximum lateral dimension of the opening 27 of the polymer layer 20 is, for example, between 1 micron and 1 micron, and in the preferred case, e.g., between 2 and 30 microns. Since the electrical pads 16 can be made small, the winding capability of the wires of the same metal layer as the electrical pads 16 can be increased, and the electrical pads 16 and the underlying thin metal layers can be reduced. Parasitic capacitance. Referring to FIG. 1b, after forming the polymer layer 20, a thick metal layer 30 can be formed on the polymer layer 20 and in the opening 27 in the polymer layer 20 to pass through a thick and wide metal line of the thick metal layer 30. 26 can electrically connect the plurality of electrical pads 16 . Referring to FIG. 1b', in the case of electrical transmission, for example, a signal outputted by a semiconductor device's poleless 12 〇 16 1308785 can be transmitted to an electrical connection via a thin metal layer of a plurality of metal/dielectric layers 14 Pad 16' is then transferred to another electrical pad 16 via a thick and wide metal line 26 (transmission path as indicated by arrows 40, 42, 44), followed by a thin film metal of multiple layers of metal/dielectric layer 14. The layer is transferred to the gate 119 of another semiconductor component.

The manufacturing process of the thick metal layer 30 as shown in FIG. 1b can be simplified by referring to FIG. 2a to FIG. 2f', where 12 represents a M〇s element or a polysilicon passive element including a gate, a source and a gate. The semiconductor device 丨2 may be connected to the electrical pad 16 via the metal/dielectric layer 14, and an opening 17 in the protective layer 18 exposes the electrical pad 16' to form a polymer by the manner described above. The layer 2 is on the protective layer 18, and the opening 27 in the polymer layer 20 exposes the electrical pads 16, as shown in Figure 2a. ^ Next, please refer to FIG. 2b first, after forming the polymer layer 20 onto the protective layer 18, the opening/covering layer 200 can be deposited on the polymer layer 2, the opening of the polymer layer 2 On the electrical contact 16, the material of the adhesion/obstruction layer is, for example, titanium alloy, chromium, chrome-copper alloy, titanium, group, slit compound or titanium nitride compound, and the thickness is about 3 micrometers. In a preferred embodiment, it is, for example, between 3 ng Str〇m and 5000 Å. Then, using the method of sputtering (_er) ore ("哗"), the seed layer 202 is formed on the adhesion/resistance 2 'the material of the seed layer 2〇2 such as copper, gold, silver, handle, ship, 姥, The thickness is between about _micrometers to 3 micrometers, and in a preferred embodiment, for example, 疋7 丨 between 300 angstroms and 10,000 angstroms. In addition, according to FIG. 2C, a thick photoresist layer 203 can be formed to pattern the thick photoresist layer 203 in a manner that the seed layer 202/, the degree is large, and the force is between 1 micrometer and a cubic micrometer, thereby opening the π 〇乂^^ J is opened in the thick photoresist layer 203 and exposed by the shed shirt ("Europe if you can use the exposure alignment (4) or 1 times steppei>s) to expose the photoresist layer (10) Ming first to Fig. 2d' can then use electroplating or 204 2〇3 17 1308785 genus layer 204 material such as copper, gold, silver, palladium, platinum, rhodium, iridium, between about 1 micron and excitation micron, in Preferably, when 2 μ = or even more than 99% of copper, the seed layer is moved with T99% of copper; when the metal layer 204 is made of the material of the electric clock, it is 90% or even more than 99%. In the case of gold, the seed layer 202 = 4 weights, 1%, or even more than 99% of the gold; the layer 204 is formed by electroplating; when the size is 2, the material of the seed layer 202 can be a large percentage by weight. Gu 2G4 Mei Yucheng weight percentage of one hundred eight + two ΐ 9% of the time 'the material of the seed layer 202 can be heavy or more than 99%; when the metal layer 204 Using the electric formula to form a percentage greater than 9G% or even greater than 99% _, the seed two Lili materials can be more than 9〇% by weight or even more than 99% of the weight; : metal layer 204 is the use of electric ore When the weight percentage is greater than 9〇% or even the amount of money, the material of the seed layer 2G2 may be more than the weight of the Xia 3^"%; when the metal layer 2〇4 is formed by the use of electric ore === When more than 90% or even more than 99% of the crucible, the material of the seed layer 2 () 2 can be used with Ray 2!^ at 9〇% or even greater than "%; when the metal '204 is using the electroplating village shape The amount of material of the seed layer 202 may be more than 90% by weight or even more than 99 〇 / 〇 of nickel. Therefore, the present invention forms a protective layer by a selective deposition process. 18 thick metal f road, less material waste, ❹ not used when precious metals such as gold, silver miscellaneous. a δ 'use to form a thin film metal standard inlay process, the metal system is all on the wafer 'Making the entire wafer® system cover a thick metal, causing the wafer to be warped Title; copper damascene process and system to polish the removal of undesired manner 181308785

The amount of damage on your knives does not form a thick yttria dielectric layer, which is very expensive. Difficult, because the thickness of the metal line is determined by the electric layer. However, due to the layer, and the deposition of thick yttrium oxide is followed by 'please refer to 2e first, after forming the metal layer 2〇4, Hf3: after 'please refer first Fig. 2f, the re-cut metal layer is used as a rhyme mask, and the layer 202 and the adhesion/barrier layer 200 not covered by the metal layer 2() 4 are sequentially removed through the side, leaving only the metal layer 2〇4 and adhesion/barrier layer 200. After the wet-side process of the τ-adhesion/barrier layer self-aligned (f) f_aligned, the undercut 205 (undercut) is formed around the adhesion/barrier layer 2〇〇 and under the metal layer 2〇4. The recessed portion 205 has a recess depth of between about 3 micrometers and 2 micrometers, and the depth of the recess depends on the etching parameters and the etching time. There is also a clear boundary between the seed layer 202 formed by sputtering and the metal layer 2〇4 formed by electroplating, for example, by transmission and scanning electron microscopy (TEM). Referring to FIG. 2g, in the above process, when the material of the metal layer 2〇4 is copper, another metal layer 206 may be formed on the metal layer 204 to prevent the metal layer 204 of the material from being corroded. The material of the metal layer 2〇6 is, for example, gold, silver, palladium, tantalum, niobium or nickel, and the thickness thereof is, for example, between i micrometers and 1 micrometer, and in the preferred embodiment is 2 micrometers. Between 10 microns and the thickness of the metal layer 2〇4 = such as between 1 micron and 100 microns, in the preferred embodiment between 2 and 10 microns. In terms of process, 'in the formation of the metal layer 204 in the photoresist layer 2〇3 - 〇5r: l. 2 Ch-t date correction replacement page 1308785 opening exposed on the seed layer 202 (as shown in Figure 2d) After the display, the metal layer 206 may be formed on the metal layer 204 by means of electricity, ore or electroless ore, and then the process of removing the photoresist layer 203 may be performed, followed by patterning the metal layer 2 4 as an etch mask, sequentially removing the seed layer 202 + and the adhesion/barrier layer 200 that are not covered by the metal layer 204 by means of button etching, leaving only the seed layer 202 and the adhesive layer under the metal layer 2〇4 / Block the early layer 2 〇〇. In this way, in the process of engraving the adhesion/barrier layer and the seed layer 202, 'covering by the metal layer can prevent the side liquid from falling off the metal layer 204 from the upper side', and then the copper can be used. The engraving agent is applied to the side seed layer 202 and the adhesion/barrier layer 200, so that the consumption of the copper metal of the metal layer 2〇4 can be reduced. In the present embodiment, since the surname for the residual seed layer 2〇2 and the adhesion/barrier layer 200 is side-by-side from the side wall of the gold spheroid, there will be a lower edge of the metal layer 206. The phenomenon of the surface being exposed to the outside. = The thick and wide metal line on the lamella layer 18 is between about 1 micrometer and the moving micrometer. The thickness of the thick and wide metal lines adjacent to the same layer can be greater than 2 micrometers. .

The above-mentioned metal process on the protective layer 18 can be made at level 1 or 2 clean room_made' and when the metal line on the protective layer 18 is made, the aligning device can be made! (1) shouting step by step (4) lithography process between the micro-^ to the shi-micron photoresist layer 2〇3, so it can be very low. Compared to the 1c film fine metal, it needs to use 5 times (5X) exposure stepper, scanner (or better), better time, please refer to Figure 2h 'in the formation of thick and wide metal lines on the polymer layer =, the additional polymer layer 222 can be formed on the thick and wide gold to protect the previously formed thick and wide metal wiring, wherein the manufacturing method of the polymer layer 2G can be referred to ', two at 20

II 1308785 The opening 223 in the polymer layer 222 of the replacement page can expose a thick and wide pad, and then a tin-lead bump or a gold bump can be formed on the pad, or the gold formed by the wire bonding process. Wires can be bonded to this pad. However, the application of the present invention is not limited thereto, and the polymer layer 222 having a flat upper surface cannot be formed due to the influence of the thick and wide line of the protrusions, so that the process of planarizing the polymer layer 222 can be performed. Forming a layer 222' having a flat upper surface as shown in FIG. 2i, wherein the material of the polymer layer 222 is, for example, phenylcyclobutene, polyimine, paiylene, porous dielectric = Elastomers, etc. Referring to FIG. 2i, the detailed process is as follows: after the polymer layer 222 is formed by spin coating, the polymer layer 222 can be hardened by a boat roasting process, followed by mechanical polishing or chemical mechanical polishing. The upper surface of the process planarization polymer layer 222' then forms an opening 223 in the polymer layer 222 to expose a thick and wide metal line junction. Or 'may be other processes: after forming the polymer layer milk by spin coating, the upper surface of the grinding ί2 can be turned off, and then the open mouth layer can be formed by micro-engraving. Within 222, the polymer layer 222 is cured by a step of exposing the pads of a thick and wide metal line. Alternatively, after the polymer layer 222 is formed by f-transfer coating, the opening 223 may be formed in the polymer layer 222 by a two-way connection followed by fine mechanical grinding. The upper surface of the process or chemical mechanical polymer layer 222 is then subjected to a series of steps to harden the polymerization a. Or, it is also another throw: after the 贱 涂 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,彳味合骑 2ms i Che New or chemical machine magic upper surface. In the above-mentioned formation of a flat poly 21 1308785 == 3⁄4 ring - the object layer is on the thick and wide gold on the financial layer 18 of FIG. 2g; in the method of forming a thick metal line, in the protective layer 18 ===In the second layer of the second layer, more thick metal lines are formed on the polymer layer 20, and the related processes can be referred to FIG. 2j and FIG. 2k. The pattern can be formed after the adhesion/barrier layer 200 and the seed layer 202 are formed on the sidewalls of the openings 27 in the polymer layer 20 and the masks 16 in the protective layer 18. On the seed layer 2〇2 on the 2222, part of the patterned photoresist layer 203, in the opening 27 of the inner surface and covering the sidewall of the opening 27, the sub-曰2〇2' can then be formed. The metal layer is applied to the seed layer 202 where the opening in the photoresist layer 2〇3 is violently exposed. In this embodiment, the adhesion/barrier layer 2 (8), the seed layer 2^) 2 ^ the formation method and material of the metal layer 204 The thickness can be referred to the adhesion/barrier layer 骂, the seed layer 2G2 and the metal layer formation method and thickness description in Fig. 2a 2f, respectively. Clear reference ® 2k ' can then remove the patterned photoresist layer 2 〇 3 and not in the metal The seed layer 202 and the adhesion/barrier layer 2 under the layer 204, wherein the depressed portion 2〇5 exists under the seed layer and around the adhesion/barrier layer 2〇0. In this embodiment, the depressed portion The size of 205 can be referred to the description of the size of the recess 2〇5 in Fig. 2f. Thus, the thick metal and line on the protective layer 18 The road may cover only a portion of the side walls of the opening 27 in the polymer layer 2〇.

1308785 In addition, when the material of the metal layer 204 is copper, another metal sound 206 can be formed on the metal layer 204 to prevent the material from being a metal layer of copper 2〇4, and the material of the metal layer 206 For example, gold, silver, palladium, platinum, money, needle or nickel, the thickness of which is, for example, between 1 micrometer and 100 micrometers, and the thickness of the metal layer _ 2〇4 is, for example, between 1 micrometer and 100 micrometers. 'As shown in Figure 21 and Figure 2tn. In the case of the process, as shown in Fig. 21, after the formation of the metal layer 204 on the seed layer 202 exposed by the opening in the photoresist layer 203 (as shown in Fig. 2j), electroplating or no The electroforming method forms a metal layer 206 on the metal layer 204, and then please refer to FIG. 2m, after which the process of removing the photoresist layer 203 can be performed, and the subsequent process is as described in g, and will not be described herein. Referring to FIG. 2j to FIG. 2m, the maximum lateral dimension of the opening 27 in the polymer layer 20 is greater than the maximum lateral dimension of the opening 17 in the protective layer 18, wherein the maximum lateral dimension of the opening 17 of the protective layer 18 is, for example, Between 1 micron and 5 micron, in the preferred case 'such as between 0.5 micrometers and 20 micrometers, and the maximum lateral dimension of the electrical pad 16 is, for example, between 1 and 5 micrometers to 5 micrometers. Between microns, preferably in the case of, for example, between 0.5 microns and 20 microns. The maximum lateral dimension of the opening 27 of the polymer layer 20 is, for example, between 1 micrometer and 1 micrometer, and preferably between 2 and 30 micrometers. In one embodiment, a plurality of thick metal layers and thick polymer layers may be formed on the protective layer as shown in Figures 3a and 3b. Referring to FIG. 3a, the polymer layer 2 is formed on the protective layer 18. The material and formation method of the polymer layer 20 can refer to the material and formation method of the polymer layer 20 as shown in FIG. 1b; then forming a thick metal. The layer 30 is on the polymer layer 20, and the electrical pads 16 are connected through the openings in the polymer layer 20 and the protective layer 18. The detailed structure and formation method of the thick metal layer 30 can be referred to as shown in Figures 2a-2g and 2j- The detailed structure and formation method of the thick metal layer shown in 2m; then the polymer layer 50 is formed on the polymer layer 20 and the thick metal layer 30. The material and formation method of the polymer layer 50 can be referred to as shown in the figure. The material of the polymer layer 20 is 23 1308785 and a forming method; then, the thick metal layer 60 is formed on the polymer layer 5, and the thick metal layer 30 is connected via the opening in the polymer layer 50, and the detailed structure of the thick metal layer 5〇 and For the formation method, reference may be made to the detailed structure and formation method of the thick metal layer shown in FIGS. 2a-2g and 2j-2m; then, the polymer layer 70 is formed on the polymer layer 5〇 and the thick metal layer 6〇, and the material of the polymer layer 70 is formed. And the formation method can refer to the figure shown in The material of the layer 20 and the formation method thereof, the opening 77 in the polymer layer 7〇 can expose the pad of the thick metal layer 60, and then a tin-lead bump or a gold bump can be formed on the pad. Alternatively, a gold wire formed by a wire bonding process can be bonded to the pad. Thus, a thick metal layer structure having a plurality of layers can be formed on the protective layer 18 # by repeatedly forming a thick metal layer and a thick polymer layer in this order. Referring to FIG. 3b, the polymer layer 20 is formed on the protective layer 18. For the material and formation method of the polymer layer 20, reference may be made to the material and formation method of the polymer layer 2〇 shown in FIG. 1b; then forming a thick metal. The layer 30 is on the polymer layer 20, and the electrical interface 16 is connected through the openings in the polymer layer 20 and the protective layer 18. The detailed structure and formation method of the thick metal layer 30 can be referred to as shown in Figures 2a-2g and 2j- The detailed structure and formation method of the thick metal layer shown in 2m; then, the polymer layer 50 having the flat upper surface is formed on the polymer layer 20 and the thick metal layer 30. The material and formation method of the polymer layer 50 can be referred to as The material and formation method of the polymer layer 222 shown in FIG. 2i; then forming a thick metal layer 60 on the polymer layer 50 having a flat upper surface, and connecting the thick metal layer 30 via the opening in the polymer layer 50, thick metal For the detailed structure and formation method of the layer 50, reference may be made to the detailed structure and formation method of the thick metal layer shown in FIGS. 2a-2g and 2j-2m; then, the polymer layer 70 is formed on the polymer layer 50 and the thick metal layer 60, Material and formation of polymer layer 70 The method can refer to the material and formation method of the polymer layer 20 as shown in FIG. 1b. The opening 77 in the polymer layer 70 can expose the bonding of the thick metal layer 60, and then the tin bump or gold bump can be formed. The gold wire formed on the pad or the wire bonding process can be bonded to the pad. Thus, a plurality of thick and thick metal wiring structures can be formed on the 24 1308785 protective layer 18 by repeatedly forming a thick metal layer and a thick polymer layer in sequence. Referring to FIG. 3c, the polymer layer 20 is formed on the protective layer 18. The material and formation method of the polymer layer 20 can be referred to the material and forming method of the polymer layer 20 as shown in FIG. ib; then, the thick metal layer 30 is formed. On the polymer layer 20, and connecting the electrical pads 16 through the openings in the polymer layer 20 and the protective layer 18, the detailed structure and formation method of the thick metal layer 3 can refer to Figures 2a-2g and 2j-2m. Detailed structure and formation method of the thick metal layer shown; then, the polymer layer 50 is formed on the polymer layer 2 and the thick metal layer 30, and the polymer layer 50 covers the sidewall of the polymer layer 20, it is worth noting When forming the polymer layer 5, a polymer film may be formed on the thick metal layer 30, the polymer layer 20, the protective layer 18, and the protective layer 18 by spin coating. The conductive pad 16 exposed by the opening 29 is then exposed to the polymer film on the protective layer and exposed by the opening 29 by lithography or lithography during the patterning of the polymer film. a polymer film on the electrical pad 16 The opening 28 can be formed to expose the thick metal layer 3〇. The material of the polymer layer 50 and a more detailed forming method can refer to the material and forming method of the polymer layer 20 as shown in FIG. The tin-lead bumps or gold bumps may be formed on the pads exposed by the openings 28 in the polymer layer 5〇 or on the electrical pads 16 exposed by the openings 29 in the protective layer 18, or in a wire bonding process. The gold wire formed may be bonded to the pads exposed by the openings 28 in the polymer layer 5 or to the electrical pads 16 exposed by the openings 29 in the protective layer 18. Referring to Figures 3a, 3b and 3c, the thick metal layer 3 of the thick metal layer 3 on the protective layer 18 can be connected to the 119 of the two M?s elements. In addition to functioning as a signal transmission function, the thick metal line 26 on the protective layer 18 can also serve as a power bus for the power supply bus or power plane of the power supply and can be connected to the thin film metal layer under the protective layer 18. Or a power plane; in addition, the thick metal line 26 on the protective layer 18 can also serve as a ground bus for the ground distribution. 25 1308785 Replacement page t replacement page '"^mwmewwewwj or ground plane' and can be connected The ground bus or ground plane of the thin film metal layer under the protective layer 18. Thus, by forming the thick metal wiring layers 30 and 60 on the protective layer 18 to form a signal line, a power supply or a ground busbar, the inside of the printed circuit board connected to the semiconductor wafer through the tin bump, the gold bump or the wire bonding wire can be simplified. Line structure. Referring to FIG. 3d, a metal cover 99 may be formed on the electrical pad 16 such as sputtered aluminum or inlaid copper exposed by the opening in the protective layer 18. The metal cover 99 may include beryllium or aluminum or electroplated gold. . After the metal cover 99 is formed, the polymer layer 20 can be formed on the protective layer 18. The material and formation method of the polymer layer 2 can be referred to the material and formation method of the polymer layer 2〇 shown in FIG. The opening in the polymer layer 2 暴露 exposes a metal cover 99, which may be formed on the polymer layer 20' and connected to the metal cover 99 via an opening in the polymer layer 20, wherein the detailed structure of the thick metal layer 30 For the formation method, reference may be made to the detailed structure of the thick metal layer 2 and the alkali method as shown in FIGS. 2a-2g and 2j-2m. The exposed metal cover " (located on the far left, metal 盍99) can be formed by a layer of aummum under the protective layer 18, or a damascene c〇pper. The short-distance interconnects 98 thick metal lines 97 of a thick metal layer on the protective layer 18, wherein the short-distance x/r j8 winding length is between 5G micrometers and 1GGG micrometers. After the shape of ^ (four), the "bump, gold bump or shed line process" can be formed on the exposed metal cover 99 (located on the leftmost metal fox 99) 'by electrically connecting to the outside line. The layer SoHi, the figure %, the figure %, and the figure % are exposed to form a thick metal i can be 1 =, the polymer layer 2G ' However, the application of the present invention is not limited thereto, and the step of contacting the 'secret' is thick Jin Gu 30 Direct 26 1308785 曰乂Λ* Afe Year of the Month Replacement Page 疋 6b and 7b as signal transmission, ground voltage connection or power voltage connection, showing the thick and wide metal line through the protective layer The concept of connecting the 塾, the pad changing position, reducing the pad configuration and increasing the pad configuration, wherein the interface is used for signal transmission, ground voltage connection or power supply voltage connection, for example. FIG. 4a illustrates the case where the fan-opening concept of the BGA substrate is used on the flip-chip package, and the integrated circuit 丨(8) containing five tin-lead bumps 10M05 is taken as an example, and the line in the BGA substrate 130 is used. 7. The bump 1〇1 can change the position of the input/output ^ to the position of the ball club ball 111, and the bump 1〇2 can change the position of the input/output point to the position of the ball solder ball 112, the bump 104 and 105 can also change the position of the wheeling/rounding point to the ball solder balls 114 and 115. The spacing between the adjacent connection points ln to U5 may be greater than the distance between the adjacent tin-lead bumps 101 to 105, and the closer to the intermediate position of the semiconductor crystal 1 的, the ball solder balls are opposite to the bumps electrically connected thereto The smaller the lateral direction, such as the lateral displacement of the ball solder ball 113 relative to the lateral displacement of the bump 103 relative to the bump 101. 4 Figure 5a shows the concept of changing the position of the input/output point on the flip chip package BGA substrate, taking the road 100 with 5 bumps 1) as an example. By using the metal lines 131 in the BGA substrate do, the pads under the bga^ board 130 can be reordered in any order, depending on the meter or package structure. For example, 'the most integrated circuit on the integrated circuit (10) is re-bonded to the second ball on the right side of the BGA substrate 130 via the metal line 131 in the BGA substrate 130 to form a ball 124 formed by ball placement. The other bumps 1〇2_1〇5 are re-arranged via the metal wires in the BGA substrate 13 and can be respectively connected to other ball-forming tins 125, 122, 123 and 121. Figure 6a shows the input/output connection. The concept of point reduction should be on the leg substrate. The tin bump 1〇1(10) can be connected to the source, ground or touch. The towel contains 5 ship convexs. A block such as ^^^ 27 1308785 integrated circuit 100 is taken as an example. Line-containing BGA substrate 13〇 structure The line includes three line units 132, 134, and 136, such as power distribution, ground distribution, and signal distribution in the integrated power supply, respectively. The line 132 in the BGA substrate 130 may be connected to the tin-lead bumps 101, 103 and 105 to a connection point 138' below the BGA substrate 13 which is, for example, a tin-lead solder ball formed by ball implantation. The other bumps ι〇2 and 104 are reconfigured via the metal lines 134 and 136 in the BGA substrate 130, and can be respectively connected to other spheroidal tin-plated solder balls 142 and 14 〇. In the method, the total number of input/output contacts for connecting the surface circuits through the BGA substrate 130' can be reduced from the original five to three. In the case of a number of tin-lead bumps, i.e., conventional flip-chip integrated circuits, it is advantageous to reconfigure the lines from the bga substrate 130 to form fewer input/output contacts. The concept of the input/output contact increase is shown in Fig. 7a for the case where the flip chip package is connected to the BGA substrate, in which the integrated circuit 100 including three tin bumps such as _(10) is taken as an example. The line structure of the BGA substrate including the line is as shown in the figure, wherein the line includes three line units (5), 153, and 155, such as power distribution, ground distribution, and 峨 distribution in the integrated circuit, respectively. The BGA substrate m(10) line 153 can connect the tin bump 1G3 to the three connection points (6), 163, and I65 under the BGA substrate 13G, such as a solder ball formed by ball bonding. After the other bumps 105 are reconfigured via the metal lines 151 and 155 in the BGA substrate 130, they can be respectively connected to other tin-lead solder balls 162 and 164 formed by ball bonding. In the method, the total number of input/output contacts for connecting the integrated circuit 1 through the BGA substrate 130 can be increased from three to five. The functions of the BGA substrate 130 described above, including the opening of the pad, the change of the pad position, the reduction of the interface configuration, and the addition of the interface configuration, can be achieved by the thick metal lines described above on the protective layer. From Figure 4b, Figure 5b, Figure, and Figure %, the thick metal line on the protective layer can realize the concept of fan separation, change the connection position 28 1308785, and increase the pad configuration, as described below. . 'The thick metal line formed on the agricultural layer can have the function of the fan-out pad. 4 The clear-exposed thick gold road has the function of the fan-out pad function. The metal interface 301_305 exposed by the mouth can pass through the above. Yes ^ 1 , fan out to connect external points 311-315, such as + mountain ° A, bumps or wire joints. The metal pads 301-305 exposed in the opening in the protective layer 4 may be a barrier _ 乂曰 a a, the opening is violent: the middle - column, the metal c is sequentially fanned out to the parallel arrangement of the external connection阳阳如,扇I===== In this embodiment, the balance of the Xie singer's squad can be greater than the adjacent gold relative to its electrical connection to the reward, such as 11, The thick gold secret road of Baoqi 4 can have the function of touching the position of the joint, as shown in the figure. Figure 5b shows that the thick metal _ has the position of the re-matching pad and the intention of the art, and the thick gold wire on the layer of the turbulent layer 4 can expose the gold pad 3〇13 of the opening of the protective layer 4 to The order and position are different from the metal connection 3 (4) 5, the external contact milk, the 3" connection external contact 321_325 such as tin bump, the gold bump 5_ may be larger than the phase 'the thick metal line formed on the protective layer 4 can The function with reduced pad configuration is shown in Figure 6b. Figure 6b shows that the thick metal line has the intention of reducing the connection. The metal pad 3 exposed by the opening in the protective layer 4 can be penetrated through the thick metal line on the protective layer 4 described above. Connected to an external contact 29 1308785 ^ to perform the same function, such as distributed power supply voltage, voltage or distribution signal, and metal pads 303, 3 〇 4 are connected to the external contact 332, 330 ' Among them, the external contacts 328, 330, 332 are, for example, tin-lead bumps, gold bumps or wire bonding pads. In this embodiment, the number of turns of the external contacts 328, 33A, 332 may be less than the total number of metal pads 3〇13= exposed by the openings in the protective layer 4. "The thick metal line formed on the vine layer 4 can have the function of increasing the pad configuration as shown in Fig. 7b. Fig. 7b shows a schematic diagram of the thick metal line having the function of adding a pad arrangement. The thick metal line can connect one of the metal pads 3〇3 exposed in the opening in the protective layer 4 to the plurality of external contacts 36, 363 and 365' to perform the same function, for example, as a distributed power source. For voltage, distributed ground voltage or distributed signal, metal pad 3 (n, 3〇5 are connected to external contacts 362, 364 respectively), such as external bumps 361_365 such as tin bumps, gold bumps or wire bonding In this embodiment, the total number of external contacts 361365 may be greater than the total number of metal pads 3〇1, 3& and 3〇5 exposed by the openings in the protective layer 4. In an embodiment, the inductor element may be formed on the protective layer by the above-described process of forming a thick metal layer on the protective layer, as shown in FIG. 8a, wherein the inductor element is composed of, for example, a horizontally wound coil. Layer 2 After the layer 18, a thick metal layer can be formed on the polymer layer 2, and the polymer layer 2 can be formed by referring to the material and formation of the polymer layer 2 as shown in FIG. The method is followed by forming a thick metal layer including the thick metal line 26 and the inductor element 34 on the polymer layer 20, and connecting the electrical pads 16 through the openings in the polymer layer 2 and the protective layer 18, thick For detailed structure and formation method of the metal layer, reference may be made to the detailed structure and formation method of the thick metal layer as shown in Figures 2a-2g and 2j-2m. In this embodiment, the inductance element 340 is in the form of a plane and is parallel to The surface of the substrate 1 , and the height of the metal/dielectric layer 14 , the protective layer 18 and the thick polymer layer 2 〇 30 1308785 Ι 0 , can make the inductance component 340 away from the bottom 10 , so The eddy current effect induced by the inductance element in the substrate 10 can be reduced, and the inductance element 340 is formed by a wide and thick metal line structure, so that the loss of the resistance energy can be reduced, so the quality parameter of the inductance element 340 can be improve. The turtle element 340 can be formed by means of electric ore, such as gold, silver or copper.

^ Low-resistance metal, the thickness of the metal line of the inductive element 340 is, for example, greater than i micrometers 'in the preferred case', such as between 2 micrometers and 1 micrometer, and the distance between adjacent metal lines of the inductive component 340 For example, it can be as small as 4 microns, and generally it is between 0.5 microns and 50 microns. In addition, another polymer layer can be formed on the thick metal line 26 and the inductive element 340. Referring to FIG. 8a, the two contacts of the inductive component 340 are connected to the electrical pads 16 exposed by the openings of the protective layer μ; however, the application of the present invention is not limited thereto, and the germanium may be the inductive component 340. One of the contacts is connected to the electrical pad 16 from the opening of the protective layer 18, and the other contact is externally connected through a tin bump, a gold bump or a wire bonding wire formed by a wire bonding process. Alternatively, the two contacts of the inductive component 340 may be externally connected to an external circuit through a tin-lead bump, a gold bump, or a wire bonding wire formed by a wire bonding process.

Referring to FIG. 8a, the inductive component 340 is formed on the polymer layer 20 on the protective layer 18. However, the application of the present invention is not limited thereto, and the configuration of the polymer layer 20 may be omitted, but the inductive component 34 may be omitted. The germanium is directly contacted on the protective layer 18. As shown in FIG. 8b, the detailed structure and formation method of the inductor element 34 can refer to the detailed structure and formation method of the thick metal layer shown in FIGS. 2a and 2j-2m. After the inductor 340 is formed, a polymer layer 341 can be formed on the inductor element 34 and the protective layer 18. The material and formation method of the polymer layer 341 can be referred to the material of the polymer layer 20 as shown in the figure. And the formation method. 9a-9b are schematic cross-sectional views showing a transformer formed on a protective layer in accordance with a preferred embodiment of the present invention. The transformer includes a bottom layer coil 360 and an upper layer 31 1308785 ~ ^ Γ ~ ΤΓ 21) - aging date correction replacement page coil 366, wherein the bottom layer coil 360 and the upper layer coil 366 are fabricated by using a metal such as ® or Tu Xi - Shen The line process 'either uses the metal line process shown in FIG. 2g or FIG. 21-2m; or the bottom layer 36 turns is made by using a metal line process as shown in FIG. 2a_2f or FIG. 2j-2k, The upper layer coil 366 is fabricated by using a metal line process as shown in FIG. 2g or FIG. 21_2m. Alternatively, the bottom layer coil 360 can be fabricated by using a metal line process as shown in FIG. 2g or FIG. 21-2m. The upper layer coil 366 is fabricated by, for example, a metal wiring process as shown in FIGS. 2a-2f or 2j-2k. The two contacts for connecting with the bottom layer, 360 are, for example, metal contacts 16 that are electrically connected to the openings in the protective layer 18, and are formed on the two contacts for connecting with the upper coils 366. A tin-lead bump or a gold bump can be connected to an external circuit such as a printed circuit board or a gold wire formed by a wire bonding process can be bonded to the contact. In this embodiment, the bottom layer coil 360 is formed on the polymer layer 20 on the protective layer 18, for example, as shown in FIGS. 9a and 9c, and the material and formation method of the polymer layer 2〇 can be referred to as shown in FIG. The material and formation method of the polymer layer 20. Alternatively, the configuration of the polymer layer 2A may be omitted, and the underlying coil 36 is formed in direct contact with the protective layer 18, as shown in Figs. After forming the bottom layer coil 360 on the protective layer 18 or on the polymer layer 20, the polymer layer 50 can be formed on the bottom layer coil 36, as shown in Figures 9a-9d. If the application is applied to a process that does not require high precision, the material and formation method of the polymer layer 50 can refer to the material and formation method of the polymer layer 20 as shown in FIG. 1b, and the polishing process can be omitted. The layer 5 has a relatively flat upper surface because the upper layer coil 366 formed later is formed on the unevenness of the polymer layer 5, so that the upper layer coil 366 cannot achieve very high precision, as shown in the figure. 9a and 9b do not. If it is applied to a process requiring high precision on the circuit, the material and formation method of the polymer layer 50 can refer to the material and formation method of the polymer layer 222 as shown in FIG. 2i, and the process can be flat by mechanical grinding or chemical mechanical polishing. The polymer layer 5 〇 32 1308785 upper surface 'because the upper layer coil 366 formed later can be formed on the flat upper surface, the upper layer coil 366 can achieve higher precision, as shown in Figures 9c and 9d. After forming the bottom layer coil 360 on the protective layer 18 or on the polymer layer 20, a polymer layer 70 can be formed on the upper layer coil 366, as shown in Figures 9a-9d, the opening 77 in the polymer layer 70 can be exposed. By connecting the two contacts of the upper layer coil 366, by forming tin bumps or gold bumps on the contacts, the upper layer coil 366 can be connected to an external circuit such as a printed circuit board, or by a wire bonding process ^ The formed gold wire can also be bonded to this joint. Material and Forming Method of Polymer Layer 7 可以 Refer to the material and forming method of the polymer layer 2 如图 as shown in FIG. 1b, the polishing process can be omitted at this time, but the polymer layer 70 has a relatively uneven upper layer. The surface is shown in Figures 9a and %. The material of the polymer layer % and the forming method can also refer to the material and the forming method of the layer 222. At this time, the upper surface of the polymer layer 5 can be planarized by a mechanical grinding or a chemical mechanical polishing process, as shown in FIG. 9d. . 10a to FIG. 2C illustrate the capacitor surface 2 in accordance with the present invention, wherein the capacitor element is formed in a protective layer.

The i-pole has a lower electrode 342, a capacitor dielectric layer 346, and a stripe method of the upper 3 and the lower block 42 such as a metal circuit process of the Fig. 212 or: If the Ls is not used, or both are used as shown in the figure. % or electrode-(4) The method of making the method 5 is, for example, the profit line » process and the process; or, the mine is made of w/ or the metal circuit shown in Figure m shows the gold-touch process.纠 % _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Niobium pentoxide (Ta205), high-polymerized poly-small tea, γ~~I compound (Si#4) or oxonium compound (Si02), tetraethyl oxymethane (TEOS), barium titanate (SrTi) 〇 3) and the like, and the thickness of the capacitor dielectric layer 346 is, for example, between 500 angstroms and 50,000 angstroms. In this embodiment, the lower electrode 342 is formed on the polymer layer 20 on the protective layer 18, as shown in FIG. 1B and FIG. 3c, wherein the material and formation method of the polymer layer 2 can be Referring to the material and formation method of the polymer layer 20 as shown in FIG. 1b; or, the configuration of the polymer layer 20 may be omitted, and the lower electrode 342 is directly contacted on the protective layer 18, as shown in FIG. In this embodiment, a polymer layer may be selectively formed on the electrode 345 above the capacitor element, and the capacitor element is protected by a resistor. The material and formation method of the polymer layer can be referred to as shown in FIG. The material and formation method of the polymer layer 20.

Referring to FIGS. 10a to 10C, the lower electrode 342 and the upper electrode 345 of the capacitor element are, for example, electrically connected to the electrical pads 16 exposed by the openings in the protective layer 18; however, the application of the present invention is not limited thereto. For example, the lower electrode 342 of the capacitive element is connected to the electrical pad 16 exposed by the opening in the protective layer 18, and the upper surface of the connecting capacitive element is, for example, transmitted through a tin bump, a gold bump or a wire bonding process. The formed wire bonding wire is externally connected to the external circuit' without being connected downward to the opening in the protective layer 18 = the exposed electrical interface 16; or the electrode on the capacitor element is torn to the protective layer 18 The electrical contact pad 16 is exposed by the opening, and the electrical contact 16 formed by the contact block, the gold bump or the cake is formed under the capacitive element. And far away from 1Ge, since the capacitive element is formed on the protective layer 18, and it is separated from the bottom of the county, it can be called 34 1308785 between the capacitive element and the turn of the county. The page change exclusive +6 ^ . '月1日#' Baogu. Further, by using the above process, an electrode 342 and 345 having a thick thickness and a surface element can be formed, so that the resistance values of the two electrodes 342 and 345 of the capacitor element can be reduced, which can be applied particularly in the field of wireless.

The polymer layer 2 can be formed on the protective layer 18 with reference to Fig. 10b and Fig. 10', and the opening in the thick polymer layer 2Q can expose the electrical pads 16 through the patterning process. In one embodiment, the maximum lateral dimension of the opening of the polymer layer 2 is less than the largest lateral dimension of the opening of the security layer 18, and the polymer layer 2 is covered by the electrical pad 16 and exposed within the protective layer 18. A portion of the area outside the opening is shown in Figure 10b. However, in another embodiment, the maximum lateral dimension of the opening of the polymer layer is greater than the maximum lateral dimension of the opening of the protective layer 18, and within the polymer layer, the opening exposes the electrical pad 16 from being exposed to the protective layer. All areas outside the opening in 18. By the arrangement of the polymer layer 2〇, the arrangement of the capacitor elements can be shifted upwards by a distance equal to the thickness of the polymer layer 20, so that the capacitor element can be disposed farther away from the semiconductor substrate 1, so that the capacitor element can be greatly reduced. The parasitic capacitance between the electric 4 and the semiconductor substrate 1 is lowered. 11a-11c illustrate cross-sectional schematic views of a resistive element formed on a semiconductor wafer, the resistive element 448 being formed on the protective layer 18 or on the polymer layer 2''. The resistor element 448 is made of a material that can provide an electrical resistance, and current can flow through the material. The resistive element 448' can be formed by physical vapor deposition or chemical vapor deposition, and the material of the resistive element 448 is, for example, a nitrogen compound (TaN), a nickel-chromium alloy (NiCr), a nickel-plated alloy (NiSn), and a tantalum (W). ), Titanium alloy (Tiw), titanium nitride compound (TiN), chromium (Cr), titanium (Ti), nickel (Ni) or group Shishi compound (Ding said) and the like. Among these materials, Nichrome provides the best temperature coefficient of resistance (Temperature)

Coefficient of Resistance) can be as small as 5 ppm/°C. The length, thickness and width of the resistive element can be designed for different applications. Referring to lib and 11c', after forming the polymer layer 20 on the protective layer 18, the resistive element 448 can be formed on the polymer layer 20, and the resistive element S448 can be replaced by the 35 1308785 ι驴·1st page in the polymer. The opening in the layer 20 is connected to the electrical pad 16 ' in the protective layer 18. The material and the forming method of the polymer layer 20 can refer to the material and forming method of the polymer layer 20 as shown in FIG. . The distance between the resistive element 448 and the semiconductor substrate ( can be increased by the configuration of the polymer layer 2 ( (the increased distance is substantially equal to the thickness of the polymer layer 20) can reduce the resistance between the resistive element 448 and the substrate 1. The parasitic capacitance effect can improve the performance of the resistive element (since the loss of parasitic capacitance can be reduced, so the electrical performance under high frequency operation can be improved). However, it is also possible to dispense with the configuration of the polymer layer 2, and the resistive element 448 is formed in direct contact with the protective layer 18 as shown in Fig. 11a. Additionally, a polymer layer can be selectively formed on the resistive element 448 to protect the resistive element 448. Referring to lla-llc, the two contacts of the resistive element 448 are connected to the electrical pads 16 exposed by the openings in the protective layer 18; however, the application of the present invention is not limited thereto, and may be One of the contacts of the resistive element 448 is connected to the electrical pad 16 exposed in the opening of the protective layer 18, and the other contact is formed by a tin-lead bump, a gold bump or a wire bonding process. The wire bonding wire is externally connected to an external circuit, and is not connected to the electrical pad 16 exposed in the opening of the protective layer 18; or the two contacts of the resistive component 448 can pass through the tin-lead bump, gold The bump or wire bonding wire formed by the wire bonding process is externally connected to an external circuit, and the electrical interface 16 exposed in the opening of the protective layer 18 is not connected. Referring to Figures 12a and 12b', there is shown a fabrication of a passive component bonded to a semiconductor wafer in accordance with an embodiment of the present invention. In the present embodiment, the solder pad 452 can be formed on the electrical pad 16 so that the electrical pad 16 can be connected to the completed passive component 454 through the fresh material loose, wherein the completed passive component 454 is completed. For example, it is a completed passive component, a capacitive component, a resistive component or other passive component. A metal layer 45 can be opened to form an electrical connection 6 exposed in the opening in the protective layer 18. The solder can be formed into the metal by a conventional electromoney process, a ball-making process or a screen printing process. On the floor. 36 1308785

The stencil correction replacement page can be soldered onto the solder 452 when the completed passive component 454 is bonded to the solder 452, and the reflow process can be used to bond the fabricated passive component 454 to the solder 452. . The fabricated passive component 454 can also have solder 453, which can improve the bond between the fabricated passive component 454 and the underlying semiconductor wafer.

Referring to FIG. 12a and FIG. 12b, when the solder 452 is completed by an electroplating process, an adhesion/barrier layer such as titanium or chromium may be formed on the semiconductor wafer by sputtering, and then the sputtering method may be used. Forming a seed layer such as copper on the adhesion/barrier layer, and then forming a photoresist layer on the seed layer, wherein an opening in the photoresist layer may expose the seed layer, and then may be formed by electroplating A copper layer is formed on the seed layer exposed by the opening in the photoresist layer, and then a nickel layer is formed on the copper layer by electroplating, and then a solder layer 452 can be formed on the nickel layer by electroplating. The thickness of the solder layer 452 is, for example, between about 5 micrometers and 500 micrometers, and the material of the solder layer 452 is, for example, a tin-lead alloy or a tin-silver alloy. Thereafter, the photoresist layer can be removed, and then the seed layer and the adhesion/barrier layer not under the patterned solder layer 452 can be removed. In this embodiment, the metal layer 450 is composed of an adhesion/barrier layer, a seed layer, and a copper layer and a nickel layer formed by electroplating, and the thickness of the metal layer 450 is, for example, οι to 2〇. Between microns. Referring to FIG. 12a and FIG. 12b, when the solder 452 is completed by a screen printing process or a ball-planting process, an adhesion/barrier layer such as titanium or chromium may be formed on the semiconductor wafer by sputtering. Then, a seed layer such as copper is formed on the adhesion/barrier layer by sputtering, and then a photoresist layer is formed on the seed layer, wherein an opening in the photoresist layer exposes the seed layer, and then A copper layer may be formed by electroplating on the seed layer exposed by the opening in the photoresist layer, and then a nickel layer may be formed on the copper layer by electroplating, and then a gold may be formed by using a shovel. The layer is on the nickel layer, after which the photoresist layer can be removed, and then the seed layer and the adhesion/barrier layer not under the patterned copper layer, the nickel layer and the gold layer can be removed. At 37 1308785

Like 5. Month 1 替换ί Replacement Page I In this embodiment, the 'metal layer 450 is composed of an adhesion/barrier layer, a seed layer; a copper layer, a nickel layer and a gold layer formed, and the thickness of the metal layer 45〇 is as It is between 0.1 microns and 20 microns. Thereafter, a solder layer 452 can be formed on the gold layer of the metal layer 450 by a screen printing process or a ball bonding process, wherein the thickness of the solder layer 452 is, for example, between about 5 micrometers and 3 micrometers, and the solder layer 452 The material is, for example, tin-lead alloy or tin-silver alloy. In this embodiment, the gold layer used to connect the metal layer (4) of the solder layer 452 should not be too thick, for example, between 微米5 μm and 1 μm. Thus, the metal layer 45 can be prevented from being excessively diffused. In the gold to solder layer 452, the brittleness problem caused by the tin-gold alloy can be avoided. * Next, the circuit design made using a thick metal layer on the protective layer will be detailed. Referring to Figures 13a-13c, the green shows the line structure for distributing the supply voltage or ground voltage. The semiconductor wiring 12 is formed on the surface layer of the semiconductor substrate, and these semiconductors 12 may be NM 〇 s elements, PM 〇 s elements, and CM 〇 s elements. Each semiconductor component 12 has a plurality of nodes that can be connected to other lines or a power/ground line for connecting a power supply voltage (Vdd) or a ground voltage (Vss). A typical semiconductor component 12 includes a power supply node, a ground node, and a signal node. . An electrostatic discharge protection circuit is formed on the surface layer of the semiconductor substrate i for protecting the semiconductor element 12 from electrostatic discharge damage of a sudden inter-parameter. Both the semiconductor element 12 and the electrostatic discharge protection line are formed in the element layer 2. The 1C circuit layer 3 is formed on the element layer 2, within the ic circuit layer 3^, and the line 561 is connected to the semiconductor element 12 and the electrostatic discharge protection line 544. The protective layer 4 is deposited on the IC circuit layer 3, and is disposed on the protective layer. The opening in 4 can expose the electrical pads of the 1C circuit layer 3. In the embodiment, the semiconductor wafer structure under the protective layer 4 can refer to the semiconductor wafer structure under the protective layer 4 in FIG. The detailed structure and manufacturing method of the back cover layer 80 having the structure of the front V thick gold f line layer and the thick polymer layer in the back layer 80 of the protective layer 4 can be referred to the drawings and FIG. 3a 3d, The thick and wide connection network 566 is formed, for example, by one or more layers of thick gold. The thick and wide connection network 566 is formed in direct contact with the contact, which is 38,308,785 years old, thick and wide. The protection line 544 can pass through the interconnect 561 in the thick and wide line of the remote layer, and the electrical discharge of the plurality of semiconductor lines 12 = the network 566 is connected in parallel to be the power bus or power plane ^1, The thick and wide connection network 566 such as a thick and wide connection or 'electrostatic discharge protection line 544 can be grounded through the ground = ΠΓ electrically connected to a plurality of semiconductor lines in parallel to connect a thick and wide connection The wire network 566, such as a ground bus or a connection, and the bumps or gold bumps of FIG. 13 may be formed on a thick and wide L or a plurality of contacts 568 such that a thick and wide wire ground is provided. Connected to the power supply terminal or the external terminal of an external circuit such as a physical circuit board. Alternatively, the wires formed by the wire bonding process can be bonded to == one or more health points 568 to make a thick and wide wired network = end. Thick and wide (4) road board material red power supply end or grounding ^ j wide connection network 566 connected to the external line through a number of contacts distributed to the external line, can make a thick and wide connection network 566 is more stable and grounded. On the date of this issue, it is not necessary to connect to each of the connection 568 of the power supply or the connection of the external ground source to the different electrostatic discharge protection circuit 544, that is, an electrostatic discharge protection circuit can be torn. Electrically connected to a plurality of connections to the external power supply or electrically connected to a plurality of connected external grounding sources 568, a plurality of connections 568 connected to the external power supply or a plurality of external grounding sources connected to the ground Sharing an ESD protection line 544 together can reduce the power loss caused by the force of the ESD protection line 54. Referring to FIG. 13c, the electrical pads 16 exposed by the openings in the protective layer 4 can be electrically connected to the thick and wide wiring network 566 through a thin film line 98 under the protective layer 4, tin-lead convex A block or gold bump may be formed on the electrical pad 16 to form a wire 39 1308785. The wire formed by the process may also be continued on the surface. The hexadecimal f6 is not directly electrically connected to the external circuit, but is electrically connected to the external circuit through the protective Ϊ1^film line 98, wherein the length of the film line % is, for example, wrong between 5G and reddish 1_«. The value bottle is that after the wide and thick interconnect network S66 is completed, the electrical pads 16 are still exposed to the same. Referring to FIG. 13b'1C, the circuit layer 3 further includes a plurality of interconnect networks 567. In the case of the layer 4, the plurality of semiconductor elements n can pass through the interconnect network 567. The plurality of interconnect networks 567 can be transmitted through the protective layer 4, and the network 566 is connected to each other. Portions of the semiconductor component 12 can be connected to the thick and wide strap shoulder 566 located on the protective layer 4 via the interconnect network 567 located at = ^4. However, the application of the present invention is not limited thereto, and it is also possible that all of the semiconductors 12 are connected to the interconnected network having a thick and wide protective layer through the interconnect network located under the protective layer 4. 566, as shown in Figure i3a and Figure i3c. Clear reference ®I 13a to FIG. 13c' can be replaced by a thick and wide network 566 disposed on the protective layer 4, which can replace the thin and thin interconnected network under the protective layer 4 in the prior art. The metal connection of the power supply or the ground busbar, so that some of the thin interconnects can remove the thick and wide connection formed on the protective layer 4, so that the parasitic capacitance of the semiconductor component can be reduced. Line network Na is more affected by changes in external voltage. In the present invention, the thick and wide connection network 566 located on the protective layer 4 can be connected in parallel to the ESD protection line 544 and the multi- and half-element devices I and 2, Since the connection network located on the protective layer 4 is thick, it is necessary to reduce the occurrence of unintended power supply (p〇wer jobs). The external power supply pad or external ground interface of the turn-on wafer connected to the power supply or ground node of the other semiconductor layer 12 may not be located in the semiconductor wafer or in the semiconductor wafer. The electrostatic discharge protection circuit of the other half of the 1308785 conductor chip is electrically connected, and 1 = system ϊ γ γ is directly connected to the other semiconductor chip. The electrostatic discharge protection circuit of the mind is known as Figure 14a-14h. The position of the protection sound 4 is from the insect, such as the network for transmitting the clock signal, the address signal, and the information; Nabi signal, etc., typical semiconductor components... number or class, at this time thick and wide connection network 566 "" or 'thick and wide connection network 566 can also transmit from electric flip = cry output Power/ground voltage. The body line 12 is shaped like a ri layer; the ri layer 12 can be an _S element: a circuit, a receiving path, an electrostatic discharge protection line 544, and a driver line formed in the HH 45 and other semiconductor elements. 2 in the shape of the 曰, the ESD protection line 544 is used for the 鳟 12 受到 _ _ _ _ ! ! ! ! ! ! ! 上 上 上 上 上 上 上 上 上 上 561 561 561 561 561 561 561 561 561 561 561 561 561 Drive test green defeat, pull static forced discharge protection 5 篗 line guardian 4 series sink l # receiver line, input / output line 545 connection. Guarantee == 3 = 3 1 4 (four) port can be exposed to the structure can be phased i The semiconductor wafer under the protective layer 4 is a circuit layer and a thick group of people. The thick gold structure and the manufacturing method, the layer or multi-voice shown in Figure 1b and the figure are thick and visible in the layer 566, such as by a contact ground; The thick and wide connection network 566 is, for example, directly #上, μ,: θ 4 , or a connection network formed on a thick polymer raft on the protective layer 4, which is connected to the IC circuit layer. The internal interconnection line 1308785 road m power protection line 544 is electrically connected to the driver line, the circuit line or the input/output line 545 in parallel. The gathering person ίίζ i4ti4d 8q 57q can be exposed to the thick burial "outside" Tin bumps or gold bumps may be formed on the pad 570, open to the external circuit, or may be bonded to the pad by a wire bonding process, so that the semiconductor wafer can be connected. .57Ϊ2Ϊ circuit. The ESD protection circuit 544 is electrically connected to the external circuit. This can avoid the occurrence of #非细丝(SU1*ge).

- When it is touched. The signal transmitted from the outer surface 57G through the receiver line 545 can be redistributed to a plurality of semiconductor elements via the bit, and the thick interconnect network 566 is then distributed to the driver line 545. After being amplified by the drive ί 5 =, it can be transmitted to the outside via the pad 57〇. The interconnected network 566, which is worthy of being thick, is not electrically connected to the outside. Between the pads ESD protection line 544 = length = 100 Ξΐϊ; = the ratio of the winding length between the device or the output / input line 545, please refer to Figure 14e-14h, in the sound of the 4th eve f,塾1611路i offers (10) County Qingcheng _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ After passing through the (four) pads 16 - the clock signal or the flip 42 1308785, the processing of the party line 545 can be redistributed to the plurality of semiconductor components 12 via the protective layer = network 566; and from the 4 = factory 5 domain It can be retransmitted to the driver line 545 via a wide and thick interconnect network located on the layer 4, and is amplified by the driver circuit 545 to the outside. It is worth noting that it is wide and thick. Even the f Wei 566 system does not make an external electrical connection, and in the production of a wide and thick interconnect, Na read, the electrical pad 16 is still exposed. Electrical connection 16 to ^ [receiver, device or output The winding line length between the input line 545 and the input line 545 may be farther than the electrical pad 16 to the electrostatic discharge protection line 544. The length of the winding between the electrical pads 16 to the length of the winding between the driver, the receiver or the output/input line 545 is, for example, between 1 〇〇 micrometer and 1 cm. In addition, adjacent electrical pads The distance between 16 is, for example, between 1 〇〇 micrometer and 1 cm. Referring to Figures 14b, 14d, 14f and 14h, the IC circuit layer 3 further includes a plurality of interconnect network 567, located under the protective layer 4' The plurality of semiconductor elements 12 can be connected to each other through an interconnect network 567, and the interconnect network 567 can be connected to each other through a thick and wide connection network 566 located on the protective layer 4. Part of the semiconductor component 12 can Without passing, the interconnect network 567 is connected to the thick and I-connected network 566 located on the protective layer 4 under the protective layer 4. However, the application of the present invention is not limited thereto, and may be all. The semiconductor component 12 is not connected to the thick and wide wiring network 566 located on the protective layer 4 via an interconnect network positioned under the protective layer 4, as shown in Figures 14a, 14c, 14e and 14g. When the distance of the connection is long distance and/or the load of the net circuits is large, the chip An intra-chip driver or receiver may be necessary, as shown in Figures 14c, i4d, I4g, and 14h, where the so-called wafer-in-the-disk driver or receiver 58 is used for processing. Signal transmission between the semiconductor components 12 within the wafer, or for processing signals between the external driver or receiver 545 and the semiconductor components, wherein the so-called crystal 43 1308785 chip is used for the external driver or receiver 545 The ## transmission between the wafer internal driver or receiver 580 and the external circuit is processed. These intra-chip drivers or receivers 580 are typically smaller than the chip external (0g:chip) driver or receiver 545, and the intra-chip driver or receiver 580 has a smaller sense amplifier (se- g —lifler), smaller latched input circuits (latched _ circuits) and “cascade stage.” In terms of the ability to detect signals, the sensitivity of the receiver is affected by the sense amplifier and the lock input. The effect of a line or series circuit. The chip-to-inside driver or receiver 580 does not have an ESD protection line and an input/output line. However, for short-distance intra-wafer wiring, a wafer-to-in-chip driver may not be required. Or the receiver, as shown in Figures 4a, 4b, 4e and 4f. Referring to Figures 14c, 14d, 14g and 14h, in the same semiconductor wafer, the signal can be transmitted via the secondary drive. Or the processing of (4) 545 and 58G is to the semiconductor component 12 or the external circuit; or the transmission of the signal can be transmitted to the semiconductor component 12 via only one driver or receiver 545, as shown in FIG. 4a and FIG. 4b, Fig. 4e and Fig. 4f. Fig. = shows a two-cylinder, receiver or input/output line 545, which is connected to the driver and the junction 545 to electrostatic discharge by using a thick and visible connection network 566. The protection line 544' is provided to the input/output line 544. Each driver, the receiving electrostatic discharge protection line a^AW input/output line 545 is connected through the thick and wide metal line 566 of the accommodating layer 2 to protect the connection. Under the layer 4 = the device 12. The driver, the connector or the input / rim ^ 544 can pass through the back protection layer 8 塾 in the electrical protection line in addition, so that the thick and bound lines on the protective layer 4 The discharge protection circuit 544 is connected to each other by electrostatic electricity as shown in Fig. 14j. The driver is connected to the 1308785 layer 15d. The plurality of semiconductor elements 12 are connected through the protection ί-wire network 566. In this embodiment, The guides are not connected to the external circuit through a wide and thick connection network 566. Insulators do not need to provide ESD protection lines or input/output lines for the disk connection network 566 connection. A thick connection network can be used for threats: if it is a semiconductor component 1 The transmission distance between 2 is very close.

In particular, the receiver or the relay is provided to process the signal transmission between the semiconductor components. The thickened connection network 566 is not required to be connected to the semiconductor component U via the receiver or the driver, such as Figure and said. If the transmission distance of the semiconductor element ^2 is very long, the component layer 2 can provide a signal transmission between the receiver or the driver = semiconductor = component 12, in which case a wide and thick connection network is applied, read and receive n or The crane is connected to the semiconductor component 12, and the receiver or driver is smaller than the receiver 1 or switch which is generally used for processing the disconnection between the external circuit and the external circuit. Referring to Figures 15b and I5d, the 1C circuit layer 3 further includes a plurality of interconnect network 'positions under the protective layer 4'. The plurality of conductor elements 12 can be interconnected via the interconnect network 567. The thick and wide connection network on layer 4 connects to the interconnect network 567. Portions of the semiconductor component 12 can be connected to the thick and wide wiring network 566 located on the protective layer 4 via the interconnect network 567 located under the protective layer 4. However, the application of the present invention is not limited thereto, and all of the semiconductor elements 12 may be connected to the thick and wide wired network located on the protective layer 4 via the interconnecting network located under the protective layer 4. 566, as shown in Figures 15a and 15c. Figure 16 illustrates the use of a series of drivers/receivers 6 (M, 602 or converters 6〇3 (tranSceiver) to transmit a signal from a semiconductor component to another semiconductor device 12b. Through a series of repeaters or The converter 603 and the wide connection 666 located at the protective layer 4 45 1308785 can transmit signals between the semiconductor components ❿ and 2 separated by a distance. The repeater or the converter 6 〇 3 generally includes a The device 6G2 and the driver 6G1 can be connected to the driver 6〇1 through the line 613 located under the protection 4, and the thickness and width of the transmission layer 4 can be transmitted between the two repeaters or the converter 603. The connection _ connection. After the semiconductor is processed and outputted by the 6G1, only the axis is protected at 6曰03, and the line 666 is transmitted to a series of repeaters or converters to receive H in the protection layer 4. Thick and wide connection 666, transmission

=== After the processing of 1f(10) is over, the semiconductor wafer structure that can be transferred to the semiconductor layer under the semiconductor layer 4 can refer to the semiconductor wafer structure under layer 4. With a thick metal circuit layer and a thick Ϊ method, the structure shown in FIG. 1b and FIG. 3a - 3d of the sigh layer 80 is thick and the thickness of the read layer 666 is made by one or more layers. The upper and wider lines 666 are formed, for example, in direct contact on the protective layer 4 or on a thick polymer layer on the protective layer 4. The dry 曰4 is used to make the (four)-connected wafer of the semiconductor element = the criterion of the column is used to determine whether the driver or the receiver is to be mounted; "When the distance of the device is less than D, the driver or the connection is not required. Then the thick and wide line f ^ connecting the way around the __ is greater than D, the guiding center Du, after connecting to the j-type driver or receiver, is connected to the half or the receiver means less than - and externally Electrostatic coffee (4) Schematic diagram of the internal structure of electricity that does not need to be connected. It is located on the semiconductor substrate; 46 1308785 Layer ϊ can refer to the description of the 1C circuit layer in phase 1a, where 74G is a film) 丨 electrically layer, 741 For the second line of the thin film metal layer, the polymer layer 742 located on the protective layer 18 on the thin film dielectric layer 740 can refer to the poly-port shown in FIG. 1b, the material of the layer 20 and the manufacturing method 'thick metal layer 743 The detailed structure and formation method of the thick metal layer shown in Fig. 2j 2m can be shown in the polymer layer 742 ^ / detailed structure and formation method.

17, in the present invention, the thickened metal line on the protective layer 18 is reduced in thickness. In the embodiment, the thickness t2 of the adhesive/barrier layer, the seed layer and one or more layers of the wire is thicker than The next day of the thin film metal layer under layer 18: the thickness U of 741, and the multiple of the thickness is between about 2 and 1, _ times. The line 743 is formed as a connection line, and its width W2 ^ the width of the thin line 741 is 2 to 100 wide and ‧ = f and the thickness t2 of the metal line 743 is about 2 micrometers to slightly The width 1 of the 曰1 is 2 or more and 2 μm, the line pitch s2 is greater than or equal to 2, and the metal line 743 as seen may have a lower resistance value. Connection 1 Please refer to FIG. 17 'As far as the structure under the protective layer 18 is concerned, the fine dielectric sound 740 has a history of about 2 micrometers, the width W1 is about 10 micrometers, and the thin film electrical layer $40 has A _ = Μ about 2 micrometers. The line spacing S1 is about 10 microns, the film dielectric & visibility w2 is about 10 microns, and the thickness of the polymer layer 742 is amine. Under the above-mentioned element, the polymer layer 742 is a thin inner metal layer 741 and a thin metal layer under the protective layer 18 to make the gold layer on the protective layer 18. The difference in the thickness of the metal line 743 on the layer 1 can be the thickness of the metal in the layer = the resistance value of the road 7743 is lower than that of the film under the protective layer, so that the resistance value can be 2.5 times smaller. After the % of the above-mentioned strips are connected, the metal structure of the sheath metal layer can be 6.25 times smaller, or about 5 times smaller than the thin metal connection line of the thin film metal connection line under the protective layer. 47 1308785 Thin two =: 'Please refer to Figure 17 for the protective layer 18 ^ ^ 溥 film metal layer connection line 741 10 micron, thin film dielectric layer 740 thickness t H 1 micron, width Wl is about micron The thin film dielectric layer 740 is about 〇·5 μm, and the line spacing S1 is about 2, and the thickness of the object layer 742 is about 5 μ half / the visibility W 2 is about 1 〇. The micron' polymerization 742 system is a polyimine. Under the above-mentioned stop parts, the S2 is about 10 micrometers, and the film of the polymer layer with the squeaking sound belongs to the thin connecting line of the metallurgical layer of the protective layer after the protective layer. The product of the resistance and capacitance is small and thin. The structure of layer 18 is 0.2« , m^774〇^ ^ 0.2 μm, and the dielectric layer of the dielectric film is dioxide; ^ === structure, metal The thickness t2 of the line 743 is about 5 μm, the width of the double layer is ::5, and the thickness d2 of the polymer layer 742 is about 5 μm. The micropolymer layer 742 is a poly-imine. Above

The film connection resistance value of the gold-SC protective layer of the line 741 and the protective layer is higher than that of the upper layer. Under the above conditions, therefore, the fine metal layer of the metal layer under the double layer S is only electro-sensitive === In another embodiment, in terms of the structure under the protective layer 18, the thin film metal layer 48 1308785 The connection line 741 has a thickness t1 of about 4 micrometers and a width wl of about 2 micrometers thin; the thickness dl of the tantalum layer 740 is about 〇.4 micrometers, and the line spacing si is about 微米2 micrometers. The electrical layer 7 is made of sulphur dioxide; in terms of the structure on the protective layer 18, the metal line 743 has a thickness t2 of about 1 〇 micrometer, a width w2 of about 1 〇 micrometer, and a thickness 介 of the dielectric layer 742. 1 〇 micron, the line spacing s2 is about 4 〇 micron, and the dielectric layer 742 is a poly-imine. Under the above conditions, the difference in thickness between the fine inner connecting metal line 741 of the fine metal layer of the sacrificial layer τ and the metal line 743 of the protective layer 18 can make the resistance value ratio protection of the metal line 743 on the protective layer 18 The resistance value of the thin inner connecting metal line 741 of the thin tantalum metal layer under the layer 18 is less than 1,2. Therefore, under the above conditions, the protective layer of the thin metal layer under the protective layer 18 can be made 10,000 times higher than that of the thin metal layer under the layer 18. According to the above discussion, the resistance-capacitance product of the fine-layered metal structure on the protective layer 18 is less than 5 times to 1 〇 _ between the thin-connected lines of the protective layer 18 and the protective metal layer. Dielectric Resistor Capacitor The dielectric layer on the protective layer 18 - several advantages of the present invention: 1) due to the use of thick and wide metal, lines (resulting in resistive dielectric polymers (causing parasitic capacitance values i see The resistance-capacitance product value of the metal line can therefore improve the response rate of the signal and improve the performance of the integrated circuit. 2) It does not need to be used in the sub-micron integrated circuit, and it does not need to be in the condition of the sub-micro-accumulation circuit. More rigorous clean room: Made in Becher's ^' or less. However, the back cover of the present invention is made of 2, /, or more, and 3). The thick metal which is placed on the protective layer of the present invention is easy to integrate 49 1308785 row, ground bus and timing distribution network. (The method of clocking the 晶片 Ι ί 统 clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock Substrate_, part or 4 to all can be replaced by a thick metal line on the layer. This can be used to make the _bga base (4) domain. Replace the line gold bumps and wire conductors to make the thick layer on the protective layer The lining is connected with two types of fan-out connectors, reconfiguring the joint position, reducing or increasing the padding to increase the design flexibility. By thick metal lines on the protective layer, reconfigure the pad position, Reduce or increase the number of pads, such as two bumps, lead bumps, gold bumps or wire pads are placed in the appropriate place, and polycrystalline === miscellaneous, especially in her package (four) method '=) Second power: =^ and the square of the distribution signal, the maximum size of the ^^^ port can be It is between 25 micrometers and 0.1 micrometers. ^= 麟 织 之 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ To replace the function of the BGA connection line, a thin rear cladding metal structure (a metal structure located on the protective layer). In this way, the BGA substrate design is thus made simpler and the cost can be greatly reduced. Although the invention of the present invention is as disclosed above, the financial scale (four) defines Ben Maoming 'any "this person" does not deviate from the spirit and the inside of the present invention, and therefore the scope of protection of the present invention is regarded as Attached to the application; the scope defined by the scope of guidance is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a is a schematic view of a semiconductor wafer of the present invention. Figure lb is a cross-sectional view of a semiconductor wafer of an embodiment of the present invention. 2a to 2m are schematic cross-sectional views showing a manufacturing process of a thick metal line. 3a to 3d are schematic cross-sectional views showing a semiconductor wafer of the present invention. Figures 4a, 5a, 6a, and 7a$ show the concept of fan-out pads, interface changeovers, reduced pad configurations, and increased pad configurations through printed circuit boards. The road meeting 6b and the material of the thick and wide metal line passing through the protective layer are now fan-out pads, receiving money for position, reducing the pad configuration and increasing the interface configuration. 8a and 8b are schematic cross-sectional views of the inductor element on the protective layer. Fig. 9a - 9d _: A schematic view of a cross section of a preferred embodiment of the present invention formed on a protective layer. The upper conductor 曰^曰 figure. 11a to 9c are schematic cross-sectional views showing the formation of a resistive element on a rotor wafer. Figs. 12a and 12b are schematic views showing the bonding of a completed passive component to a semiconductor wafer in accordance with an embodiment of the present invention. 51 1308785 Figures 13a-13c illustrate the line structure for distributing the supply voltage or ground voltage. 14a-14J are schematic diagrams of a thick and wide wired network positioned on a protective layer in accordance with an embodiment of the present invention. 15a through 15d are schematic views of a thick and wide wired network positioned on a protective layer in accordance with an embodiment of the present invention. Figure 16 is a diagram showing the use of a series of drivers/receivers connected to the network. From the view of U, and see Figure 17, a schematic diagram of the structure of the semi-guided (10) of this (4).

[Simple description of the list] Table 1 shows the product of the heterocapacitance of the metal structure on the listening layer. [Description of Patterns] 1 : Semiconductor Substrate 2: Element Layer 3: 1C Line Layer 4: Protective Layer 10: Semiconductor Substrate 12: Thin Film Dielectric Layer 12a: Semiconductor Element 12b: Semiconductor Element 14: Metal/Dielectric Layer 16: Electrical pad 17: opening 18 in the protective layer: protective layer 20 · polymer layer 26 . thick and visible metal line 52 1308785 27 : opening 28 in the polymer layer : opening 29 in the polymer layer : protective layer Opening 30: Thick metal layer 40: Arrow 42: Arrow 44: Arrow 50: Polymer layer 60: Thick metal layer

70: polymer layer 77: opening 80 in the polymer layer · · back cover 97: thick metal line 98 · short distance interconnect 99: metal cover 100: integrated circuit 101: tin-lead bump 102: tin Lead bump 103: tin-lead bump 104: tin-lead bump 105: tin-lead bump 107: line 111: ball solder ball 112: ball solder ball 113: ball solder ball 114: ball solder ball 115: Ball soldering ball 53 1308785 119 : Gate 120 : Source (Source) and Drain diffusion layer 121 : Tin-lead solder ball 122 : Tin-lead solder ball 123 : Tin-lead solder ball 124 : Tin-lead solder ball 125 : Tin-lead solder ball 130 : BGA substrate 131 : Metal line in BGA substrate

132: Line 134 in BGA substrate: Line 136 in BGA substrate: Line 138 in BGA substrate: Tin solder ball 140: Tin-lead solder ball 142: Tin-lead solder ball 151: Line 153 in BGA substrate: BGA substrate Line 155 inside: Line 161 in BGA substrate: Tin solder ball 162: Tin-lead solder ball 163: Tin-lead solder ball 164: Tin-lead solder ball 165: Tin-staggered solder ball 200: Adhesive/obstruction layer 202: Seed layer 203: thick photoresist layer 204: metal layer 54

1308785 205: recess 206: metal layer 222: polymer layer 223: opening 301 in polymer layer: metal pad 302: metal pad 303: metal pad 304: metal pad 305: metal pad 311: connect External point 312: Connect external point 313: Connect external point 314: Connect external point 315: Connect external point 321: Connect external point 322: Connect external point 323: Connect external point 324: Connect external point 325: Connect external point 328: Connect External point 330: connected external point 332: connected external point 340: inductance element 341: polymer layer 342: capacitive element lower electrode 345: capacitive element upper electrode 346: capacitive element capacitive dielectric layer 55 1308785 360: transformer Bottom coil 361: Connect external contact 362: Connect external contact 363: Connect external contact 364: Connect external contact 365: Connect external contact 366: Transformer upper layer coil 448: Resistive element 450: Metal layer

452: Solder 453: Solder 454: Passive Element 544: Electrostatic Discharge Protection Line 545: Driver Line, Receiver Line, or Input/Output Line 561: Interconnect Line 566: Thick and Wide Connection Network 567: Interconnect Network Path 568: Contact 570: Pad 580: Wafer inward driver or receiver 601: Driver/receiver 602: Driver/receiver 603: Converter 613: Line 666: Thick and wide connection 740: Thin film dielectric Layer 741: Thin film metal layer line 56 1308785 742: Polymer layer 743: Thick metal layer

57

Claims (1)

1308785 X. Patent application scope: h. Electronic component structure, including: bottom electrostatic discharge protection circuit component; body open I static, discharge protection circuit component, - semiconductor component and - second semiconductor 7 position on the recording bottom; a #膜-f film metal layer on the germanium substrate, the electrostatic discharge protection circuit element two semiconductor elements and the second semiconductor element; a Plai if, located on the first thin film metal layer, the dielectric layer Included in the first opening, the first thin film metal layer is exposed; a == adhesive/barrier layer is disposed on the dielectric layer and the first openings; and the inner thin film metal layer is located at the first The second thin film metal layer on the adhesion/barrier layer and the first opening #2" includes an electroplated copper layer on the first adhesive/barrier layer and the first openings The ESD protection circuit component opens the second opening and the fourth opening exposes the first: the thin electric discharge protection wire U-contact and the pad, the pad is connected to the static polymer layer, and is located on the protective layer The fifth layer of the polymer layer - the first contact and the second connection Point, the polymer layer has a thickness of one metal line, is located on the polymer layer, connects the first contact and the connection, and the line includes a second adhesion/barrier layer on the polymer layer , the contact and the second contact, the seed layer is on the second adhesive/transfer layer, and the connection = (2) 2 = t: the first semiconductor component is connected to the wire via the metal wire. 2. As claimed in the patent specification, the electronic component structure of the invention, the wire metal protection layer, located above the base of the crucible and on the second thin film metal layer, the protection 58 1308785 cover each month The Wi% page-changing layer comprises copper. 3. The electronic component structure as described in claim 1, wherein the layer comprises gold. 4. The electronic component structure as described in claim 1, wherein the recording layer further comprises a recording layer 5. The electronic component structure as described in claim 1, wherein the polymer layer comprises a poly-branched amine. 6. The application of the electronic component described in the first item Structure, the protective layer of the towel comprises the most abundant layer of nitrogen in the structure of the electronic component Compound sound. 7. == The electronic component structure of the description 'where the poly is 8. The electronic component structure of the second C is the first-turn 9. The electronic component barrier layer as described in the scope of claim 1 includes A metal layer containing titanium. Weighing /, 〒 ^ sticky / 10. If you apply for the special 娜 帛丨 帛丨 骑 电子 / / / / / / / / / / / / / / / / / An electronic component structure, comprising: an electrostatic discharge protection circuit component of a substrate; a semiconductor component 'located on the germanium substrate; a brother's special film metal layer, located on the stone substrate And the upper surface of the semiconductor element is located on the first thief metal layer, the dielectric layer includes a plurality of first open violent roads out of the thin film metal layer; second, = adhesive/barrier layer, located in the On the dielectric layer and in the first openings; (10) a film metal layer 'on the first adhesion/transfer layer and the second second opening-adhesive; the barrier copper layer 'the electric clock copper layer is at the first Reading the position above the secret substrate and the second thin film metal layer, the opening, the third opening and the fourth opening exposing the second thin, 59 1308785 film gold joint, - second Contact and pad; —-- a door/gate: 1乂2 on the protective layer 'the polymer layer - the fifth opening and the ϋΐ ΐ ΐ contact and the second contact, the polymer layer The thickness of the polymer layer is connected to the first layer, and the second portion of the second layer is in the second layer. On / barrier layer, a seed layer Μ on which the metal layer comprises copper electroplating Wei; ifί i a bit above the ground and the protective layer Sook; and a block / contact connected to the metal layer of the rainbow. In the electronic component structure of item 11, the towel further comprises a nickel layer on the plating metal. The secluded octagonal and 匕祜 13. As the scope of the patent application, the u layer includes - polyamidamine. The electronic component structure of the U-th aspect, wherein the polymer, H t is formed by the sub-tree to eject the topmost layer of nitrogen-wet. • The layer package application ^ ^ surrounded by the ^Tuo said the power of the county structure, correct the polymer% === two items _ sub-element structure, wherein the first viscous 17. As described in the scope of claim u丰丰姓# — The / barrier layer consists of a metal layer containing titanium. The electronic component structure of the eleventh item, wherein the first adhesive/barrier layer comprises a metal layer containing titanium. Fu/, A 汲弟一粘 19. An electronic component structure, comprising: a germanium substrate; a semiconductor component 'positioned on the germanium substrate; = Ϊ Ϊ bottom and the semiconductor component; (4) a metal layer, the dielectric layer comprising a plurality of 1308785 openings exposing the first thin film metal layer; a first adhesion/barrier layer on the dielectric layer and the first openings a second thin film metal layer is disposed on the first adhesive/barrier layer and the first openings, the second thin film metal layer includes an electroplated copper layer, and the electro-copper layer is located on the first adhesive layer And a barrier layer on the first opening; a second protective layer positioned above the germanium substrate and the second thin film metal layer, a second opening, a third opening and a The fourth opening exposes a first contact, a second contact and a pad of the second thin film metal layer; a polymer layer is disposed on the protective layer, and the fifth opening of the polymer layer And a sixth opening exposing the first contact and the second contact, the polymer layer being thicker than the dielectric layer a metal line, located on the polymer layer, connecting the first contact and the second contact, the metal line including a second adhesive/barrier layer in the polymer layer, And a second sub-layer on the second adhesion/barrier layer, an electro-mineral metal layer on the hetero-sublayer, the electroplated metal layer comprising electro-mineral gold; a metal layer, located in And above the protective layer; and the wire bonding wire 'connects the metal layer on the interface. 20. The electronic component structure of claim 19, wherein the layer comprises a polymethyleneamine. The object 2L is as claimed in the patent specification 帛19, and the protection is in the topmost layer of the Nitrogen compound in the structure of the electronic component.曰A layer, such as the electronic component structure described in the polymer item, wherein the first-viscosity 24 is as described in claim 19 of the electronic component cover/barrier layer Includes a metal layer containing titanium. Electronic components,,,. In the case of the electronic helium structure described in claim 19, the/barrier layer comprises a metal layer containing titanium. "弟一粘61 1308785 26·—Electronic component structure, including: year, month, and day correction machine page; a static discharge protection circuit component, a first semiconductor component, and a second semiconductor component a first thin film metal layer positioned on the germanium substrate, the electrostatic discharge protection circuit component, the first semiconductor component and the second semiconductor component; a dielectric layer positioned on the first thin film metal The dielectric layer includes a plurality of first openings exposing the first thin film metal layer; an adhesive/barrier layer on the dielectric layer and the first openings; a second film a metal layer on the first adhesion/barrier layer and the first openings, the second thin film metal layer comprising an electroplated copper layer on the first adhesion/barrier layer and The first opening; a protective layer on the base of the stone and the second thin film metal layer; a polymer layer on the protective layer, and a second opening in the polymer layer , a third opening and a fourth opening storm Exposing a first contact, a second contact, and a pad of the second thin film metal layer, wherein the polymer layer has a thickness greater than the pad of the dielectric layer to connect the electrostatic discharge protection circuit component; X a metal line Positioning on the polymer layer, the second opening and the third opening, connecting the first contact and the second contact, the metal circuit comprising a / φ barrier layer in the polymer layer, the a first contact and a second contact, wherein the seed resides on the second adhesive/barrier layer, a plating metal layer is on the seed layer, and the metallization layer comprises electroplated copper, the first semiconductor component The second semiconductor component is connected to the metal layer via the metal, and is disposed on the pad and the fourth opening of the polymer layer; and the tin-containing bump is connected to the metal layer on the pad. Wherein the polymer 27. The electronic component structure of claim 26, wherein the layer comprises a polymethyleneamine. 28. The electronic component structure as claimed in claim 26, wherein the protective layer 62 1308785 is a compound layer. ®5: Replace J F 29. If the scope of application is 26th = trace compound layer. The "s~*- layer includes a phenylcyclobutene. An electronic component structure in which the polymer 30. The barrier layer as described in claim 26 includes a nitride button. . A 70-piece structure in which the first paste 31. The flip-flop/26 barrier layer/metal barrier layer includes a metal layer containing titanium. ',, ", /, the first stick. 32. The barrier layer as described in claim 26 includes a metal layer containing titanium. ', σ, /, the second adhesive 33. An electronic component structure, comprising: a substrate; a body building member, a first semiconductor component and a second semiconductor component, the viewing line element The electrical layer is located on the first-thin metal layer, the opening of the dielectric layer exposing the first thin film metal layer; the/obstacle layer is located on the dielectric layer and the first openings; a thin film metal layer 'on the first adhesion/barrier layer and the second openings to the - Γί·-thin metal layer comprises an electric ore copper layer, the electroplated copper layer is located at the first adhesion layer And on the barrier layer and in the first openings; the younger-protective layer is located above the base of the stone and on the second thin film metal layer; a polymer layer is located on the protective layer, the polymer a second opening, a third opening and a fourth opening in the layer exposing a first contact, a second contact and a pad of the second thin film metal layer. The polymer layer has a thickness greater than the a thickness of the dielectric layer, the pad is connected to the electrostatic discharge protection circuit component; a metal circuit is disposed on the polymer layer, the first Connecting the first contact and the second contact in the opening and the third opening, the metal line includes a second adhesive/barrier layer on the polymer layer, the first contact and the second connection Point, a sub-layer 63 _v 1308785 1 genus is at the seed h, the second semi-conductor is connected to the conductor element via the metal line, and the genus layer is on the pad and the polymer layer In the fourth opening; the metal layer on the pad is connected by a wire bonding wire'. 34·layer 帛33 tear-shaped 1 sub-stock storage, the polymer 35 package tear-shaped electron element storage, the protective layer 36 layer, such as the package of the solution of the traitary storage, the material 37. The electronic component structure, the + the first spliced electronic component structure, wherein the (four) 39 =========================================================================== a substrate; an electrostatic discharge protection circuit component, a first semiconductor element and a two-body component on the germanium substrate; a == thin film metal layer 'located on the stone substrate, the electrostatic discharge protection circuit component, the a first semiconductor element and the second semiconductor element; a dielectric layer on the first thin film metal layer 'the dielectric opening exposes the first thin film metal layer; a first, landing/barrier layer Positioning on the dielectric layer and the first openings; a first thin film metal layer on the first adhesive/barrier layer and the first openings, the second thin film metal layer including An electric ore copper layer, the copper layer of the electric bond is on the adhesive layer/block layer of the 64 1308785 and the In the opening; a replacement page-protective layer is located above the base of the stone and on the second thin film metal layer; a polymer layer is located on the protective layer, and one of the polymer layers is θ' - the third opening And the thin opening exposes the second metal layer = a point, a second contact, and a pad. The polymer layer has a thickness greater than the dielectric sound. The pad is connected to the ESD protection circuit component; a metal line on the polymer layer, the second opening and the inside, connecting the first contact and the second contact, the metal line _: H barrier layer in the polymer layer On the first contact and the second contact, on the second adhesive/barrier layer, an electro-mineral metal layer is on the seed layer, == copper 'the first semiconductor component via the metal And a metal layer is located on the pad and in the fourth opening of the polymer layer, and the metal piece on the interface is connected by a wire. 4! The electron layer of the fourth paragraph of the patent application includes a polyamine. Fu 〃 Txiankou 42. The electronic component structure described in the patent scope f 4〇, the protective layer in the basin The electronic component structure of the first embodiment, wherein the first adhesive member has an electronic component structure, wherein the second adhesive component is an electronic component structure, comprising: a substrate; 65 1308785 9隼7净·秘£ Replacement page 半导体 a semiconductor component, located on the germanium substrate, __ a first thin film metal layer, located above the germanium substrate and the semiconductor component. - dielectric layer, located in the On the first-thin metal layer, the dielectric layer includes a plurality of openings to expose the first thin film metal layer; * a first adhesion/barrier layer on the dielectric layer and the first openings; The second thin film metal layer is located on the first adhesion/barrier layer and the first opening=the second two thin film metal layer comprises an electroplated copper layer, and the electric ore is located on the first adhesive/barrier layer And the first openings; the shin guard is located above the bottom of the bottom and the second metal layer, the film is open - the second opening and the "fourth opening σ expose one of the first contact, the second contact and the first pad of the second thin film metal layer; - the polymerization (10), the recording system, the spine: the brain , the thickness of the tender layer is large - ίί'ίί 'connects the first contact and the second S point ίίΐ ί ϊΐ on the polymer layer - the second adhesive/transfer layer is in the polymer layer, the first mine The seed layer is on the second adhesive/barrier layer, and an electro-mineral metal layer is recorded on the germanium layer, the metal layer includes an electric clock copper; a metal layer is located on the pad and above the protective layer And a wire conductor that connects the metal layer on the pad. 4==. The electronic component structure of item 47, wherein the polymer is dictated by a sub-tree of the protective layer, and the protective layer % μ ^ electrons emits the topmost nitrogen-based layer of the electron. The electronic component structure described in the item, wherein the polymer 51 is torn--the first-adhesive 52. For example, the application of the electronic component structure, wherein the first-viscosity 66 1308785 Wherein the second adhesion/barrier layer comprises a metal layer comprising titanium. 53. The electronic component structure/barrier layer of claim 47, comprising a metal layer comprising titanium. 54. An electronic component structure comprising: a germanium substrate; a germanium conductor component and a second semiconductor component on the ground substrate; a town-germanium metal layer, the hetero semiconductor, the first semiconductor component And above the conductor element of the Leyi cattle; a first electrical layer comprising a plurality of first openings exposing the first thin film metal layer; a first, a barrier layer on the dielectric layer And the first opening; the second thin film metal layer is disposed on the first adhesive/barrier layer and the first openings, the first thin film metal layer comprises an electroplated copper layer, and the electrowinning copper layer Positioning on the first adhesive/barrier layer and the first openings; a protective layer on the germanium substrate and on the second thin film metal layer; a layer of the layer on the protective layer a second opening in the polymer layer and a third opening π exposing a first contact and a second contact of the second thin film metal layer. The polymer layer has a thickness greater than the dielectric layer. a metal line in the polymer layer, the second opening and the third opening connecting the first contact and the second contact, the metal line including a second adhesive/barrier layer Above the protective layer, the first contact and the second contact, a sub-layer is on the second adhesive/barrier layer, and a plating a platoon layer on the seed layer, the plated metal layer comprising electroplated copper, the metal line connection connecting the first semiconductor element and the fourth semiconductor element via the third opening, the fourth opening exposing one of the metal lines a third contact; and a metal bump connecting the third contact. 55. The electronic component structure of claim 54, wherein the polymer layer comprises a polymethyleneamine. 56. If the electronic component structure described in the patent application is applied, the protective layer of the protective layer 67 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 L - a layer of a ^-benzene structure, wherein the polymer " is as described in the electronic component structure, wherein the electronic component structure is as described, _ 6. Such as: == two: the description of the electronic component structure 'where the second sticky 61. An electronic component structure, comprising: a stone substrate; a device and a second semiconductor tree positioned on the hetero-substrate; a first metal layer of the metal layer is located at the germanium, the first semiconductor component and The upper layer of the first thin film metal layer is exposed on the first thin film metal layer to expose the first thin film metal layer; the dielectric layer includes a plurality of =, two, and / resistance a barrier layer on the dielectric layer and the first openings; the first thin layer, the metal layer 'on the first adhesion/barrier layer and the first-opening, the first-thick metal layer Including an electric ore copper layer, the electric copper layer is located on the first adhesive/barrier layer and the first openings; a protective layer is disposed above the germanium substrate and the second thin film metal layer a layer of the layer on the protective layer, a second opening and one or two openings in the polymer layer exposing a first contact and a second contact of the second thin film metal layer The thickness of the polymer layer is greater than the thickness of the dielectric layer; a metal line located in the polymer layer, the second opening and the third Connecting the first contact and the second contact, the metal line includes a second adhesive/barrier layer above the protective layer, the first contact and the second contact, a sub-portion Positioned on the second adhesion/barrier layer, a plated metal layer is disposed on the seed layer, the plated metal layer comprises electroplated gold, and the metal line connection is replaced by the second opening and the ^ 168 1308785 ij -1 j — yl f open: connect the first-half Wei component to the first and second wire of the metal line and connect the third contact. 13=/1 ^(4) turn, shoot the polymer layer package ^-benzene n%6. 1 MW « Record 65ί Kokusaki's electric carrier structure, shoot the first component of the electronic component structure, of which the first sticky The 61st item of the electronic component structure of Saki, the early layer of the second adhesive/resistive p includes a metal layer containing titanium. 68. An electronic component structure, comprising: a germanium substrate; a = f power amplifier circuit component and a semiconductor component, located on the heterosole; and a device located at the bottom of the wire, the electrostatic discharge protection circuit element a ΪΪ layer is disposed on the first thin film metal layer, the dielectric layer includes a plurality of first openings violently exiting the first thin film metal layer; and a ^/, a barrier layer is located at the dielectric layer And a first thin film metal layer on the first adhesive/barrier layer and the first openings, the first thin film metal layer comprising an electroplated copper layer, the electroplating a layer of copper on the first adhesion/barrier layer and the first openings; a protective layer positioned over the substrate and on the second thin film metal layer; a second opening and a second opening in the polymer layer exposing a first contact of the second thin film metal layer and a second contact 69 1308785, the polymer layer having a thickness greater than the dielectric layer The thickness of the month; the replacement page of a metal line, imitation a take people k β^ .. 1 — -* ^ Θ 乂, :, , the fish ίίίί 'in the polymer layer a, the second opening and the third opening barrier layer are in the Baoding; the point is connected - the first: the three opening connection line is connected through the second opening The first component and the semiconductor component, the polymer exposing a third contact of the metal line; and the wire bonding wire 'connecting the third contact. 70. The electronic component structure described in claim 68, wherein the protective layer is the most nitrogen-based layer of the 7! In the case of Kosaki's trait, the polymer 72 is based on the electronic component structure described in Item 68. The first adhesive/barrier layer comprises a metal layer containing titanium. % 'The electronic/barrier layer as described in the scope of the patent application includes a metal layer containing titanium.偁八甲娜-粘75. A kind of electronic component structure, including: a hair base; two electrostatic discharge circuit components and semiconductor components, located on the financial substrate, and; The ESD protection circuit element is disposed on the first-thin metal layer, the dielectric layer enclosing an opening to expose the first thin film metal layer; and the first adhesion/barrier layer is located in the On the dielectric layer and in the first openings, 1308785 _ household ^ 擎 '月7·曰!! Replace the Gonggao one thin metal layer, located on the first adhesion/barrier layer ^: The first thin film metal layer includes a layer of a copper oxide layer on the first adhesive/barrier layer and the first openings; the protective layer is located above the financial substrate and On the second thin film metal layer; the second layer 'is located on the protective layer, and the second opening i in the polymer layer is the first contact and the second a thickness of the polymer layer is greater than a thickness of the dielectric layer; an inner: ϋί路 & is located in the polymer layer, the second opening The third opening two tiii point and the second contact 'the metal line includes - the second adhesive / two: ΐ ί ί 3 three-layer seven squares, the first contact and the second contact, the seed 曰 position On the early layer of the first viscous/resistance JI, a metal electric sound electric current, the metal circuit is connected to the circuit component and the semiconductor component by the ί2, and the polymer ΪΓ exposes one of the metal wires a third contact; and a metal bump connecting the third contact. 76 layers 7=^. The electronic component structure of item 75, wherein the polymer sub-element structure is directed to the layer of the most nitrogen-digested layer of the protective layer. Touching the electronic component structure of the polymer article, wherein the first spliced electronic component structure, wherein the first viscous 81 is an electronic/barrier layer as described in claim 75 The invention comprises a titanium-containing metal layered electronic read structure, wherein the second adhesive 82. is an integrated circuit wafer structure, comprising: a stone base substrate; 71 a bonding/barrier layer on the dielectric layer and the first openings. - = a thin film metal layer on the first adhesion/barrier layer and the third 1308785 口' '苐2 thin tantalum metal layer includes an electroplated copper layer, the electroplated copper layer 彳 | $-adhesive/barrier layer and the first-opening; the weaving position is calming: ί ϊ ' ί Above the Shishi base and the second thin film metal layer, the first layer of the second thin film metal layer is exposed in the protective layer; the metal line is located in the second opening And above the protective layer, the first 3 includes a second adhesion/barrier layer above the protective layer, the second opening ^ and the brother-contact, and the first seed layer is at the second adhesion On the barrier layer, a first electro-mineral metal layer is on the first seed layer; two first polymer layers are located on the first metal line, and the second layer is exposed in the polymer layer a second contact of the first metal line, the polymer layer has a thickness greater than a thickness of the dielectric layer; a first metal line, located on the first polymer layer, the second contact In the second opening, the second metal line includes a third adhesion/barrier layer on the polymer layer and the second contact - a second seed layer on the third adhesion/barrier layer, one or two electroplated metal layers on the second seed layer; and a second polymer layer on the second metal line. The integrated circuit wafer structure as described in claim 82, wherein the first polymer layer comprises a polyamine. 8) The integrated circuit wafer structure as described in the patent application scope, Wherein the protective layer comprises a nitrogen-containing layer at the topmost layer of the electronic component structure. 85. The integrated circuit wafer structure of claim 28, wherein the first polymer layer comprises 86. The integrated circuit wafer structure of claim 82, wherein the adhesive layer/block layer comprises a nitride button. 卞月87. The integral-adhesive/barrier layer described in claim 82 includes a metal layer containing titanium. The ruthenium sheet structure, wherein the ninth aspect is as described in claim 82. The layer comprises a metal layer containing titanium. The ruthenium sheet, the 构 structure, wherein the 89th. The second polymer layer of the integrated circuit according to Item 82 includes a poly-methyleneamine. The sheet, the structure of the film, wherein the product layer of the product of claim 82 is included in claim 82. Phenylcyclobutene. Roller sheet structure, wherein the 91st. As described in claim 82, the first adhesion/barrier layer comprises a metal layer containing titanium. The ninth embodiment of the integrated circuit chip structure includes: a dream substrate; a semiconductor component on the enamel substrate; a first-thin film gold layer at the bottom of the recording and the semiconductor An electrical layer on the first thin film metal layer, an opening exposing the first-lying metal layer; the n-layer including a plurality of first-adhesive/barrier layers on the dielectric layer and the The on-metal layer is located on the first adhesion/barrier layer and the two second thin film metal layers comprise an electroplated copper layer on the first adhesion/barrier layer And the first openings; a β-protective layer, located above the secret substrate and on the second thin film metal layer, one of the protective layers The first opening exposes a first contact of the second thin film metal layer; a first metal line located in the second opening and above the protective layer, the first metal line including a second adhesion/resistance a barrier layer is located above the protective layer, in the second opening and the first contact, a first seed layer is on the second adhesion/barrier layer, and a first plating metal layer is located in the first layer a sub-layer; a...=first polymer layer on the first metal line, the second opening in the polymer layer exposing a second contact of the first metal line, the polymer layer Thick 73, of which the first And wherein the first, wherein the first, wherein the first portion is greater than the thickness of the dielectric layer; the one, the road, the first polymer layer, the second contact, and the f ΐ/ί second metal line includes a third adhesion/barrier layer on the polymer layer, and a second seed layer on the second contact layer in the third adhesion/barrier layer A second electroplated metal layer is on the second seed layer, the second electrowinning layer includes an electroplated gold, and a second polymer layer is disposed on the second metal line. 93. The integrated circuit wafer structure of claim 92, wherein the polymer layer comprises a poly-branched amine. 94. The integrated circuit wafer structure of claim 92, wherein the protective layer is included in the (10) compound layer of the electronic component structure. 95. The integrated circuit wafer structure of claim 92, wherein the first polymer layer comprises a phenylcyclobutene. 96. The integrated circuit wafer structure of claim 92, wherein the adhesion/barrier layer comprises a nitride button. . θ ^ 97. If the application is for the 92nd job of the circuit chip structure, the adhesion/barrier layer includes a metal layer containing titanium. 98. The integrated circuit wafer structure of claim 92, wherein the second adhesion/barrier layer comprises a metal layer comprising titanium. 99. The integrated circuit wafer structure as described in claim 92, wherein the layer comprises a polyamine. 100. The integrated circuit wafer structure of claim 92, wherein the first polymer layer comprises a phenylcyclobutene. The integrated circuit wafer structure of claim 92, wherein the third adhesion/barrier layer comprises a metal layer comprising titanium. An integrated circuit wafer structure comprising: a germanium substrate; a semiconductor component on the germanium substrate; a first thin film metal layer over the germanium substrate and the semiconductor component; 74 1 1308785; An electric raft is disposed on the first thin film metal layer, the dielectric layer includes a plurality of first openings exposing the first thin film metal layer; and =i=f/block layer on the dielectric layer And the first openings; the D, the thin, the metal layer on the first adhesion/barrier layer and the first openings of the first film metal layer comprise an electroplated copper layer, the electroplated copper layer On the first adhesive/barrier layer and the first openings; $ is: a protective layer, located above the dream substrate and on the second thin film metal layer, the second opening in the protective layer Exposing a first contact of the second thin film metal layer; - a line located in the second opening and above the protective layer, the second adhesive/barrier layer being above the protective layer, the second On the open point, the -f-seed layer is on the second/barrier layer, and the electro-potholes are in the first seed layer. 'The first electric clock metal layer comprises - the second position on the first metal line, the degree in the polymer layer = one of the second contacts of the intermetallic line, the polymer layer thickness - ii the first - On the polymer layer, the second contact and the adhesion/barrier layer are on the polymer, a first seed layer includes - electroplated copper in the third adhesion/barrier layer; and - the first A shovel metal layer and a second polymer layer are positioned on the second metal line. 103. The integrated circuit wafer structure of claim 1, wherein the first polymer layer comprises a polymethyleneamine. r 106. The integrated circuit wafer structure according to claim 102, wherein 75 1308785 97Γ 7: an i8 ·, ', the first adhesion/barrier layer comprises a nitride group . . 107. The integrated circuit wafer structure of claim 102, wherein the first adhesion/barrier layer comprises a metal layer comprising titanium. 108. The integrated circuit wafer structure of claim 102, wherein the second adhesion/barrier layer comprises a metal layer comprising titanium. 109. The integrated circuit wafer structure of claim 102, wherein the second polymer layer comprises a polymethyleneamine. 110. The integrated circuit wafer structure of claim 102, wherein the second polymer layer comprises a phenylcyclobutene. The integrated circuit wafer structure of claim 102, wherein the third adhesion/barrier layer comprises a metal layer comprising titanium. t 76 1308785 VII. Designated representative map: (1) The representative representative of the case is: Figure 1. (2) The symbol of the symbol of this representative diagram is briefly described: 1 : Semiconductor substrate 2 : Component layer 3 : 1C wiring layer 4 : Protective layer 80 : Rear protective layer VIII. If there is a chemical formula in this case, please disclose the best indication of the characteristics of the invention. Chemical formula: