TWI301617B - Method and apparatus to improve nonvolatile memory data retention - Google Patents

Description

J301617 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The technical field of the present invention relates to non-volatile memory. Techniques for preservation of data in non-volatile memory cells affected by electrical thinning or other data storage errors (such as reading; selection: loss of boundary) and [prior art] by Lai-Newton Critical Lay algorithm The storage density added to the cells in the coffee cells is usually reduced by two 7L per non-volatile memory cells. For charge trapping memory cells, nanocrystalline memory cells, and other memory cells with localized charge structures, each cell in the partial charge partial multi-step threshold voltage algorithm encodes at least two bits. , 7", and, so many multi-step threshold voltage algorithms require many different threshold voltages. For example, a 2-bit design requires four threshold voltages, and a 3-bit design requires human boundary voltage. State, etc. If you want to squeeze out these multiple threshold voltage states within the threshold voltage range allowed by the cell, the boundary between adjacent critical voltage states will be narrowed, resulting in a non-critical voltage state. Aggregation is closer. However, such a threshold voltage algorithm will cause data errors due to charge leakage, boundary loss and interference. Figure 1 shows an example of a threshold voltage design algorithm for a non-volatile memory cell. Figure 1 shows: 低·8ν initial distribution of a low threshold voltage state 110, loop boundary 120 is 0.4V, room temperature and readout interference 13〇 is 〇15V, final threshold voltage interval 140 is 0.7V, charge loss boundary 15〇 is 〇·7 v and - the local critical voltage state 16〇 is the distribution of 〇·7ν. The following table shows the threshold voltage corresponding to different points along the voltage axis. 5 J301617

Boundary mode 15μΑ Target component ΙμΑ Vth 111 115 —^_1^5V 1.90V 2.3V 125 2.7V 135 __4.0V 2.85V 145 3.55V 155 5.4 V 4.25V 165 L__6.1V _ 4.95V Therefore 'it is better to be different The threshold voltage states are clustered closer together' and there is no increased risk of data storage errors due to disturbing adjacent threshold voltage conditions. SUMMARY OF THE INVENTION One object of the present invention is directed to a non-volatile memory volume circuit that includes non-volatile memory cells, memory cells, sense amplifier circuits, and control circuitry. Lu non-volatile memory cells include data cells and border detection cells. The data cell system is set as a data group. In some embodiments, the data set is determined by controlling the word line of a particular non-volatile memory cell. The data cells have a first working boundary. In some embodiments, the data cell has a charge loss boundary of less than 0.7V, a charge loss boundary of about 0.2V, a loop boundary of less than 〇·4ν, and the data cell line has at least two logic steps. Many levels of cells. This reference current circuit produces a reference current. Each reference current has a high sensing interval to sense the high threshold voltage and a low sensing interval to sense the low critical voltage. The reference current is 1) a standard reference current associated with a first operating interval having a first high sensing interval and a first low sensing interval, 6 J301617 2) a first monitoring reference current, associated In a second working interval, the second working interval has a second high sensing interval narrower than the first high sensing interval and a second low sensing interval shorter than the low sensing interval of the younger brother. And 3) a second monitoring reference current associated with a third working area, the third working area=having a third high sensing interval that is wider than the first high sensing interval and a narrower than the The third low sensing interval of the first low sensing interval. In some embodiments, at least one of the first and second monitored reference currents is at a lower boundary than the standard reference current and a high threshold voltage cell. In other embodiments, at least one of the first and second monitored reference currents is lower than a high boundary between the standard reference current and a low threshold voltage cell. ^ The sense amplifier circuit uses the standard reference current to sense a memory current from one of the plurality of data cells to produce a first result. The sense amplifier circuit also senses the memory current using one of: a first monitor reference current to generate a second result, and a second monitor reference current to generate a third result. In some embodiments, the sense amplifier includes a single set of sense amplifiers to sense the memory current from the data cells, and the standard reference current, and to the first and the second monitor current One of them is connected in series. In some other embodiments, the sense amplifier includes a plurality of sets of sense amplifiers for respectively sensing the standard reference current, and utilizing at least one of the first and second monitored reference currents from the negative cells Recall current. In still other embodiments, the sense amplifier includes a plurality of sets of sense amplifiers for sensing the utilization of the standard reference current, respectively, and utilizing the first and second monitor reference currents to record current from the data cells. The comparison logic compares the first result with at least one of the second result and the third result from the sense amplifier circuit. In various embodiments, the comparison logic responds to one of the comparison results as 7 J301617 when the memory current falls outside the second working boundary or the charge is lost from a non-volatile memory cell. Touch, ίίϋexample/contains the external accessibility of the circuit (4), and there is an output of the integrated circuit that is used in the output makeup r =: ί;==Γτ;:4 to: The frequency is shown in the embodiment - the first result control should compare which of the second gentleman 1 flute results with the first result; =, ί - data cells. For example, this standard refers to an electrical multiplexer to select a second result or a third result. In the other real 'j 抖 田 田 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 In his embodiment, if the home of her quasi-reference current is used - the result is the high threshold voltage, then the result = the second wire is _, and if the standard conversion current ^ ^ is the low threshold voltage , the position - the result and the third result of the first two cases in the 'in a memory operation' only use one of the first - monitoring reference and the second monitoring reference current. In some embodiments, a control circuit is further included that is configured by applying a bias voltage to the data cells (10) in response to a memory user mode command. Bean" The user mode age (4) The receipt of the circuit causes the control circuit to bias and place at least the data cells of the poor cells to generate the memory current. The craft circuit updates the at least-data cell in response to an error in the first result that is consistent with one of the second result or the second result. It is another object of the present invention to provide a method of operating a non-volatile memory, comprising: responding to a memory user mode command to perform a step of applying a bias configuration to a non-volatile memory data cell to generate a representation store The memory value is one of the data values in the non-volatile memory cell, and the data values are associated with a low threshold voltage and a high threshold voltage. a step of generating a reference current, each of the reference currents having a high sensing region 8 J301617 to sense the high critical and/or domain interrogation_low threshold voltage, comprising: generating a standard parameter, a substep of the current, It is associated with a first working interval having a high sensing interval and a first low sensing interval. Generating a sub-plane of the -first-controlled reference current, which is associated with a second working interval, the second I-interval having a second high sensing interval narrower than the first high and - wider than the first A measurement interval of a low sensing interval. and

Generating a second monitoring reference electrical sub-step, the phase being in a third working interval, the third guarding interval having a wider throne than the first high sensing interval and - narrower than a third low-sensing interval of the first-low_interval; using the standard reference current to sense the at least one memory current to generate a first result, and further performing at least one of the following: a substep of monitoring a reference current to sense the at least one-memory current to produce a second result, and

Sensing the at least one memory by the second monitoring reference current to generate a third result substep; and wherein the L is compared to the first result, and the second result and the third result are at least one of Flute- ̄ ί ί ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ The current senser - monitors the reference current to sense and utilize the second monitor parameter - in series. In still other embodiments, at least only the first monitored reference current is utilized to "and utilize one of the reference currents to sense one of the two." In some embodiments, the first result control should compare which of the second result or the ninth 1301617 third result is compared to the first result to determine whether the at least one data cell needs to be updated. In other embodiments, if the first result of using the standard reference current is the high threshold voltage, the first result is compared with the second result, and if the first result of using the standard reference current is The low threshold voltage is then compared to the third result. Other embodiments further include: updating the at least one data cell in response to an error in the first result that is consistent with the second result or one of the third results. [Embodiment] Fig. 1 shows a graph of a critical voltage distribution of a non-volatile memory cell. 105 is the low limit of the initial threshold voltage. 11〇The initial distribution interval. The m system is the intermediate value of the initial threshold voltage. The 115 system is the high limit of the initial threshold voltage. 12〇 is the cyclic boundary of the low threshold voltage. Room temperature drift and readout interference of the 130 series threshold voltage. The 140 series circuit reads the interval and the final critical dust interval of the array cells. 150 series charge loss interval. The low limit of the 155 series high threshold voltage distribution. 16〇 is the critical voltage of the stylized cells. The high limit of the 165 series high threshold voltage distribution. Figure 2 shows a schematic diagram of the non-volatile memory cells divided into a data memory portion and a boundary detection memory portion, respectively, which are determined by a data sense amplification | § portion and a boundary detection sense amplifier portion. The data memory portion of the non-volatile memory cells includes data regions from 1 to N 21 (). The content of this data portion of the non-volatile memory cells is amplified by data sensing to a portion 215. The boundary detection memory portion 220 of the non-volatile memory cells includes a plurality of portions, and each portion corresponds to a different one of the data memory segments 1 to N 210. Thus, each data memory segment has at least one pair of boundary detection memory cells. Each section of the data memory includes a plurality of memory cells of 1301617 that are respectively taken by the word line. In one embodiment, each word line of the memory cell has at least one corresponding boundary detection memory cell. The content of the boundary detection memory portion of the non-volatile memory cell is read by the boundary detection sense amplifier portion 225. Therefore, the content of a specific portion of the data memory portion 21 can be read in parallel with the content of the corresponding portion of the boundary detecting memory portion 220. The valley within the boundary detection memory portion 220 sensed is then compared to the initial content of comparison block 235. If an error occurs in the comparison, the corresponding data cell block needs to be updated. By storing at least one initial value from the boundary detection array to the comparison block 235, the boundary detection array data can be

The initial values are compared, wherein the comparison block 235 includes a comparison memory and a comparison circuit. Figure 3 shows a schematic diagram of memory cells divided into a data memory portion and a boundary detection memory portion, the content of which is determined by a sense amplifier portion. Then, the sensed content of the boundary detection memory portion is compared with the initial content of the comparison memory 335. The memory cells of Figure 3 are similar to the memory cells of Figure 2. However, the sense amplifier portion 315 is simultaneously used by the data memory portion of the non-volatile memory cells including the data segments 1 to N210 and the boundary detection memory portion of the non-volatile memory cells 22 including a plurality of portions. Each of the plurality of parts corresponds to a different data memory section 1 to N210. Therefore, the contents of a specific portion of the data memory portion 21 can be read in series with the contents of the corresponding portion of the boundary detecting memory portion 220. The data sensed from the boundary detection memory portion 220 can be compared to the original value in the comparison block 235. ^ Figure 4 shows a threshold voltage design algorithm for a non-volatile memory cell having a narrow charge loss boundary compared to the threshold voltage design algorithm of Figure 1. The threshold voltage of the 155 Series data array is divided by the lower 4 limits. The 411 line boundary detects the initial distribution of cells. The circulatory boundary of the 441-series data cell D1. The boundary boundary of the 442-line boundary detection cell D2. 451-line side J301617 The high-threshold voltage distribution of the boundary detection array. The narrower threshold voltage distributions 411 and 452 correspond to the low threshold voltage state and the high threshold voltage state of the boundary detection cells, respectively. The high threshold voltage state of the data cells corresponds to a standard reference current level and a wider charge loss boundary 441. The low boundary of the high critical voltage state 452 of the boundary detection cell corresponds to a monitored current reference level 442. Since the boundary detection high threshold voltage state 452 has a narrower range than the standard current reference level 441, errors that cannot maintain the charge in the corresponding boundary detection cells will be detected earlier than the error of the data cell. Corresponding to the narrower boundaries of the bounded cells, thus controlling the new plasma of the data memory cells. The table below shows the threshold voltages corresponding to different points on the voltage axis. $ Algorithm, - data cells do not need to be maintained for a long time - large charge loss ^ Based on this algorithm, the data cells can maintain - smaller Wei boundaries and improve the memory of the volatilized memory cells. Monitor the reference f Μ (_it can be adjusted to monitor the C.M. Τ·············································

Target component ΙμΑ

12 j3〇l617 #t $ —for the threshold of non-volatile memory cells _ design deduction ϊ ϊ ϊ 记忆 memory cells have narrow cycle boundaries and charge loss boundaries ^ 临界 threshold voltage distribution 511 and 552 respectively corresponding to the boundary Cell, shirt, and high-critical state. The fine J critical record is programmed to the critical voltage level β3 155. This boundary check ΐίΐί *critical voltage level system B3, 55G. Between the high-throttle level B, 550 of the boundary detection cells and the final critical voltage interval B2, 551 has a - rut boundary. And between the high critical voltage level B3 of the data cell and the final critical, the pressure interval B2 165 has a wider boundary. Therefore, no > staying with the corresponding reference cell towel error will be detected earlier than the data cell error. Corresponding to the narrower boundary of the border detection cells, this controls the update time of the data memory cells. The table below shows the threshold voltages corresponding to different points on the voltage axis ^. According to this algorithm, the data cells do not need to be long-lasting - large charge loss boundaries. Based on this algorithm, data cells can maintain I, small 5 cycle boundaries and improve the working range of non-volatile memory cells. The critical voltage 511 can also be adjusted to monitor the CM&RT+RD· interval to narrow this interval and improve the working range.

13 1301617

Ll^J_^l6v 1 — 4, 45V ] Fig. 6 shows a job flow chart for controlling the output of the R/B pin signal to display the status of the update function. In 610, a user mode command is received, such as reading, programming, erasing, reading an identification code, and the like. In 62〇, the sensing action is performed. In 630, the result of the sense amplifier is used to confirm whether the update cycle & bound fails due to the narrowing of the working boundary. If there is no error, 635 waits for the next sensing operation. If there is an error in 640, the signal of the standby/busy pin is at the low level. Therefore, a state machine controls the standby/in-use pin k number in response to the detected error. Finally, in 650, the error cell is updated to the data cell line. ~ Figure 7 shows a job flow diagram for controlling a plurality of R/B pin signals to show the status of the update function. This job establishes an update function in the memory. In 702, a user mode command is received, such as stylizing a particular data memory cell. The R-pin signal (Pin R_bl) goes to the low level. In 7〇4, the user mode starts. In 706, it is confirmed whether the data memory cell needs to be updated. If an update is required, the job continues to 7〇8 and stores the sector address. If no update is required, the user mode is stopped in 7丨〇. Similarly, after 708, the job continues in 71〇 and the user mode is stopped. At 712, depending on whether there is an update. If there is no need for updating, the job ends in 720, and the R-bl and R-b2 pin signals go to the high level. If there is a need for an update, the job continues to 714. In 714, the R-M pin signals to the high level, and the R-b2 pin signals to the low level. In 716, in the absence of the first update, the system will output and complete the final mode result, but will not be able to enter any new user commands. In 718, the memory system is updated, located via the segment address and stored in 7-8. The job ends in 72〇' and the R-and R-b2 pin signals go to the high level. The following truth table shows the state of the memory indicated by the R-Μ and R-b2 pin signals. 14 J301617 R—bl RJ)2 Standby 1 1 In use (Busy) 0 X Update (Refresh) 1 0

Figure 8 shows the critical voltage distribution of a memory cell. 8〇1 is the low limit of the low critical voltage distribution B1. The high limit of the 802 series low threshold voltage distribution B2 \ 8 〇 5 is the low limit of the high threshold voltage distribution B3. 8〇6 series high threshold voltage distribution B4 high limit. A standard sense amplifier will use a standard reference current (normal-Iref) 807 to sense memory data and have a boundary D1 810 for charge loss of high threshold voltage cells and charge gain for low threshold voltage cells. Boundary D2 811. In the absence of an update, the memory needs to provide a large interval to allow the memory cells to obtain charge loss or charge gain, for example, after 1 ε cycle and 1 year later. This design imposes a considerable loss on a wide circuit sensing interval, especially for multiple levels in a cell. Therefore, the use of additional monitoring reference currents 1 (monitor-Irefl) 808 and monitoring reference currents 2 (monit〇Uref2) 809 can reduce the threshold voltage boundary of memory cells in memory sensing. For example, the monitoring reference current 808 has a sensing boundary D1, 812 that is narrower than D1 810 and a sensing boundary D2' 813 that is wider than D2 811, so the monitoring reference current j has a high threshold voltage. A smaller sensing interval for cells and a larger sensing interval for cells with low threshold voltage. Since the monitoring reference current is one, a high threshold voltage cell is more likely to fail than a low critical voltage cell, so the monitoring reference current j is used to detect the boundary of the high critical voltage. When the high threshold voltage of the memory cell produces a charge loss, the sensing with the monitoring reference current of 1 will fail, but the sensing with the standard reference current will still pass. If the logic data sensed by the standard reference current is a high pro 15 • 1301617 boundary voltage leaf 'slightly accurate reference current sensing current 1 sense of the first - logic caution · poetry = Bei Zhu dish control reference ' then the f The body will understand that the memory cell of this memory cell needs = more sensing boundary m, 816 and one relative to D2 8 ^

D2,, ^7, therefore monitoring the reference current - 2 has - for low critical power ^ = smaller ^ then 3 and - for a larger sensing interval of high threshold voltage cells. Due to the use of the 彡 电流 — — — — — — — — — — 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低* Memory cells <A low threshold voltage produces a charge gain, and the sense with the monitor reference current of -2 will fail, but the sense with the standard reference current will still pass. If the standard reference money domain is measured: #_—low threshold voltage, the logic data of the standard reference current system will be compared with the second logic data sensed by the reference current 2 . If the comparison result is a mismatch, then the memory will know that the memory cell of the memory cell needs to perform an update. Monitoring Reference Current-1 and Monitoring Reference System-2 can be used separately or simultaneously. For example, when the negative material is 1, it is compared with the first logical data; if the data is =0, the second logical data is compared. This description describes the high threshold voltage of the cells and the charge gain of the cells with low threshold voltages. Another embodiment has charge loss from low threshold voltage cells and charge gain in high threshold voltage cells. Figure 9A shows a job flow diagram for performing parallel sensing to determine whether to perform the update function. The data cells 910 are obtained via word lines and bit lines. A data cell selected from the data cell 910 provides measurement of current memory current cells (memory_Icell) 911 via one of the one-dimensional lines. The measured current memory current cell 911 is sensed by the standard sense amplifier 922 using the standard reference current 912 to obtain the normal data 901; and the monitor sense amplifier 923 is used to monitor the reference current -1 913 Then, the first logic data 16 • 1301617 902 is obtained and sensed, and is sensed by the monitoring sense amplifier 924 using the monitoring reference current one 2 914 to obtain the second logic 903. The first logic 902 and the second logic 903 are input to a data multiplexer (data_MUX) 925 and selected by the standard data 901. If the standard data 9〇1 is a high threshold voltage, the data multiplexer 925 will output the first logic data 9〇2 as the input to the comparison logic 930. If the standard data 9.1 is a low threshold voltage, the data multiplexer 925 outputs the second logic 903 as an input to the comparison logic 930. The comparison logic block 930 also receives the standard data 9〇1 as an input. The k-quasi-sensing amplifier 922 compares the memory current cell 911 with a reference current 912 of the reference voltage and produces a standard data 9〇1 output. The supervisory sense amplifier 1 923 compares the memory current cell 911 with the monitor reference current 1 913 and produces a first data 9〇2 output. The monitor sense amplifier, the memory current cell 911 is compared with the monitor reference current one 2 914, and the second logic data 903 is output. Based on the comparison logic 930 comparing the output of the standard 901 to the data multiplexed 925 output, the comparison logic 930 outputs a match or mismatch result to the state machine or microcontroller, and the sorrow or micro control The device 940 will determine whether to update the data memory cells selected from the data memory cells. Figures 9B and 9C show the correlation diagrams for the use of monitoring • reference current -1 instead of monitoring reference current -2, and the use of monitoring reference current ^ instead of monitoring reference current-1. If only one monitoring test current is applied, the data multiplexer 925 will be unnecessary. / Figure 10A shows a job flow diagram for performing serial sensing to determine if the update function is to be performed. In tandem sensing, the memory does not require additional dish control amplification states 923 and 924. The standard sense amplifier is sensed in multiple cycles with different reference voltages, standard reference current, monitoring reference current, and monitoring reference current 2 . This workflow can be performed in non-volatile memory (as shown in Figure 8) and there is no need to monitor the sense amplifier. In ι〇ι〇 中' according to the standard data memory operation, the standard sensing implementation system uses the standard reference .1301617 ΐϋ reference electricity such as the production of the standard output. In 1015 Lai (four) dumped 11 g (four) electricity °). In the secret, the monitoring current of the reference current 12 is monitored to produce a sensing-being output. In the middle, the first logical data is stored to the temporary i^rglsterJ). In 1030, the second monitoring sensing system monitors the control data to generate an output of the sensed second logic data. In , check the logic data to the scratchpad 2 (four) coffee-2). For example, 1040 data; if the standard data is high critical, then compare dreams at 1045, t:, temporary savings 1 ’ if the standard data is low critical, then at 1050 than ‘two Tnlf temporary state 2. In 1〇55, the check data is matched or not f +, if the data does not match, it is updated. Figure 10B and Λ f"7 female display to the new control reference Wei" _ no test reference current reference current -2 (four) no monitoring reference button 1 pattern. Applying only the right-monitoring reference current will not use step 1040. Heart ϋ f series - integrated non-volatile memory cells and updated circuits 2 early, thinking. The integrated circuit test includes a memory array 1150, and the array on the two-body substrate uses non-volatile memory cells and ΐϊίϋϊί. The _115G memory cells can be individual cells that are connected to a row of towels, or are connected to each other at a complex number == coupling to a plurality of words read 1102 set along the row of the array 1150. - The column decoder is integrated into the memory array, and a plurality of bit lines _ are placed. The address is provided in the busbar Cong Cry, Γ 111 111 111103 and row decoder 110 data sensing amplification, boundary detection amp, data input structure, and comparison block in the box 经由 via the data concentrator The coupled-to-column decoder is provided by the line 1111 from the input/output & on the integrated circuit 1100, or other internal or external data source from the integrated circuit 1100, to the operator of the block 11G6. structure. #料 is via (4) output line (1) 5 18 J301617 The sense amplification in block 11G6 is the input / f = on the integrated circuit η (8), or to other internal or external data destinations of the integrated circuit _. , eight hard configuration device 1109 control bias configuration supply voltage η 〇 8 = such as used to erase the confirmation and stylization confirmation voltage, and used to stylize, erase, and read memory cell configuration. ί上图—The integrated circuit with non-volatile memory cells and updated circuits. The integrated circuit 12A includes a memory array 115A,

ΐ 资料 A data and measurement area of a non-volatile cell on a semiconductor substrate. The memory cells of the cells may be individual cells that are attached to the array of towels or interconnected to a plurality of arrays of towels. The data sensing comparison block and the data input structure in the box are coupled to the column decoder 11〇3 via the resource 1107. The data is supplied to the data input structure in block 1106 via the data input line from the input/output terminals on the integrated circuit 1200, or from the gossip of the integrated circuit, or from an external data source. The data is passed from the block header to the input/output terminals on the integrated circuit 1200 via the data output line 1115, or to other internal or external data destinations of the integrated circuit 12 (8). Figure 1 is a simplified schematic diagram of an integrated circuit with non-volatile memory cells and a renewed circuit. The integrated circuit test includes - memory _ 135 〇, using the data memory cells on the semi-conductor plate. The memory cells of the array 1350 can be individual cells that are interconnected to the array or interconnected to each other. - Line Decoding ^11Q1 is conjugated to a plurality of characters, lines 1102 set along the line of memory array 1350. A column of decoders Π03 is coupled to a plurality of bits ^ i ^ 104 disposed along the column of memory array 1350. The address is provided on the bus 11〇5 to provide to the column decoder n〇3 and the row decoding n iim. The fine-grained H, the monitor-made A|i, the comparison block, and the data input structure in block 1306 are coupled to the column decoder 1103 via the data bus. The material is supplied to the data in block 13〇6 via the data input line 1U1 from the input/output terminal on the 19/1301617 body circuit 1300, or other internal or external data source from the integrated circuit 13〇〇. Input structure. The data is from the sense amplifier in block 13〇6 via data output line 1115 to the input/output terminal on integrated circuit 1300, or to other internal or external data destinations of integrated circuit η(8). Figure 14 is a simplified schematic diagram of an integrated circuit with non-volatile memory cells and a renewed circuit. The integrated circuit 14A includes a memory array 135, and the array disposed on a semiconductor substrate uses data memory cells. The address is provided on bus 1105 to provide to column decoder 11〇3 and row decoder hoi. The sense amplifier, the comparison block, and the data input structure in block 14〇6 are flanked by the data combiner 11〇7 to the column decoder·. The data is supplied to the data input structure in block 1406 via data input line 1111 from the input/output terminals on integrated circuit 14 or other internal or external data sources from integrated circuit 1400. The data is passed from the sense amplifier in block 1406 to the input/output terminal just above the integrated circuit via data output line n15, or to other internal or external data destinations of integrated circuit 1400. The present invention has been described with reference to the specific embodiments described above, but it is understood that the embodiments of the present invention are intended to be illustrative of the present invention. Therefore, the various embodiments are possible embodiments, and all of these variations and improvements are possible without departing from the spirit and scope of the invention. [Simple description of the diagram] The threshold voltage design of the cells of the 甘 第 龄 麟 麟 转发 转发 转发 转发 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中Divided into a data memory part and a • 1301617 boundary detection memory part of the schematic diagram, the amplifier part and a boundary detection of the cries of the eight J-knife 枓 枓 枓 隐 隐 之 枓 枓 枓 枓 枓 枓 比较 比较 比较The initial data of the body is compared with the parent 0, and the third figure shows the sound of the non-volatile memory boundary detection memory. (10) σ Ρ 及 八 八 八 八 八 及 及 及 及 及 及 及 及 及 及 及 及 及 感 感 感 感 感 感 感 感The boundary check nozzle (4) is compared with the initial data of the comparison. μ 4th BU, page * 临界 in a non-volatile memory cell threshold voltage design 渖 ^ method, its application, quasi-reference current and monitoring reference power narrower charge loss boundary. a white eight early 乂 乂 第 第 第 第 另 - - - - - - 用于 用于 用于 用于 用于 用于 用于 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界 临界Distribution boundaries and gamma-bound distribution boundaries. The output of the lion's pin signal in the state to display the update function. Figure 7 shows the operation flow of controlling the output of a plurality of r/b pin signals to display the new function status. Figure 8 shows a critical voltage distribution for non-volatile memory cells with a narrow charge loss boundary and CM by using normaljref, monitorJrefl, and m〇nit〇r-Iref2 but without &B; +RT+RD boundary. / Figure 9A shows a workflow for performing parallel sensing to determine whether an update should be performed, the wiper updates the functional fresh sense amplifier, and the monitor sense amplifier with g 2 and the second monitor reference current (eg, 8 design). Fig. 9B shows a workflow similar to that of Fig. 9A for performing parallel sensing, except that it uses the first monitor reference current without using the second monitor parameter 21 - 1301617 current. Large =:===:= ° and 5)) / sense sensing side - and second monitoring reference current.

Cheng, the flow of the 1GA chart of the paste. Rhyme - 1 " control reference f flow without using the second monitoring reference power 10C picture display - similar to the series sensing operation flow of Figure 10A, which enables the second monitoring reference current without using the first monitoring channel 0 - 11 shows a block diagram for performing parallel sensing to determine whether to perform an update function including boundary detection cells and a boundary detection amplifier. Figure 12 shows a block diagram for performing tandem sensing to determine whether to perform an update function. The sensing includes border detection cells. Figure 13 shows a block diagram of parallel sensing to determine whether to perform an update function that includes both a standard sense amplifier and a monitor sense amplifier. The standard sense amplifier senses normal-Iref and the monitor sense amplifier senses monitor_Iref. Figure 14 shows a block diagram of performing series sensing to determine whether to perform an update function, the sensing includes a sense amplifier to sense normal-Iref and monitor-Iref〇22 1301617 in different cycles. [Main component symbol Explanation] 105 initial threshold voltage low limit 110 initial distribution interval 111 initial threshold voltage intermediate value 115 initial threshold voltage high limit 120 low threshold voltage cycle boundary 130 threshold voltage room temperature drift and readout interference 140 circuit f buy Interval and array cell final critical voltage interval φ 150 charge loss interval 155 high threshold voltage distribution low limit 160 threshold voltage of programmed cell 165 high threshold voltage distribution high limit 210 data memory portion 215 data sense amplifier portion 220 boundary Detection Memory Portion 225 Boundary Detection Sense Amplifier Portion 235 Comparison Block 315 Sense Amplifier Section 335 Comparison Memory 411 Low Threshold Voltage Distribution 441 Charge Loss Boundary 452 South Critical Voltage Sorrow 511 Low Threshold Voltage State 550 High Threshold Voltage Level 551 Final threshold voltage interval 552 high threshold voltage state 801 Low threshold of low threshold voltage distribution 23 • 1301617 802 low threshold voltage distribution high limit 805 South critical voltage distribution low limit 806 South critical voltage distribution south limit 807 standard reference current 808, 809 monitoring reference current 810 charge loss boundary 811 Charge gain boundary 812, 813, 815, 816, 817 sensing boundary 901 standard data 902 first logic data 903 second logic data 910 data cell 911 measurement current memory current cell 913, 914 monitoring reference current 923, 924 monitoring sense Amplifier 925 Data Multiplexer 930 Compare Logic 940 State Machine/Microcontroller 1100, 1200, 1300, 1400 Integrated Circuit 1101 Row Decoder 1102 Word Line 1103 Column Decode 1104 Bit Line 1105 Bus 1106, 1206, 1306 1406 Block 1107 Data Bus 1108 Bias Configuration Supply Voltage 1109 Bias Configuration State Machine 24 • 1301617 1111 Data Input Line 1115 Data Output Line 1150, 1350 Memory Array B Bu, B2, B2', B3, B4 Threshold Voltage Distribution D1, D1', D2, D2' sensing boundary normal_Iref standard reference current monitor-Iref (1, 2) monitoring parameters Test current CM cycle boundary RT room temperature drift RD readout interference

25

Claims (1)

• 1301617 X. Patent application scope: 1. A non-volatile memory integrated circuit comprising: non-volatile memory cells, comprising: a plurality of data cells storing at least some data values, the data values being associated with a low threshold voltage And a high threshold voltage; a reference current circuit for generating a reference current 'each of the reference currents has a high-sensing interval to sense the high threshold voltage and a low sensing interval to sense the low threshold voltage, The reference currents include: a standard reference current associated with a first operating interval having a first high sensing interval and a first low sensing interval of the spring; a first monitored reference current associated with a second a second working interval, the second working interval having a second high sensing interval narrower than the first high sensing interval and a second low sensing interval wider than the first low sensing interval; The second monitoring reference current is associated with a third working interval, the third working interval having a third high sensing interval wider than the first high sensing interval and a narrower than the first low a third low sensing interval of the measurement interval; the one or more sets of sense amplifier circuits use the standard reference current to sense a memory current from one of the plurality of data cells to generate a first result, and the following two At least one of the comparisons utilizes the first monitored reference current to generate a second result, and the second monitored reference current is utilized to generate a third result, and the logic is compared The first result is at least one of the first result and the third result from the sense amplifier circuit. ^ If you apply for a patent range! The integrated circuit of the item, wherein the one or more sets of sense amplifying-single-single-sense sense amplifiers sense the data and the standard reference current, and at least the first and second monitoring references联 0 L 26 .1301617 3. The integrated circuit of claim 1, wherein the one or more sets of sense amplifiers comprise: - a first set of amplifiers - the standard reference current to sense from the data The memory current of the cell; and - the second set of ~ amplifiers _ at least one of the first and second reference currents to sense the memory current from the data cells. One or more of the sense amplifications 4. The integrated circuit of claim 1 includes: using the standard reference f stream to produce a data from the first set of sense amplifiers, the memory current of the cells; a second set of sense amplifiers, data The memory current of the cell; and a third set of sense amplifiers, the memory current of the data cells. Using the first-monitoring reference current to sense from the using the second monitoring reference current For example, the integrated circuit of the first aspect of the patent scope further includes: - an externally accessible contact of the integrated circuit, having: an output state indicating that the integrated circuit is in use. 27 • 1301617 8. The integrated circuit of claim 1 further comprising: a first externally accessible contact of the integrated circuit, the first externally accessible contact indicating at least that the integrated circuit is determining Whether there is a need for an update; and a second externally accessible contact of the integrated circuit, the second externally accessible contact indicating at least whether the integrated circuit is ready to receive a new instruction or to update. 9. The integrated circuit of claim 1, wherein the plurality of data cells have a charge loss boundary of less than 0.7 V. 10. The integrated circuit of claim 1, wherein the plurality of data cells have a charge loss boundary of about 0.2 V. 11. The integrated circuit of claim 1, wherein the plurality of data cells have a loop boundary of less than 0.4 V. 12. The integrated circuit of claim 1, wherein the plurality of data cells are multi-order cells. 13. The integrated circuit of claim 1, wherein at least one of the first and second monitored reference currents is higher than the standard reference current and a low boundary indicating a high threshold voltage cell. 14. The integrated circuit of claim 1, wherein at least one of the first and second monitored reference currents is lower than the standard reference current and a south boundary indicating a low threshold voltage cell. 15. If the integrated circuit of claim 1 is applied, wherein the first result control should be compared with the first result of 28 1301617 2 or the second result, so as to determine Update the at least one data cell. Ice t applies for the integrated circuit of the first item of the patent scope, wherein: the current of the reference current - the result is the high critical reliance, the first junction f is compared with the second result, and the standard reference current - The result is the low threshold voltage, then the first result is compared to the third result. For example, the integrated circuit of claim 16 of the patent scope, wherein the standard reference current control - the feed material IH is selected to select the second result or the third result. The integrated circuit of the first aspect of the invention further includes: the body is configured to apply a bias voltage to the data cells in response to receiving the control circuit of the user mode command The control two-way target is biased to at least one data cell of the data cells to generate the memory current, and the control circuit updates the at least-data cell to respond to the first-th or the third result One of the first results of the match is wrong. It touches the monitoring reference, and one of the claws is used in at least one memory operation. 2〇· A method for scaly hair memory, comprising: a response-memory user mode command, executing, storing, arranging to at least one non-volatile memory data cell to generate a representation; q > 'a non-volatile memory At least one memory of the data value in the cell is a flow of 29 1301617, the data values being associated with a low threshold voltage and a high threshold voltage; generating a reference current, each of the reference currents having a high sensing interval to sense the a high threshold voltage and a low sensing interval to sense the low threshold voltage, including: generating a standard reference current, associated with a first operation having a first high sensing interval and a first low sensing interval Interval; generating a first monitoring reference current, associated with a second working interval, the second working interval having a second high sensing interval narrower than the first high sensing interval and a wider than the first a second low sensing interval of a low sensing interval; and φ generating a second monitoring reference current associated with a third working interval, the third working interval having a wider than the first high sensing interval a third high sensing interval and a third low sensing interval narrower than the first low sensing interval; using the standard reference current to sense the at least one memory current to generate a first result and further performing At least one of: using the first monitoring reference current to sense the at least one memory current to generate a second result; and sensing the at least one memory electrical Φ stream by using the second monitoring reference current to generate a third result; and at least one of the first result, and the second result and the third result. 21. The method of claim 20, wherein the utilizing the standard reference current to sense the at least one memory current system occurs in parallel with at least one of the following at least one memory operation: utilizing the first monitored reference current to sense and The second monitored reference current is utilized for sensing. 22. The method of claim 20, wherein the standard reference current is utilized to sense the at least one memory current system in series with one of: utilizing the first monitor 30 1301617 reference current to sense and utilize the first Second, monitor the reference current for sensing. 23. The method of claim 2, wherein in at least one of the memory operations, only the first monitored reference current is utilized to sense and utilize the second monitored reference current to sense either occur. = · The method of claim 20, wherein the first result control is to compare the second result or the third result with the first result to determine whether the at least one data needs to be updated cell. 25· = the method of claim 20, wherein: if the reference current of the standard is used, the first j* monitoring reference current is sensed, and, D, D is the high threshold voltage' And sensing by using the first monitoring reference current of the standard reference current. ...when the wood is the low threshold voltage, the method of the second aspect of the patent application is used. Update the at least-data cell in response to an error containing one of the first results of the match. , μ di two results or the third result 31