TWI396206B - Laminated Chip Rheostat - Google Patents
Laminated Chip Rheostat Download PDFInfo
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- TWI396206B TWI396206B TW093139856A TW93139856A TWI396206B TW I396206 B TWI396206 B TW I396206B TW 093139856 A TW093139856 A TW 093139856A TW 93139856 A TW93139856 A TW 93139856A TW I396206 B TWI396206 B TW I396206B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/105—Varistor cores
- H01C7/108—Metal oxide
- H01C7/112—ZnO type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/12—Overvoltage protection resistors
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Description
本發明關於一種積層型晶片變阻器。The present invention relates to a laminated wafer varistor.
變阻器為藉由電壓可使電阻值非線性地變化的元件,例如,具有如施加超過指定電壓值(變阻電壓)的電壓的話,元件的電阻會大幅減少,使得原本幾乎無法流通的電流急遽地開始流通的特性。具有此種特性的變阻器多被搭載於電子設備,作為使電路免於受到靜電或雷擊所造成之異常電壓影響的保護用元件來使用。A varistor is an element that can change a resistance value nonlinearly by a voltage. For example, if a voltage exceeding a specified voltage value (varistor voltage) is applied, the resistance of the element is greatly reduced, so that an electric current that is almost impossible to circulate is violently The characteristics of the beginning of circulation. A varistor having such characteristics is often mounted on an electronic device and used as a protective element that protects the circuit from abnormal voltages caused by static electricity or lightning strikes.
電路保護用的變阻器例如會被並聯於電子設備中之電源電路等,在通常的動作時起作用為絕緣元件。並且,當有稱為電湧及干擾的異常電壓進入電子設備內時,變阻器會依此異常電壓而電阻值急遽縮小,因此,會起作用成為使電湧及干擾所致之異常電壓通過的旁路。如此一來,可防止異常電壓進入電源電路,藉此可抑止電湧及干擾等對電子設備的破壞。The varistor for circuit protection is, for example, connected in parallel to a power supply circuit or the like in an electronic device, and functions as an insulating element during normal operation. Moreover, when an abnormal voltage called surge and interference enters the electronic device, the varistor will rapidly reduce the resistance value according to the abnormal voltage, and therefore, it will function as an abnormal voltage caused by surge and interference. road. In this way, abnormal voltages can be prevented from entering the power supply circuit, thereby suppressing damage to electronic equipment such as surges and interference.
近年,對電子設備小型化的要求升高,而搭載於此等電子設備的變阻器也同樣被要求小型化。作為可達成上述般的小型化且上述特性也優良的變阻器,例如已知有如特公昭58-23921號公報上記載般地,將內部電極及以ZnO作為主成分之變阻層交互積層,並在藉此得到之積層體的端部上形成外部電極的積層型之晶片變阻器。In recent years, demands for miniaturization of electronic devices have increased, and varistor equipped with such electronic devices has also been required to be miniaturized. As a varistor which achieves the above-described miniaturization and is excellent in the above-described characteristics, it is known that, as described in Japanese Patent Publication No. Sho 58-23921, an internal electrode and a varistor layer containing ZnO as a main component are alternately laminated. Thereby, a laminated type varistor in which an external electrode is formed on the end portion of the laminated body is obtained.
作為此ZnO型的積層型晶片變阻器的內部電極,多半使 用具有可耐變阻層形成時之燒結溫度的耐熱性及優良電氣特性的Pt。然而,Pt非常地昂貴,因此,如內部電極使用Pt的話,會有積層型晶片變阻器在製造上所需之成本增加的問題。因此,為了減低製造成本,已有提案以比Pt價廉的Pd-Ag合金等作為內部電極用之材料來使用的積層型晶片變阻器。As the internal electrode of the ZnO type laminated wafer varistor, most of the internal electrodes Pt having heat resistance and excellent electrical characteristics which are resistant to the sintering temperature at the time of formation of the varistor layer. However, Pt is very expensive, and therefore, if Pt is used for the internal electrode, there is a problem that the cost of the laminated wafer varistor is increased in manufacturing. Therefore, in order to reduce the manufacturing cost, a laminated wafer varistor which is used as a material for internal electrodes than a Pd-Ag alloy which is inexpensive Pt has been proposed.
例如,特開平5-283209號公報記載有一種積層型晶片變阻器,其具有:內部電極,其係由Pd-Ag合金形成;及變阻層,其係以ZnO為主成分,作為副成分含有Pr。此外,特開平10-12406號公報記載有一種積層型晶片變阻器,其係具有:內部電極,其係由Pd-Ag合金形成;及變阻層,其係以ZnO為主成分,作為副成分含有Bi2 O3 等。For example, Japanese Laid-Open Patent Publication No. Hei 5-283209 discloses a laminated wafer varistor comprising: an internal electrode formed of a Pd-Ag alloy; and a varistor layer containing ZnO as a main component and Pr as a subcomponent. . Japanese Laid-Open Patent Publication No. Hei 10-12406 discloses a laminated wafer varistor comprising an internal electrode formed of a Pd-Ag alloy and a varistor layer containing ZnO as a main component and containing as a subcomponent. Bi 2 O 3 and the like.
此等專利文獻記載之積層型晶片變阻器中,內部電極並非使用昂貴的Pt,因此,可減低其製造成本,工業上為有用。然而,依上述特開平5-283209號公報記載之積層型晶片變阻器,在製造時之燒結之際會發生內部電極及變阻層的體積收縮差異,因此,有時會有兩者剝離等不良的情形發生。In the laminated wafer varistor described in the above patent documents, the internal electrode is not expensive Pt, and therefore, the manufacturing cost can be reduced, which is industrially useful. However, the laminated wafer varistor disclosed in the above-mentioned Japanese Patent Publication No. Hei 5-283209 has a difference in volume shrinkage between the internal electrode and the varistor layer during sintering at the time of production. occur.
此外,最近,積層型晶片變阻器在基板上乃以銲接來搭載的情形,亦即使用所謂表面安裝型之變阻器的情形愈來愈多。然而,依上述特開平10-12406號公報記載之積層型晶片變阻器,在銲接於基板上後施加電壓時的洩漏電流會有大到無法忽略的傾向,因此,具有難以得到所需之變阻電壓值的缺點。Further, recently, a laminated wafer varistor has been mounted on a substrate by soldering, that is, a so-called surface mount type varistor has been used more and more. However, in the laminated wafer varistor disclosed in Japanese Laid-Open Patent Publication No. H10-12406, the leakage current when a voltage is applied after soldering on the substrate tends to be large, and it is difficult to obtain a desired varistor voltage. The disadvantage of the value.
為此,作為能夠解決上述的內部電極及變阻層之剝離問題、及銲接後之洩漏電流之問題的積層型晶片變阻器,有一種積層型晶片變阻器被開發出來,其具有:變阻層,其係以ZnO為主成分,作為副成分含有Pr;及內部電極,其係在由Pd形成之導電材料中添加Al2 O3 (例如,專利第3449599號公報資料)。Therefore, as a laminated wafer varistor capable of solving the above-described problems of the peeling of the internal electrode and the varistor layer and the leakage current after soldering, a laminated wafer varistor has been developed which has a varistor layer. ZnO is used as a main component, and Pr is contained as a subcomponent; and an internal electrode is added to the conductive material formed of Pd, and Al 2 O 3 is added (for example, Patent No. 3449599).
然而,作為顯示積層型晶片變阻器具有之特性的重要指標之一,被周知的有耐電能量。此為顯示在施加指定之衝擊電流時,相對於變阻電壓之初始值的變化率在±10%以內時之最大電能者,並為積層型晶片變阻器之耐久性的基準的值。此耐電能量愈大之變阻器,愈難發生電湧等之異常電流所造成的破壞,可視為可靠性愈高者。However, as one of the important indexes for exhibiting the characteristics of the laminated wafer varistor, it is known that there is resistance to electric energy. This is the value indicating the maximum electric energy when the rate of change of the initial value of the varistor voltage is within ±10% when the specified inrush current is applied, and is the reference value of the durability of the laminated wafer varistor. The greater the resistance to electric energy, the more difficult it is to cause damage due to abnormal currents such as surges, which can be regarded as the higher the reliability.
本發明人在檢討上述專利第3449599號公報所記載之積層型晶片變阻器之耐電能量時,發現此等變阻器以先前使用之元件尺寸下,雖具有充分大的耐電能量,惟當元件尺寸縮小時,具體而言當內部電極之間隔為60 μm以下時,會有耐電能量顯著降低的現象。When the inventors of the present invention reviewed the electric power resistance of the laminated wafer varistor disclosed in the above-mentioned Japanese Patent No. 3449599, it was found that these varistor have sufficiently large electric power resistance at the element size previously used, but when the component size is reduced, Specifically, when the interval between the internal electrodes is 60 μm or less, the electric energy resistance is remarkably lowered.
最近,積層型晶片變阻器被希望能夠更進一步小型化,惟依此小型化,會發生如上述之耐電能量大幅降低,因此,目前並未出現在小型化及耐電能量的雙方上充分具有實用性的積層型晶片變阻器。Recently, a laminated wafer varistor has been expected to be further miniaturized. However, since the above-described miniaturization is caused, the electric power resistance is greatly reduced as described above, and therefore, there is no practicality in miniaturization and electric energy resistance. Multilayer wafer varistor.
本發明為有鑑於上述背景者,其目的在於提供一種積層型晶片變阻器,其即使在元件小型化的情況中也能確保充 分的耐電能量。The present invention has been made in view of the above circumstances, and an object thereof is to provide a laminated wafer varistor capable of ensuring charging even in the case where components are miniaturized. The resistance to electric energy.
本發明人在對上述專利第3449599號公報記載之積層型晶片變阻器隨著尺寸縮小而積層型晶片變阻器之耐電能量變小的原因進行調查的結果,發現其中原因之一為:變阻層中添加的Pr易與為內部電極材料之Pd產生反應,因為此反應,變阻層中之Pr被吸收至內部電極。如上所述,當變阻層中之Pr被吸收至內部電極時,變阻層中之Pr濃度會變小,不僅造成變阻電壓不正常地下降,也使耐電能量變小。The inventors of the present invention investigated the cause of the decrease in the electric resistance of the laminated wafer varistor as described in the above-mentioned Japanese Patent No. 3449599, and found that one of the causes is that the varistor layer is added. Pr is easily reacted with Pd which is an internal electrode material because Pr in the varistor layer is absorbed to the internal electrode. As described above, when Pr in the varistor layer is absorbed to the internal electrode, the Pr concentration in the varistor layer becomes small, causing not only an abnormal decrease in the varistor voltage but also a decrease in the withstand voltage.
此外,在對上述現象進行更進一步之檢討的結果,發現尤其在內部電極之週邊區域中之Pr濃度變小,此Pr濃度變小的區域導致了變阻電壓之下降,連帶地引起耐電能量的下降。Further, as a result of further review of the above phenomenon, it was found that the Pr concentration in the peripheral region of the internal electrode became small, and the region where the Pr concentration became small caused a decrease in the varistor voltage, and the electrical energy resistance was caused in combination. decline.
本發明人依據上述發現,發現藉由抑制變阻層中之Pr被吸收至內部電極中,便可充分確保積層型晶片變阻器之耐電能量,進而完成了本發明。Based on the above findings, the inventors have found that the piezoelectric energy of the laminated wafer varistor can be sufficiently ensured by suppressing the absorption of Pr in the varistor layer into the internal electrode, and the present invention has been completed.
亦即,本發明之積層型晶片變阻器的特徵為包含:變阻器素體,其係具有以ZnO為主成分且作為副成分含有Pr的複數個變阻層、及內部電極,而此內部電極除了Pd、Ag之外,尚含有相對於上述Pd及上述Ag的合計100質量份為0.0001至1.0質量份的Al氧化物,並夾住各變阻層般地被約略平行配置;及外部電極,其係設置於變阻器素體之端部,分別連接於內部電極。That is, the laminated wafer varistor of the present invention is characterized by comprising: a varistor element body having a plurality of varistor layers containing ZnO as a main component and containing Pr as a subcomponent, and an internal electrode, wherein the internal electrode is in addition to Pd In addition to Ag, the Al oxide is 0.0001 to 1.0 part by mass based on 100 parts by mass of the total of the above Pd and the Ag, and is disposed approximately in parallel with each of the varistor layers; and an external electrode It is disposed at the end of the varistor body and is respectively connected to the internal electrode.
上述積層型晶片變阻器中之內部電極除了含有通常使用作為電極材料的Pd之外,更進一步作為必要成分而含有Ag 及Al氧化物之兩成分。將此Ag及Al氧化物組合起來使用的話,會有良好地被吸收至Pd中的傾向。因此,含有此等成分之內部電極近乎於飽和狀態,難以再吸收更多的添加物。如此一來,此積層型晶片變阻器中,如上述般之變阻層中之Pr被吸收至內部電極的情形會受到抑制,使得因為變阻層之Pr濃度下降所導致之耐電能量之下降極端地變少。惟,本發明之作用並不以此為限。The internal electrode in the above-mentioned laminated wafer varistor contains, in addition to Pd which is generally used as an electrode material, further contains Ag as an essential component. And two components of Al oxide. When this Ag and Al oxide are used in combination, they tend to be well absorbed into Pd. Therefore, the internal electrodes containing these components are nearly saturated, making it difficult to absorb more additives. As a result, in the laminated wafer varistor, the case where Pr in the varistor layer is absorbed to the internal electrode as described above is suppressed, so that the decrease in the withstand voltage due to the decrease in the Pr concentration of the varistor layer is extremely extreme. Fewer. However, the effects of the present invention are not limited thereto.
如上述般地,本發明之積層型晶片變阻器中,變阻層中之Pr被吸收至內部電極的情形會極少,因此,被一對內部電極所夾之變阻層中,Pr會具有近乎均勻的濃度分布。As described above, in the laminated wafer varistor of the present invention, Pr in the varistor layer is rarely absorbed to the internal electrode, and therefore, Pr is almost uniform in the varistor layer sandwiched by the pair of internal electrodes. Concentration distribution.
此外,本發明之積層型晶片變阻器中,變阻層中之Pr向內部電極之遷移少,因此,此積層型晶片變阻器中之變阻層會為幾乎沒有如以往般顯著地在接於內部電極區域有Pr濃度下降的情形者。亦即,具有上述構造之積層型晶片變阻器中,被一對內部電極夾住之變阻層中之每固定體積的Pr含量會與此變阻層中接於於一對內部電極中至少一方之區域中之每固定體積的Pr含量約略相同。Further, in the laminated wafer varistor of the present invention, since the Pr in the varistor layer migrates less toward the internal electrode, the varistor layer in the laminated varistor is hardly connected to the internal electrode as in the prior art. The region has a situation in which the concentration of Pr is decreased. In other words, in the laminated wafer varistor having the above configuration, the Pr content per fixed volume of the varistor layer sandwiched by the pair of internal electrodes is at least one of the pair of internal electrodes connected to the varistor layer. The Pr content per fixed volume in the region is approximately the same.
此積層型晶片變阻器中之變阻層具有如上述般的均勻的Pr濃度分布。此分布狀態換言之可視為:變阻層之相鄰於內部電極之指定區域中之每固定體積的Pr含量與變阻層之積層方向中央部的指定區域中之每固定體積的Pr含量約略相同的狀態。The varistor layer in the laminated wafer varistor has a uniform Pr concentration distribution as described above. In other words, the distribution state can be regarded as that the Pr content of each fixed volume in the specified region adjacent to the internal electrode of the varistor layer is approximately the same as the Pr content of each fixed volume in the designated region of the central portion of the varistor layer in the lamination direction. status.
依具有此等構造之積層型晶片變阻器,在藉由電子微探分析手法進行分析時,可得到以下所示的結果:亦即,由 被一對內部電極夾住之變阻層中與內部電極接於之區域得到的Pr之X光強度會與由此變阻層中之一對內部電極間之中央位置得到的Pr的X光強度約略相同。According to the laminated wafer varistor having such a structure, when analyzed by an electronic microprobe analysis method, the following results can be obtained: that is, by The intensity of the X light of Pr obtained in the region of the varistor layer sandwiched by the pair of internal electrodes and the region where the internal electrode is connected, and the X-ray intensity of Pr obtained from the central position between one of the internal electrodes of the varistor layer The approximate is the same.
更具體而言,上述積層型晶片變阻器中,內部電極間之間隔以20至60 μm為佳。如以往般地內部電極之間隔大時,亦即變阻層之厚度大時(具體而言,超過80 μm時),雖然可見到如上述般地因為Pr被吸收所致之內部電極週邊區域的Pr濃度下降,惟變阻層中存在有許多具有充分Pr濃度的區域,因此,耐電能量下降的情形並不致太大。然而,內部電極的間隔為60 μm以下時,變阻層之Pr濃度低的區域會變多,因此會有導致耐電能量顯著下降的傾向。另一方面,具有上述構造的本發明之積層型晶片變阻器為如上述般地可大幅抑制Pr濃度下降者,因此,在內部電極間之距離設為20至60 μm時的情況中,以耐電能量的觀點來看會為特別有成效者。More specifically, in the above laminated type varistor, the interval between the internal electrodes is preferably 20 to 60 μm. When the interval between the internal electrodes is large, that is, when the thickness of the varistor layer is large (specifically, when it exceeds 80 μm), the peripheral region of the internal electrode due to the absorption of Pr as described above can be seen. The Pr concentration is lowered, but there are many regions having a sufficient Pr concentration in the varistor layer, and therefore, the situation in which the electric power resistance is lowered is not too large. However, when the interval between the internal electrodes is 60 μm or less, the region in which the Pr concentration of the varistor layer is low is increased, and thus the electric power resistance tends to be remarkably lowered. On the other hand, the laminated wafer varistor of the present invention having the above-described structure can greatly suppress the decrease in the Pr concentration as described above. Therefore, in the case where the distance between the internal electrodes is 20 to 60 μm, the electric energy is resistant. The point of view will be particularly effective.
此外,上述積層型晶片變阻器中,內部電極以相對於Pd 100質量份含有1至95質量份的Ag為佳。當內部電極設為上述般的構造時,可更顯著地抑制Pr的被吸收,結果易於確保充分大之耐電能量。Further, in the above laminated type varistor, the internal electrode preferably contains 1 to 95 parts by mass of Ag based on 100 parts by mass of Pd. When the internal electrode has the above-described structure, the absorption of Pr can be more remarkably suppressed, and as a result, it is easy to ensure a sufficiently large electric power resistance.
以下,對於本發明偏好之實施方式,參照圖示來詳細加以說明。此外,相同之元件將標示相同之符號,並省略重覆之說明。此外,上下左右等之關係乃以圖式之位置關係為準。Hereinafter, embodiments of the preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same elements will be denoted by the same reference numerals and the description of the repeated description will be omitted. In addition, the relationship between the top, bottom, left, and right is based on the positional relationship of the schema.
首先,參照圖1來說明本實施方式之積層型晶片變阻器。圖1為模式性地顯示偏好之實施方式的積層型晶片變阻器之剖面圖。積層型晶片變阻器1具有由複數個變阻層2及被配置成夾住此各變阻層2之內部電極4a(第一內部電極)及內部電極4b(第二內部電極)所構成的變阻器素體5。First, a laminated wafer varistor of the present embodiment will be described with reference to Fig. 1 . 1 is a cross-sectional view schematically showing a laminated wafer varistor of a preferred embodiment. The laminated wafer varistor 1 has a varistor element composed of a plurality of varistor layers 2 and internal electrodes 4a (first internal electrodes) and internal electrodes 4b (second internal electrodes) arranged to sandwich the varistor layers 2 Body 5.
此外,此變阻器素體5之兩端部上,設有分別與內部電極4a及內部電極4b電性連接的一對之外部電極6。此外,外部電極6之外側上,依序形成有鍍Ni層8及鍍Sn層10而被覆於外部電極6上。藉由此等之外部電極6、鍍Ni層8及鍍Sn層10,構成了外部端子12。Further, a pair of external electrodes 6 electrically connected to the internal electrode 4a and the internal electrode 4b are provided at both end portions of the varistor element body 5. Further, on the outer side of the external electrode 6, a Ni plating layer 8 and a Sn plating layer 10 are sequentially formed to cover the external electrode 6. The external terminal 12 is formed by the external electrode 6, the Ni plating layer 8, and the Sn plating layer 10.
變阻層2為以ZnO為主成分且作為副成分含有Pr者,具有5至60 μm左右之厚度。此變阻層2將上述兩成分包含作為必要成分,因此,具有顯示變阻特性之指標之一的非線性係數(α )大等的優良的變阻特性。The varistor layer 2 has a thickness of about 5 to 60 μm, which is mainly composed of ZnO and contains Pr as an auxiliary component. Since the varistor layer 2 contains the above two components as an essential component, it has excellent varistor characteristics such as a large nonlinear coefficient ( α ) which is one of the indexes showing the varistor characteristics.
變阻層2除了上述成分之外,也可含有可進一步提升變阻特性的微量添加物,例如可含有Co、Al、K、La、Si、Ca等之金屬及此等之氧化物的任意組合。當中,作為使變阻層2含有之微量添加物偏好為Al氧化物,尤其偏好Al2 O3 。藉由如此般地含有Al氧化物,會有非線性指數(α)進一步變大的傾向。The varistor layer 2 may contain, in addition to the above components, a trace additive which further enhances the varistor characteristics, for example, a metal which may contain Co, Al, K, La, Si, Ca, or the like, and any combination of these oxides. . Among them, as the trace additive contained in the varistor layer 2, an Al oxide is preferred, and Al 2 O 3 is particularly preferred. When the Al oxide is contained in this manner, the nonlinear index (α) tends to be further increased.
構成上述變阻層2之材料的最適當的例子有以ZnO為97.725莫耳%,Pr為0.5莫耳%,Co為1.5莫耳%,Al為0.05莫耳%,K為0.05莫耳%,Cr為0.1莫耳%,Ca為0.1莫耳%,Si為0.02莫耳%的組合材料。The most suitable examples of the material constituting the above-mentioned varistor layer 2 are 97.725 mol% of ZnO, 0.5 mol% of Pr, 1.5 mol% of Co, 0.05 mol% of Al, and 0.05 mol% of K. The composition of Cr was 0.1 mol%, Ca was 0.1 mol%, and Si was 0.02 mol%.
內部電極4a、4b由含有Ag及Pd的導電材料、及添加於此導電材料中之Al氧化物形成,具有0.5至5 μm左右之厚度。此內部電極4a、4b中之Al氧化物的含量相對於Pd及Ag之合計100質量份為0.0001至1.0質量份。此外,作為添加於此導電材料中之Al氧化物,以Al2 O3 為佳。The internal electrodes 4a and 4b are formed of a conductive material containing Ag and Pd and an Al oxide added to the conductive material, and have a thickness of about 0.5 to 5 μm. The content of the Al oxide in the internal electrodes 4a and 4b is 0.0001 to 1.0 part by mass based on 100 parts by mass of the total of Pd and Ag. Further, as the Al oxide added to the conductive material, Al 2 O 3 is preferred.
內部電極4a、4b中,如Al氧化物含量相對於Pd及Ag之合計100質量份為未滿0.0001質量份的話,變阻層燒結時內部電極4a、4b及變阻層的收縮率差異會變大,兩者會有剝離之虞。另一方面,如超過1.0質量份的話,內部電極4a、4b會難以燒結,因此,導電性變低,與外部電極的導通變得不充分,而有變阻特性降低的傾向。In the internal electrodes 4a and 4b, if the content of the Al oxide is less than 0.0001 parts by mass based on 100 parts by mass of the total of Pd and Ag, the difference in shrinkage ratio between the internal electrodes 4a and 4b and the varistor layer during the varistor layer is changed. Big, the two will be stripped. On the other hand, when the amount is more than 1.0 part by mass, the internal electrodes 4a and 4b are less likely to be sintered. Therefore, the conductivity is lowered, the conduction with the external electrode is insufficient, and the varistor characteristics tend to be lowered.
此外,內部電極4a、4b中之作為導電材料的Pd及Ag以如下所示的比例來含有為佳:亦即,相對於Pd 100質量份,以含有1至95質量份的Ag為佳。Further, it is preferable that Pd and Ag which are conductive materials in the internal electrodes 4a and 4b are contained in a ratio as follows: that is, it is preferable to contain 1 to 95 parts by mass of Ag with respect to 100 parts by mass of Pd.
如相對於Pd 100質量份的Ag含量未滿1質量份的話,變阻層2中之Pr被內部電極4a、4b吸收的程度會變大,藉此會有積層型晶片變阻器1之耐電能量變小的傾向。另一方面,如Ag含量超過95質量份的話,內部電極4a、4b的熔點會過低,有時會在燒結變阻層之際,導致內部電極4a、4b熔解而無法得到良好的變阻特性的情形。When the Ag content is less than 1 part by mass with respect to 100 parts by mass of Pd, the degree of absorption of Pr in the varistor layer 2 by the internal electrodes 4a, 4b becomes large, whereby the electric resistance of the laminated varistor 1 is changed. Small tendency. On the other hand, if the content of Ag exceeds 95 parts by mass, the melting points of the internal electrodes 4a and 4b may be too low, and the internal electrodes 4a and 4b may be melted when the varistor layer is sintered, and good varistor characteristics may not be obtained. The situation.
變阻器素體5為上述的變阻層2及內部電極4a、4b交互積層而成者。此變阻器素體5之端部上形成有具有10至50 μm左右之厚度的一對外部電極6,此等分別與內部電極4a、4b中之一方電性連接。外部電極6的構成材料為能夠與內部電 極4a、4b良好地連接者即可,並無特別的限制,例如有Pd、Pt、Ag及任意組合此等金屬而成之合金。當中,以比較價廉且具有與內部電極4a、4b之接合性良好之特性的Ag為佳。The varistor element body 5 is formed by alternately laminating the above-described varistor layer 2 and internal electrodes 4a and 4b. A pair of external electrodes 6 having a thickness of about 10 to 50 μm are formed on the end portions of the varistor element body 5, and are electrically connected to one of the internal electrodes 4a and 4b, respectively. The external electrode 6 is made of a material that can be internally charged The poles 4a and 4b may be well connected, and are not particularly limited, and examples thereof include an alloy of Pd, Pt, Ag, and any combination of these metals. Among them, Ag which is relatively inexpensive and has good bonding properties with the internal electrodes 4a and 4b is preferable.
此外部電極6的表面上,為被覆外部電極6而依序形成有厚度約0.5至2 μm之鍍Ni層8、及厚度約2至6 μm之鍍Sn層10。此等的鍍層為主要目的在於提高積層型晶片變阻器1以迴銲處理來搭載於基板等時的銲錫耐熱性及銲錫浸潤性而形成者。據此,在能夠達成此目的的情況下,在外部電極6表面上形成之鍍層並沒有必要為上述材料的組合。例如,作為構成鍍層的其他材料,舉例來說有Sn-Pb合金等,並且組合上述Ni及Sn來使用也適合。此外,相關之鍍層也可僅由一層來構成的層。On the surface of the external electrode 6, a Ni plating layer 8 having a thickness of about 0.5 to 2 μm and a Sn plating layer 10 having a thickness of about 2 to 6 μm are sequentially formed to cover the external electrode 6. The above-mentioned plating layer is mainly formed by improving solder heat resistance and solder wettability when the laminated wafer varistor 1 is mounted on a substrate or the like by a reflow process. Accordingly, in the case where this object can be attained, the plating formed on the surface of the external electrode 6 is not necessarily a combination of the above materials. For example, as another material constituting the plating layer, for example, a Sn-Pb alloy or the like is used, and it is also suitable to use the above-mentioned Ni and Sn in combination. Furthermore, the associated coating may also be a layer composed of only one layer.
具有此種構造之積層型晶片變阻器1中,被夾置於一對內部電極4a、4b間的變阻層2具有作為副成分添加之Pr約略均勻分散的狀態。本發明之積層型晶片變阻器具有此種狀態的變阻層,因此,如以下所示般地,具有比以往者優良的變阻特性。In the laminated wafer varistor 1 having such a structure, the varistor layer 2 interposed between the pair of internal electrodes 4a and 4b has a state in which Pr added as an auxiliary component is approximately uniformly dispersed. Since the laminated wafer varistor of the present invention has the varistor layer in this state, it has excellent varistor characteristics as compared with the prior art.
以下參照圖2至圖6,對於本發明之積層型晶片變阻器與以往之積層型晶片變阻器的差異,以各自的變阻層之狀態來比較並加以說明。2 to 6, the difference between the laminated wafer varistor of the present invention and the conventional laminated wafer varistor will be described and compared with the state of each varistor layer.
圖2至圖5為顯示對以往之積層型晶片變阻器(具有由Pd形成之內部電極、及含有ZnO及Pr之變阻層的積層型晶片變阻器)以電子微探分析手法(EPMA)觀察之結果的一例之圖。此外,圖2及圖4中,顯示愈接近白色(顏色愈淡)Pr濃度 愈大。此外,圖3中,L1顯示Pr的X光強度,L2顯示Pd的X光強度。再者,圖5中,L3顯示Pr的X光強度,L4顯示Pd的X光強度。2 to 5 are views showing the results of an electronic microanalytical method (EPMA) observed on a conventional laminated wafer varistor (an internal electrode having Pd and a varistor having a varistor layer containing ZnO and Pr) An example of a picture. In addition, in Fig. 2 and Fig. 4, the closer to white (the lighter the color) the Pr concentration is displayed. The bigger it is. Further, in Fig. 3, L1 shows the X-ray intensity of Pr, and L2 shows the X-ray intensity of Pd. Further, in Fig. 5, L3 shows the X-ray intensity of Pr, and L4 shows the X-ray intensity of Pd.
圖2為顯示對沿著內部電極之間隔為80 μm之積層型晶片變阻器之積層方向的剖面以EPMA觀察而得到的Pr濃度分布之圖。此外,圖3為顯示對圖2觀察之剖面以EPMA沿著積層方向進行微探分析而得到的Pr之X光強度之圖。藉由圖2及圖3,確認在內部電極之間隔為80 μm的積層型晶片變阻器中,各變阻層接於到內部電極的區域具有極小的Pr濃度。此外,確認在一對內部電極間之中央區域具有比接於於內部電極之區域高的Pr濃度。Fig. 2 is a view showing a Pr concentration distribution obtained by observing a cross section of a laminated wafer varistor having an interval of 80 μm along the internal electrodes as observed by EPMA. In addition, FIG. 3 is a graph showing the X-ray intensity of Pr obtained by microprobe analysis of the EPMA along the lamination direction in the cross section observed in FIG. 2. 2 and 3, it was confirmed that in the laminated wafer varistor having an internal electrode interval of 80 μm, each of the varistor layers had a very small Pr concentration in the region to the internal electrode. Further, it was confirmed that the central region between the pair of internal electrodes had a higher Pr concentration than the region connected to the internal electrode.
更進一步地,圖4為顯示對沿著內部電極之間隔為20 μm之積層型晶片變阻器之積層方向的剖面以EPMA觀察而得到的Pr之濃度分布之圖。此外,圖5為顯示對圖4觀察之剖面以EPMA沿著積層方向進行微探分析而得到的Pr之X光強度之圖。藉由圖4及圖5,確認Pr大部分存在於與內部電極存在之區域重疊之位置,各變阻層之Pr濃度(圖4)及Pr之X光強度(圖5)變成極小。Further, FIG. 4 is a view showing a concentration distribution of Pr obtained by EPMA observation of a cross section in the lamination direction of a laminated wafer varistor having an interval of 20 μm along the internal electrodes. In addition, FIG. 5 is a graph showing the X-ray intensity of Pr obtained by microprobe analysis of the EPMA along the lamination direction in the cross section observed in FIG. 4. 4 and 5, it was confirmed that most of Pr exists at a position overlapping the region where the internal electrode exists, and the Pr concentration (Fig. 4) of each varistor layer and the X-ray intensity (Fig. 5) of Pr become extremely small.
在此,作為內部電極之構成材料的Pd及變阻層中之Pr為極易發生反應者。因此,具有上述構造之以往的積層型晶片變阻器中,藉由此反應,變阻層中之Pr會被吸收於內部電極,如圖2至圖5所示般地,接於到內部電極之區域的Pr濃度會變小。Here, Pd which is a constituent material of the internal electrode and Pr in the varistor layer are highly susceptible to reaction. Therefore, in the conventional laminated wafer varistor having the above structure, Pr is absorbing the internal electrode in the varistor layer, and is connected to the internal electrode as shown in FIGS. 2 to 5 The concentration of Pr will become smaller.
如此般地接於到內部電極之區域的Pr濃度變小的話,該 區域的ZnO之結晶粒界中存在的Pr會極少。通常,含有ZnO之變阻層的變阻特性,特別為非線性係數(α)及耐電能性等之特性被認為相當依存於ZnO之結晶粒界中存在的Pr。因此,ZnO之結晶粒界中存在的Pr變少的話,會導致此等之變阻特性顯著降低的結果。When the concentration of Pr connected to the region of the internal electrode is reduced as described above, There is very little Pr present in the grain boundary of ZnO in the region. In general, the varistor characteristics of the varistor layer containing ZnO, particularly the characteristics of the nonlinear coefficient (α) and electric resistance, are considered to be relatively dependent on the Pr present in the grain boundary of ZnO. Therefore, when Pr is present in the crystal grain boundary of ZnO, the varistor characteristics are remarkably lowered.
上述之內部電極對Pr的吸收顯著地可見於變阻層中由面對內部電極之接於面起至距離10 μm左右之位置止的區域內。因此,內部電極間之間隔愈小,具體而言在60 μm以下的情況中,變阻層之變阻特性的降低程度會變大,因此,有易於引起積層型晶片變阻器整體的變阻特性之降低的傾向。尤其,在內部電極之間隔為20 μm以下時(參照圖4及圖5),會變成變阻層中之Pr大部分被內部電極吸收之狀態。The absorption of Pr by the internal electrode described above is remarkably found in the region of the varistor layer which is located from the surface facing the internal electrode to a position of about 10 μm. Therefore, the smaller the interval between the internal electrodes, specifically, in the case of 60 μm or less, the degree of reduction in the varistor characteristics of the varistor layer becomes large, and therefore, the varistor characteristics of the laminated varistor as a whole are liable to occur. The tendency to decrease. In particular, when the interval between the internal electrodes is 20 μm or less (see FIGS. 4 and 5), most of Pr in the varistor layer is absorbed by the internal electrodes.
另一方面,圖6為顯示對本發明偏好之實施方式之積層型晶片變阻器1以EPMA觀察之結果的一例之圖。此外,圖6所示之積層型晶片變阻器中,內部電極4a、4b的間隔為20 μm。亦即,圖6為顯示對沿著實施方式之積層型晶片變阻器1之積層方向的剖面以EPMA進行觀察而得到的Pr之濃度分布之圖。On the other hand, Fig. 6 is a view showing an example of the result of EPMA observation of the laminated wafer varistor 1 of the embodiment of the preferred embodiment of the present invention. Further, in the laminated wafer varistor shown in Fig. 6, the interval between the internal electrodes 4a and 4b is 20 μm. In other words, FIG. 6 is a view showing a concentration distribution of Pr obtained by observing the cross section along the lamination direction of the laminated wafer varistor 1 of the embodiment.
依圖6,確認Pr在與內部電極4a、4b重疊的區域內幾乎不存在,而在變阻層2中均勻存在。此外,由於Pr如此般地均勻存在,因此,確認在變阻層2中接於到內部電極的區域中的Pr濃度乃與此變阻層2中之一對內部電極間之中央區域的Pr濃度大致相同。According to Fig. 6, it was confirmed that Pr hardly exists in the region overlapping the internal electrodes 4a, 4b, but is uniformly present in the varistor layer 2. Further, since Pr is uniformly present, it is confirmed that the concentration of Pr in the region of the varistor layer 2 connected to the internal electrode is the concentration of Pr in the central region between one of the internal electrodes of the varistor layer 2 Roughly the same.
本實施方式的積層型晶片變阻器1中,內部電極4a、4b除 了Pd以外,尚含有Ag及Al氧化物。為此,內部電極4a、4b成為近乎於飽和狀態的狀態,使得上述般之內部電極4a、4b對變阻層2中之Pr的吸收極難發生。並且,如上般地抑制Pr之被吸收的結果,如圖6所示般地,Pr在變阻層2中成為均勻分散的狀態,亦即,成為在變阻層2中具有約略固定之濃度分布的狀態。In the laminated wafer varistor 1 of the present embodiment, the internal electrodes 4a and 4b are divided In addition to Pd, it also contains Ag and Al oxides. For this reason, the internal electrodes 4a and 4b are in a state of being nearly saturated, so that the absorption of Pr in the varistor layer 2 by the above-described internal electrodes 4a and 4b is extremely difficult to occur. Further, as a result of suppressing the absorption of Pr as described above, as shown in FIG. 6, Pr is uniformly dispersed in the varistor layer 2, that is, it has an approximately fixed concentration distribution in the varistor layer 2. status.
具有在此般的Pr均勻分布狀態的變阻層2中,極少會如以往的積層型晶片變阻器中在接於到內部電極之區域內發生Pr濃度降低的情形。亦即,被一對的內部電極4a、4b所夾的變阻層2中之每固定體積的Pr含量會與變阻層2之接於到一對內部電極4a、4b中至少一方的區域中之每固定體積的Pr含量大致相同。In the varistor layer 2 having the above-described uniform distribution of Pr, there is little possibility that the Pr concentration is lowered in the region where the internal electrode is connected in the conventional laminated wafer varistor. That is, the Pr content per fixed volume of the varistor layer 2 sandwiched by the pair of internal electrodes 4a, 4b is in contact with the varistor layer 2 in at least one of the pair of internal electrodes 4a, 4b. The Pr content per fixed volume is approximately the same.
此外,對於變阻層2之上述狀態,換言之可表示成如下:亦即,被一對內部電極4a、4b所夾之變阻層2中接於到內部電極4a、4b中至少一方的區域中之每固定體積的Pr含量會與變阻層2中在一對內部電極4a、4b間之中央區域的每固定體積的Pr含量約略相同。Further, the above state of the varistor layer 2, in other words, can be expressed as follows: that is, the varistor layer 2 sandwiched by the pair of internal electrodes 4a, 4b is connected to at least one of the internal electrodes 4a, 4b. The Pr content per fixed volume may be approximately the same as the Pr content per fixed volume in the central region between the pair of internal electrodes 4a, 4b in the varistor layer 2.
在此,變阻層2中接於到內部電極4a、4b的區域,在偏好的情況下,乃指變阻層2中由與內部電極4a、4b之接於面起至距離10 μm左右之位置為止的區域。Here, the region of the varistor layer 2 connected to the internal electrodes 4a, 4b, in the case of preference, means that the varistor layer 2 is connected to the surface of the internal electrodes 4a, 4b by a distance of about 10 μm. The area up to the location.
接著,參照圖7來說明具有上述構造之積層型晶片變阻器1的製造方法。圖7為顯示偏好之實施方式之積層型晶片變阻器的製造方法之流程圖。Next, a method of manufacturing the laminated wafer varistor 1 having the above configuration will be described with reference to FIG. 7 is a flow chart showing a method of manufacturing a laminated wafer varistor of a preferred embodiment.
首先,將構成變阻層2的主成分的ZnO、副成分的Pr之金 屬或氧化物、及其他微量添加物分別加以秤量而成為指定的比例後,混合各成分來調整變阻材料(工序S11)。在此情況中,微量添加物以混合成相對於主成分之ZnO為ppm單位的量為佳。之後,在此變阻材料內添加有機黏合劑、有機溶劑、有機可塑劑等,使用球磨機等進行20小時左右的混合及粉碎而得到研磨液。First, the ZnO of the main component of the varistor layer 2 and the gold of the Pr of the subcomponent are added. The genus or oxide and other trace additives are weighed to a predetermined ratio, and then the components are mixed to adjust the varistor material (step S11). In this case, it is preferred that the trace amount is mixed in an amount of ppm relative to the main component of ZnO. Thereafter, an organic binder, an organic solvent, an organic plasticizer, or the like is added to the varistor, and the mixture is pulverized by a ball mill or the like for about 20 hours to obtain a polishing liquid.
將此研磨液藉由刮刀(Doctor blade)法等周知的方法塗布於聚對苯二甲酸二乙酯(PET)薄膜上後,加以乾燥而形成厚30 μm左右之膜,將得到的膜由PET薄膜剝離下來而得到胚薄片(工序S12)。This polishing liquid is applied onto a polyethylene terephthalate (PET) film by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm, and the obtained film is made of PET. The film is peeled off to obtain a green sheet (step S12).
接著,準備內部電極4a、4b用之材料的將Pd、Ag、Al2 O3 及其他添加物製成漿狀的內部電極漿料。將此內部電極漿料藉由網版印刷等以指定之圖案進行印刷後,對此漿料進行乾燥,形成具有指定圖案之內部電極漿料層(工序S13)。Next, an internal electrode slurry in which Pd, Ag, Al 2 O 3 and other additives are slurried is prepared as a material for the internal electrodes 4a and 4b. After the internal electrode paste is printed in a predetermined pattern by screen printing or the like, the slurry is dried to form an internal electrode slurry layer having a predetermined pattern (step S13).
在製作成複數片在表面上形成有此內部電極漿料層的胚薄片後,將此等複數片積層成胚薄片及內部電極漿料層呈交錯狀而形成積層體(工序S14)。在如此得到的積層體上,視必要更進一步積層僅由上述胚薄片積層而成的保護用之胚薄片後,切割成所需的尺寸而得到胚晶片。After the green sheet in which the internal electrode slurry layer is formed on the surface of the plurality of sheets is formed, the plurality of laminated green sheets and the internal electrode slurry layers are formed in a staggered manner to form a laminate (step S14). On the laminated body thus obtained, if necessary, a protective embryo sheet formed by laminating only the above-mentioned embryonic sheet is laminated, and then cut into a desired size to obtain a embryonic wafer.
之後,對此胚晶片實施180至400℃、0.5至24小時左右的加熱處理而進行去黏合劑處理後,進一步進行1000至1400℃、0.5至8小時左右之燒成(工序S15),得到變阻器素體5。藉由相關之燒成,胚晶片中之胚薄片會成為變阻層2,內部電極漿料層會成為內部電極4a及4b。對於如此得到之變阻 器素體5,在實施接下來的形成外部電極6之工序之前,可一併與研磨材料等放入研磨容器內等來實施元件表面之平滑處理。Thereafter, the embryo wafer is subjected to a heat treatment at 180 to 400 ° C for about 0.5 to 24 hours to perform a debonding treatment, and further calcined at 1000 to 1400 ° C for about 0.5 to 8 hours (step S15) to obtain a varistor. Element 5. By the associated firing, the embryonic sheet in the embryonic wafer becomes the varistor layer 2, and the internal electrode paste layer becomes the internal electrodes 4a and 4b. For the varistor thus obtained Before the step of forming the external electrode 6 is carried out, the element body 5 can be placed in a polishing container or the like together with an abrasive or the like to perform smoothing of the surface of the element.
接著,在變阻器素體5的兩端部上,以能分別與內部電極4a及4b接於般地,塗布上主要含有Ag的外部電極漿料後,對此漿料以550至850℃左右進行加熱(燒結)處理,形成由Ag形成之一對的外部電極6(工序S16)。Next, at the both end portions of the varistor element body 5, the external electrode paste mainly containing Ag is applied to the internal electrodes 4a and 4b, and the slurry is applied at about 550 to 850 ° C. The heating (sintering) treatment is performed to form the external electrode 6 which is formed by a pair of Ag (step S16).
之後,在外部電極6表面上,藉由電鍍等來依序形成鍍Ni層8及鍍Sn層10,得到積層型晶片變阻器1(工序S17)。Thereafter, the Ni plating layer 8 and the Sn plating layer 10 are sequentially formed on the surface of the external electrode 6 by plating or the like to obtain a laminated wafer varistor 1 (Step S17).
依據如此構成之積層型晶片變阻器1,將可得到如下所示之成效:亦即,積層型晶片變阻器1具有Pr以約略固定的濃度而分散之狀態的變阻層2,因此,相較於與內部電極接於的區域中之Pr濃度極小的以往的積層型晶片變阻器,具有優良的非線性係數(α)及耐電能量。According to the laminated wafer varistor 1 configured as described above, it is possible to obtain the effect that the laminated wafer varistor 1 has the varistor layer 2 in a state where Pr is dispersed at a substantially fixed concentration, and therefore, compared with A conventional laminated wafer varistor having a very small Pr concentration in a region where the internal electrode is connected has an excellent nonlinear coefficient (α) and electric power resistance.
此外,在此積層型晶片變阻器1中,即使內部電極4a、4b之間隔為20 μm以下時,幾乎沒有Pr被內部電極4a、4b吸收。因此,即使在嘗試元件的大幅小型化時,極少會有如以往之變阻器發生的耐電能量之降低。Further, in the laminated wafer varistor 1, even when the interval between the internal electrodes 4a and 4b is 20 μm or less, almost no Pr is absorbed by the internal electrodes 4a and 4b. Therefore, even when an attempt is made to greatly reduce the size of the element, there is little reduction in the withstand electric energy generated by the conventional varistor.
以下,藉由實施例來更進一步詳細說明本發明,惟本發明並不限於此等的實施例。Hereinafter, the present invention will be described in further detail by way of examples, but the invention should not be construed as limited.
<積層型晶片變阻器之製造><Manufacture of laminated wafer varistor>
首先,在純度99.9%的ZnO(97.725 mol%)中,添加Pr(0.5 mol%)、Co(1.5 mol%)、Al(0.005 mol%)、K(0.05 mol%)、 Cr(0.1 mol%)、Ca(0.1 mol%)及Si(0.02 mol%)來調製變阻材料。First, in a purity of 99.9% ZnO (97.725 mol%), Pr (0.5 mol%), Co (1.5 mol%), Al (0.005 mol%), K (0.05 mol%), A varistor material was prepared by Cr (0.1 mol%), Ca (0.1 mol%), and Si (0.02 mol%).
此外,另外依表1至3所示之配方量,準備了包含Pd、Ag及Al2 O3 中至少2種的內部電極漿料。Further, in addition to the formulation amounts shown in Tables 1 to 3, an internal electrode slurry containing at least two of Pd, Ag, and Al 2 O 3 was prepared.
使用此變阻材料及內部電極漿料,依圖7所示之步驟,製造了由變阻材料形成之變阻層2、包含Pd、Ag及Al2 O3 中至少2種之內部電極4a、4b、由Ag形成之外部電極6、鍍Ni層8及鍍Si層10所構成,並具有圖1所示形狀的No.1至47的積層型晶片變阻器。各積層型晶片變阻器分別設為長1.6 mm、寬0.8 mm及高0.8 mm的尺寸。Using the varistor material and the internal electrode paste, a varistor layer 2 formed of a varistor material, and an internal electrode 4a containing at least two kinds of Pd, Ag, and Al 2 O 3 are produced according to the procedure shown in FIG. 4b. The laminated electrode varistor of Nos. 1 to 47 having the outer electrode 6, the Ni plating layer 8, and the Si plating layer 10 formed of Ag and having the shape shown in FIG. Each of the laminated wafer varistor is set to have a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm.
此外,No.1、2、10、18、26、33、34及41的積層型晶片變阻器方面,此等的Al2 O3 含量為0%,因此作為比較例,至於No.8、16、24、32、40及47的積層型晶片變阻器方面,此等的Al2 O3 含量超過1.0質量份,因此作為比較例。Further, in the laminated wafer varistor of No. 1, 2 , 10, 18, 26, 33, 34, and 41, the Al 2 O 3 content is 0%, and therefore, as a comparative example, as for No. 8, 16, In the laminated wafer varistor of 24, 32, 40, and 47, the Al 2 O 3 content exceeds 1.0 mass part, and thus is a comparative example.
<特性評估><Feature evaluation>
使用各積層型晶片變阻器,依如下所示之方法進行了變阻電壓之測定、非線性指數(α)之測定、耐電能量之測定、及耐濕負載試驗。對No.1至18的積層型晶片變阻器所得到之結果顯示於表1,對No.19至36的積層型晶片變阻器所得到之結果顯示於表2,對No.37至47的積層型晶片變阻器所得到之結果顯示於表3。Using the laminated wafer varistor, the measurement of the varistor voltage, the measurement of the nonlinearity index (α), the measurement of the withstand electric energy, and the moisture resistance load test were carried out in the following manner. The results obtained for the laminated wafer varistor of No. 1 to 18 are shown in Table 1. The results obtained for the laminated wafer varistor of Nos. 19 to 36 are shown in Table 2, and the laminated wafer of No. 37 to 47 is shown. The results obtained with the varistor are shown in Table 3.
(變阻電壓之測定)(Measurement of varistor voltage)
在各積層型變阻器中的一對外部端子12間,施加並逐漸加大電壓,測定1 mA之電流開始流通的電壓,以此作為各 變阻器的變阻電壓。A voltage is applied and gradually applied between a pair of external terminals 12 of each laminated varistor, and a voltage at which a current of 1 mA starts to flow is measured. The varistor voltage of the varistor.
(非線性指數(α)之測定)(Measurement of nonlinear index (α))
一面使施加於各積層型晶片變阻器的一對外部端子12間的電壓緩緩地變化,一面測定流經變阻器的電流值,測得1 mA之電流流經時的電壓(V1mA )及0.1 mA之電流流經時的電壓(V0.1mA )。接著,將得到的值代入下式(1)而計算出非線性指數α:α=log(1/0.1)/log(V1mA /V0.1mA )………(1)The voltage flowing through the varistor was measured while the voltage applied between the pair of external terminals 12 of the laminated varistor was gradually changed, and the voltage (V 1 mA ) and the current of 1 mA were measured. The voltage at which the current flows (V 0.1mA ). Next, the obtained value is substituted into the following formula (1) to calculate a nonlinear index α: α = log (1/0.1) / log (V 1mA / V 0.1mA ) (1)
(耐電能量之測定)(Measurement of electric energy resistance)
首先,在各積層型晶片變阻器的一對外部端子12間,一面以示波器觀察,一面施加具有自上升起10 μ秒後達到峰值的90%,並在達到峰值後,自上升起1000 μ秒後成為峰值的50%之波形的電壓,以示波器觀察藉由施加此波形的電壓而得到的電流波形。First, between the pair of external terminals 12 of each laminated wafer varistor, 90% of the peak value is applied after 10 μsec from the rise, and after 1000 μsec from the rise after the peak is applied. The voltage of the waveform of 50% of the peak value is observed by an oscilloscope to observe a current waveform obtained by applying a voltage of the waveform.
以得到之電壓波形及電流波形相乘得到電力波形後,藉由對此電力波形進行積分,計算出施加上述波形之電壓時的電能值。並且,緩緩提高此電能值,將變阻電壓之變化率超過±10%時視為積層型晶片變阻器被破壞,而以未發生破壞之電量值的最大值作為耐電能量(份:焦耳)。After the obtained voltage waveform and the current waveform are multiplied to obtain a power waveform, the power waveform is integrated to calculate the electric energy value when the voltage of the waveform is applied. Further, when the electric energy value is gradually increased, when the rate of change of the varistor voltage exceeds ±10%, the laminated varistor is broken, and the maximum value of the electric quantity that has not been broken is taken as the electric power (part: joule).
(耐濕負載試驗)(moisture resistance test)
首先,將No.1至47的積層型晶片變阻器分別製作20個,並測定了各樣本的變阻電壓。實施一面在此等樣本上施加為各別之變阻電壓之0.6倍的電壓,一面以85℃、80% RH的條件進行1000小時處理的耐濕負載試驗。之後,測定耐 濕負載試驗後之各樣本的變阻電壓,由No.1至47的積層型晶片變阻器的20個樣本中,計算出變阻電壓之變化率超過±10%的樣本個數,將此個數作為因為耐濕負載試驗而發生的不合格品的個數。First, 20 laminated thin film varistor Nos. 1 to 47 were fabricated, and the varistor voltage of each sample was measured. A moisture-resistant load test was carried out by applying a voltage of 0.6 times the respective varistor voltages to the samples and performing the treatment for 1000 hours under the conditions of 85 ° C and 80% RH. After that, measure resistance The varistor voltage of each sample after the wet load test was calculated from the 20 samples of the laminated wafer varistor of No. 1 to 47, and the number of samples whose rate of change of the varistor voltage exceeded ±10% was calculated. The number of defective products that occurred due to the moisture resistance load test.
依據表1至3,內部電極含有Pd、Ag及Al2 O3 ,且Al2 O3 之含量在本發明範圍內的積層型晶片變阻器均具有超過0.1 J的耐電能量,配外,因為耐濕負載試驗而發生的不合格品為0。在此所謂耐電能量0.1 J以上的值一般在實用積層型晶片變阻器時用來判斷為具有充分的可靠性者。According to Tables 1 to 3, the laminated electrode varistor having an internal electrode containing Pd, Ag, and Al 2 O 3 and having an Al 2 O 3 content within the scope of the present invention has an electric resistance of more than 0.1 J, which is externally affected by moisture resistance. The non-conforming product that occurred during the load test was zero. Here, the value of the electric power resistance of 0.1 J or more is generally used to determine that it has sufficient reliability in the case of a practical laminated wafer varistor.
<藉由EPMA的積層型晶片變阻器剖面之觀察><Observation of profile of laminated magnet varistor by EPMA>
使用No.1的積層型晶片變阻器(內部電極僅由Pd所構成的積層型晶片變阻器;充當比較例)及No.45的積層型晶片變阻器(內部電極以70/30的組成而含有Ag/Pd的積層型晶片 變阻器;作為本發明之積層型晶片變阻器),依據以下所示的方法,藉由電子微探分析手法(EPMA)測定了積層型晶片變阻器中的各成分(Pr、Co、Pd及Ag)之濃度分布。A laminated wafer varistor of No. 1 (a laminated wafer varistor composed of only Pd; a comparative example) and a laminated wafer varistor of No. 45 (the internal electrode contains Ag/Pd in a composition of 70/30) Laminated wafer A varistor; as a laminated wafer varistor of the present invention, the concentration of each component (Pr, Co, Pd, and Ag) in the laminated wafer varistor is measured by an electron microprobe analysis method (EPMA) according to the method described below. distributed.
首先,對各積層型晶片變阻器由其寬度方向(圖1之左右方向)的側面進行研磨直至相當於長度方向(圖1中之前後方向)之中央位置的剖面露出。將露出的剖面以EPMA進行觀察,觀察此剖面上之各元素的濃度分布。觀察No.1的積層型晶片變阻器而得到之Pr、Co、Pd及所有組成的濃度分布分別示於圖8至圖11。此外,觀察No.45的積層型晶片變阻器而得到之Pr、Co、Pd、Ag及所有組成的濃度分布分別示於圖12至圖16。此外,圖8至圖16中,顏色愈淡的區域表示對應之元素的含量愈多。First, each of the laminated wafer varistor is polished from the side surface in the width direction (the horizontal direction in FIG. 1) until the cross section corresponding to the center position in the longitudinal direction (the front-rear direction in FIG. 1) is exposed. The exposed cross section was observed with EPMA, and the concentration distribution of each element on the cross section was observed. The concentration distributions of Pr, Co, Pd, and all compositions obtained by observing the laminated wafer varistor of No. 1 are shown in Figs. 8 to 11, respectively. Further, the concentration distributions of Pr, Co, Pd, Ag and all the compositions obtained by observing the laminated wafer varistor of No. 45 are shown in Figs. 12 to 16, respectively. Further, in FIGS. 8 to 16, the area where the color is lighter indicates the content of the corresponding element.
藉由圖8至圖11,得知在相當於以往的積層型晶片變阻器的No.1之積層型晶片變阻器中,Pr在與Pd重疊的位置上-亦即,在存在內部電極的位置上-存在有許多,Pr在變阻層中之存在量極少。8 to 11, it is found that in the laminated wafer varistor of No. 1 corresponding to the conventional laminated wafer varistor, Pr is at a position overlapping with Pd, that is, at the position where the internal electrode exists - There are many, and Pr is present in a very small amount in the varistor layer.
另一方面,如圖12至圖16所示,得知在相當於本發明之積層型晶片變阻器的No.45之積層型晶片變阻器中,Pr在與Pd及Ag重複的位置上-亦即,在內部電極存在的位置上-幾乎不存在,此外,Pr在變阻層中呈均勻分布的狀態。On the other hand, as shown in FIG. 12 to FIG. 16, it is found that in the laminated wafer varistor of No. 45 corresponding to the laminated wafer varistor of the present invention, Pr is at a position overlapping with Pd and Ag - that is, At the position where the internal electrodes are present - almost absent, in addition, Pr is uniformly distributed in the varistor layer.
如上述之說明,依本發明,即使將元件小型化的情況中,也能提供可確保充分之耐電能量的積層型晶片變阻器。As described above, according to the present invention, even in the case where the device is miniaturized, a laminated wafer varistor capable of ensuring sufficient electric power resistance can be provided.
1‧‧‧積層型晶片變阻器1‧‧‧Laminated wafer varistor
2‧‧‧變阻層2‧‧‧variable resistance layer
4a、4b‧‧‧內部電極4a, 4b‧‧‧ internal electrodes
5‧‧‧變阻器素體5‧‧‧varistor body
6‧‧‧外部電極6‧‧‧External electrode
8‧‧‧鍍Ni層8‧‧‧Ni plating
10‧‧‧鍍Sn層10‧‧‧Sn plating layer
12‧‧‧外部端子12‧‧‧External terminals
圖1為模式地顯示偏好之實施方式的積層型晶片變阻器 之剖面圖。1 is a stacked type wafer varistor that modally displays a preferred embodiment Sectional view.
圖2為顯示以EPMA觀察內部電極之間隔為80 μm之積層型晶片變阻器之沿著積層方向之剖面而得到的Pr濃度分布之圖。Fig. 2 is a view showing a Pr concentration distribution obtained by observing a cross section of a laminated wafer varistor having an interval of internal electrodes of 80 μm along the lamination direction by EPMA.
圖3為顯示對圖2觀察之剖面以EPMA沿著積層方向進行微探分析而得到的Pr之X光強度之圖。Fig. 3 is a graph showing the X-ray intensity of Pr obtained by microprobe analysis of the EPMA along the lamination direction in the cross section observed in Fig. 2.
圖4為顯示對內部電極之間隔為20 μm之積層型晶片變阻器之沿著積層方向之部面以EPMA觀察而得到的Pr之濃度分布之圖。Fig. 4 is a graph showing the concentration distribution of Pr obtained by EPMA observation of the surface of the layered wafer varistor having an internal electrode interval of 20 μm along the lamination direction.
圖5為顯示圖4觀察之剖面以EPMA沿著積層方向進行線分析而得到的Pr之X光強度之圖。Fig. 5 is a graph showing the X-ray intensity of Pr obtained by performing line analysis of EPMA along the lamination direction in the cross section observed in Fig. 4.
圖6為顯示對實施方式之積層型晶片變阻器1之沿著積層方向之剖面以EPMA觀察而得到的Pr之濃度分布之圖。FIG. 6 is a view showing a concentration distribution of Pr obtained by observing the cross section in the lamination direction of the laminated wafer varistor 1 of the embodiment.
圖7為顯示偏好之實施方式的積層型晶片變阻器之製造方法之流程圖。7 is a flow chart showing a method of manufacturing a laminated wafer varistor of a preferred embodiment.
圖8為顯示藉由EPMA觀察之No.1之積層型晶片變阻器之剖面上的Pr濃度分布之圖。Fig. 8 is a graph showing the Pr concentration distribution on the cross section of the laminated wafer varistor of No. 1 observed by EPMA.
圖9為顯示藉由EPMA觀察之No.1之積層型晶片變阻器之剖面上的Co濃度分布之圖。Fig. 9 is a view showing a Co concentration distribution on a cross section of a laminated wafer varistor of No. 1 observed by EPMA.
圖10為顯示藉由EPMA觀察之No.1之積層型晶片變阻器之剖面上的Pd濃度分布之圖。Fig. 10 is a graph showing the Pd concentration distribution on the cross section of the laminated wafer varistor of No. 1 observed by EPMA.
圖11為顯示藉由EPMA觀察之No.1之積層型晶片變阻器之剖面上的所有成分之濃度分布之圖。Fig. 11 is a graph showing the concentration distribution of all components on the cross section of the laminated wafer varistor of No. 1 observed by EPMA.
圖12為顯示藉由EPMA觀察之No.45之積層型晶片變阻器 之剖面上的Pr濃度分布之圖。Figure 12 is a multilayer wafer varistor showing No. 45 observed by EPMA. A plot of the concentration of Pr concentration on the profile.
圖13為顯示藉由EPMA觀察之No.45之積層型晶片變阻器之剖面上的Co濃度分布之圖。Fig. 13 is a view showing a Co concentration distribution on a cross section of a laminated wafer varistor of No. 45 observed by EPMA.
圖14為顯示藉由EPMA觀察之No.45之積層型晶片變阻器之剖面上的Pd濃度分布之圖。Fig. 14 is a graph showing the Pd concentration distribution on the cross section of the laminated wafer varistor of No. 45 observed by EPMA.
圖15為顯示藉由EPMA觀察之No.45之積層型晶片變阻器之剖面上的Ag濃度分布之圖。Fig. 15 is a graph showing the Ag concentration distribution on the cross section of the laminated wafer varistor of No. 45 observed by EPMA.
圖16為顯示藉由EPMA觀察之No.45之積層型晶片變阻器之剖面上的所有成分之濃度分布之圖。Fig. 16 is a graph showing the concentration distribution of all components on the cross section of the laminated wafer varistor of No. 45 observed by EPMA.
1‧‧‧積層型晶片變阻器1‧‧‧Laminated wafer varistor
2‧‧‧變阻層2‧‧‧variable resistance layer
4a、4b‧‧‧內部電極4a, 4b‧‧‧ internal electrodes
5‧‧‧變阻器素體5‧‧‧varistor body
6‧‧‧外部電極6‧‧‧External electrode
8‧‧‧鍍Ni層8‧‧‧Ni plating
10‧‧‧鍍Sn層10‧‧‧Sn plating layer
Claims (8)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003435078A JP3924563B2 (en) | 2003-12-26 | 2003-12-26 | Multilayer chip varistor |
Publications (2)
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TW200532714A TW200532714A (en) | 2005-10-01 |
TWI396206B true TWI396206B (en) | 2013-05-11 |
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TW093139856A TWI396206B (en) | 2003-12-26 | 2004-12-21 | Laminated Chip Rheostat |
Country Status (4)
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JP (1) | JP3924563B2 (en) |
KR (1) | KR101060970B1 (en) |
CN (1) | CN100541675C (en) |
TW (1) | TWI396206B (en) |
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KR100411721B1 (en) * | 2000-10-19 | 2003-12-18 | 주식회사 바이오제네시스 | Apparatus for fluorine coating of teeth |
JP4910513B2 (en) * | 2005-07-25 | 2012-04-04 | Tdk株式会社 | Surge absorption circuit |
KR100834307B1 (en) * | 2005-11-15 | 2008-06-02 | 티디케이가부시기가이샤 | A method of producing a laminated type chip varistor |
JP4710560B2 (en) * | 2005-11-15 | 2011-06-29 | Tdk株式会社 | Manufacturing method of multilayer chip varistor |
JP2007165639A (en) * | 2005-12-14 | 2007-06-28 | Tdk Corp | Varistor and method of manufacturing varistor |
JP4492579B2 (en) * | 2006-03-31 | 2010-06-30 | Tdk株式会社 | Varistor body and varistor |
KR100839682B1 (en) * | 2006-12-22 | 2008-06-19 | 주식회사 아모텍 | Complex chip device |
JP4888225B2 (en) * | 2007-03-30 | 2012-02-29 | Tdk株式会社 | Varistor and light emitting device |
JP5696623B2 (en) * | 2011-08-29 | 2015-04-08 | Tdk株式会社 | Chip varistor |
CN112951530A (en) * | 2021-03-29 | 2021-06-11 | 北京交通大学 | Aging-resistant composite arrester with gap for electric locomotive and motor train unit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283209A (en) * | 1992-04-03 | 1993-10-29 | Murata Mfg Co Ltd | Laminated varistor |
TW434587B (en) * | 1998-07-08 | 2001-05-16 | Murata Manufacturing Co | Chip thermistors and methods of making same |
US6339367B1 (en) * | 1999-03-26 | 2002-01-15 | Tdk Corporation | Laminated chip type varistor |
US6346871B1 (en) * | 1998-01-09 | 2002-02-12 | Tdk Corporation | Laminate type varistor |
US20030043013A1 (en) * | 2001-08-30 | 2003-03-06 | Matsushita Electric Industrial Co., Ltd. | Zinc oxide varistor and method of manufacturing same |
-
2003
- 2003-12-26 JP JP2003435078A patent/JP3924563B2/en not_active Expired - Lifetime
-
2004
- 2004-12-21 TW TW093139856A patent/TWI396206B/en active
- 2004-12-23 KR KR1020040110926A patent/KR101060970B1/en active IP Right Grant
- 2004-12-24 CN CNB2004101026611A patent/CN100541675C/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283209A (en) * | 1992-04-03 | 1993-10-29 | Murata Mfg Co Ltd | Laminated varistor |
US6346871B1 (en) * | 1998-01-09 | 2002-02-12 | Tdk Corporation | Laminate type varistor |
TW434587B (en) * | 1998-07-08 | 2001-05-16 | Murata Manufacturing Co | Chip thermistors and methods of making same |
US6339367B1 (en) * | 1999-03-26 | 2002-01-15 | Tdk Corporation | Laminated chip type varistor |
US20030043013A1 (en) * | 2001-08-30 | 2003-03-06 | Matsushita Electric Industrial Co., Ltd. | Zinc oxide varistor and method of manufacturing same |
Also Published As
Publication number | Publication date |
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JP2005197281A (en) | 2005-07-21 |
JP3924563B2 (en) | 2007-06-06 |
TW200532714A (en) | 2005-10-01 |
CN100541675C (en) | 2009-09-16 |
KR101060970B1 (en) | 2011-09-01 |
CN1637961A (en) | 2005-07-13 |
KR20050067026A (en) | 2005-06-30 |
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