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TWI383506B - Schottky diode device and method for fabricating the same - Google Patents

Schottky diode device and method for fabricating the same Download PDF

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TWI383506B
TWI383506B TW98115970A TW98115970A TWI383506B TW I383506 B TWI383506 B TW I383506B TW 98115970 A TW98115970 A TW 98115970A TW 98115970 A TW98115970 A TW 98115970A TW I383506 B TWI383506 B TW I383506B
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region
doped region
type doped
diode device
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TW98115970A
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TW201041147A (en
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Huang Lang Pai
Hung Shern Tsai
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Vanguard Int Semiconduct Corp
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Description

蕭基二極體裝置及其製造方法Xiaoji diode device and manufacturing method thereof

本發明係關於半導體裝置,且特別是關於一種蕭基二極體(Schottky diode)裝置及其製造方法。The present invention relates to semiconductor devices, and more particularly to a Schottky diode device and a method of fabricating the same.

蕭基二極體(Schottky diode)為具有金屬-半導體接面(metal-semiconductor junction)的一種半導體裝置,於此金屬-半導體接面結構之電流-電壓特性則按照所施加電壓的極性而定。A Schottky diode is a semiconductor device having a metal-semiconductor junction, and the current-voltage characteristics of the metal-semiconductor junction structure depend on the polarity of the applied voltage.

當蕭基二極體處於順向偏壓時(即陽極施加正電壓以及於陰極施加負電壓)可使得載子導通,而當蕭基二極體處於逆向偏壓時(即陽極施加負電壓以及於陰極施加正電壓)則載子不易導通,因而與一般pn接面二極體具有同樣之單向導通特性。另外,由於蕭基二極體係為單載子移動,故於順向偏壓時具有相對低之臨界電壓且於順逆向偏壓切換時反應速度極快。When the Schottky diode is in a forward bias (ie, a positive voltage is applied to the anode and a negative voltage is applied to the cathode), the carrier can be turned on, and when the Schottky diode is in a reverse bias (ie, the anode is applied with a negative voltage and When a positive voltage is applied to the cathode, the carrier is not easily conductive, and thus has the same unidirectional conduction characteristics as a general pn junction diode. In addition, since the Xiaoji two-pole system moves as a single carrier, it has a relatively low threshold voltage in the forward bias and a very fast response speed in the forward bias switching.

請參照第1圖,顯示了一種習知蕭基二極體裝置100的剖面情形。如第1圖所示,蕭基二極體裝置100包括了n型漂移區(n drift region)104、陽極電極112、陰極電極114以及形成於n型漂移區(n drift region)104內之n+摻雜區116等主要構件。n型漂移區104係形成於p型矽基底102之表面內,而於n型漂移區104表面形成有兩分隔之場氧化物108,以於n型漂移區104表面定義出為場氧化物108所分隔之陽極區150以及陰極區160。於n型漂移區104表面上更形成有經圖案化之層間介電層110,其覆蓋了場氧化物108及其鄰近之n型漂移區104與n+摻雜區116的部分表面,而由鈦、氮化鈦、鎢、鋁等金屬材質所形成之陽極電極112與陰極電極114則分別覆蓋並穿透層間介電層110以分別實體接觸位於陽極區150內之n型漂移區104以及位於陰極區160內之n+摻雜區116。於陽極區150內鄰近場氧化物108處之n型漂移區104內分別形成有一p型摻雜區106,以避免於電極112鄰近n型漂移區104與場氧化物108處區域內形成高電場,藉以提升蕭基二極體裝置100的逆向偏壓下之電壓崩潰表現。於蕭基二極體裝置100內之陽極電極112及相接觸之n型漂移區104間之介面即為一金屬-半導體接面120。Referring to Figure 1, a cross-sectional view of a conventional Schottky diode device 100 is shown. As shown in FIG. 1, the Schottky diode device 100 includes an n-type drift region 104, an anode electrode 112, a cathode electrode 114, and n+ formed in an n-drift region 104. Main components such as doped region 116. The n-type drift region 104 is formed in the surface of the p-type germanium substrate 102, and two separate field oxides 108 are formed on the surface of the n-type drift region 104 to define the field oxide 108 on the surface of the n-type drift region 104. The anode region 150 and the cathode region 160 are separated. A patterned interlayer dielectric layer 110 is formed on the surface of the n-type drift region 104, which covers a portion of the surface oxide 108 and its adjacent n-type drift region 104 and n+ doped region 116, and is made of titanium. The anode electrode 112 and the cathode electrode 114 formed of a metal material such as titanium nitride, tungsten or aluminum respectively cover and penetrate the interlayer dielectric layer 110 to physically contact the n-type drift region 104 located in the anode region 150 and at the cathode, respectively. The n+ doped region 116 within region 160. A p-type doped region 106 is formed in the n-type drift region 104 adjacent to the field oxide 108 in the anode region 150 to avoid formation of a high electric field in the region of the electrode 112 adjacent to the n-type drift region 104 and the field oxide 108. In order to enhance the voltage collapse performance of the Xiaoji diode device 100 under the reverse bias. The interface between the anode electrode 112 in the Xiaoji diode device 100 and the n-type drift region 104 in contact with each other is a metal-semiconductor junction 120.

另外,為了進一步提升蕭基二極體裝置100之逆向偏壓下的崩潰電壓,n型漂移區104內之n型摻質濃度通常不可高於2.0*1016 atoms/cm3 。如此之n型漂移區104的摻質濃度雖有助於提升蕭基二極體裝置100於逆向偏壓下的崩潰電壓表現,但是卻使得蕭基二極體裝置100於順向偏壓下流通於陽極區150與陰極區160間的單位面積電流受到限制。In addition, in order to further increase the breakdown voltage under the reverse bias of the Schottky diode device 100, the n-type dopant concentration in the n-type drift region 104 is generally not higher than 2.0*10 16 atoms/cm 3 . The doping concentration of the n-type drift region 104 helps to increase the breakdown voltage performance of the Schottky diode device 100 under reverse bias, but causes the Schottky diode device 100 to circulate under forward bias. The current per unit area between the anode region 150 and the cathode region 160 is limited.

因此,便需要一種新穎之蕭基二極體裝置,以滿足逆向電壓下的高崩潰電壓以及順向偏壓下的高單位面積電流等元件需求。Therefore, there is a need for a novel Schottky diode device that meets the high breakdown voltage at reverse voltage and high unit area current under forward bias.

有鑑於此,本發明提供了一種蕭基二極體裝置及其製造方法,以改善其崩潰電壓與單位面積電流等電性表現。In view of the above, the present invention provides a Xiaoji diode device and a method of fabricating the same to improve the electrical performance of the breakdown voltage and current per unit area.

依據一實施例,本發明提供了一種蕭基二極體裝置,包括:一p型半導體結構;一n型漂移區,設置於該p型半導體結構表面,其中該n型漂移區包括摻質濃度相異之一第一n型摻雜區以及一第二n型摻雜區,而該第二n型摻雜區係環繞該第一n型摻雜區之側壁且具有較該第一n型摻雜區為高之摻質濃度;複數個隔離結構,設置於該n型漂移區之該第二n型摻雜區內,以定義出一陽極區以及一陰極區,其中該陽極區露出該第一n型摻雜區之表面而該陰極區部分露出該第二n型摻雜區之表面;一第三n型摻雜區,設置於為該陰極區所部分露出之第二n型摻雜區表面,其中該第三n型摻雜區具有高於該第二n型摻雜區之摻質濃度;一陽極電極,設置於該陽極區內之該第一n型摻雜區之上;以及一陰極電極,設置於該陰極區內之該第三n型摻雜區之上。According to an embodiment, the present invention provides a Schottky diode device comprising: a p-type semiconductor structure; an n-type drift region disposed on a surface of the p-type semiconductor structure, wherein the n-type drift region includes a dopant concentration Dividing a first n-type doped region and a second n-type doped region, and the second n-type doped region surrounds a sidewall of the first n-type doped region and has a first n-type The doped region is a high dopant concentration; a plurality of isolation structures are disposed in the second n-type doping region of the n-type drift region to define an anode region and a cathode region, wherein the anode region is exposed a surface of the first n-type doped region and the cathode region partially exposing a surface of the second n-type doped region; a third n-type doped region disposed at a second n-type doping partially exposed for the cathode region a surface of the impurity region, wherein the third n-type doped region has a dopant concentration higher than the second n-type doped region; an anode electrode disposed over the first n-type doped region in the anode region And a cathode electrode disposed above the third n-type doped region in the cathode region.

依據另一實施例,本發明提供了一種蕭基二極體裝置之製造方法,包括:提供一p型半導體層;形成一n型漂移區於該p型半導體層表面內,其中該n型漂移區包括一第一n型摻雜區以及環繞該第一n型摻雜區之一第二n型摻雜區,而該第二n型摻雜區具有高於該第一n型摻雜區之摻質濃度;形成數個隔離結構於鄰近該第一n型摻雜區之該第二n型摻雜區之內,進而於該p型半導體層上定義出一陽極區與一陰極區,其中該陽極區露出了該第一n型摻雜區及鄰近該第一n型摻雜區之該第二n型摻雜區之一部分,而該陰極區僅露出了該第二n型摻雜區之另一部分;形成一第三n型摻雜區於該陰極區所露出之該第二n型摻雜區之內;以及於該陽極區與陰極區內分別形成一陽極電極與一陰極電極,以分別實體接觸該第一n型摻雜區與該第三n型摻雜區。According to another embodiment, the present invention provides a method of fabricating a Schottky diode device, comprising: providing a p-type semiconductor layer; forming an n-type drift region in a surface of the p-type semiconductor layer, wherein the n-type drift The region includes a first n-type doped region and a second n-type doped region surrounding the first n-type doped region, and the second n-type doped region has a higher than the first n-type doped region a concentration of the dopant; forming a plurality of isolation structures in the second n-type doped region adjacent to the first n-type doped region, thereby defining an anode region and a cathode region on the p-type semiconductor layer, Wherein the anode region exposes a portion of the first n-type doped region and the second n-type doped region adjacent to the first n-type doped region, and the cathode region exposes only the second n-type doping Another portion of the region; forming a third n-type doped region within the second n-type doped region exposed by the cathode region; and forming an anode electrode and a cathode electrode in the anode region and the cathode region, respectively And physically contacting the first n-type doped region and the third n-type doped region, respectively.

為了讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉一較佳實施例,並配合所附圖示,作詳細說明如下:The above and other objects, features, and advantages of the present invention will become more apparent and understood.

第2-6圖為一系列剖面圖,顯示了依據本發明一實施例之蕭基二極體裝置之製造方法。2-6 are a series of cross-sectional views showing a method of fabricating a Schottky diode device in accordance with an embodiment of the present invention.

請參照第2圖,首先提供一p型半導體結構,例如為一p型半導體層202。p型半導體層202例如為含矽、矽鍺之半導體材料之磊晶層或基板之一部。接著於半導體基板202之表面形成數個圖案化之罩幕層204並露出部分之p型半導體層202。接著,針對p型半導體層202施行一離子佈植程序206並採用此些罩幕層204做為離子佈植罩幕,因此於p型半導體層202內形成了數個相分隔之n型摻雜區208。離子佈植程序206係採用磷與砷等n型摻質,其所採用之離子佈植能量約介於500KeV~800KeV,而所佈植n型摻質劑量則約介於2*1012 ~8*1012 atoms/cm2Referring to FIG. 2, a p-type semiconductor structure, such as a p-type semiconductor layer 202, is first provided. The p-type semiconductor layer 202 is, for example, an epitaxial layer of a semiconductor material containing germanium or germanium or a portion of a substrate. A plurality of patterned mask layers 204 are then formed on the surface of the semiconductor substrate 202 to expose portions of the p-type semiconductor layer 202. Next, an ion implantation process 206 is performed on the p-type semiconductor layer 202 and the mask layer 204 is used as an ion implantation mask, thereby forming a plurality of phase-separated n-type dopings in the p-type semiconductor layer 202. Area 208. The ion implantation process 206 uses n-type dopants such as phosphorus and arsenic, and the ion implantation energy used is about 500KeV~800KeV, and the n-type dopant dose is about 2*10 12 ~8. *10 12 atoms/cm 2 .

如第2圖所示,由於p型半導體層202之上形成有數個分隔之罩幕層204,故於離子佈植程序206施行後於所形成之相分隔之數個n型摻雜區208之間分別存在有一未經n型摻雜之p型條狀區210,其仍具有相同於p型半導體層202之摻雜特性與摻質濃度。在此,此些罩幕層204分別具有介於0.4μm~0.8μm之寬度W且相鄰罩幕層204之間存在有介於0.4μm~0.8μm之間距P。如此,可藉由調整形成於p型半導體層202上的罩幕層204數量、其寬度W以及相鄰罩幕層204之間距P而達到控制所形成之p型條狀區210的數量、範圍與輪廓。As shown in FIG. 2, since a plurality of separate mask layers 204 are formed on the p-type semiconductor layer 202, the n-type doped regions 208 are separated from the formed phase after the ion implantation process 206 is performed. There is a p-type strip region 210 which is not doped with n-type, respectively, which still has the same doping characteristics and dopant concentration as the p-type semiconductor layer 202. Here, the mask layers 204 each have a width W of 0.4 μm to 0.8 μm and a distance P between 0.4 μm and 0.8 μm between adjacent mask layers 204. Thus, the number and range of the p-type strip regions 210 formed by the control can be adjusted by adjusting the number of the mask layers 204 formed on the p-type semiconductor layer 202, the width W thereof, and the distance P between the adjacent mask layers 204. With contours.

請參照第3圖,於移除形成於p型半導體層202上之罩幕層204(請參見第2圖)之後,接著施行一回火程序(未顯示),以於1000~1100℃之溫度下進行回火處理。因此,於回火程序施行過後,於p型半導體層202表面便形成了一第一n型摻雜區214以及環繞此第一n型摻雜區214側壁之一第二n型摻雜區212,而第一n型摻雜區214與第二n型摻雜區212之底面分別接觸了p型半導體層202。在此,第二n型摻雜區212內的摻質濃度約介於2*1016 ~8*1016 atoms/cm3 ,第一n型摻雜區214內摻質濃度約介於4*1015 ~2*1016 atoms/cm3 ,而第二n型摻雜區212內的摻質濃度高於第一n型摻雜區214內摻質濃度,且先前之p型條狀區210於回火程序施行過後便不復存在。第一n型摻雜區214與第二n型摻雜區212組成了蕭基二極體裝置之n型漂移區250。Referring to FIG. 3, after removing the mask layer 204 formed on the p-type semiconductor layer 202 (see FIG. 2), a tempering process (not shown) is performed to maintain a temperature of 1000 to 1100 ° C. The tempering process is performed. Therefore, after the tempering process is performed, a first n-type doping region 214 and a second n-type doping region 212 surrounding one of the sidewalls of the first n-type doping region 214 are formed on the surface of the p-type semiconductor layer 202. The first n-type doped region 214 and the bottom surface of the second n-type doped region 212 respectively contact the p-type semiconductor layer 202. Here, the dopant concentration in the second n-type doping region 212 is about 2*10 16 ~8*10 16 atoms/cm 3 , and the dopant concentration in the first n-type doping region 214 is about 4*. 10 15 ~ 2 * 10 16 atoms / cm 3 , and the dopant concentration in the second n-type doping region 212 is higher than the dopant concentration in the first n-type doping region 214, and the previous p-type strip region 210 After the tempering procedure was implemented, it no longer existed. The first n-type doped region 214 and the second n-type doped region 212 constitute an n-type drift region 250 of the Schottky diode device.

請繼續參照第3圖,接著於n型漂移區250表面形成圖案化之一罩幕層216並分別露出位於第一n型摻雜區214兩側之第二n型摻雜區212的一部分。接著採用罩幕層216作為離子佈植罩幕而施行一離子佈植程序218,以於位於第一n型摻雜區214兩側之第二n型摻雜區212之內分別形成了一p型摻雜區220。離子佈植程序218係採用如硼之p型摻質,其所採用之離子佈植能量約介於40KeV~80KeV,而所佈植p型摻質劑量則約介於8*1013 ~5*1014 atoms/cm2Referring to FIG. 3, a patterned mask layer 216 is then formed on the surface of the n-type drift region 250 and a portion of the second n-type doping region 212 on both sides of the first n-type doping region 214 is exposed. Then, an ion implantation process 218 is performed by using the mask layer 216 as an ion implantation mask to form a p in the second n-type doping region 212 on both sides of the first n-type doping region 214. Type doped region 220. The ion implantation process 218 uses a p-type dopant such as boron, which uses an ion implantation energy of about 40 KeV to 80 KeV, and the implanted p-type dopant dose is about 8*10 13 ~5*. 10 14 atoms/cm 2 .

請參照第4圖,接著於除去罩幕層216(請參見第3圖)之後,於n型漂移區250內之第二n型摻雜區212表面及其內形成兩分隔之隔離結構222,以於n型漂移區250表面定義出此蕭基二極體裝置之陽極區260與陰極區270。在此,隔離結構222係繪示為習知之場氧化物(filed oxide)且可為習知場氧化物製程所形成,但並非加以限定本發明,隔離結構222亦可採用其他型態之隔離結構。於形成隔離結構222時可同時對於先前形成之p型摻雜區220(請參見第3圖)進行回火動作,並於隔離結構222形成後同時將之轉化成為鄰近並包覆各隔離結構222的一邊角之p型摻雜區220。此p型摻雜區220亦部分延伸進入了第一n型摻雜區214之內。接著形成一圖案化之罩幕層224,以大體覆蓋了隔離結構222與陽極區260並露出了陰極區270內之第二n型摻雜區212的表面。接著進行一離子佈植程序226以於第二n型摻雜區212表面形成了n+摻雜區228以作為陰極接點之用。離子佈植程序226係採用磷與砷等n型摻質,其所採用之離子佈植能量約介於40KeV~60KeV,而所佈植n型摻質劑量則約介於1*1015 ~5*1015 atoms/cm2Referring to FIG. 4, after removing the mask layer 216 (see FIG. 3), two separate isolation structures 222 are formed on the surface of the second n-type doping region 212 in the n-type drift region 250 and therein. The anode region 260 and the cathode region 270 of the Schottky diode device are defined on the surface of the n-type drift region 250. Here, the isolation structure 222 is shown as a conventional filed oxide and can be formed by a conventional field oxide process, but the invention is not limited thereto, and the isolation structure 222 can also adopt other types of isolation structures. . When the isolation structure 222 is formed, the previously formed p-type doping region 220 (see FIG. 3) may be simultaneously tempered, and after the isolation structure 222 is formed, the isolation structure 222 is simultaneously formed into adjacent and covered isolation structures 222. The p-doped region 220 of the one corner. The p-doped region 220 also extends partially into the first n-type doped region 214. A patterned mask layer 224 is then formed to substantially cover the isolation structure 222 and the anode region 260 and expose the surface of the second n-type doped region 212 within the cathode region 270. An ion implantation process 226 is then performed to form an n+ doped region 228 on the surface of the second n-type doped region 212 for use as a cathode junction. The ion implantation process 226 uses n-type dopants such as phosphorus and arsenic, and the ion implantation energy used is about 40KeV~60KeV, and the n-type dopant dose is about 1*10 15 ~5. *10 15 atoms/cm 2 .

請參照第5圖,於移除罩幕層224(見於第4圖)之後,接著形成圖案化之層間介電層230,其分別大體覆蓋了隔離結構222及鄰近隔離結構222之部分p型摻雜區220與n+摻雜區228。於層間介電層230內形成有一開口235與237,分別大體露出第一n型摻雜區214之整個表面以及部分之n+摻雜區228表面。Referring to FIG. 5, after removing the mask layer 224 (see FIG. 4), a patterned interlayer dielectric layer 230 is formed, which substantially covers the isolation structure 222 and a portion of the p-type dopant adjacent to the isolation structure 222. The impurity region 220 and the n+ doping region 228. Openings 235 and 237 are formed in the interlayer dielectric layer 230 to expose the entire surface of the first n-type doping region 214 and a portion of the surface of the n+ doping region 228, respectively.

請參照第6圖,接著形成圖案化之電極層232與234,其中電極層232係設置於p型摻雜區220與第一n型摻雜區214之上且部分覆蓋鄰近之層間介電層230,而電極層234則設置於n+摻雜區228之上且部分覆蓋鄰近之層間介電層234。電極232與234分別作為陽極電極與陰極電極之用,其可採用如鈦、氮化鈦、鎢、鋁等金屬材料且可採用如沈積、研磨與蝕刻等習知製程所形成。Referring to FIG. 6, a patterned electrode layer 232 and 234 are formed, wherein the electrode layer 232 is disposed over the p-type doping region 220 and the first n-type doping region 214 and partially cover the adjacent interlayer dielectric layer. 230, and the electrode layer 234 is disposed over the n+ doped region 228 and partially covers the adjacent interlayer dielectric layer 234. The electrodes 232 and 234 are used as an anode electrode and a cathode electrode, respectively, and may be formed of a metal material such as titanium, titanium nitride, tungsten, aluminum, or the like, and may be formed by a conventional process such as deposition, grinding, and etching.

如第6圖所示,顯示了依據本發明之一實施例之蕭基二極體裝置,其主要包括:一p型半導體結構(例如p型半導體層202);一n型漂移區,設置於p型半導體結構表面,其中n型漂移區包括摻質濃度相異之一第一n型摻雜區(例如第一n型摻雜區214)以及一第二n型摻雜區(例如第二n型摻雜區212),而第二n型摻雜區係環繞該第一n型摻雜區之側壁且具有較第一n型摻雜區為高之摻質濃度;複數個隔離結構(例如隔離結構222),設置於n型漂移區之第二n型摻雜區內,以定義出一陽極區(例如陽極區260)以及一陰極區(例如陰極區270),其中該陽極區露出第一n型摻雜區之表面而陰極區部分露出第二n型摻雜區之表面;一第三n型摻雜區(例如n+摻雜區228),設置於為該陰極區所部分露出之第二n型摻雜區表面,其中第三n型摻雜區具有高於第二n型摻雜區之摻質濃度;一陽極電極(例如陽極電極232),設置於陽極區內之該第一n型摻雜區之上;以及一陰極電極(例如陰極電極234),設置於陰極區內之該第三n型摻雜區之上。As shown in FIG. 6, a Schottky diode device according to an embodiment of the present invention is shown, which mainly includes: a p-type semiconductor structure (for example, p-type semiconductor layer 202); an n-type drift region, which is disposed on a p-type semiconductor structure surface, wherein the n-type drift region comprises a first n-type doped region (eg, a first n-type doped region 214) and a second n-type doped region (eg, a second) having different dopant concentrations An n-type doped region 212), and the second n-type doped region surrounds a sidewall of the first n-type doped region and has a higher dopant concentration than the first n-type doped region; a plurality of isolation structures ( For example, the isolation structure 222) is disposed in the second n-type doping region of the n-type drift region to define an anode region (eg, the anode region 260) and a cathode region (eg, the cathode region 270), wherein the anode region is exposed. a surface of the first n-type doped region and a portion of the cathode region exposing a surface of the second n-type doped region; a third n-type doped region (eg, n+ doped region 228) disposed to be partially exposed for the cathode region a second n-type doped region surface, wherein the third n-type doped region has a higher dopant concentration than the second n-type doped region; an anode electrode (eg, an anode) 232), disposed on the first n-doped region of the anode region; and a cathode over the electrode (e.g., cathode electrode 234), disposed on the third n-type doped region of the cathode region.

於本實施例中,蕭基二極體裝置係包括了由摻質濃度相對較低之第一n型摻雜區214與摻質濃度相對較高之第二n型摻雜區212所組成之一n型漂移區250,其中第一n型摻雜區214係實體接觸了陽極電極232,基於其相對為低之n型摻質濃度,因而有助於提升於陽極電極232與第一n型摻雜區214間之金屬-半導體接面280處的逆向偏壓時的崩潰電壓表現。另外,由於介於陽極區260與陰極區270間之第二n型摻雜區212具有相對高之n型摻質濃度,因而可改善蕭基二極體裝置之單位面積電流量。In this embodiment, the Schottky diode device includes a first n-type doping region 214 having a relatively low dopant concentration and a second n-type doping region 212 having a relatively high dopant concentration. An n-type drift region 250, wherein the first n-type doped region 214 is in physical contact with the anode electrode 232, based on its relatively low n-type dopant concentration, thereby contributing to the elevation of the anode electrode 232 and the first n-type The breakdown voltage at the reverse bias of the metal-semiconductor junction 280 between the doped regions 214. In addition, since the second n-type doping region 212 between the anode region 260 and the cathode region 270 has a relatively high n-type dopant concentration, the amount of current per unit area of the Schottky diode device can be improved.

另外,參照第2~6圖之製造流程,本發明之蕭基二極體裝置之製造方法係針對如第1圖所示之習知蕭基二極體裝置內用於形成n型漂移區104之光罩進行圖樣修正,即可形成如第6圖所示之由兩種不同n型摻質濃度之n型摻雜區所組成之n型漂移區250,且不會造成製造流程所需光罩數的增加,並可藉由適度調整p型條狀區210的數量、寬度及p型條狀區210間的間距而達成控制蕭基接面280下之n型摻質濃度的目的。Further, referring to the manufacturing flow of FIGS. 2 to 6, the manufacturing method of the Schottky diode device of the present invention is for forming the n-type drift region 104 in the conventional Schottky diode device as shown in FIG. The pattern mask is modified to form an n-type drift region 250 composed of two different n-type doping regions of different n-type dopant concentrations as shown in FIG. 6 without causing light required for the manufacturing process. The number of masks is increased, and the purpose of controlling the n-type dopant concentration under the Schottky junction 280 can be achieved by appropriately adjusting the number and width of the p-type strip regions 210 and the spacing between the p-type strip regions 210.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100...蕭基二極體裝置100. . . Xiaoji diode device

102...p型矽基底102. . . P-type germanium substrate

104...n型漂移區104. . . N-type drift region

106...p型摻雜區106. . . P-doped region

108...場氧化物108. . . Field oxide

110...層間介電層110. . . Interlayer dielectric layer

112...陽極電極112. . . Anode electrode

114...陰極電極114. . . Cathode electrode

116...n+摻雜區116. . . n+ doped region

120...金屬-半導體接面120. . . Metal-semiconductor junction

150...陽極區150. . . Anode region

160...陰極區160. . . Cathode region

202...p型半導體層202. . . P-type semiconductor layer

204...罩幕層204. . . Mask layer

206...離子佈植程序206. . . Ion implantation procedure

208...n型摻雜區208. . . N-doped region

210...p型條狀區210. . . P-type strip

212...第二n型摻雜區212. . . Second n-doped region

214...第一n型摻雜區214. . . First n-doped region

216...罩幕層216. . . Mask layer

218...離子佈植程序218. . . Ion implantation procedure

220...p型摻雜區220. . . P-doped region

222...隔離結構222. . . Isolation structure

224...罩幕層224. . . Mask layer

226...離子佈植程序226. . . Ion implantation procedure

228...n+摻雜區228. . . n+ doped region

230...層間介電層230. . . Interlayer dielectric layer

232、234...電極232, 234. . . electrode

235、237...開口235, 237. . . Opening

250...n型漂移區250. . . N-type drift region

260...陽極區260. . . Anode region

270...陰極區270. . . Cathode region

280...金屬-半導體接面280. . . Metal-semiconductor junction

W...罩幕層/p型條狀區之寬度W. . . Width of the mask layer/p-type strip

P...罩幕層/p型條狀區之間距P. . . Mask layer / p-type strip area

第1圖顯示了一習知蕭基二極體裝置之剖面情形;以及Figure 1 shows a cross-sectional view of a conventional Xiaoji diode device;

第2-6圖為一系列剖面圖,顯示了依據本發明一實施例之蕭基二極體裝置之製造方法。2-6 are a series of cross-sectional views showing a method of fabricating a Schottky diode device in accordance with an embodiment of the present invention.

202...p型半導體層202. . . P-type semiconductor layer

212...第二n型摻雜區212. . . Second n-doped region

214...第一n型摻雜區214. . . First n-doped region

220...p型摻雜區220. . . P-doped region

222...隔離結構222. . . Isolation structure

228...n+摻雜區228. . . n+ doped region

230...層間介電層230. . . Interlayer dielectric layer

232、234...電極232, 234. . . electrode

250...n型漂移區250. . . N-type drift region

260...陽極區260. . . Anode region

270...陰極區270. . . Cathode region

280...金屬-半導體接面280. . . Metal-semiconductor junction

Claims (18)

一種蕭基二極體裝置,包括:一p型半導體結構;一n型漂移區,設置於該p型半導體結構表面,其中該n型漂移區包括摻質濃度相異之一第一n型摻雜區以及一第二n型摻雜區,而該第二n型摻雜區係環繞並接觸該第一n型摻雜區之側壁且具有較該第一n型摻雜區為高之摻質濃度,且其中該第一n型摻雜區之底面實體接觸該p型半導體結構;複數個隔離結構,設置於該n型漂移區之該第二n型摻雜區內,以定義出一陽極區以及一陰極區,其中該陽極區露出該第一n型摻雜區之表面而該陰極區部分露出該第二n型摻雜區之表面;一第三n型摻雜區,設置於為該陰極區所部分露出之第二n型摻雜區表面,其中該第三n型摻雜區具有高於該第二n型摻雜區之摻質濃度;一陽極電極,設置於該陽極區內之該第一n型摻雜區之上;以及一陰極電極,設置於該陰極區內之該第三n型摻雜區之上。 A Schottky diode device comprising: a p-type semiconductor structure; an n-type drift region disposed on a surface of the p-type semiconductor structure, wherein the n-type drift region comprises a first n-type doping different in dopant concentration a doped region and a second n-type doped region, the second n-type doped region surrounding and contacting the sidewall of the first n-type doped region and having a higher doping than the first n-type doped region a concentration of the first n-type doped region physically contacting the p-type semiconductor structure; a plurality of isolation structures disposed in the second n-type doped region of the n-type drift region to define a An anode region and a cathode region, wherein the anode region exposes a surface of the first n-type doped region and the cathode region partially exposes a surface of the second n-type doped region; a third n-type doped region is disposed on a surface of the second n-type doped region partially exposed by the cathode region, wherein the third n-type doped region has a dopant concentration higher than the second n-type doped region; an anode electrode is disposed at the anode Above the first n-type doped region in the region; and a cathode electrode, the third n-type doped region disposed in the cathode region On. 如申請專利範圍第1項所述之蕭基二極體裝置,其中該第一n型摻雜區具有介於4*1015 ~2*1016 atoms/cm3 之摻質濃度,而該第二n型摻雜區具有介於2*1016 ~8*1016 atoms/cm3 之摻質濃度。The Xiaoji diode device according to claim 1, wherein the first n-type doping region has a dopant concentration of 4*10 15 ~2*10 16 atoms/cm 3 , and the first The two n-type doped regions have a dopant concentration of between 2*10 16 and 8*10 16 atoms/cm 3 . 如申請專利範圍第1項所述之蕭基二極體裝置,其 中該第二n型摻雜區之底面接觸該p型半導體結構。 Such as the Xiaoji diode device described in claim 1 of the patent scope, The bottom surface of the second n-type doped region contacts the p-type semiconductor structure. 如申請專利範圍第1項所述之蕭基二極體裝置,更包括一p型摻雜區,設置於為該陽極區所露出之該第一n型摻雜區與該第二n型摻雜區表面之內並包覆該些隔離結構之一的邊角。 The Xiaoji diode device according to claim 1, further comprising a p-type doping region disposed on the first n-type doping region and the second n-type doping exposed for the anode region. Within the surface of the miscellaneous region and covering the corners of one of the isolation structures. 如申請專利範圍第4項所述之蕭基二極體裝置,其中該p型摻雜區具有介於8*1015 ~5*1016 atoms/cm3 之摻質濃度。The Schottky diode device of claim 4, wherein the p-type doped region has a dopant concentration of between 8*10 15 and 5*10 16 atoms/cm 3 . 如申請專利範圍第4項所述之蕭基二極體裝置,更包括一層間介電層,設置於該些隔離結構與該陽極電極與陰極電極之間,該層間介電層分別覆蓋該些隔離結構及其鄰近之p型摻雜區及第三n型摻雜區之一部分。 The Xiaoji diode device according to claim 4, further comprising an interlayer dielectric layer disposed between the isolation structure and the anode electrode and the cathode electrode, wherein the interlayer dielectric layer covers the plurality of layers An isolation structure and a portion of the adjacent p-type doped region and the third n-type doped region. 如申請專利範圍第4項所述之蕭基二極體裝置,其中該陽極電極實體接觸該p型摻雜區與該第一n型摻雜區。 The Schottky diode device of claim 4, wherein the anode electrode physically contacts the p-type doped region and the first n-type doped region. 如申請專利範圍第1項所述之蕭基二極體裝置,其中該第三n型摻雜區具有介於1*1017 ~5*1017 atoms/cm3 之摻質濃度。The Xiaoji diode device according to claim 1, wherein the third n-type doping region has a dopant concentration of between 1*10 17 and 5*10 17 atoms/cm 3 . 如申請專利範圍第1項所述之蕭基二極體裝置,其中該陽極電極與該陰極電極包括鈦、氮化鈦、鎢或鋁。 The Schottky diode device of claim 1, wherein the anode electrode and the cathode electrode comprise titanium, titanium nitride, tungsten or aluminum. 一種蕭基二極體裝置之製造方法,包括:提供一p型半導體層;形成一n型漂移區於該p型半導體層表面內,其中該n型漂移區包括一第一n型摻雜區以及環繞並接觸該第一n型摻雜區之一第二n型摻雜區,而該第二n型摻雜區具有高於該第一n型摻雜區之摻質濃度,且其中該第一n型摻 雜區之底面實體接觸該p型半導體結構;形成數個隔離結構於鄰近該第一n型摻雜區之該第二n型摻雜區之內,進而於該p型半導體層上定義出一陽極區與一陰極區,其中該陽極區露出了該第一n型摻雜區及鄰近該第一n型摻雜區之該第二n型摻雜區之一部分,而該陰極區僅露出了該第二n型摻雜區之另一部分;形成一第三n型摻雜區於該陰極區所露出之該第二n型摻雜區之內;以及於該陽極區與陰極區內分別形成一陽極電極與一陰極電極,以分別實體接觸該第一n型摻雜區與該第三n型摻雜區。 A method for fabricating a Schottky diode device, comprising: providing a p-type semiconductor layer; forming an n-type drift region in a surface of the p-type semiconductor layer, wherein the n-type drift region comprises a first n-type doped region And surrounding and contacting a second n-type doped region of the first n-type doped region, wherein the second n-type doped region has a dopant concentration higher than the first n-type doped region, and wherein First n-type doping The bottom surface of the impurity region physically contacts the p-type semiconductor structure; and a plurality of isolation structures are formed in the second n-type doped region adjacent to the first n-type doped region, thereby defining a p-type semiconductor layer An anode region and a cathode region, wherein the anode region exposes a portion of the first n-type doping region and the second n-type doping region adjacent to the first n-type doping region, and the cathode region is exposed only Another portion of the second n-type doped region; forming a third n-type doped region within the second n-type doped region exposed by the cathode region; and forming respectively in the anode region and the cathode region An anode electrode and a cathode electrode respectively physically contact the first n-type doped region and the third n-type doped region. 如申請專利範圍第10項所述之蕭基二極體裝置之製造方法,其中該第一n型摻雜區具有介於4*1015 ~2*1016 atoms/cm3 之摻質濃度,該第二n型摻雜區具有介於2*1016 ~8*1016 atoms/cm3 之摻質濃度,而該第三n型摻雜區具有介於1*1017 ~5*1017 atoms/cm3 之摻質濃度。The manufacturing method of the Schottky diode device according to claim 10, wherein the first n-type doping region has a dopant concentration of 4*10 15 ~2*10 16 atoms/cm 3 , The second n-type doped region has a dopant concentration of between 2*10 16 and 8*10 16 atoms/cm 3 , and the third n-type doped region has a range of 1*10 17 to 5*10 17 The dopant concentration of atoms/cm 3 . 如申請專利範圍第10項所述之蕭基二極體裝置之製造方法,其中形成該n型漂移區於該p型半導體層表面內包括:於該p型半導體層上形成複數個分隔之第一罩幕層;施行一第一離子佈植程序,採用該些第一罩幕層作為佈植罩幕,於該p型半導體層內形成複數個分隔之第四n型摻雜區以及位於該些第四n型摻雜區間之複數個p型條狀區;移除該些第一罩幕層;以及 施行一第一回火程序,以於該p型半導體層內形成該第一n型摻雜區以及環繞該第一n型摻雜區之該第二n型摻雜區,藉以組成該n型漂移區。 The method of manufacturing a Schottky diode device according to claim 10, wherein the forming the n-type drift region in the surface of the p-type semiconductor layer comprises: forming a plurality of spacers on the p-type semiconductor layer a mask layer; performing a first ion implantation process, using the first mask layer as an implantation mask, forming a plurality of spaced fourth n-type doped regions in the p-type semiconductor layer and located a plurality of p-type strip regions of the fourth n-type doping region; removing the first mask layers; Performing a first tempering process to form the first n-type doped region and the second n-type doped region surrounding the first n-type doped region in the p-type semiconductor layer, thereby forming the n-type Drift zone. 如申請專利範圍第12項所述之蕭基二極體裝置之製造方法,其中該些p型條狀區具有介於0.4μm~0.8μm之寬度以及該些p型條狀區之間具有介於0.4μm~0.8μm之間距。 The method for manufacturing a Schottky diode device according to claim 12, wherein the p-type strip regions have a width of between 0.4 μm and 0.8 μm and the p-type strip regions are interposed therebetween. Between 0.4μm and 0.8μm. 如申請專利範圍第10項所述之蕭基二極體裝置之製造方法,其中形成該些隔離結構之前,更包括:形成一第一罩幕層,部分露出鄰近該第一n型摻雜區之該第二n型摻雜區之一部分;以及施行一第一離子佈值程序,採用該第一罩幕層作為佈植罩幕,以於鄰近該第一n型摻雜區之該第二n型摻雜區之表面形成一p型摻雜區。 The method for manufacturing a Schottky diode device according to claim 10, wherein before forming the isolation structures, the method further comprises: forming a first mask layer partially exposed adjacent to the first n-type doping region a portion of the second n-type doped region; and performing a first ion routing process using the first mask layer as an implant mask to be adjacent to the second of the first n-type doped regions The surface of the n-type doped region forms a p-type doped region. 如申請專利範圍第14項所述之蕭基二極體裝置之製造方法,其中於形成該些隔離結構時更包括:同時將該p型摻雜區轉變成為位於該第一n型摻雜區與該第二n型摻雜區連結處之一p型保護環,以包覆該些隔離結構之一邊角。 The manufacturing method of the Schottky diode device of claim 14, wherein the forming the isolation structure further comprises: simultaneously converting the p-type doped region into the first n-type doped region; And a p-type guard ring connected to the second n-type doping region to cover a corner of the isolation structure. 如申請專利範圍第15項所述之蕭基二極體裝置之製造方法,其中該p型保護環具有介於8*1015 atoms/cm3 ~5*1016 atoms/cm3 之摻質濃度。The method for manufacturing a Schottky diode device according to claim 15, wherein the p-type guard ring has a dopant concentration of 8*10 15 atoms/cm 3 to 5*10 16 atoms/cm 3 . . 如申請專利範圍第10項所述之蕭基二極體裝置之製造方法,其中該些隔離結構係為場氧化物。 The method of manufacturing a Schottky diode device according to claim 10, wherein the isolation structures are field oxides. 如申請專利範圍第15項所述之蕭基二極體裝置之 製造方法,其中該陽極電極與陰極電極包括鈦、氮化鈦、鎢或鋁。 Such as the Xiaoji diode device described in claim 15 A manufacturing method, wherein the anode electrode and the cathode electrode comprise titanium, titanium nitride, tungsten or aluminum.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614755A (en) * 1993-04-30 1997-03-25 Texas Instruments Incorporated High voltage Shottky diode
US20050006662A1 (en) * 2003-07-11 2005-01-13 Jean-Luc Morand Rectifying and protection diode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614755A (en) * 1993-04-30 1997-03-25 Texas Instruments Incorporated High voltage Shottky diode
US20050006662A1 (en) * 2003-07-11 2005-01-13 Jean-Luc Morand Rectifying and protection diode

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