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TWI355054B - Method for fabricating a packaging substrate - Google Patents

Method for fabricating a packaging substrate Download PDF

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Publication number
TWI355054B
TWI355054B TW97118200A TW97118200A TWI355054B TW I355054 B TWI355054 B TW I355054B TW 97118200 A TW97118200 A TW 97118200A TW 97118200 A TW97118200 A TW 97118200A TW I355054 B TWI355054 B TW I355054B
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Taiwan
Prior art keywords
layer
metal layer
thickness
metal
wafer carrier
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TW97118200A
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Chinese (zh)
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TW200950029A (en
Inventor
Chang Fu Chen
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Unimicron Technology Corp
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Priority to TW97118200A priority Critical patent/TWI355054B/en
Publication of TW200950029A publication Critical patent/TW200950029A/en
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Publication of TWI355054B publication Critical patent/TWI355054B/en

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  • Wire Bonding (AREA)

Description

1355054 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種晶片載板的製造方法,特別是有關於一 種覆晶載板(flip-chip substrate)的製造方法,能以自動對準 (self-aligned)方式在載板的覆晶面上形成接合凹孔加她% aperture),藉此提升阻焊對位精度(s〇lderniaskregistrati⑽ accuracy) ° 【先前技術】 如熟習該項技藝者所知,晶片載板乃是半導體後段製程中常 使用到_裝猶’其魏包骑結“齡機板(酬、 保護晶片與散熱。晶片載板主要是由多層圖案化導線層以及多層 絕緣層疊合而成,不同層的導線層則是藉由形成在絕緣層中的電 鍍導通孔(plated through hole)構成電氣連結。 過去晶片封裝結構巾,晶>}主要是叫線接合(wifeb祕㈣ 的方式與晶片載板連接。隨著晶片技術;高頻、高腳數發展, 傳統打線接合封裝逐漸無法滿足電性上的要求,業界於是發展出 覆晶封裝(flipchip)技術。相較於傳統打線接合技術,覆晶封裝是 採用錫鉛凸塊(solder bump)作為晶片與晶片載板連接的封裝技 術’除了能夠大幅度提高晶片接_密度之外,更可以降低雜訊 5 1355054 的干擾、強化電性的效能、提高散熱能力及縮減封裝體積。 然而,目前覆晶載板的製造技術仍有瓶頸需要進一步克服與 改善。舉例來說,習知技術是在形成阻焊(s〇ldermask)層後,需另 外再以曝光(exposure)及顯影(devel〇pment)技術於阻焊層中形成阻 知開口’暴露出下方的金屬塾’但是這樣的作法卻會面臨到難以 解決的對位偏差(misalignment)問題。 【發明内容】 本發明之主要目的即在提供—種鑛的覆晶載板的製造方 法,以解決上述先前技術之不足與缺點。 為達上述及其它目的,本發明提供一種晶片载板的製造方 法,首先提供-包層板,其由—第—金屬層、—第二金屬層及一 敍刻+止層層$麻,祕刻停止層夾設該第―金屬層與該第二 金屬層之間’接著將該第一金屬層定義成一第—導線圖案,其中 該第-導線職包括複數個金屬塾,接著於該第_導線圖案上廢 合一絕緣層,錄將該第二金屬層㈣成複數個凸塊焊塾,隨後 去除未被該複數彳祕稱麵駐住的紐贿謂,暴露出部 絕緣層以及該第-導賴案,再於暴露出的魏緣層及該 線圖案上形成-阻焊層,其中該阻焊層填滿該複數個 燁塾之間的雜,麟露出錢凸塊轉的上絲,最後將暴露 6 1355054 出的各該凸塊桿塾的上表面_掉—部分的厚度,藉此自 形成複數個接合凹孔。 + 為讓本發明之上述目的、特徵、和優點能更明顯易懂,下文 特舉較佳實财式’並配合所_式,作詳細制如下。然而如 下之較佳實財式額式贿參考與制用,並_來對 加以限制者。 【實施方式】 請參閱第1圖至第10 ® ’其為爾本發·佳實關一種覆 晶载板的製造方法所緣示的剖面示意圖。如第丨圖所示首先提 供一包層板(cladding Sheet)卜其由一第一金屬層1〇、一侧停止 層(etChingSt〇Player)12以及一第二金屬層14所構成,触刻停止層 12失設於第一金屬層1〇與第二金屬層14之間。其中較佳者,第 -金屬層10及第二金屬層Μ均為銅f|,停止層U為錄镇 或銀箱,但不限於此。根據本發明之較佳實施例,包層板丨可以 是銅-鎳-銅(Cu/Ni/Cu)三層板或者銅-銀·銅(Cu/Ag/Cu)三層板。 根據本發明之較佳實施例,第一金屬層1〇的厚度約介於1〇 微米至30微米,例如18微米,蝕刻停止層12的厚度約介於i微 米至2微米左右’第二金屬層14的厚度約介於4〇微米至12〇微 米,例如,60微米或者80微米。其中,較佳者,第二金屬層14 7 1355054 的厚度大於第一金屬層10的厚度。 如第2圖所示,接著利用微影及蝕刻製程,將第一金屬層⑴ 定義成第一線路圖案l〇a’其中第一線路圖案1〇a包括介層接觸墊 102以及金屬墊104。前述的微影及蝕刻製程包括在第一金屬層⑴ 上形成一第一光阻乾膜(圖未示),在第二金屬層14上形成一二二 光阻乾膜⑽未^),然後’僅_第—光阻乾膜曝光及顯影,在第 -金屬層1G上形成-侧遮罩贿’接著,選擇性地將未被該餘 刻遮罩圖案覆蓋的第-金屬層祕除,暴露出部分的侧停止層 12,最後,將該蝕刻遮罩圖案以及第二光阻乾膜去除。 曰 ▲如第3圖所示,接著在第一線路圖案咖上以及暴露出的钱 刻停止層12上喊1騎2G,例如,材(卿剛、娜樹 脂⑷m刪to B祕up版)、環氧樹脂、聚亞軸㈣咖㈣等。1355054 IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a wafer carrier, and more particularly to a method of fabricating a flip-chip substrate capable of automatically aligning (self-aligned) way to form a recessed hole on the flip-chip surface of the carrier plate and add her % aperture), thereby improving the accuracy of the solder joint alignment (s〇lderniaskregistrati(10) accuracy) ° [Prior technology] as familiar with the artist It is known that the wafer carrier is used in the semiconductor back-end process. It is often used in the process of manufacturing the board. It is mainly composed of multiple layers of patterned conductor layers and multilayer insulation. The conductive layer of different layers is electrically connected by a plated through hole formed in the insulating layer. In the past, the wafer package structure, crystal >} is mainly called wire bonding (wifeb secret (four) The method is connected with the wafer carrier. With the development of high-frequency and high-frequency, the traditional wire bonding package can not meet the electrical requirements. The industry has developed a flip chip package (fl Ipchip) technology. Compared with the traditional wire bonding technology, the flip chip package uses tin-lead bumps as the package technology for connecting the wafer to the wafer carrier board. In addition to greatly improving the wafer bonding density, Reduce the interference of noise 5 1355054, enhance the performance of electricity, improve the heat dissipation and reduce the package volume. However, there are still bottlenecks in the manufacturing technology of flip chip carrier, which need to be further overcome and improved. For example, the conventional technology is After forming a solder mask layer, an exposure and development technique is additionally used to form a blocking opening in the solder mask to expose the underlying metal germanium. However, such a process may The problem of misalignment is difficult to solve. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a flip-chip carrier for seeding, to solve the above-mentioned deficiencies and shortcomings of the prior art. And other objects, the present invention provides a method for fabricating a wafer carrier, which first provides a cladding layer comprising a -metal layer, a second metal layer, and a lithography + The first layer of the first metal layer is defined as a first conductor pattern, wherein the first conductor layer includes a plurality of metals塾, then, an insulating layer is scrapped on the first ray pattern, and the second metal layer (four) is recorded into a plurality of bump solder dies, and then the buds that are not retained by the nickname are exposed. An insulating layer and the first guiding method, and forming a solder resist layer on the exposed Wei edge layer and the line pattern, wherein the solder resist layer fills the impurity between the plurality of turns, and the exposed The upper wire of the money bump is turned, and finally the thickness of the upper surface_off-portion of each of the bump bars of 6 1355054 is exposed, thereby forming a plurality of engaging recesses. In order to make the above objects, features and advantages of the present invention more comprehensible, the following is a detailed description of the preferred embodiments of the present invention. However, the following is the preferred real-esttainment bribe reference and system, and _ to limit the person. [Embodiment] Please refer to Fig. 1 to Fig. 10' for a schematic cross-sectional view of a method for manufacturing a flip-chip carrier. As shown in the figure, a cladding sheet is first provided, which is composed of a first metal layer 1 , an end stop layer 12 and a second metal layer 14 . The layer 12 is lost between the first metal layer 1 and the second metal layer 14. Preferably, the first metal layer 10 and the second metal layer are both copper f|, and the stop layer U is a town or a silver box, but is not limited thereto. According to a preferred embodiment of the present invention, the clad plate 丨 may be a copper-nickel-copper (Cu/Ni/Cu) three-layer plate or a copper-silver-copper (Cu/Ag/Cu) three-layer plate. In accordance with a preferred embodiment of the present invention, the thickness of the first metal layer 1 约 is between about 1 μm and 30 μm, for example, 18 μm, and the thickness of the etch stop layer 12 is between about 1 μm and about 2 μm. Layer 14 has a thickness of between about 4 microns and 12 microns, for example, 60 microns or 80 microns. Preferably, the thickness of the second metal layer 14 7 1355054 is greater than the thickness of the first metal layer 10. As shown in Fig. 2, the first metal layer (1) is then defined as a first line pattern 10a' using a lithography and etching process, wherein the first line pattern 1a includes a via contact pad 102 and a metal pad 104. The foregoing lithography and etching process includes forming a first photoresist dry film (not shown) on the first metal layer (1), forming a two-two photoresist dry film (10) on the second metal layer 14, and then 'only_first-resistive dry film exposure and development, forming a side mask on the first metal layer 1G'. Next, selectively removing the first metal layer not covered by the residual mask pattern, A portion of the side stop layer 12 is exposed, and finally, the etch mask pattern and the second photoresist dry film are removed.曰 ▲ As shown in Figure 3, then on the first line pattern coffee and on the exposed money stop layer 12, shout 1 ride 2G, for example, material (Qing Gang, Na Resin (4) m deleted to B secret up version), Epoxy resin, poly-Asian axis (four) coffee (four) and so on.

在絕緣層^上形成有—第三金屬層22,例如,銅箱。當·然,也可 以直接在第-線路圖案1〇a上以及暴露出的侧停止層^上壓合 一背膠銅箔(RCC)。 口 機圖所Γ:接著進行一鑽孔製程,例如,雷射鑽孔或者 接;墊102二第二金屬層22以及絕緣層20中相對應於介層 、位置,鑽出複數個介層通孔2〇2,藉 介層接觸塾1G2。 _暴路出部分的 8 1355054 如第5圖所不,進行一電錢製程,例如無電電鑛製程’於介 •層通孔202内及第三金屬層22的表面上形成一電鑛銅層24,如此 '* 在絕緣層20中形成導電通孔202a。 如第6圖所示進行一銅厚縮減(⑺口卩沉製程利 如拋光或研磨等技術,分職少第二金屬層14及第三金屬層η 的厚度至所要的厚度!_ ’例如,在減厚之後,第二金屬層Μ的 籲厚度較佳钓介於15微米至25微米之間,第三金屬層^的厚度較 佳約介於15微米至25微米之間。 —第7圖所示’接著利用微影及姓刻製程,將第三金屬層Μ 定義成第二線路圖案咖,其中包括錫球焊墊您以及細線路 224,而將第二金屬層M定義成凸塊桿塾伽师邱_,並且暴 露出部分的钱刻停止層12。凸塊焊塾H2相對應於金屬塾1〇4的 I 同躺㈣的微減賴製程包姉成-光阻乾膜(圖未 不)’對該光阻乾膜曝光及顯影,以形成一侧遮罩圖帛,接著, 選擇性地將未被該_遮罩圖案覆蓋的金屬層鱗 蝕刻遮罩圖案去除。 著如第8圖所示,選擇性地將暴露出的勉刻停止層η餘 ^ ’僅保留凸塊焊塾142正下方_刻停止層12。此時,覆晶載 =第一面(或覆晶面)職上已形成有複數個用來與覆晶晶 月連接的凸塊焊塾142,以及内炭在絕緣層2〇中的金屬線路圖案 9 1355054 他’而凸塊焊势142即透職刻停止層12與金屬線路圖荦伽 中相對應的金屬塾104構成電性連結。在覆晶載板刚的第二面(或 •主機板面}1_上,已形成有包括錫球焊塾222的金屬線路圖案 22a ’其中金屬線路圖案22以系形成在絕緣層2〇的表面上。 如第9圖所τ ’接著在覆晶載板1〇〇的第一面職上形成阻 焊(S〇ldermaS騎302,其實施方式可以是採塗佈或者印刷方法, 鲁使阻焊们02填滿該複數個凸塊焊墊Η2之間的空隙’配合後續 的到平步驟’使得最後凸塊焊塾142的上表面與阻焊層3〇2的表 面同高。換言之,必須使得凸塊焊墊142的上表面能夠被暴露出 來,而不能被阻焊層302覆蓋住。在覆晶载板1〇〇的第二面· 上’則形成有阻焊層304 ’並藉由曝光及顯影製程,於阻焊層3〇4 中定義出阻焊開孔312,暴露出部分的錫球焊墊222。 .如第10圖所示,最後在覆晶載板100的第一面l〇〇a上進行 一蝕刻製程,蝕刻掉部分厚度的凸塊焊墊142,以自動對準 (self-aligned)方式形成接合凹孔(b〇nding aperture)322。在姓刻凸塊 焊墊142時’可以利用一光阻乾膜(圖未示)覆蓋並保護住覆晶載板 100的第一面l〇〇a。本發明的優點在於覆晶面1〇〇a上的接合凹孔 322係以自動對準方式形成的,而非如先前技藝以曝光顯影製程形 成,因此,接合凹孔322可以完全與凸塊焊墊142精準對位而不 會有偏移,有效的提升了阻焊對位精度。 以上所述僅為本發明之較 圍所做·笪妈i t 貫苑例,凡依本發明申請專利範 =艾〜修飾’皆應屬本發明之涵蓋範圍β 【圖式簡單說明】 第1圖至第10圖為依據本發明較佳實施例所繪示的剖面示意圖。 【主要元件符號說明】 1 包層板 10 第一金屬層 10a 第一導線圖案 12 姓刻停止層 14 第二金屬層 20 絕緣層 22 第三金屬層 22a 第二導線圖案 24 電鍍銅層 100 覆晶載板 100a 第一面 100b 第二面 102 介層接觸墊 104 金屬墊 142 凸塊焊塾· 202 介層通孔 202a 導電通孔 222 錫球焊墊 224 細線路 302 阻焊層 304 阻焊層 312 阻焊開扎 322 接合凹孔A third metal layer 22, for example, a copper box, is formed on the insulating layer. Alternatively, a backing copper foil (RCC) may be directly laminated on the first-line pattern 1A and the exposed side stop layer. The port machine diagram is followed by: performing a drilling process, for example, laser drilling or bonding; the pad 102 and the second metal layer 22 and the insulating layer 20 corresponding to the interlayer and the location, and drilling a plurality of layers Hole 2〇2, through the layer contact 塾1G2. 8 1355054 of the violent passage section, as shown in Fig. 5, performs an electric money process, such as an electroless ore process, forming an electro-copper layer on the surface of the interlayer dielectric layer 202 and the third metal layer 22. 24, such that a conductive via 202a is formed in the insulating layer 20. As shown in Fig. 6, a copper thickness reduction is performed ((7) a technique such as polishing or grinding, which divides the thickness of the second metal layer 14 and the third metal layer η to a desired thickness!_', for example, After the thickness reduction, the thickness of the second metal layer is preferably between 15 micrometers and 25 micrometers, and the thickness of the third metal layer is preferably between 15 micrometers and 25 micrometers. The second metal layer Μ is defined as a second line pattern coffee, including a solder ball pad and a thin line 224, and the second metal layer M is defined as a bump rod, as shown by the lithography and surname process.塾 师 师 Qiu _, and exposed part of the money to stop the layer 12. The bump solder 塾 H2 corresponds to the metal 塾 1 〇 4 I lie down (four) of the micro-reduction process package - the photoresist dry film (Figure not No) 'exposing and developing the photoresist dry film to form a side mask pattern, and then selectively removing the metal layer scale etching mask pattern not covered by the mask pattern. As shown, the exposed etch stop layer η is selectively retained only below the bump 142. At this time, the flip chip = the first side (or the flip face) has formed a plurality of bump pads 142 for connection with the flip chip, and the metal lines of the inner carbon in the insulating layer 2 Pattern 9 1355054 He's the bump soldering potential 142, that is, the through-stop layer 12 is electrically connected to the metal germanium 104 corresponding to the metal trace. In the second side of the flip-chip carrier (or host On the board surface 1__, a metal wiring pattern 22a' including a solder ball 塾222 is formed, in which the metal wiring pattern 22 is formed on the surface of the insulating layer 2''. As shown in Fig. 9, τ' is followed by flip chip The first surface of the carrier 1 is formed with a solder mask (S〇ldermaS ride 302, which may be in the form of a coating or printing method, and the solder resists 02 fill the plurality of bump pads 2 The gap between the gaps 'following the subsequent flattening step' is such that the upper surface of the last bump solder 142 is at the same height as the surface of the solder resist layer 3〇2. In other words, the upper surface of the bump pad 142 must be exposed. It cannot be covered by the solder resist layer 302. On the second surface of the flip-chip carrier 1 ·, a solder resist layer 304 is formed. And by the exposure and development process, a solder resist opening 312 is defined in the solder resist layer 3〇4, and a portion of the solder ball pad 222 is exposed. As shown in FIG. 10, finally on the flip chip carrier 100 An etching process is performed on the first side 10a, and a portion of the thickness of the bump pad 142 is etched away to form a bonding aperture 322 in a self-aligned manner. When the bump pad 142 is used, a photoresist dry film (not shown) can be used to cover and protect the first surface 10a of the flip chip 100. The advantage of the present invention is that the flip chip is on the 1a surface. The engagement recess 322 is formed in an automatic alignment manner instead of being formed by an exposure development process as in the prior art. Therefore, the engagement recess 322 can be perfectly aligned with the bump pad 142 without offset, effectively Improve the accuracy of solder mask alignment. The above description is only for the comparison of the present invention. The example of the invention is based on the invention. The scope of the invention is as follows: [Simplified description of the drawing] Figure 1 10 is a schematic cross-sectional view of a preferred embodiment of the present invention. [Main component symbol description] 1 cladding plate 10 first metal layer 10a first wire pattern 12 last stop layer 14 second metal layer 20 insulating layer 22 third metal layer 22a second wire pattern 24 electroplated copper layer 100 flip chip Carrier 100a First side 100b Second side 102 Via contact pad 104 Metal pad 142 Bump solder 塾 202 Interlayer via hole 202a Conductive via 222 Tin ball pad 224 Thin line 302 Solder mask 304 Solder mask 312 Solder masking 322

Claims (1)

1355054 十、申請專利範圍: h —種晶片載板的製造方法,包含有: 提供-包層板’其由-第-金屬層、—第二金屬層及一敍刻停 止層層疊構成’該酬停止層纽於該第—金屬層無第 層之間; ”蜀 將該第-金屬狀義成-第—導線圖案,包括複數個金屬塾; 於該第一導線圖案上壓合一絕緣層; 將該第二金屬層定義成複數個凸塊焊墊; 去除未被該複數個凸塊焊墊所覆蓋住的該侧停止層暴露出 部分的該絕緣層以及該第一導線圖案; 上於暴露出的該絕緣層及該第一導線圖案上形成一阻焊層,其中 該阻焊層填滿該複數個凸塊_之_空隙,並暴露出各該 焊墊的上表面;以及 將暴路出的各該凸塊焊塾的上表面钱刻掉一部分的厚度,藉此 自動對準形成複數個接合凹孔。 2. 如申請專概圍第1機述之⑼載板的製造方法,其中該第 —金屬層包含銅。 3. 如申請專利範圍第1項所述之晶片載板的麟方法,其中該第 二金屬層包含銅。 12 1355054 1355054 ,其中#刻 ,募中該第 ’其中该第 4·如申請專概圍第丨項所述之晶片載板的製造方法 停止層包含鎳或銀。 5·如申請專利範圍第1項所述之晶片載板的製造方漆 二金屬層的厚度大於該第一金屬層的厚度。1355054 X. Patent application scope: h—a manufacturing method for a wafer carrier board, comprising: providing a cladding board comprising a layer of a -metal layer, a second metal layer and a layer of a stop layer a stop layer is formed between the first metal layer and the first layer; and the first metal pattern is formed into a plurality of metal wires; and an insulating layer is pressed on the first wire pattern; The second metal layer is defined as a plurality of bump pads; the insulating layer and the first conductive pattern exposed by the side stop layer not covered by the plurality of bump pads are removed; Forming a solder resist layer on the insulating layer and the first wire pattern, wherein the solder resist layer fills the plurality of bumps and exposes an upper surface of each of the pads; The upper surface of each of the bump pads is engraved with a portion of the thickness, thereby automatically aligning to form a plurality of engaging recesses. 2. For the method of manufacturing the carrier board of the first embodiment (9), The first metal layer contains copper. 3. If the patent application scope The method for processing a wafer carrier according to any one of the preceding claims, wherein the second metal layer comprises copper. 12 1355054 1355054, wherein #刻,"中中中中中中中的第4 The manufacturing method of the wafer carrier comprises a layer of nickel or silver. 5. The wafer carrier of claim 1 is manufactured to have a thickness greater than a thickness of the first metal layer. 6.如申請專利範圍第!項所述之晶片載板的製造方法 二金屬層的厚度介於40微米至120微米。 7.如申請專概圍第1項所述之晶片栽板的製衫法,其中该第 一金屬層的厚度介於1〇微米至3〇微来。 8.如申請專利範圍第1項所述之晶片栽板的製造方法,其中該雜 刻停止層的厚度約介於1微米至2微米。 • 9.如申請專利範圍第1項所述之晶片戟板的势造方法,其中該絕 緣層包含預浸材、ABF樹脂、環氧樹脂或聚。 w· —種晶片載板的製造方法,包含有: 提供-包層板’其由-第-金屬層、1二金屬層及一餘刻停 .止層層疊構成,該侧停止層夾設於該第〜金屬層與該第二金屬 層之間; 將該第-金屬層定義成-第-導線_,包括複數個介層接觸 墊及金屬墊; 13 1355054 於έ亥第一導線圖案上壓合一絕緣層及一第三金屬層; 在該絕緣層中形成複數個導電通孔,使該第三金屬層電連結該 介層接觸墊; 將該第三金屬層定義成一第二線路圖案; 將S亥第二金屬層定義成複數個凸塊焊墊; 去除未被該複數個凸塊焊墊所覆蓋住的該蝕刻停止層,暴露出 部分的該絕緣層以及該第一導線圖案;6. If you apply for a patent range! The method for manufacturing a wafer carrier according to the invention has a thickness of the metal layer of from 40 μm to 120 μm. 7. The method of claim 1, wherein the first metal layer has a thickness of from 1 micron to 3 micron. 8. The method of fabricating a wafer board according to claim 1, wherein the rug stop layer has a thickness of between about 1 micrometer and 2 micrometers. 9. The method of forming a wafer raft as described in claim 1, wherein the insulating layer comprises a prepreg, an ABF resin, an epoxy resin or a poly. The method for manufacturing a wafer carrier includes: providing a cladding plate comprising: a -metal layer, a two metal layer, and a layer of a stop layer, the side stop layer being sandwiched Between the first metal layer and the second metal layer; the first metal layer is defined as a -first wire _, comprising a plurality of via contact pads and a metal pad; 13 1355054 is pressed on the first wire pattern of the έ Forming an insulating layer and a third metal layer; forming a plurality of conductive vias in the insulating layer, electrically connecting the third metal layer to the via contact pad; defining the third metal layer as a second line pattern; Defining a second metal layer of S Hai into a plurality of bump pads; removing the etch stop layer not covered by the plurality of bump pads, exposing a portion of the insulating layer and the first conductive pattern; ▲於暴露出的該絕緣層及該第一導線圖案上形成一阻焊層,其中 =阻焊層填滿該複數個凸塊焊塾之間的空隙,並暴露出各該凸塊 焊墊的上表面;以及 將暴露出的各該凸塊焊塾的上表面餘刻掉一部分的厚度,夢此 自動對準形成複數個接合凹孔。 g 12.如申請專利範圍第 第一金屬層包含銅。 1〇項所述之晶片她的製造方法,其中該 13.如申請專利範㈣1G項所述之晶片載板的製 刻停止層包含鎳或銀。 造方法,其中蝕 14.如申請專利範圍第10項所述之晶片裁板的製 造方法,其中該 1355054 第二金屬相厚度大於該第—金顧的厚度。 ;|5.如中請專利範圍第H)項所述之晶片載板的製造方法,其中該 第一金屬層的厚度介於4〇微米至12〇微米。 16. 如申請專利細第1G項所述之晶片触的製造方法,其中該 第一金屬層的厚度介於1〇微米至3〇微米。 17. 如申請專利範圍第1()項所述之晶片載板的製造方法,其中該 蝕刻停止層的厚度約介於丨微米至2微米。 18. 如申請專利範圍第10項所述之晶片载板的製造方法,其中該 絕緣層包含預浸材、娜樹脂、環氧樹月旨或聚亞酿胺。 19. 如申請專利範圍第1〇項所述之晶片載板的製造方法,其中另 .包含有分別將該第二金屬層及該第三金屬層減厚至〆預定厚度範 圍。 20. 如申請專利範圍第19項所述之晶片載板的製造方法,其中該 預定厚度範圍介於15微米至25微米之間。 21. 如申請專利範圍第1〇項所述之晶片載板的製造方法,其中該 第二線路圖案包括錫球焊塾以及細線路。 15▲ forming a solder resist layer on the exposed insulating layer and the first wire pattern, wherein the solder resist layer fills the gap between the plurality of bump pads and exposes the bump pads The upper surface; and the thickness of a portion of the exposed upper surface of each of the exposed bumps is automatically aligned to form a plurality of engaging recesses. g 12. The first metal layer contains copper as in the patent application. The method of manufacturing the wafer according to the above aspect, wherein the etch stop layer of the wafer carrier as described in claim 1 (4) 1G contains nickel or silver. The method of manufacturing a wafer blank according to claim 10, wherein the thickness of the second metal phase is greater than the thickness of the first metal. The method of fabricating a wafer carrier as described in claim H), wherein the first metal layer has a thickness of from 4 μm to 12 μm. 16. The method of fabricating a wafer contact according to the invention, wherein the first metal layer has a thickness of from 1 μm to 3 μm. 17. The method of fabricating a wafer carrier according to claim 1 wherein the thickness of the etch stop layer is between about 丨 microns and 2 microns. 18. The method of fabricating a wafer carrier according to claim 10, wherein the insulating layer comprises a prepreg, a naphthalene resin, an epoxy resin or a poly-branched amine. 19. The method of fabricating a wafer carrier according to claim 1, wherein the second metal layer and the third metal layer are respectively thickened to a predetermined thickness range. 20. The method of fabricating a wafer carrier according to claim 19, wherein the predetermined thickness ranges from 15 micrometers to 25 micrometers. 21. The method of fabricating a wafer carrier according to claim 1, wherein the second wiring pattern comprises a solder ball solder bump and a thin wiring. 15
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI790880B (en) * 2021-08-16 2023-01-21 大陸商深南電路股份有限公司 Packaging mechanism and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI790880B (en) * 2021-08-16 2023-01-21 大陸商深南電路股份有限公司 Packaging mechanism and manufacturing method thereof

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