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TWI239059B - Chip packaging method chip package structure - Google Patents

Chip packaging method chip package structure Download PDF

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Publication number
TWI239059B
TWI239059B TW093124616A TW93124616A TWI239059B TW I239059 B TWI239059 B TW I239059B TW 093124616 A TW093124616 A TW 093124616A TW 93124616 A TW93124616 A TW 93124616A TW I239059 B TWI239059 B TW I239059B
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Taiwan
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chip
layer
pins
scope
conductor layer
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TW093124616A
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TW200608497A (en
Inventor
Chien Liu
Sheng-Tai Tsai
Meng-Jen Wang
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Advanced Semiconductor Eng
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Publication of TW200608497A publication Critical patent/TW200608497A/zh

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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    • H01L2924/1815—Shape

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

I23905j9586twf.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝方法與晶片封裝結 構’且特別是有關於一種採用覆晶接合之晶片封裝方法與 晶片封裝結構。 【先前技術】
>近年來’隨著半導體製程技術的不斷成熟與發展，各 種高效能的電子產品不斷推陳出新，而積體電路(Integrated Circuit, 1C)元件的積集度(integrati〇n)也不斷提高。在積體 電路元件之封裝製程中，積體電路封裝(ICpackaging)扮演 著相當重要的角色，而積體電路封裝型態可大致區分為打 線接合封裝(Wire Bonding Package，W/B Package)、貼帶自 動接合封裝（Tape Automatic Bonding Package，TAB
Package)與覆晶接合封裝(Flip Chip package，F/c package) 等型式，且每種封裝形式均具有其特殊性與應用領域。值 知注意的是，無論何種封裝方式均需要一承載s(carrier)， 且承載器上之接腳係與晶片上之焊墊(b〇nding pad)電性連 接，其中承載器例如是導線架（lead frame)或基板 (substrate) 〇 圖1A至圖1D繪示習知凸塊化晶片承載器封裝結構 (bump chip carrier package structure, BCC package structure) 之製造々IL程示意圖。請先參照圖1A與圖IB，習知凸塊化 曰曰片承載器封裝結構1〇〇的製造方法包含下列步驟。首 先，提供一銅金屬層11G，而銅金屬層11()具有一第一表 M3o86twf.doc 面110a與相對於第一表面n0a之一第二表面11%。然 後’在第一表面ll〇a與第二表面ll〇b上分別形成一圖案 化光阻層（patterned photoresist layer) 122 與一光阻層 (photoresist layer)124，如圖1A所示。之後，對於銅金屬 層進行一半敍刻製程(half etching process)，以形成一 晶片容置凹槽112a與多個凸點凹槽112b。接著，在晶片 容置凹槽112a之内側壁上形成一鍍層i32a，並且同時在 凸點凹槽112b之内壁上形成一凸點鍍層132b。隨後，移 除位於銅金屬層110表面上之圖案化光阻層122與光阻層 124，如圖1B所示。 請參照圖1C，將一黏膠層140塗佈於晶片容置凹槽 112a之底部，並將晶片ι5〇配置於黏膠層14〇上，其中晶 片150具有多個焊墊152,其係位於晶片ι5〇之一表面上。 然後’藉由一打線製程(wire b〇n(Jing pr〇CeSS)形成多條焊線 (bondingwire)160,以分別電性連接凸點鍍層132b與晶片 50之知塾152之間。接著，在銅金屬層11〇上形成一封 裝膠體(111〇1(1丨1^(；〇11^〇1111(1)170，而封裝膠體170係包覆晶 片150與焊線160。 請參照圖1D，接著移除銅金屬層110,以形成暴露之 接點134。在形成接點134之後，即完成了習知凸塊化晶 片承載器封裝結構1〇〇的製作。在凸塊化晶片承載器封裝 結構100中’晶片丨5〇上之焊墊152可透過焊線160與接 點134電性連接至外界。 承上所述’晶片14〇係藉由焊線160電性連接至凸點 86twf.doc 鎪層mb，因此適當的線弧高度 (loop length)能夠避免焊線 ，’:、綠弧長度 玖佶Μ立…山 160產生斷裂或產生電性短 路。值付心的疋’由於焊線⑽之線 :須設定在-定的範圍内，因此習知凸塊化晶片承以 裝結構漏之厚度與面積也就無法進一步縮小 於習知凸塊化W承載器封裝結構⑽係 ^ 於焊塾152與接點134之間，因此其電性品質仍受限S 線160的長度與焊線16〇的材料特性。 【發明内容】 、有蓉於此，本發明的目的就是在提供一種晶片封裳方 法’用以製造出尺寸較小之晶片封裝結構(ehip邱 structure) ° 此外’本發明的又-目的就是在提供一種晶片封裝結 構’其具有較小的尺寸。 基於上述目的或其他目的，本發明提出一種晶片封裝 方法，係先提供-導體層’並在導體層之—表面上形成多 個接腳(lead)。然後，提供一晶片，而晶片之一表面上具有 多個凸塊(bump) ’並將晶片以覆晶方式配置於導體層^， 以使晶片藉由凸塊電性連接至接腳。隨後，在導體層上形 成一封裝膠體，以包覆晶片與這些凸塊。接著，移&導^ 層以暴露出這些接腳以及封裝膠體。 依照本發明的較佳實施例所述，導體層例如是一金屬 層。此外，導體層例如是一銅層。 依照本發明的較佳實施例所述，接腳例如是複合金屬 I239〇5^6twfdoc 層。在一實施例中，這些接腳例如是鎳-金之複合金屬層。 在另一實施例中，這些接腳例如是鈀_鎳_鈀_金之複合金屬 層。 依照本發明的較佳實施例所述，接腳的形成方法例如 包括對於導體層進行一餘刻製程以形成多個凹槽，然後在 這些凹槽内形成接腳。 依照本發明的較佳實施例所述，在將晶片配置於導體 層上之前，晶片封裝方法例如更包括在這些接腳上形成多 個預銲料(presolder)。此外，在形成這些接腳之前，晶片封 裝方法例如更包括形成一銲罩層（s〇lder mask)於導體層 上且知罩層係暴露出接腳的部分區域。另外，形成預銲 料的方法例如是網板印刷(printin幻。 依照本發明的較佳實施例所述，在將晶片配置於導體 層上之前，晶片封裴方法例如更包括將一散熱片（heat spreader)配置於導體層上，以使晶片配置於導體層上之 後，散熱片能夠位於晶片與導體層之間。在一實施例中， 在將散熱片配置於導體層上之後，晶片封裝方法例如更包 括形成-散熱膠層於散熱片上，以使晶片配置於導體層上 之後，散祕層_位於晶片與散糾之間。在另一實施 將散熱片配置於導體層上之後，晶片封裝方法例如 匕言形成一 ί辰氧樹脂層（ep〇xy)於散熱片上，以使晶片配 置於導體層上之後’環氧樹脂層_位於晶片與散孰片之 严曰 1 0 μ 依照本發明的較佳實施例所述，移除導體層之方法例 oc I23905a6tw,d 如包括微影/餘刻製程。 封穿3：^=或其他目的，本發明提出—種晶片封裝 iij 晶片、—封裝膠體與多數個板狀接腳， 二日日之一表面上具有多個凸塊。此外，封裝膠體係句 凸株。再者’這些板狀接腳係配置於封裝膠 其中為係藉由凸塊與晶綱連接， 依照本發明的較佳實施賴述，這魏狀接腳例如是 _之複合金屬^在另—實施财 Pd-Ni-Pd_Au之複合金屬層。 -卿例如疋 =本發_較佳實施麵述m :面其r=’且封裝膠體係暴露出= 配裝 結構更包括-環氧樹脂層，其係配置=與 基於上述’本發明之^縣方法係將 i裝Si :二=明之晶片封裝方法所形成之:片 釘裝、，、口構具有較佳的電性品質。此外 =承載器封裝結構，本發明之晶片封魏構 易二 明如下。 式’作詳細說 12390描— 【實施方式】 【第一實施例】 、圖2A至圖2£繪示本發明第一較佳實施例之晶片封 方法的剖面流程示意圖。請先參照圖2A與圖2B，曰片^ 步驟。首先’提供一導體層210 ’ ：導』 三川具有一第一表面210a以及相對於第一表面幻如之 一第二表面2l〇b。本實施例中，導體層21〇例如是 (copper foil)、金屬層或是其他材料層。然後，在導體層^ 之第一表面21〇a上形成多個接腳34〇，如圖2B所示' ，繼續參照圖2Α，形成接腳獨的步驟例如是 導體層210之第一表面薇與第二表面雇上分別开^ 二圖S光阻層222與一光阻層224。之後，對於導^ 212。1^一^製程(etChing ΡΓ〇叫，以形成多個凹槽 另外；凹槽212内形成接腳34〇(如圖2Β所示）。 =腳340例如是由^鎳|金所構成之 =複合金屬層或其他材質 “與=層Z位於導體層21〇表面上之圖崎 辦展照81 3 ’其♦示本發明第—較佳實施例之另-導 體層與接腳的剖面示意圖。 導 成方式並不限定於上述^^仏③的疋，接腳340的形 而接腳獨的形成方(如圖2A與圖2B所示）， 腳340。換言之，在^疋在導體層210上直接形成接 導體層2H)淮行一腳340的製程中亦可不用對於 蝕亥丨製程，且接腳34〇係凸出於導體 123905]¾ 86twf.doc 210表面。第一實施例僅以圖2Β所繪示之接腳340與導體 層210的配置方式進行說明，但圖3所緣示之接腳34〇與 導體層210的配置方式亦可應用於第一實施例中。 請繼續參照圖2C，提供一晶片310,且晶片310之一 表面上具有多個凸塊320。然後，將具有凸塊32〇之晶片 310置放於導體層210上，以使晶片310上之凸塊320能 夠分別對應配置於接腳340上。本實施例中，在將晶片31〇 置放至導體層210上之前，晶片封裝方法例如係選擇性地 在這些接腳340上分別形成預銲料(presoiderpso。由於本 發明係採用熔點較低之預銲料35〇,因此本發明可以降低 迴銲溫度(reflow temperature)，進而降低後續製程的熱預算 (thermal budget)，而形成預銲料35〇之方式例如是網板印 刷(printing)。另外，為了避免預銲料35〇於迴銲製程後產 生污染，因此在形成預銲料35〇之前亦可在導體層上 先形成-銲罩層’且鐸罩層係暴露出接腳的部分區域（此 種設計未繪示）。值得注意的是，本發明並不限制需先在 接腳340上形成預銲料35〇，才進行迴銲製程(refl〇w process) 〇 請繼續參照圖2D至圖2E，對於晶片310、凸塊32〇 與導體層210進行-迴鮮製程(refl〇w)，因此凸塊32〇能夠 電性地連，晶片310與接腳34〇之間。值得注意的是，晶 片31〇係藉由凸塊320以覆晶方式與接腳mo電性連接。 接著’對於晶片310與凸塊320騎一封膠製程_ 卿㈣’以便於在導體層21〇上形成—封裝膠體33〇，以 I2390^86twfdoc 使得封裝膠體330包覆晶片310與凸塊32〇，進而保護晶 片310與接腳340之連接(connecti〇n)，如圖2D所示。隨 後，移除導體層210以暴露出接腳34〇以及封裝膠體33〇， 進而形成一晶片封裝結構300 (如圖2E所示），而移除導 體層210之方法例如是微影/蚀刻製程。以下，將對於晶片 封裝結構300做進一步說明。 請繼續參照圖2E，晶片封裝結構300包括一晶片 310、多個凸塊320、一封裝膠體330與多個接腳340。其 中，封裝膠體330係包覆晶片310與凸塊320,且晶片310 · 係藉由這些凸塊320以覆晶方式(flip chip)與接腳340電性 連接。此外，接腳340係凸出於封裝膠體330之表面，且 接腳340更可供晶片封裝結構300後續與外界電性連接之 用。另外，封裝膠體330不僅能夠保護晶片310免於受到 濕氣或外力的破壞，更可確保晶片31〇與接腳340之間的 電性連接關係。值得一提的是，若是形成引腳340的過程 中並未蝕刻導體層210，則引腳340與封裝膠體330具有 共同的表面（此種實施例係採用圖3所繪示之導體層21〇 與接腳340所形成）。 攀 承上所述，相較於使用打線接合技術之習知凸塊化晶 片承載器封裝結構1〇〇 (如圖1D所示），晶片封裝結構 300之晶片310係採用覆晶方式(flip chip)電性連接至接腳 34〇’因此晶片封裝結構3〇〇之厚度較薄且面積也較小。此 外’相較於習知凸塊化晶片承載器封裝結構10〇採用焊線 160以電性連接晶片150與凸點鍍層132b之間，採用凸塊 12 1239051- =電，接晶片31G與接腳34G之晶片_結構_ 有車父佳的電性品質(e〗ectrical perf〇rmance)。 【第二實施例】 圖4A與圖4崎示依照本發明第二較佳實施例之 面結構示意圖。若是第二實施例的標號^ =者’其係表示在第二實施财所指明的構^ 係雷同於在4 -實施射所指_構件，在此不再 請配合參照圖2C與圖4Α，為了降低晶片 溫度，本實施例可在將晶片·配置於導體層2i〇上= (如圖2C所不），形成一散熱片 其中散熱膠層47。係配置於散熱;： 形成具有散熱片之晶片封裝結構伽 (如圖，戶斤不）。此外’封裝膠體33〇係暴露出散熱片 丄面、i散熱片460例如是銅箔或是其他金屬片 (metai sheet)。值得一提的是，散熱片働不僅能夠婵加曰 結構權的散熱效能，更可避免凸塊320 “ 清參照圖4B ’散妖勝層47π -λ__γ 抑 以& 亦可用一環氧樹脂層480 =取代。此卜’為了更進一步降低晶片31〇的操作溫度， ，4A與圖4B之封裝膠體33()亦可暴露出^⑽之部分 表面（如圖4A與圖4B之虛線部分） 係凸出於封裝膠㈣，但料腳細 ’圖3二-之導：：具有共同的表面（此種實施例係採用 圖3所纷不之導體層210與接腳340所形成）。 123 職-fdoc 綜上所述，本發明之晶片封裝方法與晶片封褒結構具 有下列優點： ^ 〃 一、 相較於習知凸塊化晶片承載器封裝結構，本發明 之晶片封裝結構，其晶片係採用覆晶方式電性連接^接 腳，因此晶片封裝結構之厚度較薄。此外，由於晶片係採 用覆B曰方式電性連接至接腳，因此本發明之晶片封農方'法 所形成之晶片封裝結構具有較佳的電性品質。 ^ ' 二、 在不增加封裝結構厚度的情況下，本發明之晶片 封裝=法更可形成具有散熱片之晶片封裝結構，以降=晶 片的操作溫度。此外，配置散熱片之方式更可控制盘 接腳之間的凸塊高度。 一 雖;、、;本發明已以較佳實施例揭露如上，然其並非用以 本發明’任何熟習此技藝者’在不脫離本發明之精神 口=内，當可作些許之更動與潤飾，因此本發明之保護 ，圍虽視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 之製繪示f知凸塊化晶片承載— 方法本發㈣—較佳實關之晶片封裝 的剖本發明第一較佳實施例之另—導體層與接腳 封裝方圖二:本㈣ 123905i^86twf.d 【主要元件符號說明】 100:習知凸塊化晶片承載器封裝結構 110 :銅金屬層 110a、210a :第一表面 110b、210b :第二表面 112a :晶片容置凹槽 112b :凸點凹槽 122、222 :圖案化光阻層 124、224 :光阻層 · 132a :鍍層 132b :凸點鍍層 134 :接點 140 :黏膠層 150、310 :晶片 152 :焊墊 160 :焊線 170、330 :封裝膠體 φ 210 :導體層 212 :凹槽 300 :晶片封裝結構 320 :凸塊 340 :接腳 350 :預銲料 460 :散熱片 15 1239059 13586twf.doc 470 :散熱膠層 480 :環氧樹脂層
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Claims (1)

  1. f.doc I23905,S86tw 十、申請專利範圍·· 1· 一種晶片封裝方法，包括： 提供一導體層； 在該導體層之-表面上形成多數個接腳； 提供= 曰片，該晶片之一表面上具有多數個凸塊； 將该曰曰片以覆晶方式配置於該導體 藉由該些凸塊電性連接至該些接腳； _ ，：體層均成一封裝膠體’以包覆該晶片與該些 凸塊，Μ及 =導:層，以暴露出該些接腳以及該封裝膠體。 2.如申s月專利範圍第1項所述之晶片封装方法，盆中 該導體層係為一金屬層。 了裒万沄 3·如申請專利範圍第2項所述之晶片 該導體層係為一銅層。 τ戒万汝，、平 4·如申請專利範圍第1項所述之晶片封裝方法，立中 該些接腳為複合金屬層。 衣乃忒/、Υ 5·如申請專利範圍第4項所述之晶片封裝方法，其中 該些接腳為Ni-Au之複合金屬層。 ’ 6·如申請專利範圍第4項所述之晶片封裝方法，其中 该些接腳為pd_Ni_Pd_Au之複合金屬層。 7·如申請專利範圍第1項所述之晶片封裝方法，其中 該些接腳的形成方法包括： 〃 對於該導體層進行一姓刻製程，以形成多數個 ； 以及 17 16twf.doc 在該些凹槽内形成該些接腳。 8. 如申請專利制第1項所述之晶片封|方法，其中 在將該晶片配置於該導體層上之前，更包括在該些接腳 形成多數個預鮮料(pres〇lder)。 9. 如申請專利_第8項所述之晶片封裝方法， 在形成該些預銲料之前，更包括形成-銲罩層(_erm、ask) 於该導體層上，且贿罩層縣露出該些接腳的部分 10. 如申請專利範圍第8項所述之晶片封裝方法，盆 中形成該些預銲料的方法包括網板印刷(printing)。、 η.如申料利翻第1項所述之晶片封裝方法，甘 中在將該晶片配置於該導體層上之前，更包括將—散^ (heat spreader)配置於該導體層上，以使該晶片配置於= 體層上之後’該散熱片係位於該晶片與該導體層之間^ 12·如申請糊範圍第u項所述之晶片封裝方 中將《熱>}配置於該導體層上之後，更包括 ^ 膠層於該散熱片上，以使該晶片配置於該導體層 ^ 忒散熱膠層係位於該晶片與該散熱片之間。 13. 如申請專利範圍第㈣所述之晶片封 中將該散熱片配置於該導體層上之後，更包括形成=其 樹脂層(eP，f該散熱片上，以使該晶片配置於該導二； 上之後’躲氧樹脂層係位於該晶#與該散糾之胃 14. 如帽糊朗第丨項所述之晶片封裝方 中移除該導體層之方法包括濕姓刻製程。 其 15· —種晶片封裝結構，包括： I23905g86twf,O( 一晶片，該晶片之一表面上具有多數個凸塊； ;封裴膠體，包覆該晶片與該些凸塊；以及 ^多數個板狀接腳，配置於該封裝膠體之一表面上， 該些板狀接腳係藉由該些凸塊與該晶片電性 些板狀接腳為複合金屬層。 /、肀5亥 16•如巾請專利範圍第15項所述之晶片封裝 中該些板狀接腳為Ni_Au<複合金屬層。 、°冓，、 17·如申請專利範圍第15 中該些_卿咖Au _構’其 18·如申請專利範圍第⑴ 曰 包括-散熱片，位於該些心崎边之曰曰片難結構，更 出該散熱片之部分表面。▲之間，且該封装膠體係暴露 19·如申請專利範圍第 包括一散熱膠層，配置於la員所述之晶片封裝結構，更 π.如申請專利範圍^8t片與該晶片之間。 包括一環氧樹脂層，配詈於# 、所述之晶片封裝結構，更 ;μ散熱片與該晶片之間。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821122B2 (en) 2005-12-22 2010-10-26 Atmel Corporation Method and system for increasing circuitry interconnection and component capacity in a multi-component package
US8237266B2 (en) 2005-12-20 2012-08-07 Atmel Corporation Component stacking for integrated circuit electronic package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8237266B2 (en) 2005-12-20 2012-08-07 Atmel Corporation Component stacking for integrated circuit electronic package
US8525329B2 (en) 2005-12-20 2013-09-03 Atmel Corporation Component stacking for integrated circuit electronic package
US7821122B2 (en) 2005-12-22 2010-10-26 Atmel Corporation Method and system for increasing circuitry interconnection and component capacity in a multi-component package

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