TWI233619B - Circuits and methods for changing page length in a semiconductor memory device - Google Patents

Abstract

A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Description

Ϊ233619 D. Description of the Invention: Cross Reference to Related Applications This application claims the priority of Korean Patent Application No. 2002-72093 filed with the Korean Intellectual Property Office on November 19, 2002. [Technical field to which the invention belongs] The present invention is directed to a semiconductor memory device whose architecture allows a user to change the page length of a semiconductor device. In addition, the present invention is directed to a circuit and method for changing the page length of a t-conductor device, in which the addressing mechanism and the control circuit system can activate one or more corresponding word lines (with the same column) of the memory cell array block of the memory cell array. Address) to change the page length in accordance with the operating mode. [Prior art]

At present, semiconductor memory devices provide various operating modes with a wide range of applications. For example, synchronous semiconductor memory devices (such as SDRAM (Synchronous Dynamic Random Access! Memory)) can be made to register mode registers (Satoshi) to support variable line address frequency f observation. Device latency (CL) and surge length (BL) modes. These semiconductor memory devices are used in various devices and applications, such as the main memory of electronic devices, network communication systems, control systems, multimedia applications, and PCs (personal computers). σ " 1C explains the hidden shoulder wooden structure of the semiconductor memory device according to the prior art #. As shown in FIG. 1A, the semiconductor memory device 100 includes a plurality of banks 100A, 100B, i00r, OC, and 100D. Each memory bank represents, for example, the logical single open of the memory of p (, 0 female & recognition, section early X ', and each bank can be composed of one or more memory modules (such as DIMM (double line φ # _ y, • A σ has hidden change group), SIMM (single line memory

O: \ 89 \ 89II3 DOC 1233619 group)). Each memory bank 100A, 100B, 100c, 100D is further logically divided into a plurality of memory cell array blocks. For example, as shown in the exemplary embodiment of FIG. 丨 B, the memory bank 100A includes four memory cell array blocks, 100b, 100c, 100d. In addition, each memory cell array block 1008, 100b, 100c, and 10 are further logically divided into a plurality of secondary memory cell array blocks, where each secondary memory cell array block is controlled by the related control circuit system. For example, as shown in FIG. 1 (: an example of a concrete example), the memory cell array block 100a includes four memory cell array blocks ii 0, i 20, i 30, and i 4. The memory cell array block 100a further includes a plurality of word line drivers 111, 121, 131 141, where each sub-line driver is connected to one of the secondary memory cell array blocks 110, 120, 130, 140 and a plurality of The secondary decoders 112, 122, 132, 142 and a row of decoders 15 are related. The memory architecture shown in Figures 1A-C is generally implemented in partially activated semiconductor memory devices, such as fast-cyclic dynamic random access memory (FCRAM) ) 'By using, for example, bank block addresses (CBAs) to start one of the secondary memory cell array blocks 110, 120, 13 and 140, perform data access or update operations. _ From the example, it is known that the memory is implemented The access operation, in response to a predetermined location-address, initially selects one of the memory banks u0A, 100b, i00c, 100D, and then responds to the predetermined address (such as a column address) in the selected one. Select a memory cell array block 100a, 100b, 100 in the memory bank c, 100d. Then, in response to, for example, a block address (CBA), a memory cell array block is selected once (in the selected memory cell array block). For example, in the exemplary implementation of FIG. 1C

O: \ 89 \ 891t3.DOC due to 1233619 cases. Jiyi Shanfan array block i technique includes four secondary memory blocks 110 120 130, 140 ′. Therefore, two rows of block addresses (CBAS) are used to select one of the secondary s memory blocks. More specifically, during a write or read operation (memory access), the column address RAi (i 2,3, ...) is input to the column decoder "ο and decoded. Then, According to the decoding result, the column decoder 15 will start one of a plurality of regular word line activation signals (nwe) corresponding to the input column address RAi. In response to the other / column address RA1 (i = 0, l) With CBA, one of the decoders 112, 122, 132, and 142 will generate a character line power signal with a predetermined boost level, and output a character 0 line power signal to the character line driver m, 121, 131, 141 Corresponding to the middle. In response to the sub-line power supply signal and the word line actuation signal NEW, the word line activates the word lines WL_〇, WL-2, WL-3 via a predetermined switching circuit (not shown). The corresponding one. As long as the character line is activated, the selected secondary memory cell array block is inputted to the row position and decoded to read or write data to the selected secondary memory block. In the DRAM of the memory architecture shown in -1C, since the memory cell array block can only be activated at any given time, 10, 12, 10, 13 ’, 140’, the paging length of a semiconductor device is fixed. Known in the art ’paging’ refers to the number of bits that can be accessed from a column of addresses, and the number of row positions-determines the size of the π paging. For example: In the memory cell array block in FIG. 1C, assuming that the total number of external input addresses is η, the total number of row addresses of the row selection line (CSL) used to select each memory cell array block is η-2. This is because one of the four secondary memory cell array blocks 100a, 100b, 100c, 100d is selected using two rows of addresses. Corresponding to a selected secondary memory cell array area

O: \ 89 \ 89113.DOC 1233619 The page length of the block-starting character line is fixed to the structure shown in the wide 1C to provide a long fixed page 2 long production.-A semiconductor with a page length of 2n or wide &Amp; clothing SDRAM). _Siyizhi (for example, this has the advantage of the orientation of a semi-V-shaped device that can be used for a given application, the length of the front door blade.) [Summary of the invention] The present invention is directed to a financial conductor memory device, which The architecture allows the user to = the page length of the semiconductor device. In addition, the present invention also refers to the circuit and method of the page length of the semiconductor device ... The addressing mechanism and control circuit system can activate one or more corresponding words of the memory unit array memory single dragon block The element line (with the same column address) is used to change the page length in accordance with the rules. The advantage is that by changing the page length, the present invention is suitable for operating between semiconductor devices with different page lengths. The semiconductor m includes—a memory cell array logically divided into i㈣ memory blocks. Each memory block in # is addressed by a corresponding block address, a plurality of character line control circuits, and each character line Control = all related to the-of these memory blocks to activate the-character lines of the relevant memory blocks; and a control circuit for selecting and controlling the control lines of these word lines, One or more corresponding word lines with the same column address to change the page length of a semiconductor memory device. Preferably, the control circuit receives a row of block addresses (such as a row of block positions) and a first control Signal is input, and then a second control signal is generated

O: \ 89 \ 89I13.DOC 1233619 2τΓΓ moves multiple word line control circuits. In-specific embodiment Product: 2. In the pre- & instruction and external address, the dynamic mode register group dynamics are all two control signals. In other specific embodiments, the control signal generator is fixed by programming the control signal generator caused by wire bonding,! Port or fuse cutting. In addition, in a specific embodiment, the memory system includes a memory cell array having a memory cell array that is logically 2 = a plurality of memory blocks. Each memory block in the memory pack f / is a corresponding block address, · A plurality of sub-element line control circuits, Penzhong Jiukong-, and Zhong-sub-line control circuits are related to these memory areas ▲ of-related 'to start a character line of the relevant memory block, and one for Select the control circuit that controls the word line control circuits, and start with the same Z bit =-or multiple corresponding word lines to change—the semiconductor memory device is the page length. In another embodiment of the present invention, a method for changing the length of a hidden page of a memory cell array having a memory cell array logically divided into a plurality of memory blocks is provided, wherein each memory block is Addressed by a pair of deer blocks: address. The method includes generating a first control signal of a plurality of page length # operation modes; and generating a second control signal according to the first control signal and a 2 e-block address. In response to the second control signal, one or more word lines in the memory blocks with an identical column address are selected to be provided to provide a page length of the memory device corresponding to the regular page length operation mode. . These and other specific embodiments, aspects, and advantages of the present invention will be described shortly, and the following preferred specific embodiments can be understood by referring to the accompanying drawings ^

O: \ 89 \ 89113.DOC -10- 1233619 Concise. [Embodiment] The present invention is directed to a semiconductor memory device. The wooden structure of agricultural and summer equipment allows users to change the page length of a semiconductor device. I would also like to say “a”, according to the circuit and method of the preferred embodiment of the present invention, it ’s jealous. It is based on one of the second memory cell blocks that can be selected to start the memory cell block. Word line (with the same column address) to change the page length of the semiconductor memory device in a regular operation mode. FIG. 2 is a high-level diagram of a memory cell array frame according to a specific embodiment of the present invention, which can change the page length of a semiconductor memory device. The exemplified specific embodiment can be regarded as an extension of the memory architecture shown in FIG. 1C, in which the control and addressing mechanism causes the page length to be changed (as opposed to the structure of FIG. 1C with a fixed page length). Referring to FIG. 2, a semiconductor memory device includes a memory cell array block 2 having a memory array logically divided into a plurality of secondary memory cell array blocks 11, 12, 13, 140 (or “secondary memory block”). 〇〇 (or " memory block "), where each memory block is addressed by a corresponding block address (such as a CBA (line block address)). In an exemplary embodiment, shown The 4 secondary memory blocks (blocks 0, 丨, 2 and 3) are for explanation, but it is known that the memory block 2000 may include more or less secondary memory blocks. Lu Jiyi Block 200 It further includes a plurality of word line drivers 111, 12 1, 131, 141, wherein each of the word line drivers lu, ι21, ι31, ι41 and one of a plurality of secondary memory blocks 110, 12, 130, 140, and a plurality of The secondary decoders 212, 222, 232, and 242 are related, and each of the secondary decoders 212, 222, 232, and 242 is related to one of the word line drivers m, 121, 131, and 141. Each corresponding secondary decoder / word The yuan line driver pair has a word for starting one phase O: \ 89 \ 89113.DOC -11-1233619 one word of the memory block The word line control circuit of the element line. In brief, the control circuit 250 selects the control word line control circuit to select the secondary memory block 110, 120, which has the same column address as the column address decoded by the column decoder 150, One or more corresponding character lines of 130 and 140 ... two-zero, WL-i, WL-2, WL-3, thereby changing the paging length of the semiconductor memory device. More specifically, the column decoder 15 receives and Decode a second input column address RAi (wherein 2, 3, ..., η), and activate a normal word line activation signal (NWE) corresponding to the position of the input column according to the decoding result. Control circuit 25. Receive a row of block address (CBA) and a control signal as inputs, and accordingly output the corresponding control signal to the secondary decoders 212, 222, 232, 242 in response. The secondary decoders 212, 222, 232, 242 receive The control signal from the control circuit 25 and a first column address RAi (where 丨 :: ^ and 丨) are generated, and then control signals are output to the word line driver 111, 121, 131, 141. According to the secondary decoding Control signals of the decoders 212, 222, 232, and 242 and from the column decoder 15 0 NWE signal, word line driver 丨 丨, [2 1, 1, 3 1, 1, 141 will choose to start one or more of the secondary memory blocks 1 丨 0, 120, 130, 140 with the same column address Corresponds to the character lines wl-0, WL-1, WL-2, and WL-3 to change the page length of the semiconductor memory device. For example, in the exemplary embodiment of FIG. 2, it is assumed that the rows of each memory block The number of addresses is η-2, and then the character line of one of the secondary memory blocks can be activated to obtain a 2η · 2 page length; (11) The corresponding character line of two secondary memory blocks can be activated to obtain 2η 1 Page length; (iii) The corresponding character lines of all four secondary memory blocks can be activated to obtain a 2n page length. Therefore, in the exemplary embodiment of FIG. 2, according to the control signal and to

O: \ 89 \ 89113.DOC -12-1233619 The combination of the CBA inputs of the control circuit 250 selects the drive by the control circuit 250—or multiple word line drivers lu, 121, 131, 141. Therefore, the number of start word lines with the same column address can be adjusted to change the page length of the semiconductor memory device as expected. "Figure 3 is a% road map of a memory cell array block according to a specific embodiment of the present invention, which can change the paging length of a semiconductor memory device according to the law of operation mode. The circuit diagram of Figure 3 illustrates one of the general architectures of Figure 2 Special implementation. For example, FIG. 3 illustrates a specific embodiment of the control circuit 25 in FIG. 2. In addition, in FIG. 3, the sMRS (mode register group) generates a control signal input to the control circuit, which can be set by the user. The control # of the control output changes the page length as expected. More specifically, referring to FIG. 3, the memory block 300 of the semiconductor memory device includes logical division into a plurality of secondary memory blocks 110, 12 Memory arrays of 0, 13, and 14, in which block addresses CBA0, CBA can be used; uf times of memory block addressing. In the exemplary embodiment, 4 times of memory blocks (block 0, block 0, 1, 2 and 3) are for explanation, but it is known that the memory block 300 may have more or less memory blocks. The memory block 300 further includes a plurality of word line drivers m, 121, 131 , 141, where each character line driver lu 121, and i4i are related to one of a plurality of secondary memory blocks 110, 120, 13 and 14, and a plurality of secondary decoders 312, 322, 332, and 342, among which each of the decoders 3, 12, 322, 332 and 342 are related to one of the word line drivers m, ni, m, and ι4ι. Each corresponding decoder / word line driver pair has a word line control circuit, and according to the control output from the control circuit 360 output Signal start-up

O: \ 89 \ 89113.DOC -13- 1233619 One character line of the memory block. In summary, the control circuit 360 selects the control word line control circuit to select the activation of the column address and the column calcite horse! 5 〇 Decoded sub-memory block with the same address ^ (^^ (^^ (^ buckle one or more of the corresponding character line boundaries ^… / WL_2, WL_3, to change the page length of the semiconductor memory device More specifically, the column decoder 150 receives and decodes a second input column address 1 ^ (wherein 2, 3,. &Quot;, 11), and starts according to the decoding result—corresponding to the input column position The normal sub-element line activation signal (NWE). The control circuit receives as input the row block addresses CBA0 and CBA1 and the control signals PL0B and PL1B generated by the control signal generator 35, and then according to the input block address and The control signal outputs the control signal to the secondary decoder 3 12, 322, 332, 342. The secondary decoder 312, 322, 332, 342 receives the control signal from the control circuit 36 and a first column address RAi (where丨), and then generate control signals output to the sub-line drivers 111, 12 1, 13 1, 141. According to the control signals from the secondary decoders 312, 322, 332, 342 and the NWE signals from the column decoder 150, Word line driver, ι21, 13 1, 141 will choose to start with the same column address One or more corresponding word lines wl__〇, WL-1, WL-2, WL-3 'of the secondary memory block 丨 丨 〇, 丨 20, 130, 140 to change the page length of the semiconductor memory device. Control The signal generator 350 includes an instruction buffer 351, an address buffer 352, and a mode register group (MRS) 353. A memory controller (or, for example, a CPU) transmits a predetermined instruction signal and an address signal. To the control signal generator 350 ° instruction buffer 351 receives the predetermined instruction signal, and the address buffer 352 receives the external address signal from the memory controller. MRS 353 from the instruction buffer O: \ 89 \ 89113.DOC -14-1233619 351 and address buffer 352 receive instructions and address signals, and then output control signals PLOB and PL1B according to the input instructions and address signals.

The control circuit 360 preferably includes a plurality of inverters 361, 362, 365, 366 and a plurality of NAND circuits 363, 364, 367, 368. Inverter 361 receives a row of block address complements as input, and inverter 362 receives a row of block address CBA0 as input. The NAND circuit 363 receives the output signals of the inverter 361 and the control signals PL0B and PL1B as inputs. The NAND circuit 364 receives as input an output signal from one of the inverters 362 and control signals PL0B and PL1B. The inverter 365 receives a row of block address complements CBA1B as an input, and the inverter 366 receives a row of block address CBA1 as an input. The NAND circuit 367 receives an output signal of an inverter 365 and a control signal PL1B as inputs. The NAND circuit 368 receives an output signal and a control signal from one of the inverters 366 as inputs. § The memory block 3 0 0 further includes a pre-decoder 3 75, a plurality of row decoders 371, 372, 373, 374 and a plurality of logic circuits 381, 382, 383, 3 84, 39i, 392, 393, 394, 395, 396, 397, 3 98, the following will

Explain its function. In addition to the address for the row block address, the pre-decoder 375 receives and pre-decodes a row address. For example, in the exemplary embodiment of FIG. 3, assuming that the total number of addresses is n, since two bits are used by CB A, n-2 row addresses are input to the pre-decoder 375. The logic circuit 392 receives the row block addresses CBA0B and CBA1B as inputs. The logic circuit 394 receives the row block addresses CBA0 and CBA1B as inputs. Logic circuit 396 receives row block addresses CBA0B and CBA1 as inputs. The logic circuit 398 receives the row block addresses CBA0 and CBA1 as inputs. Logic circuits 392, 394, 396, and 398 are inverters 391, 393, 395, and 397, respectively. O: \ 89 \ 89113.DOC -15- 1233619 The selection circuit 381 receives one of the inverters 391 Yushan > ^ output ^ and the pre-decoder 3 or one output signal as input, and outputs a tiger to the The first memory is £ 110 for a trip to decoder 371. The logic L bait circuit 382 receives one round signal from the inverter 393 and one round from the pre-decoder 375, and outputs L 铡 as input, and outputs a sign to the second memory block. 'Guanzhiyu decoder 372. Logic circuit 383 receives the output of one of the inverters 395 and imitates the output signal of one of the pre-decoders 375 and the input signal, and outputs a signal u related to the secondary memory block 13. Decoder 373 . The edit circuit 384 receives one of the output signal of the inverter 397 and the pre-decoder 375-the output signal is input, and outputs a signal to the decoder 374 related to the fourth memory block 4o. . . In the above-mentioned exemplary embodiment of FIG. 3, the change of the control signal generated by the MRS 353 in the control signal generation 350 is used to adjust the page length as expected. The MRS 353 outputs the control signal processed by the control circuit 36 (), such as the rule of the control signal generator 350 from the memory controller or the external command and address received, for example, to implement an operation mode. As can be seen from the examples, FIGS. 4A-4C illustrate various operation modes, in which the page length of the semiconductor memory device of FIG. 3 can be changed according to the control signals PL0B and PL1B. In particular, FIG. 4A is a table for explaining an operation mode, in which the two tied L numbers PL0B and plib are both closed / cut off (for example, the logic level is high), and the page length is 2 pages. The k-levels of block addresses CBA0 and CBA1 only activate one of the secondary memory blocks. In addition, FIG. 4B is a table for explaining the operation mode, in which only the control signal PL0B is enabled / disabled (for example, the logic level is low), and the page length of 211-1 is obtained, in which the logic of the block address CB A1 When the level is low, start two secondary memory blocks 0 and 1, or

O: \ 89 \ 89113.DOC -16- 1233619 When the logic level of the Tianxing block address CB A1 is high, two secondary memory blocks 2 and 3 are activated (in this mode, it has nothing to do with CBA〇) . In addition, FIG. 4 (: is a table used to explain an operation mode, in which only the control signal pL1B is activated / enabled (for example, the editing level is low), and the page length is obtained, in which all the sub-memory blocks (0, 1, 2 and 3) are all activated, regardless of the logical level of the row block address CB0AACBA1. Refer to the exemplary embodiments of FIGS. 3 and 4A, 4B, and 4C, which will be described in further detail in accordance with the present invention. Each operation mode of the semiconductor memory device. Referring to FIG. 3, the control signal generator 35o receives an external command and address, and uses MRS 353 to generate predetermined control signals Fan and PL1B in response to the command and address. The control circuit 36o receives The row block addresses are ^^ 80 and [] 88, 1 and the control bluffs PL0B and PL1B, and then output control signals to the secondary decoders 312, 322, 332, and 342. The secondary decoders 312, 322, 332, and 342 are based on The control signal of the control circuit 360 and a first column address RAi (where 1 = 0, t selects the corresponding word line driver 111, 121, m, 141 to start. When the self-horse dissector 1 50 generates regular word lines When the signal NWE is activated, the secondary solution is activated: the device outputs a word line of electricity Signal (ρχι) to a corresponding character line driver. Activate one of the selected secondary memory blocks corresponding to the line driver-0, machine-1, WL-2, WL-3. In other words, the character line driver 111, 121, 131, 141 In response to the normal word line activation signal nwe generated by the column decoding H 350, the output signals of the corresponding secondary decoders 312, 322, 332, 342 are switched to a activated word line, One of the character lines of the related secondary memory block is activated. The following will refer to FIGS. 5 and 6 for further details of an exemplary decoder and character line driver according to the present invention. The example of the occult body can be implemented in the device of FIG. 3, for example

O: \ 89 \ 89ll3.DOC -17-1233619. An operation mode of a semiconductor memory device with the exemplary structure of FIG. 3 can be selected to activate one of the secondary memory blocks 110, 120, 130, and 140 to obtain a 2n_2 page length. In particular, when the control signals PL0B and PL 1B are turned off (for example, the logic “high” state), only one of the secondary memory blocks 110, 120, 130, and 140 is in accordance with the logical states of the row block addresses CBA0 and CBA1. Close, as shown in Figure 4A. In addition, in this operating mode, one of the row decoders 371, 372, 3 73, and 374 is activated according to the logical state of the row block addresses CBA0 and CBA1. By way of example, suppose two control signals PL0B and PL1B are both closed (for example, in a logic high state), and the row block addresses CBA0 and CBA1 are both logic "low". In this case, the outputs of NAND gates 363 and 367 will be logic, 'high,' , Causing the secondary decoder 312 to be activated (assuming, of course, the required address signal RAi is input to the secondary decoder 312). Then the secondary decoder 312 will generate an appropriate control signal to cause the word line driver 111 to start the secondary memory block 丨丨 〇 One word line WL-0. In addition, because the row block address 0] 800 and (^) 8 people 1 are in a low level of complaint, so there are only logic circuits 3 92, 3 91, and 3 8 1 will operate and thus activate the row decoder 37: 1. The row decoder 371 receives The row address of the decoder 375 is poor, and then a row selection line (CSL) is selected from the 2n · 2 row selection lines (csl) on the secondary memory block 110. That is, the secondary memory area corresponding to the activation The semiconductor memory device of the block has a 2 "page length. For example, in the paging mode operation, the word line (column) is maintained to be activated, and at the same time, two row addresses are sequentially applied to access the memory cell of the activated column. Another- The operation mode of a semiconductor memory device with the exemplary structure of FIG. 3 can be activated by two secondary memory blocks to obtain a 2 „] page length. In particular, O: \ 89 \ 89U3.DOC -18-1233619, if Start the control signal PLOB (for example, the logic “low” state) and turn off the control signal PL 1B (for example, the logic “high” state). According to the logic state of the row block addresses CB A1 B and CBA1, two secondary memory areas will be activated. The block has nothing to do with the logical state of the row block address CBA0 and CBA0B, as shown in Figure 4B. More specifically, if the row block address CBA1 has a logic "low" state, the secondary memory block 110 is started. And 120 word lines WL-0 and WL-1, and the logical state of the row block address CBA0 In addition, if the row block address CBA1 has a logic "high" state, the character lines WL_2 and WL-3 of the secondary memory blocks 130 and 140 are activated, and there is no relation with the logic state of the row block address CBA0. In addition, in this operating mode, according to the logical state of the row block address CBA0, it is possible to choose to start the row decoder related to the next-time memory block. By way of example, suppose the control signal PL0B (such as logic 'f low π state), and turn off the control signal PL1B (for example, logic "high" state). In this case, since the control signal PL1B with a "high" logic level is input to the two NAND gates 363 and 364 of the control circuit 360, the output of each NAND circuit will be in a logic "high" state, which is in line with the block level. The logic states of addresses CBA0 and CBA0B are not involved. It is further assumed that the row block address CBA1 has a logic "low" state, so the output of the NAND circuit 367 will be in a logic "high" state. In this case, since the outputs of the NAND circuits 363, 3 64, and 3 67 are logic "High", so the secondary decoders 31 2 and 322 are activated (assuming, of course, that the desired address signal RAi is input to the secondary decoder). Then the secondary decoders 3 12 and 322 will generate appropriate control signals, so that the corresponding word line drivers 111 and 121 activate the word lines WL_0 and WL_1 of the secondary memory blocks 110 and 120. Furthermore, when the row block address CBA1 is in a logic "low" state and the secondary record is started: O: \ 89 \ 89113.DOC -19- 1233619 The hidden block 11G and 12G 'row decoders 371 and 372 should be respectively Start to know the length of the blade page. In a preferred embodiment, according to the logical state of the row block address CBAG, start a k-selection line (CSL) on the next memory block 1⑺ or η◦. For example, in FIG. 3, if the row block address cba0 is at a logic low L, the input to the NAND circuit 392 will be a logic "high". The lamp selection line (CSL) generated by the self-decoder 371 is started at 110, and the row line of the secondary memory block 110 is selected in response to the row selection line (CSL). Next, by changing the row block address cba0 to a logic "high," all inputs of the NAND circuit 394 are logic "high," and the decoder 37 of the row memory block 110 is closed, and The decoder 372 of the secondary memory block 12 is activated. Therefore, for the exemplary operation mode shown in FIG. 4B, the page length related to the activated character line is 2n, which is obtained by the operation mode of FIG. 4A. Twice the page length. That is, if the user needs a semiconductor memory device with a page length, the control signal generator 35o generates an activation control signal PL0B and inputs it to the control circuit 36o to change the page length of the semiconductor memory device. u 'Another operation mode of the semiconductor memory device with the exemplary structure of FIG. 3 The memory can be activated four times to obtain a 2n page length. In particular, if the control signal PL 1B is activated (for example, logic, low, 'state), all secondary memory blocks 11, 120, 130, and 140 will be activated, and the row block addresses CBAOB, CBAO, The logic states of CBA1B and CBA1 are not involved, as shown in Figure 4C. More specifically, if the control signal PL1B is logic "low", the output of each NAND circuit 363, 364, 367, and 368 of the control circuit 360 will be logic O: \ 89 \ 89113 DOC -20-1233619 `` High '' ', Has nothing to do with the logical state of the row block addresses CBAOB, CBAO, CBA1B and CBA1. In this operation mode, the character lines WL-0, WL-1, WL-2, and WL-3 of the secondary memory blocks 1 丨 〇, 120, 130, and 140 will be activated, and the row block addresses CBA0 and CBA1 The logical state is not involved. In addition, in this operation mode, the row decoder related to the secondary memory block to be started can be selected according to the logic state of the row block addresses CBA0 and CBA1. Therefore, whether to start a given row selection line (CSL) for one memory block depends on the logic state of the row block addresses CBA0 and CBA1. Therefore, in this case, the 'semiconductor device has a 2n page length. The advantage of the exemplary embodiment of FIG. 3 is that, since the mode register group 353 is implemented by the control signal generator 350, the mode register group 353 can output a control signal 'to change the semiconductor device according to the address and instruction control. Page length. Exemplary embodiments of the secondary decoder and word line driver shown in FIG. 3 will now be discussed with reference to FIGS. 5 and 6. Fig. 5 is a circuit diagram illustrating a secondary decoder according to an embodiment of the present invention. For the sake of explanation and analysis, FIG. 5 shows a specific embodiment of the secondary decoder 312 of FIG. 3. FIG. 6 is a circuit diagram of a part of a driver circuit system of a word line driver according to a specific embodiment of the present invention. Referring to FIG. 5, the secondary decoder 3 1 2 includes a NAND circuit 510, first and first inverters 520 and 530. The NAND circuit 510 receives a first column of addresses RAi (where i = 0, 1) and outputs control signals from the financial assistance circuits 363 and 367 of the control circuit 36. The first inverter 52 receives the output signal of the NAND circuit 51 and generates a first gate signal PXIDG. The second inverter 53〇 receives

O: \ 89 \ 89ll3 DOC -21-1233619 The output signal of the NAND circuit 510 generates a word line power signal Pχί at an elevated level. The secondary decoders 3 and 2 also output a second gate signal ρχΐΒ (which is the output of the NAND circuit 510).

Referring to FIG. 6, a word line driver 600 includes a plurality of Mos transistors MN1, MN2, MN3, and MN4. The power supply voltage vcc is supplied to the gate of the Mos transistor MN1. The first ~ terminals of the MOS transistor MN1 are connected to the regular word line actuation signal (NWE) line (as described above, the NWE is generated by the column decoder 150). The second terminal of the MOS transistor MN1 is connected to the gate terminal of the MOS transistor MN2. The first terminal of the MOS transistor MN2 is connected to the word line power signal PXI (e.g., output from the secondary decoder 312). The second terminal of the MOS transistor MN2 is connected to the word line WL. The gate of the MOS transistor MN3 is connected to the first gate signal 卩 100 (for example, output from the decoder 312). The gate of the ^ 03 transistor ^^ 4 is connected to the second gate signal PXIB (for example, output from the decoder 3 12). The number of word line driver circuits 600 implemented in a given word line driver ill, 121, 131, 141 in FIG. 3 is equal to the number of word lines on the corresponding secondary memory block. The secondary decoder 312 and the word line driver 600 (belonging to the word line driver 111) activate the word line WL_0 in response to the first column address RAi (where i = 0 and 1) and the output signal of the control circuit 360. More specifically, the sub-decoder 312 and the word line driver 600 operate as follows. The secondary decoder 312 generates a first gate signal PXIDG, a second gate signal PXIB, and a word line power signal PXI according to the input control signal and the column address. In particular, only when the first column address RAi (where i = 0 and 1) and the output signals of the NAND circuits 363 and 367 of FIG. 3 are in the logic, high, and state, the first gate signal PXIDG and the character The line power signal PXI is in a logic O: \ 89 \ 89U3.DOC -22-1233619 π high " state. In this case, the second gate signal PXIB for the pre-charged word line WL is in a logic “low” state. In the word line driver 600 of FIG. 6, the power supply voltage VCC is supplied to the gate of the MOS transistor MN1. Therefore, the MOS transistor MN1 is always on. When the first gate signal PXIDG and the word line power signal PXI are in a logic "high" state, and the second gate signal PXIB is in a logic "low" state, the MOS transistor MN3 is on. And the MOS transistor MN4 is turned off. Therefore, in this case, the word line power signal PXI is connected to the word line WL and the word line WL is activated. In other words, if the first gate signal PXIDG and the word line power signal PXI In the logic "low" state and the second gate signal PXIB is in the logic "high" state, the MOS transistor MN3 is turned off and the MOS transistor MN4 is turned on. Therefore, in this case, the word line WL is turned off. In the exemplary embodiment of FIG. 3 described above, the control signal generator 350 implements the MRS 353 with a semiconductor memory device, and generates a control signal that can change the page length. It is known that other methods and devices for generating control signals can be implemented according to the present invention. For example, FIG. 7 illustrates a control signal generator circuit 700 implemented by wire bonding according to another embodiment of the present invention, and FIG. 8 illustrates a control signal generator implemented by fuses according to another embodiment of the present invention. More specifically, the control signal generator 700 shown in FIG. 7 includes a plurality of bonding pads 710a, 710b, 710c, 720a, 720b, 720c, and inverters 711, 721. The bonding pads 710a and 720a are connected to the power supply voltage VCC, and the bonding pads 710b and 720b are grounded. One input terminal of the inverter 711 is connected to the bonding pad 710c, and one input terminal of the inverter 721 is connected to the bonding pad 720c. Inverted O: \ 89 \ 89113.DOC -23-1233619 The controllers 711 and 721 output control signals Du and Fan respectively. The process of connecting the bonding pads 71oc to 71oa or 71b, and the bonding pads 720c to 720a or 720b are performed during the manufacture of semiconductor memory devices. The logic state of the first control signal PL0B and the second control signal will depend on the connection of the bonding pads. For example, as shown in FIG. 7, the bonding pad 71k is connected to the bonding pad 710b, the bonding pad 720c is connected to the bonding pad 72〇a, and the control #bl PL1B is set to a logic “high” state, and the control signal hole is set to a logic “low” "status. Therefore, if the control signal generator circuit 700 of FIG. 7 is implemented in the exemplary embodiment of FIG. 3, the page length of the semiconductor memory device will be 2n] (see FIG. 4B). As a matter of course, the connection between the bonding pads is variable to generate control signals of different logic states to obtain a desired page length. It is known that the connection between the bonding pad and the power pin (VCC, VSS) can be connected by metal or wire. Referring to FIG. 8, a control signal generator 800 according to another embodiment of the present invention has two diode-coupled MOS transistors MP1 and MP2, laser melting wires 812 and 822, and inverters 813 and 823. The MOS transistor MP1 has a light-emitting diode connection, in which the gate and the drain of the MOS transistor MP1 are connected to each other, and the source is connected to the power supply voltage VCC. The laser fuse 812 is connected between the MOS transistor MP1 and the pole and the ground voltage. The inversion 8 1 3 inverts the signals of the MOS transistor M ρ 1 and the terminal, and outputs a control signal PL 1B. Similarly, the MOS transistor MP2 also has a diode coupling connection, in which the gate and the drain of the Mos transistor MP2 are connected to each other, and its source is connected to the power supply voltage VCC. The laser fuse 822 is connected between the drain of the MOS transistor MP2 and the ground voltage. The inverter 823 inverts the signal of the MOS transistor MP2 drain terminal O: \ 89 \ 89U3.DOC -24-1233619 phase 'and outputs the control signal PLOB. The logic state of the control signals PL0B and PL1B depends on the laser fuse status. More specifically, if the laser fuse 812 or 822 is cut off, the corresponding control signal will have a logic, low, and status. If the laser fuse 812 or 822 is not cut off, the corresponding control signal will have a Logic "high" state. For example, if the laser fuse is connected, and the laser fuse 822 is cut off, the control signal pl0b is in a logic ", low" state, and the control signal hole ⑶ is in a "logic, high" state. In this case Next, if the control signal generator circuit 800 is implemented in the exemplary embodiment of FIG. 3, the page length of the semiconductor memory device will be 2n (see FIG. 4B). Naturally, the control signal generator 800 is adapted to The logic states of the fuses 812 and 822 generate control signals with different logic states. Fig. 9 is a high-level flowchart of a method for changing the length of a semiconductor memory wave blade according to a specific embodiment of the present invention. The method for changing the page length of the IC memory device includes generating a first control signal of one of the plurality of page length operation modes (step 91); generating a first control signal according to the first control k and a block address. Two control signals (step 92); and then according to the page length operation mode, the second control signal is used to change the page length of the semiconductor device (step 930). In generating step (step 910) comprises generating a first control signal in accordance with an external command "received from the memory controller or the cpu address of the first control signal. For example, steps M3 can be used, which is not controlled by the 彳 § generator 35 which is not controlled in FIG. 3. In other embodiments of the present invention, a device or method such as a control signal generator circuit and a method such as that described with reference to Figs. 7 or 8 can be used to generate the _th control signal.

O: \ 89 \ 891I3.DOC -25- 1233619 In addition, the step of generating the second control signal (step 920) can be referred to, for example, as described in FIG. 3, so that the control circuit processes the control signal from the control signal generator. And a row of block addresses to generate a first control signal that can selectively control each sub-element line control circuit of the memory block. Furthermore, the step of adjusting the page length in response to the second control number 4 (step 930) preferably includes, in response to the second control signal, selecting one or more corresponding word lines with the same column address in the memory block to be activated. To change the page length of the semiconductor memory device. FIG. 10 illustrates a simplified block diagram of a memory system in which the present invention can be implemented. The memory system 1000 includes a CPU 1001, a memory controller 1002, and a plurality of Lu Jiyi modules 1003. The memory module 1003 includes a plurality of semiconductor memory devices 1004 for implementing the present invention. The CPU 1001 may be a microprocessor unit (MPU) or a network processing unit (NPU). The CPU 1001 is connected to the memory controller 1002 via the first bus system B1 (such as the control bus, the data bus, and the address bus), and the memory controller 1002 via the second bus system B2 (control bus (Data bus, data bus, address bus) are connected to the memory module. In the exemplary architecture of FIG. 10, the CPU 1001 controls the memory controller 1002, and the memory controller 1002 controls the memory ι〇〇4 (but it is known that the CPU can be used to directly control the memory without using Individual memory controller). In the exemplary embodiment of FIG. 10, each memory module 〇003 may represent, for example, a memory bank, and each memory device 1004 of a given memory module 1003 may represent a memory device capable of implementing the present invention. . In this case, each A memory device 1004 can be logically divided into a plurality of secondary memory blocks, and the page length can be changed as controlled as described above. The control circuit system for performing memory access and / or changing the page length can be located in the memory device.

O: \ 89 \ 89I13.DOC -26- 1233619 In a preferred embodiment, the memory device of the memory module can have x8 bits of organization, and the memory device of another memory module can have Sichuan bytes. , 哉 means' different § self-memory modules can operate in different bit organizations. In another embodiment of the present invention, the memory system may include one or more individual semiconductor memory devices (instead of the memory module & having multiple memory devices as shown in FIG. 10), and (No memory controller). In this specific embodiment, the memory device is directly in communication with the central processing unit. This semi-integrated 3 memory device may have an X 8-bit organization, while the other semiconductor memory device may have a > < 16-bit organization. That is, different memory modules can operate in different bit organizations. In another implementation, the memory line according to the present invention may include direct and. The hidden controller (without CPU) communicates with one or more individual semiconductor memory devices (replaces the memory module with multiple memory devices as shown in Figure 10). In this embodiment, one memory device may have a heterogeneous organization, while the other memory device has an X1 6-bit organization. Although reference has been made here to the illustrative embodiments, it should be understood that the present invention is not limited to the specific embodiments of the precise systems and methods described herein. Those skilled in the art will not deviate from the scope of the present invention or In spirit, various other changes and improvements can be made. It is intended to incorporate all such changes and improvements into the scope of the invention as defined by the scope of the accompanying patent application. [Schematic description] Figures IA, 1B, and 1C are diagrams illustrating the hierarchical memory architecture of a semiconductor memory device according to the prior art. FIG. 2 is a block diagram of a memory cell array block O: \ 89 \ 89ll3 DOC -27-1233619 according to a specific embodiment of the present invention, which can change the page length of a semiconductor memory device. FIG. 3 is a circuit diagram of a memory cell array block according to a specific embodiment of the present invention, which can use a control signal generated by an MRS (mode register group) to change the page length of a semiconductor memory device. "Figures 4A, 4B, and 4C are table diagrams illustrating the various operation modes of the memory cell array block of Figure 3 ', in which different page lengths of the semiconductor memory arrangement can be obtained. Figure 5 illustrates the operations that can be performed in the circuit of Figure 3 A circuit diagram of a secondary decoder according to a specific embodiment of the present invention. FIG. 6 is a circuit diagram of a word line driver according to a specific embodiment of the present invention that can be implemented in the circuit of FIG. 3. FIG. 7 illustrates a circuit according to the present invention. A control signal generator according to a specific embodiment. Fig. 8 illustrates a control signal generator according to another embodiment of the present invention. Fig. 9 is a method for changing the page length of a semiconductor memory device according to a specific embodiment of the present invention. High-level flowchart. Figure 10 A simplified block diagram of a memory system capable of implementing the present invention. [Illustration of Representative Symbols] Component Name Semiconductor Memory Device Memory Bank Memory Cell Array Block Secondary Memory Cell Array Block Word Line Driver Part numbers 100 100A, 100B, 100C, 100D 100a, 100b, 100c, 100d 110, 120, 130, 140 μm, m, 141 112, 122, 132, 142 212, 222, 232, secondary decoders 242, 312, 322, 332, 342 O: \ 89 \ 89113.DOC -28- 1233619 150 column decoder 200, 300 memory block 250, 360 control circuit 350, 800 control signal Generator 351 Instruction buffer 352 Address buffer 353 Mode register group 361, 362, 365, 366, inverter 711, 721, 813, 823 363, 364, 367, 368, 510 NAND circuit 371 ~ 374 line decoders 375 pre-decoders 381 ~ 384, 391 ~ 398 logic circuits 520 first inverter 530 second inverter 600 word line driver 700 control signal generator circuit 710a, 710b, 710c, 720a, 720b 720c bonding pads 812, 822 laser fuse 1000 memory system 1001 central processing unit (CPU) 1002 memory controller 1003 memory module 1004 memory O: \ 89 \ 89113 DOC -29-

Claims (1)

1233619 Patent application scope: 1. A semiconductor device comprising: a memory cell array logically divided into a plurality of memory blocks, wherein each memory block is addressed by a corresponding block address; a plurality of characters Line control circuit, wherein each word line control circuit is related to the memory blocks to activate a word line of the relevant memory block; and-a control circuit for selecting and controlling the word line control circuits俾 Start with _ or a plurality of corresponding character lines at the same column address to change a page length of the semiconductor memory device. 2. If the device is the oldest in the scope of patent application, the control circuit receives a row of block addresses and a first control signal as inputs, and then generates a second control number to selectively activate one or more word line control circuits. . 3. If the intention of applying for the 2nd dream field of the patent scope further includes a control signal generator 'its receiving-external instructions and-external addresses, and then generating the first according to the external instructions and the external addresses control signal. 4. The device according to item 3 of the patent application, which causes the control signal generator to include:-a positioner for receiving the external address and generating-an internal address;-for receiving the external instruction and generating an internal An instruction register of instructions; and > a mode register group for generating the first control signal according to the internal address and the internal instruction. O: \ 89 \ 89I13.DOC 1233619 5. 6. 7. 8 · If the word line control circuit in the device 1 of the scope of patent application 2 has a sub-decoder circuit and a related word line driver circuit . For example, the device in the scope of patent application No. 5, each of the secondary decoder circuits in # receives a column address and the second control signal output from the control circuit to selectively activate the related word line driver circuit. For the device in scope i of the patent application, the block position in # includes a row of addresses or a row of addresses. < Exhibition, further including a control operation for generating the first control signal of item 2 of the patent scope, such as * * $ + $ k 利 彳. A state is generated in which the control signal generator is configured to generate the first control signal via one of wire bonding, JS, strong σ A Bingjunkou metal option and fuse option. 9. The device according to item 2 of the patent application scope, wherein when the first control signal temple βρ is closed, the sub-element line W at the memory blocks and the first control signal is activated when the first control signal is closed. , At least two character lines with the same column address at the two memory blocks of the plurality of memory blocks are activated. 10 · —A memory system including: a memory controller for generating a plurality of instructions and position signals; and a first-memory module for receiving the instructions and position signals such as 5H, the first memory module includes # 略 壮 职 ^ The plurality of memory devices of the δ self-memory device, wherein the first memory device includes:-an array of memory cells that are logically divided into a plurality of memory blocks, where each a self-memory block is-corresponding Block addressing, · A plurality of word line control circuits, where each word line control circuit is O: \ 89 \ 89II3.DOC -2-1233619 related to one of these memory blocks to activate the relevant memory A word line of a block; and a control circuit for selecting and controlling the word line control circuits, and activating one or more corresponding word lines with addresses in parallel to change a semiconductor memory device Page length. 11. The memory system according to item 10 of the patent application scope, further comprising a second memory module that receives the instructions and position signals generated by the memory controller, and the second memory module includes a second memory module having a second memory device. A plurality of memory devices, wherein the second memory device includes a memory cell array logically divided into a plurality of memory blocks; wherein the first memory device has a first bit organization and the second memory device has a A second-bit organization, wherein the first-bit organization is different from the second-bit organization. 12. The memory system according to item 10 of the patent application, wherein the control circuit receives a row of block addresses and a first control signal as inputs, and then generates a first control k number to select to activate one or more word lines. Control circuit. 13. The memory system according to item 12 of the patent application scope, further comprising a control signal generator, wherein the control signal generator includes: a receiver for receiving an address signal generated from the memory controller and generating an internal address A position buffer; an instruction buffer for receiving an instruction generated from the memory controller and generating an internal instruction; and-a mode temporarily for generating the first control signal according to the internal address and the internal instruction Register group. O: \ 89 \ 89113.DOC 1233619 Μ · As described in the 13th of the scope of patent application, where "㈣ 卜 控制 ##" is activated in one of the memory blocks of the plurality of memory blocks Word lines, and when the first control signal is activated, at least two word lines with the same column address at two of the plurality of memory blocks are activated. 15 · —Memory System Including: a central processing unit for generating a plurality of instructions and position signals; and a first memory module receiving the instructions and position signals, the first Lu Jiyi fork group includes a plurality of numbers having a first memory device Memory devices, wherein the first memory device includes: a memory cell array logically divided into a plurality of memory blocks, wherein each memory block is addressed by a corresponding block address; a plurality of character line controls Circuit, each character line control circuit in the circuit is related to one of the five memory blocks to activate a character line of the relevant memory block; and control for remotely controlling the character line control circuits Circuits One or more corresponding word lines of the address to change the page length of a semiconductor memory device. 6. The memory system of item 5 of the patent claim, further including a receiving = instructions issued by the central processing unit. The second memory module and the position signal, and the β-h5 first memory module includes a plurality of ft devices with a second memory device. The second memory device includes a logically divided into a plurality of memory blocks. Memory cell array; wherein the first memory device has a first bit organization, and the second record O: \ 89 \ 89I13.DOC 1233619 the memory device has a second bit organization, wherein the first bit organization and The second bit organization is different. Π · If the memory system of the patent application No. 5 is applied, the first memory device further includes a control signal generator, wherein the control signal generator includes: An address signal generated by the central processing unit and generating a location buffer of an internal address; an instruction buffer for receiving an instruction generated from the central processing unit and generating an internal instruction And a mode register group for generating the first control signal according to the internal address and the internal instruction. 18. For example, the memory system of claim 17 of the patent application scope, wherein when the first control signal is turned off, that is, A character line is activated at one of the plurality of memory blocks, and when the first control signal is activated, it is activated at the two memory blocks of the plurality of memory blocks. At least two character lines with the same column address. 19. The memory system of the fifth item of the patent application scope, wherein the central processing unit is a network processing unit (npu). 20. A memory system, including ·· A memory controller for generating a plurality of instructions and position signals; and a first memory device receiving the instructions and position signals, wherein the first memory device includes: a logical partition into a plurality of memory blocks Memory cell array, where each memory block is addressed by a corresponding block address; O: \ 89 \ 89I13.DOC 1233619 a plurality of word line control circuits, wherein each word line control circuit is -Relevant to the memory block to activate a character line of the relevant memory block; and a control circuit for selecting and controlling the control lines of these character lines, 俾 to activate one or more corresponding characters with the same address Line to change the page length of a semiconductor memory device. 21 · If the memory system of item 20 of the patent application scope, further includes-a second memory device that receives the instructions and position signals generated by the memory controller, the second memory device includes-is logically divided into a plurality of An array of memory cells in a memory block; wherein the first memory device is a 笸,-1 a first-ever mortal organization, and the second memory device has a second byte, $, of which the first bit The organization is different from this second-bit organization. 22 · —a memory system comprising:-a central processing unit for generating a plurality of instructions and position signals; and-a first memory device for receiving such instructions and position signals, the-memory device includes: The memory cell array is divided into a plurality of memory blocks, where each memory block is addressed by a corresponding block address; the plurality of word line control mines &#; Zuo circuits' where each word line control circuit is Related to one of the right blocks of these memory blocks to activate a character line of the relevant memory block; and one to choose to control poverty! Control circuit of this kind of 7L line control circuit, 俾 Starter-one or more corresponding word lines in the same column address to change O: \ 89 \ 89113 DOC -6-1233619 a page length of the semiconductor memory device . 23. If the memory of item 22 in the scope of the patent application is the second, further the central processing unit | I # receives the second # of the special instruction and the position signal generated, wherein the -memory dream 罟 ° has hidden Memory unit array of memory blocks;. There are a plurality of the first memory device having a second bit organization and the two bit organizations being different. The first unit is organized, and the second record includes the mth weaving and the first and second processing orders, and the central processing order. 24. The memory system element of the 22nd application scope is a network process. Unit (NPU). 25. The memory system unit of item 22 of the patent application is a microprocessor unit (MPU). 26. —f A method for changing the page length of a semiconductor memory device having a memory cell array logically divided into a plurality of memory blocks, wherein each base block is addressed by a corresponding block address, the The method includes the steps of: generating a first control signal with a plurality of page length operation modes uniformly; " generating a second control signal according to the first control signal and a block address; and in response to the second control signal, selecting One or more word lines in the memory blocks having an identical column address are activated to provide a page length of the semiconductor memory device corresponding to the regular page length operation mode. O: \ 89 \ 891I3.DOC 1233619 27. The method of claim 26 in the scope of patent application, wherein the step of generating the first control signal includes the steps of: receiving a command signal and a bit address signal; The position signal generates the first control signal. 28. The method of claim 27 in the scope of patent application, wherein the No.-control; language) number is generated by a pattern register group. 29. The method of claim 26, wherein the step of activating one or more character lines in the memory blocks includes the steps of: inputting the second control signal and a row of positions at a plurality of decoders; And activate one or more word line drivers related to the memory blocks according to the word line power signal generated by the decoder. O: \ 89 \ 89113.DOC