1227498 坎、發明說明： 【發明所屬之技術領域】 本發明係關於用於控制一元件之電子控制裝置，更具體 而言’係關於一種能夠覆寫控制資料的電子控制裝置。 【先前技術】 控制資料，例如用於控制_元件等之控制程式及控制參 數，儲存於一非揮發性記憶體（R〇M)中，藉此即使當電池 斷開且有時提供給使用者時控制資料亦不會被擦除。舉例 而5，一電子控制裝置用於控制引擎、變速箱及其它汽車 零件，且所產生的控制資料儲存於該電子控制裝置内的一 ROM 中。 在琢電子控制裝置裝入一汽車中之後，汽車製造商或經 銷商可能希望根據一受控元件（例如實際引擎或變速箱）之 特性來校準控制資料。因此，控制資料通常儲存於一可重 寫的非揮發性記憶體（例如一 EEPROM(電可擦可程式規劃 ROM)或一快閃記憶體（快閃EEpR〇M))中，從而可覆寫該等 控制資料。快閃EEPROM之特徵在於其内部電路相 且其成本較低。 快閃EEPROM之儲存區劃分為複數個儲存塊，因此在一 覆寫作業中可針對每一儲存塊擦除及/或寫入資料。舉例而 s，對於一具有兩個儲存塊且每塊之儲存容量為U千护一 組（KB)的64 KB快閃EEPROM，每32 KB實施一資科覆寫f 業。然而，對於快閃EEPR0M，在實施一資料覆寫作業時 ，該儲存塊内的資料無法讀出。 ’ 1227498 )中二:於快閃一’與在，隨機存取記憶體 若需要1—資料覆寫作業所需時間很長。因此， =據—受控元件(例如一引擎)之特性實施校 ^至快咖PRQM之㈣通常暫時 .. 除錯益）中。爾後，在引擎停機後，使用错存㈣ 邵储存元件中的資料對快閃eepr〇m實 μ 因此，芒i #丄时/ 伐局作菓。 每:要對早個㈣EEP議實施多项校準，則需針對 又卞重複±述作業，該等重複作業極其耗時。 在:==上述問題而設計’且其目標為提供-種即使 覆寫㈣^私中亦能夠對—非揮發性記憶體實施資料 複冩作業的電子控制裝置。 【發明内容】 一、、、奸决上相_，根據中請專利範圍第㈣之本發明提供 =具有-非揮發性記憶體和_揮發性記憶體的電子控制 ㈣揮發性記憶體與揮發性記憶體可儲存用於控制 = <控制資料。該電子控制裝置包括—控制器，該控 、、、發丨内的資料來實施控制資料的 並在疋成校準後將儲存於揮發性記憶體内的資料窝 入至非揮發性記憶體。 根據中請專利範圍第2項之本發明提供中請㈣範圍^ 包子控制裝置’其中該控制器在校準開始時，將擬校 午非揮發性記憶體内的資料儲存於揮發性記憶體中；並使 用儲存於揮發性記憶體内的資料來校準控制資料。 據中叫專利|a圍第3項之本發明提供_請專利範圍第1 1227498 項或第2項之電子控制裝置’其中該控制器進一步識別擬校 準非揮發性記憶體的一位址，並在校準開始時，賦予揮發 性记憶體相同於非揮發性記憶體之位址，並在校準過程中 優先為揮發性記憶體實施資料處理。 根據申請專利範圍第4項之本發明提供申請專利範圍第1 項至第3項中任一項之電子控制裝置，其進一步包括一用於 控制非揮發性記憶體中資料的控㈣存器，其中該控制器 在校準完成時，將非揮發性記憶體之位址及已校準控制資 料窝入至孩控制暫存器，並利用窝入至該控制暫存器中的 位址和已校準控制資料來寫人至非揮發性記憶體。 根據申請專利範圍第5項之本發明提供申請專利範園第4 私子控制裝置，其進—步包括_用於控制該控制暫存 器使用權限的權限暫存器，纟中當窝人至揮發性記憶體時 ，控制構件設定該權限暫存器，並在寫入作業完成後，清 除該權限暫存器。 根據中請專利範圍第6項之本發明提供中請專 項至第5項中任一項 固矛丄 …子控制裝置，其中該元件具有複數 個早兀，控制资料镞A、人地丄十 ; 士應於每一單元的非揮發性記憶 〜Λ 體具有—能夠鍺存對應^擬校準單元的 控制資料的儲存容量。 根據申凊專利範園第7項士 項至第6項中任子、^發明提供申請專利範圍第1 具有至少兩個或多個二塊置’其中非揮發性記憶體 ㈣寫入儲存塊π另針對每一儲存塊實施寫入作 使用另一儲存塊控制該元件。 1227498 =t π ^範圍第1所述之本發明’儲存於揮發性記 憶姐中的資料料實施控制料的校準。當校準完成後， 將儲存於揮發性記憶體中的資料“至非揮發性記憶體。 因此，安裝於電子控制裝置中的揮發性記憶體可用於校準 儲存有㈣控制該元件之控制資料的非揮發性記憶體。在 彼種情況下，無需使用一外部儲存元件(例如一除錯器)即可 貫施校準。藉由實施此一寫入作業，可在受控元件正在運 作的同時達成校準。 根據申請專利範圍W項所述之本發明，當校準開始時 擬权準非揮發性記憶體中的資料將儲存人揮發性記憶體中 ’並使用儲存於揮發性記憶體中的資料來校準控制資料。 因此’可使用預調整控制資料作為_起點來達成校準。藉 由將標準控制資料儲存人非揮發性記憶體中，僅需根㈣ 控兀件特性實施微調，由此可達成有效校準。 根據申請專利範圍第3項所述之本發明，在校準開始時， 識別擬校準的非揮發性記憶體之位址。爾後，賦予揮發性 記憶體相同於該非揮發性記憶冑之位玉止，且隸準過程中 ’優先為揮發性記憶體實施資料處理。亦即在記憶體配置 圖中’將揮發性記憶體之記憶體區域設定為交#於擬校準 記憶體區域之上。因此，該電子控制裝置即使在校準作業 中亦可照樣使用一個位址來控制該元件。 根據中請專利範圍第4項所述之本發明，當校準完成後’ 將揮發性記憶體之位址及已校準控制資料寫入至控制暫存 益中。爾後，使用儲存於該控制暫存器中的位址及已校準 1227498 控制資科來執行一非揮發性記憶體寫入。揮發性記㈣中 ^料可藉由該控制暫存器可靠地寫入至非揮發性二體 根據申請專利範圍第5项所述之本發明，該電子控制裝置 具有—用於控制該控制暫存器使用權限的權限暫存器。當 寫入至揮發性記憶體時，將設^該權限暫存器 作業完成後，該權限暫存器將被清除。因Λ，僅可在實施 -寫入作業時對該控制暫存器實施記憶體管③。 Λ 根據中請專利範圍第6項所述之本發明，揮發性記憶體且 有一能夠儲存對應純校準單元的控制資科㈣存容量^、 因此’揮發性記憶體儲存容量可限制為校準所需容量，由 此可減小該電子控制裝置之尺寸並降低其成本。里’ 根據申請專利範圍第7項所述之本發明，非揮發性記憶體 包括至少兩或多個儲存塊’且針對每一儲存塊分別實二 寫入作業。當寫入至儲存塊時，可使用另—错存塊控制該 元件。由此可在元件正在受控時覆寫非揮發性記憶體中的 控制資料。因此，無需重新啟動受控元件或電子控制裝置 即可有效達成校準。 【實施方式】 下文參照圖i至圖7詳細闇述本發明一具體實施例。在兮 具體實施例中’如圖1所示，假定使用-電子控制單： (酬）1〇來控制-受控目標u(例如—汽車引擎）。亦即在 ECU 10安裝於汽車内之後，枋進从^ w、史 払卑作為控制資料的控制參數 ，藉以控制構成該汽車的每一單元。 1227498 一作為非揮發性記憶體的快 該 ECU 10 包括一 CPU 1〇〇、 作為揮發性記憶體的校準RAM 1 02。該 閃 EEPROM 101 及一 ECU 10亦包括未圖示的一梓絲招Ann J日f叙梃組及一 A/D轉換器等等。 該C P U 1 0 〇組態用於勃杯辟六 〜厅」瓦執仃储存於快閃EEPR〇m 101、校準 RAM 102等中的各種程式。 快問EEPROM 101包含關於由用於控制的控制指令 和控制參數的資料。該具體實施 <列中所用快閃eepr〇m⑻ 共具有64千位元組（KB)的儲存容量。儲存區域由32kb的儲 存塊（在記憶體配置圖中分別為"塊〇"和"塊丨”）組成。對於一 覆寫作業’逐塊實施-資料擦除和—寫人作業。對於每一 受控單元，”塊0"包含相關於控制指令之資料，而"塊丨"則包 含相關於控制參數之資料。在該具體實施例中，假定在控 制受控目標U的過程中，"塊〇，，中的—控制指令可導致覆寫 ”塊1π中的控制參數。 权準RAM 102係一用於在校準過程中暫時儲存預定資料 的記憶體。對於該校準RAM 102，應使用一其儲存容量能 夠儲存對應於每一受控單元的控制參數的記憶體。該具體 實施例中的校準RAM 102具有2 KB的儲存容量。 ECU 10進一步包括一輸入/輸出介面部分12〇。Ecu 1〇之 每一部分皆藉由該輸入/輸出介面部分12〇連接至一使用者 介面部分12及一受控目標U。該使用者介面部分12由使用 者用於指定受控目標11並確認參數。 受控目標11為一元件，例如一引擎、變速箱和擬控制的 其它元件。ECU 10自安裝於受控目標U中的各傳感器接收 11 1227498 f科’並藉由輸入/輸出介面部分120將資料輸出至致動器 等等。 CPU 100藉由一位址匯流排連接至一位址解碼器11〇。該 位址解碼器U〇根據— 象术自CPU 100的位址信號將一信號輸 出^其對應輸出端。在該具體實施例中，cpu i⑻及位址解 碼器11 0用作控制構件。 /址解碼裔i 10包括一初始化暫存器⑴。該初始化暫存 =u 1包括·一用於儲存相關於一實施校準區域之位址的資 料的區域，及-用於儲存相關於校準RAM 1G2之激活的資 料的區域（激活位兀）。在該具體實施例中，當校準如 激活時’激活位元中將輸入"1 ”。 此外，ECU 10包括一超級使用者模式暫存器112作為一權 限暫存益，其用於控制該模式（在下文中稱作，，超級使用者 模式”）以針對快閃EEPR〇M 1〇1授予一覆寫權限。當設定為 超級使用者模式時，包含於超級使用者模式暫存器丨丨2中的 權限位元中將輸入” 1 ”。 ECU 10進一步包括一快閃控制暫存器U3作為一控制暫 存器，用於控制非揮發性記憶體中的資料。該快閃控制暫 存态113用於超級使用者模式中。該快閃控制暫存器113保 留擬寫入至快閃EEPROM 101的位址及已校準控制參數。 此外，CPU 100、校準RAM 102、快閃控制暫存器113及 輸入/輸出介面部分120分別連接至資料匯流排，從而藉由 資料匯>jfL排發送和接收資料。 接下來，將參照圖2至圖7闡述ECU 10所實施作業中一用 12 1227498 於將儲存於快閃EEPROM 101中的資料重寫為適合於受控 目標11之資料之作業。 在ECU 10正在依據儲存於快閃EEPROM 1〇丨中的資料於 制受控目標Π的同時’使用者可使用使用者介面部分12發 出一有關受控目標11之校準指令。該指令藉由輸入/輸出介 面部分120及資料匯流排傳送至CPU 100。 隨後，ECU 10進入校準模式，在該校準模式下開始圖2 所述之過程。首先，CPU 100確定快閃EEPROM 101上的一 校準區域（S1-1)。在彼種狀況下，CPu 1〇〇向初始化暫存器 111之激活位元輸入π 1 ’’，以激活校準RAM 1 02。此外，一實 施校準區域之位址儲存於初始化暫存器111中。 然後’將快閃EEPROM之校準區域中的資料複製至校準 RAM 102(S 1-2)。此一作業參照圖4所示的一記憶體配置圖 500來闡述。在該|己憶體配置圖5〇〇中設定有：一對應於校 準RAM 102的記憶體區域501 ; —對應於快閃EEPROM 101 之’’塊0’’的1己憶體區域5 02 ;及一對應於其，，塊丨，，的記憶體區 域503。在該具體實施例中，記憶體區域5〇3中的位置6〇〇〇 至67FF假定為一校準區域504。然後，在步驟（§卜2)中，將 校準區域504中的資料複製至對應於校準ram 1 02的記憶 體區域5 0 1。 然後，將校準RAM 102交疊於校準區域之上（sl-3)。此一 作業參照圖5所示的記憶體配置圖5 1 〇來闡釋。在該步驟中 ’在？己憶體配置圖5 10上設定的校準ram 1 02之記憶體區域 5〇1匹配到針對校準區域504設定的位址。此意味著為記憶 13 1227498 體區域501與校準區域504賦予同一位址。 然後，根據受控目標π之特性執行校準處理（si_4)。此一 作業參照圖3所示流程圖來闡釋。使用者可使用使用者介 部分12發出一針對用於控制受控目標π的參數資料等2 = 改指令（S2-1)。在彼種狀況下，cpu丨⑻將執行各種作業: 例如讀取或覆寫記憶體配置圖5 1〇上的資料。 若需處理交疊校準RAM 102的記憶體區域（當在步驟 (S2-2)中選擇’’是”時），則依據校準RAM 1〇2中的資料實施 處理（S2-3)。亦即，若在初始化暫存器lu之激活位元中設 定”1”，則針對賦予快閃EEPR0M 101與校準RAM 1〇2相同 位址（在孩具體實施例中為位置6〇〇〇至671?17)的記憶體區域 所實施的每一處理，亦會針對校準RAM 1〇2之記憶體區域 501實施。 反之’若需處理未交疊校準RAM 1 02的區域（當為，，否”時） ’則照常在記憶體配置圖5 10上快閃EEPROM 1 0 1中的資料 上實施處理（S2-4)。 然後’若具有任何新的資料處理指令（當在步驟（32巧）中 選擇’’否’’時），則重複步驟（S2-1)至（S2-4)來實施校準。反之 若找到適用於焚控目標11的合適參數值，則使用者可 使用使用者介面部分12發出一指令來結束校準。若發出一 用於結束校準的指令（當在步驟（S2-5)中選擇”是”時），則常 式將返回圖2所示的流程。 接下來’設定為超級使用者模式（S 1-5)。具體而言，在超 級使用者模式暫存器112之權限位元中輸入，，1”。在彼種狀 14 1227498 況下’儲存於校準RAM 1()2中的控制參數將寫入快閃 EEPROM 101中（S1_6)。亦即，如同圖6中記憶體配置圖 所不，a又疋於記憶體配置圖52〇上的校準ram 之記憶體 區域5(M中的資料將寫入至校準區域5〇心具體而言，在超 、及使用者模式中’可在έ£ι憶體目己置圖上存取快N控制暫存 器113。然後，儲存於校準RAM 1〇2中的位址和資料寫入至 快閃控制暫存器113中。此外，根據儲存㈣閃控制暫存器 113中的位址，將儲存於快閃控制暫存器113中的資料寫入 至快閃EEPROM 101上的位址中。同時，Ε(：υ⑺繼續依據 儲存於記憶體區域502中的資料來控制受控目標丨i。 當该程式結束時，清除超級使用者模式暫存器丨丨2之權限 位元，且退出超級使用者模式並返回正常模式。此外，初 始化暫存器111之設定發生改變（31_7)。此時，初始化暫存 器111之激活位元被清除，由此產生圖7所示的一記憶體配 置圖530。亦即校準RAM 102之記憶體區域5〇1被移除，且 在記憶體配置圖530中生成已寫入校準RAM 1〇2之資料之 校準區域531。然後，ECU 10使用快閃EEPR〇M 1〇1中的覆 寫資料來控制受控目標11。隨後，快閃EEPR〇]Vi之覆寫作 業結束。 根據前述之具體實施例，可獲得下列特點。在前述具體 實施例中，ECU 10包括快閃控制暫存器113，並在校準結束 時進入超級使用者模式。在該模式中，快閃控制暫存器i ^ 3 變得可在記憶體配置圖上存取。然後，使用快閃控制暫存 器U 3將儲存於校準RAM 102内的資料程式規劃入快閃 15 1227498 EEPROM 101。因此，即使在助10正在作業時，亦可擦 除或覆寫快閃EEPROM 101之一特定區域中的資料。按常規 ’在覆寫快閃EEPROM101之前，受控目標⑴貝停機且卿 之控制將中斷。因此’當實施另—校準時，需重新啟動 ECU 1 〇及受控目標丨丨。在彼種情況下，啟動後，受控目標 11:需經過一段時間方可穩定。而根據該具體實施例所： ，藉由在党控目標11仍在作業的同時實施校準，則可 完成校準任務。 在珂述具體實施例中，可使用超級使用者模式在ECU 10 作業過程中實施校準。因此，即使在校準RAM102較小(例 )時亦可有政達成校準。藉由使用此一小容量校準 =AM 102 ’可縮小Ecu 1G之尺寸。此外，由於&趟相當昂 貝因此使用一小的杈準RAM 102可容許降低£CU 10之成 本。 在前述具體實施例中，安裝於ECU H)中的校準RAM 102 用於覆寫快閃EEPR0M 101中的資料。亦即则1〇自身具 有一用於覆寫快閃EEPR〇M丨〇丨中資料的機制。其使得無需 將权準資料儲存至一外部儲存元件⑼如一除錯器）中。由此 可有效覆寫儲存於快閃EEpR〇M 1〇1中的資料。 在W述具體實施例中，在校準開始時，實施校準之區域 勺位址將儲存於初始化暫存器111中。該位址可用於將快 門EEPROM 1〇1中的資料複製至校準尺舰服，並在快閃 =EPR〇M 1〇1之权準區域5〇4内設定校準^之記憶體 區戈50 1此思味著可根據校準區域來設定校準RAM i 〇2之 16 1227498 設定區域。 應瞭解，前述具體實施例可作如下修改。在前述具體實 施例中，當程式結束時，將清除超級使用者模式暫存器n 2 之權限位元，且退出超級使用者模式以返回至正常模式。 同時，清除初始化暫存器111之激活位元。反之，若連續實 施另一受控目標1 1之校準，則可在初始化暫存器11丨中設定 一實施一新校準作業之區域之位址，同時使初始化暫存器 111之激活位元維持為” 1 ”，由此可連續實施校準。 在前述具體實施例中，使用一具有2 KB儲存容量的校準 RAM 102，儘管其並非限定於此。其容量可涵蓋一單一校 準所需的記憶體區域。此外，可使用一具有更大儲存容量 之校準RAM 102來同時對更多受控目標丨丨實施校準。 在前述具體實施例中，在控制受控目標1丨的作業過程中 ，使用快閃EEPROM 101之”塊〇，，的一控制指令來覆寫，n，， 的控制參數，儘管其並非限定於此。可於一包括一需要覆 寫的快閃EEPROM 101的電子控制裝置中實施此作業。 在前述具體實施例中，快閃EEPROM 1 01之校準區域中的 資料在步驟S1-2中複製至校準ram 102。或者，若在兮# 準區域中無控制資料，可跳過該步驟。 在則述具體實施例中，受控目標Π (例如一汽車引擎）由心 子控制裝置（ECU 10)控制，儘管其並非限定於此。關鍵在 於’該裝置可包括一快閃EEPROM 101，且可於一可執^ 身資料覆寫的電子控制裝置中實施。 如上文之詳述，根據本發明，即使在控制作業期間亦。 17 1227498 覆寫非揮發性記憶體之資料。 【圖式簡單說明】 圖1為一闡釋本發明一具體實施例之ECU(電子控制裝置） 之總體結構的示意圖； 圖2為一用於解釋一快閃EEPR0M之覆寫作業的流程圖； 圖3為另一用於解釋一快閃EEpR〇M之覆 圖， 圖4為—記憶體配置圖之說明圖； 圖5為 一記憶體配置圖之另一說明圖 圖6為 一記憶體配置圖之再一說明圖 圖7為 一記憶體配置圖之又一說明圖 【圖式代表符號說明】 10 電子控制單元（ECU) 11 受控目標 12 使用者介面 100 CPU 101 快閃EEPROM 102 校準RAM 110 位址解碼器 111 初始化暫存器 112 超級使用者模式暫存器 113 快閃控制暫存器 120 I/O介面 位址匯流排 資料匯流排 1227498 (Sl-l) (Sl-2) (Sl-3) (Sl-4) (Sl-5) (Sl-6) (Sl-7) (S2-1) (S2-2) (S2-3) (S2-4) (S2-5) 500 501 502 503 504 510 520 530 531 確定快閃EEPROM上的校準區域 將校準區域中的資料複製至校準RAM 將校準RAM交疊於校準區域之上 校準處理 設定超級使用者模式 使用快閃控制暫存器將校準RAM中的 資料程式規劃至快閃EEPROM中 改變初始化暫存器的設定 結束 校準處理 發出資料處理指令 處理交疊校準RAM之區域？ 根據校準RAM中的資料處理 根據快閃EEPROM中的資料處理 結束校準？ 返回 否 記憶體配置圖 校準RAM 快閃EEPROM(塊0) 快閃EEPROM(塊1) 校準區域 記憶體配置圖 記憶體配置圖 記憶體配置圖 校準區域 191227498 Description of invention: [Technical field to which the invention belongs] The present invention relates to an electronic control device for controlling a component, and more specifically, to an electronic control device capable of overwriting control data. [Prior art] Control data, such as control programs and control parameters used to control _ components, are stored in a non-volatile memory (ROM), so that even when the battery is disconnected and sometimes provided to the user Control data will not be erased. For example, 5, an electronic control device is used to control the engine, transmission, and other automobile parts, and the generated control data is stored in a ROM in the electronic control device. After an electronic control device is installed in a car, the car manufacturer or dealer may wish to calibrate the control data based on the characteristics of a controlled component, such as an actual engine or transmission. Therefore, the control data is usually stored in a rewritable non-volatile memory (such as an EEPROM (Electrically Erasable Programmable Programming ROM) or a flash memory (Flash ERPROM)), so that it can be overwritten. Such control information. Flash EEPROM is characterized by its internal circuit phase and its low cost. The storage area of the flash EEPROM is divided into a plurality of storage blocks, so data can be erased and / or written for each storage block in an overwrite operation. As an example, for a 64 KB flash EEPROM with two storage blocks and a storage capacity of one kilobyte (KB), each 32 KB is implemented to overwrite the f industry. However, for flash EEPR0M, when a data overwrite operation is performed, the data in the storage block cannot be read. ’1227498) in the second: Yu flash one’ and in, random access memory If you need 1-data overwrite operation takes a long time. Therefore, according to the characteristics of the controlled element (such as an engine), the implementation of the calibration is usually carried out temporarily .. After that, after the engine is stopped, the data in the flash memory is used to verify the flash eepr0m μ. Therefore, the mang i # 丄 时 / 局 局 will be the result. Each: To implement multiple calibrations for the earlier EEP meeting, it is necessary to repeat the operations described above, which are extremely time-consuming. Designed in: == the above problems, and its goal is to provide an electronic control device that can perform data recovery operations on non-volatile memory even if it is overwritten. [Summary of the invention] First, the first phase of the _, according to the scope of the patent application of the present invention provides = electronic control with-non-volatile memory and _ volatile memory volatile memory and volatile Memory can be used for control = < control data. The electronic control device includes a controller, which controls the data to implement the control data, and after the calibration is completed, the data stored in the volatile memory is embedded into the non-volatile memory. According to the present invention, the scope of the present invention is to provide the scope of the invention according to item 2 of the invention. ^ The bun control device 'where the controller stores the data in the non-volatile memory to be volatile memory at the beginning of calibration; The data stored in the volatile memory is used to calibrate the control data. According to the Chinese patent, the third aspect of the present invention provides the electronic control device of the patent scope No. 1 1227498 or No. 2 wherein the controller further identifies a bit address of the non-volatile memory to be calibrated, and At the beginning of the calibration, the volatile memory is given the same address as the non-volatile memory, and data processing is performed preferentially for the volatile memory during the calibration process. According to the invention of claim 4 of the present invention, an electronic control device according to any of claims 1 to 3 is provided, which further includes a control register for controlling data in non-volatile memory, When the controller completes the calibration, the address of the non-volatile memory and the calibrated control data are embedded in the child control register, and the address and the calibrated control embedded in the control register are used. Data to write people to non-volatile memory. According to the invention of item 5 of the scope of the patent application, the invention provides the fourth private child control device of the patent application park. Its further steps include _ an authority register for controlling the use of the control register. In the case of volatile memory, the control component sets the permission register, and clears the permission register after the writing operation is completed. According to the invention of claim 6 of the scope of the present invention, the present invention provides a special spear 丄 ... sub-control device according to any one of the claims 5, wherein the element has a plurality of early Wu, control data 镞 A, person and land ten; The non-volatile memory of each unit should have a storage capacity capable of storing the control data of the corresponding calibration unit. According to any of the 7th to 6th paragraphs of the Shenfan Patent Fanyuan, the invention provides the scope of patent application No. 1 has at least two or more two blocks, in which the non-volatile memory is written into the storage block. Writing is also performed for each memory block to control the element using another memory block. 1227498 = t π ^ Range The invention described in No. 1 of the present invention 'is stored in the volatile memory, and the control material is calibrated. When the calibration is completed, the data stored in the volatile memory is transferred to the non-volatile memory. Therefore, the volatile memory installed in the electronic control device can be used to calibrate the non-volatile memory that stores control data that controls the component. Volatile memory. In either case, calibration can be performed without using an external storage element (such as a debugger). By implementing this writing operation, calibration can be achieved while the controlled element is operating According to the invention described in the W range of the patent application, when the calibration is started, it is intended that the data in the non-volatile memory will be stored in the human volatile memory 'and the data stored in the volatile memory will be used for calibration. Control data. Therefore, you can use pre-adjusted control data as a starting point to achieve calibration. By storing standard control data in non-volatile memory, you only need to perform fine-tuning based on the characteristics of the control element to achieve effective calibration. According to the invention described in item 3 of the scope of the patent application, at the beginning of the calibration, the address of the non-volatile memory to be calibrated is identified. Then, the volatility is given. The sexual memory is the same as the non-volatile memory, and the process of 'prioritizing data processing for volatile memory is performed during the calibration process. That is, in the memory configuration map, the memory area of the volatile memory is set. Weijiao is on the memory area to be calibrated. Therefore, the electronic control device can still use an address to control the component even in the calibration operation. According to the invention described in the fourth patent scope, when After the calibration is complete, write the address of the volatile memory and the calibrated control data into the control temporary storage benefit. Then, use the address stored in the control register and the calibrated 1227498 control resource to perform a Non-volatile memory writing. The volatile memory can be reliably written to the non-volatile binary by the control register. According to the invention described in item 5 of the patent application scope, the electronic control device Has—The permission register used to control the use of the control register. When writing to volatile memory, the permission register will be set. After the operation of the permission register is completed, the permission register will be cleared. The memory tube of the control register can only be implemented during the write-write operation. Λ According to the invention described in item 6 of the patent application, the volatile memory has a memory capable of storing the corresponding pure calibration unit. Controlling the asset storage capacity ^, therefore, 'the volatile memory storage capacity can be limited to the capacity required for calibration, thereby reducing the size and cost of the electronic control device. According to the present invention, the non-volatile memory includes at least two or more storage blocks', and each write operation is performed separately for each storage block. When writing to the storage block, the component can be controlled by using another-misstored block Therefore, the control data in the non-volatile memory can be overwritten when the component is being controlled. Therefore, the calibration can be effectively achieved without restarting the controlled component or the electronic control device. [Embodiment] The following reference is made to FIG. I to FIG. 7 details a specific embodiment of the present invention. In the specific embodiment, 'as shown in FIG. 1, it is assumed that an electronic control unit: (remuneration) 10 is used to control a controlled target u (for example, a car engine).That is, after the ECU 10 is installed in the car, the control parameters 从 w and Shi 払 bei are used as control data to control each unit constituting the car. 1227498 Fast as non-volatile memory The ECU 10 includes a CPU 100 and a calibration RAM 102 as a volatile memory. The flash EEPROM 101 and an ECU 10 also include a non-illustrated Ann J. F.S.S.A. group, an A / D converter, and so on. The C P U 100 configuration is used for various programs stored in the Flash EEPROM 101, the calibration RAM 102, and the like. Quick EEPROM 101 contains information about the control instructions and control parameters used for control. The flash memory EEPROM used in this implementation has a total storage capacity of 64 kilobytes (KB). The storage area consists of 32 kb storage blocks (in the memory configuration diagram, " blocks " and " blocks " respectively.). For an overwrite operation, the implementation of -data erasure and -writer operations. For each controlled unit, "block 0" contains information related to control instructions, and "block 丨" contains data related to control parameters. In this specific embodiment, it is assumed that in the process of controlling the controlled object U, the "control instruction in block 0," may cause the control parameter in "block 1π" to be overwritten. The weight RAM 102 is used for Memory for temporarily storing predetermined data during calibration. For the calibration RAM 102, a memory capable of storing control parameters corresponding to each controlled unit should be used. The calibration RAM 102 in this embodiment has 2 The storage capacity of KB. The ECU 10 further includes an input / output interface section 120. Each part of the Ecu 10 is connected to a user interface section 12 and a controlled target U through the input / output interface section 120. The user interface portion 12 is used by a user to specify a controlled target 11 and confirm parameters. The controlled target 11 is a component such as an engine, a transmission, and other components to be controlled. The ECU 10 is self-installed on the controlled target U Each sensor in the receiver receives 11 1227498 f 'and outputs data to an actuator, etc. via the input / output interface section 120. The CPU 100 is connected to a bit decoder 11 through a bit bus. The address decoder U0 outputs a signal ^ its corresponding output terminal according to the address signal of the CPU 100. In this specific embodiment, the CPU and the address decoder 110 are used as control components. The decoder i 10 includes an initialization register ⑴. The initialization register = u 1 includes an area for storing data related to an address of an implementation calibration area, and-for storing data related to the calibration RAM 1G2. The area of the active data (active bit). In this specific embodiment, "1" will be entered in the active bit when the calibration is active. In addition, the ECU 10 includes a super-user mode register 112 as a privilege temporary benefit, which is used to control the mode (hereinafter, referred to as the super-user mode) for the flash EEPR0M 1〇1 An overwrite permission is granted. When set to the super user mode, the permission bit included in the super user mode register 丨 2 will be entered as "1". The ECU 10 further includes a flash control register U3 is used as a control register to control the data in non-volatile memory. The flash control register 113 is used in the super user mode. The flash control register 113 retains the data to be written to the flash. The address and calibrated control parameters of the flash EEPROM 101. In addition, the CPU 100, the calibration RAM 102, the flash control register 113, and the input / output interface section 120 are connected to the data bus, respectively, so that the Next, the operations performed by the ECU 10 will be explained with reference to FIGS. 2 to 7. The 12 1227498 is used to rewrite data stored in the flash EEPROM 101 into data suitable for the controlled target 11. Jobs in ECU 10 While controlling the controlled target UI based on the data stored in the flash EEPROM 10, the user can use the user interface section 12 to issue a calibration command about the controlled target 11. The command is provided through the input / output interface The part 120 and the data bus are transmitted to the CPU 100. Then, the ECU 10 enters a calibration mode, and starts the process described in FIG. 2 in this calibration mode. First, the CPU 100 determines a calibration area (S1-1) on the flash EEPROM 101 ). In that case, CPu 100 inputs π 1 '' to the activation bit of the initialization register 111 to activate the calibration RAM 102. In addition, the address of an implementation calibration area is stored in the initialization register 111. Then 'copy the data in the calibration area of the flash EEPROM to the calibration RAM 102 (S 1-2). This operation is explained with reference to a memory configuration diagram 500 shown in FIG. 4. The body configuration diagram 500 sets: a memory area 501 corresponding to the calibration RAM 102;-a memory area 5 02 corresponding to the `` block 0 '' of the flash EEPROM 101; and a corresponding memory area 502 ,, block 丨 ,, memory area 503. In this device In the embodiment, the positions 6,000 to 67FF in the memory area 503 are assumed to be a calibration area 504. Then, in step (§ 2), the data in the calibration area 504 is copied to correspond to the calibration ram The memory area of 10 2 is 50 1. Then, the calibration RAM 102 is overlapped on the calibration area (sl-3). This operation is explained with reference to the memory configuration shown in FIG. 5 and FIG. 5. In this step ’ The memory area 5101 of the calibration ram 1 02 set on the memory configuration diagram 10 matches the address set for the calibration area 504. This means that the memory 13 1227498 has the same address as the body area 501 and the calibration area 504. Then, a calibration process (si_4) is performed according to the characteristics of the controlled target π. This operation is explained with reference to the flowchart shown in FIG. 3. The user can use the user interface section 12 to issue a 2 = modification command (S2-1) for parameter data and the like for controlling the controlled target π. In that case, the CPU will perform various tasks: for example, reading or overwriting the data on the memory configuration figure 5 10. If the memory area of the overlapping calibration RAM 102 needs to be processed (when YES is selected in step (S2-2)), the processing is performed based on the data in the calibration RAM 102 (S2-3). That is, If "1" is set in the activation bit of the initialization register lu, the flash EEPR0M 101 is assigned the same address as the calibration RAM 10 (in the specific embodiment, the position is 6000 to 671? Each process performed in the memory area of 17) is also performed for the memory area 501 of the calibration RAM 102. Conversely, 'to deal with the area of the non-overlapping calibration RAM 102 (when yes, no') ) 'As usual, the processing is performed on the data in the flash EEPROM 1 01 on the memory configuration map 5 10 (S2-4). Then if there is any new data processing instruction (when '' No 'is selected in step (32)), repeat steps (S2-1) to (S2-4) to perform calibration. Conversely, if a suitable parameter value is found for the incineration control target 11, the user can use the user interface section 12 to issue a command to end the calibration. If an instruction is issued to end the calibration (when “YES” is selected in step (S2-5)), the routine will return to the flow shown in FIG. 2. Next 'is set to super user mode (S 1-5). Specifically, enter "1" in the permission bit of the super user mode register 112. In the case of 14 1227498, the control parameters stored in the calibration RAM 1 () 2 will be written into the flash. (S1_6) in the EEPROM 101. That is, as shown in the memory configuration diagram in FIG. 6, a is located in the memory area 5 (the data in M of the calibration ram on the memory layout diagram 52) will be written to the calibration The area 50 center specifically, in the super and user modes, the fast N control register 113 can be accessed on the memory map, and then stored in the calibration RAM 102. The address and data are written to the flash control register 113. In addition, the data stored in the flash control register 113 is written to the flash according to the address in the storage flash control register 113 In the address on EEPROM 101. At the same time, E (: υ⑺ continues to control the controlled target according to the data stored in memory area 502. i. When the program ends, clear the superuser mode register 丨 2 Permission bit, and exit superuser mode and return to normal mode. In addition, initialize the register 111 The setting is changed (31_7). At this time, the activation bit of the initialization register 111 is cleared, thereby generating a memory configuration diagram 530 shown in FIG. 7. That is, the memory area 501 of the calibration RAM 102 is calibrated. It is removed, and a calibration area 531 of the data written in the calibration RAM 1 02 is generated in the memory configuration diagram 530. Then, the ECU 10 uses the overwritten data in the flash EEPR0M 10 to control the control Objective 11. Subsequently, the overwriting operation of the flash EEPR0] Vi is completed. According to the foregoing specific embodiment, the following features can be obtained. In the foregoing specific embodiment, the ECU 10 includes a flash control register 113 and is calibrated. Enter the super user mode at the end. In this mode, the flash control register i ^ 3 becomes accessible on the memory map. Then, using the flash control register U 3 will be stored in the calibration RAM The data program in 102 is planned to flash 15 1227498 EEPROM 101. Therefore, even when the assistant 10 is working, the data in a specific area of flash EEPROM 101 can be erased or overwritten. Before flashing EEPROM101, the controlled target Qing's control will be interrupted. Therefore, when another calibration is performed, ECU 10 and the controlled target need to be restarted. In that case, after starting, controlled target 11: it takes a period of time to stabilize. According to the specific embodiment, the calibration task can be completed by performing the calibration while the party control target 11 is still operating. In the specific embodiment described above, the super user mode can be used during the operation of the ECU 10 The calibration is performed. Therefore, even when the calibration RAM 102 is small (for example), the calibration can be achieved politically. By using this small capacity calibration = AM 102 ′, the size of Ecu 1G can be reduced. In addition, because & trips are quite expensive, using a small quasi-RAM 102 can allow a cost reduction of £ CU 10. In the foregoing specific embodiment, the calibration RAM 102 installed in the ECU PD is used to overwrite the data in the flash EEPR0M 101. That is, 10 itself has a mechanism for overwriting the data in the flash EEPROM 丨 〇 丨. It eliminates the need to store authorization data in an external storage element (such as a debugger). This can effectively overwrite the data stored in the flash ERepROM 100. In the specific embodiment described above, at the beginning of calibration, the address of the area where the calibration is performed will be stored in the initialization register 111. This address can be used to copy the data in the shutter EEPROM 1101 to the calibration ruler suit, and set the memory area of the calibration ^ in the flash area = 504 of the right area of the flash = EPR0M 1101. 50 1 This means that the calibration RAM i 〇2 16 1227498 setting area can be set according to the calibration area. It should be understood that the foregoing specific embodiments may be modified as follows. In the foregoing specific embodiment, when the program ends, the authority bit of the super user mode register n 2 is cleared, and the super user mode is exited to return to the normal mode. At the same time, the activation bit of the initialization register 111 is cleared. Conversely, if the calibration of another controlled target 11 is continuously performed, the address of an area where a new calibration operation is performed can be set in the initialization register 11 丨, and at the same time, the activation bit of the initialization register 111 can be maintained. Is "1", so calibration can be performed continuously. In the foregoing specific embodiment, a calibration RAM 102 having a storage capacity of 2 KB is used, although it is not limited thereto. Its capacity can cover the memory area required for a single calibration. In addition, a calibration RAM 102 with larger storage capacity can be used to perform calibration on more controlled targets simultaneously. In the foregoing specific embodiment, during the operation of controlling the controlled target 1, a control instruction of "block 0," of flash EEPROM 101 is used to overwrite the control parameter of "n", although it is not limited to Therefore, this operation can be implemented in an electronic control device including a flash EEPROM 101 that needs to be overwritten. In the foregoing specific embodiment, the data in the calibration area of the flash EEPROM 101 is copied to step S1-2. Calibrate ram 102. Or, if there is no control data in the quasi area, you can skip this step. In the specific embodiment described above, the controlled target (such as a car engine) is controlled by the mind control device (ECU 10) Although it is not limited to this. The key point is that the device can include a flash EEPROM 101 and can be implemented in an electronic control device that can overwrite personal data. As detailed above, according to the present invention, even During the control operation. 17 1227498 Overwrite the data of non-volatile memory. [Simplified description of the figure] Figure 1 is a schematic diagram illustrating the overall structure of an ECU (electronic control device) according to a specific embodiment of the present invention. FIG. 2 is a flowchart for explaining a flashing EEPR0M overwrite operation; FIG. 3 is another for explaining a flashing EEPROM; FIG. 4 is an explanatory diagram of a memory configuration diagram; FIG. 5 is another explanation of a memory configuration diagram. FIG. 6 is another explanation of a memory configuration diagram. FIG. 7 is another explanation diagram of a memory configuration diagram. [Illustration of representative symbols of the diagram] 10 Electronic control unit ( (ECU) 11 Controlled target 12 User interface 100 CPU 101 Flash EEPROM 102 Calibration RAM 110 Address decoder 111 Initialization register 112 Super user mode register 113 Flash control register 120 I / O interface bits Address Bus Data Bus 1227498 (Sl-l) (Sl-2) (Sl-3) (Sl-4) (Sl-5) (Sl-6) (Sl-7) (S2-1) (S2- 2) (S2-3) (S2-4) (S2-5) 500 501 502 503 504 510 520 530 531 Determine the calibration area on the flash EEPROM Copy the data in the calibration area to the calibration RAM Overlap the calibration RAM on The calibration process above the calibration area is set in the super user mode. The flash control register is used to program the data in the calibration RAM to the flash EEPROM. Initialize the register settings. Finish the calibration process. Issue the data processing instruction to process the area of the overlapping calibration RAM. According to the data processing in the calibration RAM, complete the calibration according to the data processing in the flash EEPROM. Return to No. Memory map calibration RAM flash EEPROM (block 0) Flash EEPROM (block 1) Calibration area Memory configuration diagram Memory configuration diagram Memory configuration diagram Calibration area 19