1261337 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種溝渠電容之製作方法，由指一種利用低階 光罩(low grade mask)製作溝渠電容與記憶單元之深溝渠之方法。 【先前技術】 動恶1^1機存取記憶體(dynamic random access memory，以下簡 稱為DRAM)是由許多記憶單元(memory cell)所構成之積體電路， 同時它也是目前最主要的揮發性(volatile)記憶體之一。隨著各種電 子產品朝小型化發展之趨勢，DRAM元件的設計也必須符合高積 集度、高密度之要求，而溝渠電容DRAM元件結構即為業界所廣 泛採用之咼禮、度DRAM架構之一，其係在半導體基材中钱刻出深 溝渠並於其内製成溝渠電容，並製作相對應之金氧半導體(M〇s) 笔晶體加以電連接，因而可有效縮小記憶單元之尺寸，妥善利用 晶片空間。 請參閱第1圖至第3圖，第1圖至第3圖為習知製作溝渠電容 之剖面示意圖，而第2圖為第1圖之中沿2_2,切線之剖面示意圖。 請先參閱第1圖與第2圖，習知製作溝渠電容1〇之方法，係先在 一表面設置有一硬遮罩(hardmask)層104之矽基底1〇〇上，形成一 圖案化之光阻(圖未示），用來定義出複數個溝渠電容的位置。 接者進行圖案轉移製程，以於硬遮罩層1〇4中形成複數個定義溝 1261337 渠電容10的開口 102，再利用這些硬遮罩層1〇4内之開口 ι〇2， 於石夕基底100中侧出複數個深溝渠。然後依序於各溝渠内形成 擴散區域106、電容介電層觸、以及電容下電極11〇，完成溝渠 電谷10之製作，其中，擴散區域1〇6係用來作為溝渠電容川之 埋入電極(buried plate)。 接下來’如第3圖所示，利用蝕刻、沉積、化學機械研磨&娜)、 離子佈植等製程’依續於兩相鄰之溝渠電容ω間形成淺溝隔離 (swallow french isolation，STI)202 及各閘極 204、側壁子 206 及源 極/汲極208，最後再視產錢格之需求，選擇性進行—金屬魏 (salicide)製程，並利用複數個接觸插塞⑽福咖細未示)與其 他元件及金屬内連線相電連接。 然而 ，上述之習知技術係先利用具有陣列式之溝渠圖案的光 罩，以於光阻及硬鮮中定義出如第丨圖所示之溝渠陣列，進而 於石夕基底中_形成各深溝渠，_又需要再·—具有陣列式 STI圖案之光罩’以於兩相鄰之溝渠電額形錢溝換句話 說，t兩縣不但必有高積紐要求之x方向及γ方向之對 準考量，故增加其在㈣、顯影及似博步驟失敗之可能性而影 響良率’而且在進行淺溝隔離的製程時，擴散區域與電容下電極 亦非常容__、清洗、化學機械研鮮製程的破壞與汗染， 而影響溝渠電容的電性表現。 1261337 【發明内容】 因此本㈣之主要目的係提供—溝渠電容與記鮮元 方法。 、 根據本發狀所提供之方法，首先提供—基底，並於該基底内 j形成-栅狀之淺溝隔離以及由—硬遮罩層覆蓋之主動區域。接 耆於該基底上形成-圖案化之光阻，以定義出各溝渠結構位置。 修在去除該光阻之後’利用該硬遮罩層及該淺溝隔離作為一遮罩， 向下侧出複數個深溝渠，並於該等深溝渠中依序形成擴散區 j电们| $層。之後填人多晶♦作為電訂電極，完成溝渠電 #之製作。再去除該硬鮮層，於鱗主舰域上形成複數個電 _及其_之趣子。最該雜元壯形成毅個接觸插 基，完成DRAM之製作。 _々、、值得注意的是’由於本發明所提供之方法係以該硬遮罩層及該 等淺溝隔離作為料，所財發贿定義絲阻之光罩， 係為不需要考慮γ方向之光罩。也就是說，僅需要再利用一初 階光罩，即可定義出本發明所需之圖案。 另外’ P遺著半導體元件的整合趨勢，許多晶片往往會同時兼具 f個不同的種類設計。故根據本發明所提供之方法，更易於系統 日日片上進仃曝光製程，且更可減低在高密度排列的光罩圖案進行 曝光製程時’ w雜移失敗的可能性。 1261337 為讓本發明之上述目的、特徵、和優點能更明顯易懂，後文特 舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下 之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加 以限制者。 【實施方式】 睛參閱第4圖至第π圖，第4圖至第13圖係顯示本發明之製 φ 作溝渠電容之第一較佳實施例的示意圖。請先參閱第4圖及第5 圖，第5圖係第4圖中沿5-5,切線之剖面示意圖。首先提供一基 底300 ’例如一 p型摻雜之半導體基底(semic_u伽：、 石夕日日圓(wafer)或石夕覆絕緣(smcon on insuiat〇r，s〇I)基底，其上包含 有一柵狀之淺溝隔離(shau〇w如滅is—，STI)3〇2，以及複數個 被淺溝隔離302所定義並隔離之主動區域3〇3。其中，每一個主動 區域303表面均分別覆蓋有一由氮矽化合物等材料所構成之硬遮 春罩層304，而且各主動區域303係沿X方向與γ方向形成一緊密 之陣列排列。此外，各主動區域303均係為一長條型區域，且其 較長邊係沿X方向設置。 請參閱第6圖及第7圖，第7圖係第6圖中沿7_7切線之剖面 示意圖。接著，利用光阻塗佈、曝光、顯影、固化(curing)等製程， 於基底300表面形成複數個彼此平行之長條狀光阻4〇〇，分別覆蓋 住部分之淺溝隔離3〇2以及各硬遮罩層3〇4之部分區域，以於任 兩相鄰之光阻400間之各主動區域303中分別定義出一深溝渠之 1261337 位置。 值得注意岐’由練顧擇比不同，故在本触實施例中， 含石夕氧化合物組成之淺溝隔離她以及由氮魏合物所構成之硬 遮罩層304 ’均係用來作為後續之钱職程之侧遮罩。因此本發 明之溝渠_可由—不需要具有高積缝要求之χ方向及Y額 之對準考量的鮮所定義出來。換句話說，本發要利用一乂 # 方向對準考里之初階光罩〇owgrademask) ’形成複數條平行且長 邊係/。Y方向„又置之長條狀光阻4〇〇，並配合柵狀之淺溝隔離搬 以及壬陣列排列之各硬遮罩層3〇4，即可利用主動區域對深溝渠自 對準(active t0 trench self_align)的方式來定義出本發明所需之各溝 渠的位置。 隨後如第7圖所示，利用光阻4〇〇及淺溝隔離3〇2作為餘刻遮 罩來進行-侧製程，用以去除未被光阻彻覆蓋之各硬遮罩層 • 304的部分。 在去除光阻400之後，請參閱第8圖及第9圖，第9圖係為第 8圖中沿9_9切線之剖面示意圖。如第8圖與第9圖所示，接著利 用淺溝隔離302及剩下之硬遮罩層304作為韻刻遮罩來蝕刻基底 300 ’以於各主動區域303中分別形成一深溝渠5〇2。 如第10圖所示，隨後利用砷矽玻璃(arsenic silicate glass，ASG) 1261337 擴散技術、離子佈植或斜角離子佈植等摻雜製程，於溝渠5〇2之 表面側壁及底部之基底3〇〇進行高濃度之n+摻雜，形成一擴散區 域504。之後，再利用沉積、熱氧化等製程，於各溝渠502之侧壁 及底部表面分別形成一電容介電層(capacit〇r dielectric layer)5〇6， 例如一氧化餐氮化矽_氧化石夕(〇N〇)介電層，但不限於此。然後於 深溝渠502内填滿一多晶矽層5〇3,再利用回蝕刻或化學機械研磨 (CMP)等製程來去除部份之多晶石夕層5〇3，並使剩餘之多晶石夕層 _ 503略低於硬遮罩層3〇4及淺溝隔離302，以於各深溝渠502内分 別形成一電谷下電極(capacitor bottom electrode)508，完成溝渠電容 之製作。 接著本發明可再視產品設計、製程規格與電性表現等之需求， 進行水平式或垂直型金氧半導體(M0S)電晶體之製程，以形成相對 應之MOS電晶體及字元線(word line)而與各溝渠電容加以電連 _ 接’進而製備所需之DRAM甚至是單電晶體靜態隨機存取記憶體 (l_Transistor Static Random Access Memory，1T-SRAM)的記憶單元 (memory cen)。例如在去除硬遮罩層3〇4之後，再進行標準之邏輯 製程，以熱氧化或沉積等方式於暴露出的基底3〇〇表面及電容下 電極508表面形成一閘極介電層70〇，如第n圖所示。 請參閱第12圖，於閘極介電層700上形成一多晶矽層(未顯 示），並以黃光暨蝕刻製程(PEP)將此多晶矽層定義出閘極結構 512然後利用閘極結構512作為遮罩，進行一輕摻雜汲極⑹2製 1261337 程。接下來進行侧壁子(spacer)803之製作，並利用閘極結構5i2、 及侧壁子803作為遮罩，再進行一重摻雜源極/汲極8〇4離子佈植 製程。之後如第13圖所示，利用一自行對準金屬矽化物阻擋層光 罩（salicide-blocked，SAB mask)或擴散光罩(implant mask)，進行一 自行對準金屬矽化物製程(salidde)，以於閘極結構512與源極/汲 極804表面上形成金屬矽化物層812、814。且此自行對準金屬矽 化物阻擋層光罩或擴散光罩與第6圖中用以對光阻4〇〇曝光之光 _ 罩可為_之遮罩。至此，完成單電晶體雜隨機存取記憶 (IT SRAM)之溝‘式電谷$憶單元之製程。最後再沉積一層間介 電層(ILD)808 ’並形成位元線插基806，進而將源極8〇4與其它電 . 路相電連接，純12 ®和第13圖_露之步驟為具有通常知識 者所熟知，故在此並不多加贅述。 值得注意的是，如前所述，本發明所提供之方法，不僅適用於 製作動態隨機存取記憶體之溝渠電容，亦用以製作單電晶體靜態 存取記憶體(1T_SRAM)之溝渠電容結構。接下來，請參閱第14圖 至第18目$ 14圖至帛18目為本發明之製作溝渠電容之第二車交 佳實施例的示意圖。本發明之第二實施例與第4圖至第13圖所示 之第-實施例之主要不同之處係在於第9圖及其後之溝渠電容的 結構，以使其可適用於雙電晶體雙電容記憶 的製程中。 為方便說明，以下敘述僅針對第9圖之後的製程詳加說明，而 11 1261337 其他元件製程步驟皆相同於第4圖至第9圖所示之第一實施例， 故不多加贅述。如第14圖所示，在去除光阻4〇〇之後，利用淺溝 隔離322及剩下之硬遮罩層3〇4作為蝕刻遮罩來蝕刻基底3〇〇，以 於一對相鄰之主動區域3〇3中分別形成一深溝渠522及523。請注 意，在第二較佳實施例中，本發明係調整此蝕刻製程之蝕刻參數， 以同時侧部分之淺溝隔離322及基底300，使得侧完深溝渠 522、523呀，淺溝隔離322亦被蝕刻至約略與基底3〇〇表面相同 南度之位置。 接下來請參閱第15圖，_种玻璃(ASG)擴散技術、離子佈 植或斜鱗子佈植等摻雜製程，於深溝渠522、523之表面侧壁及 底部之基底3G0進行高濃度之N+摻雜，形成一擴散區域524。其 後，再利用沉積、熱氧化等製程，於硬遮罩層綱及深溝渠522 之侧壁及底部形成-電容介電層526，例如氧切_氮煤氧化石夕 (ΟΝΟ)等之介電層。之後於深溝渠切内填滿一多晶石夕層別，再 利用回钱刻或化學機械研磨(CMp)等製程來去除部份之多晶石夕層 52〇，並使剩餘之多晶梦層52()仍覆蓋住淺溝隔離切，以於深溝 渠522、523内形成—相連接之電容下_ 528，而且沿γ方向上 設置之各深溝渠之1容下電極均係為—相連接之結構。在去除硬 =杨綱之後，接著再進行標準之邏輯製程，以熱氧化或沉積 暴路出的基底300表面及電容下電極528表面形成一閘 極介電層700，如第16圖所示。 12 1261337 清茶閱第17圖，於閘極氧化層7〇〇上形成一多晶石夕層(未顯 不）’亚以黃光暨侧製程將此多晶石夕層定義此閘極結構525及 527以閘極結構525及527為遮罩，進行一輕摻雜汲極8〇2製程。 接下來進行側壁子8〇3之製作，並利用閘極結構525 、527及側壁 子803作為遮罩’進行一重摻雜祕/汲極804離子佈植製程，且 該離子佈植製程亦施加於覆蓋住淺溝隔離322之相連接的電容下 電極528表面。1261337 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a trench capacitor, and a method for fabricating a trench capacitor and a deep trench of a memory cell using a low grade mask. [Prior Art] Dynamic random access memory (hereinafter referred to as DRAM) is an integrated circuit composed of many memory cells, and it is also the most important volatility at present. One of the (volatile) memories. With the trend of miniaturization of various electronic products, the design of DRAM components must meet the requirements of high integration and high density, and the structure of trench capacitor DRAM components is one of the widely used DRAM architectures in the industry. The semiconductor substrate is engraved with a deep trench and a trench capacitor is formed therein, and a corresponding metal oxide semiconductor (M〇s) pen crystal is electrically connected, thereby effectively reducing the size of the memory cell. Make good use of the wafer space. Please refer to Fig. 1 to Fig. 3, and Fig. 1 to Fig. 3 are schematic cross-sectional views of a conventional trench capacitor, and Fig. 2 is a cross-sectional view taken along line 2-2 and tangent in Fig. 1. Please refer to FIG. 1 and FIG. 2 first. It is a method for fabricating a trench capacitor 1 ,. First, a hard mask layer 104 is disposed on a surface of a substrate 1 to form a patterned light. Resistance (not shown) is used to define the location of a plurality of trench capacitors. The pattern transfer process is performed to form a plurality of openings 102 defining the trench capacitors 1261337 in the hard mask layer 1〇4, and then using the openings ι〇2 in the hard mask layers 1〇4, in Shi Xi A plurality of deep trenches are formed in the side of the substrate 100. Then, a diffusion region 106, a capacitive dielectric layer contact, and a capacitor lower electrode 11〇 are formed in each trench to complete the fabrication of the trench electric valley 10, wherein the diffusion region 1〇6 is used as a trench capacitor. Electrode (buried plate). Next, as shown in Figure 3, using etching, deposition, chemical mechanical polishing, and ion implantation, the process of forming a shallow trench isolation between two adjacent trench capacitors ω (swallow french isolation, STI) 202 and each of the gate 204, the side wall 206 and the source/drain 208, and finally, depending on the demand of the production grid, selectively perform a metal salicide process and utilize a plurality of contact plugs (10) Not shown) is electrically connected to other components and metal interconnects. However, the above-mentioned conventional technique first utilizes a photomask having an array of trench patterns to define a trench array as shown in the first figure in the photoresist and the hard fresh, and further forms a deep depth in the base of the stone Ditch, _requires again - a mask with an array of STI patterns' for the two adjacent ditches, the electric form of the money groove, in other words, the two counties must not only have the x-direction and the gamma-direction required by the high-capacity Alignment considerations, so increase the probability of failure in (4), development and similar steps, and affect the yield'. In the process of shallow trench isolation, the diffusion area and the capacitor lower electrode are also very __, cleaning, chemical machinery The destruction and sweating of the fresh-process process affects the electrical performance of the trench capacitor. 1261337 [Summary content] Therefore, the main purpose of this (4) is to provide a method for ditches and capacitors. According to the method of the present invention, a substrate is first provided, and a shallow trench isolation and a active region covered by a hard mask layer are formed in the substrate. A patterned photoresist is formed on the substrate to define the location of each trench structure. After removing the photoresist, the hard mask layer and the shallow trench isolation are used as a mask, and a plurality of deep trenches are formed on the lower side, and diffusion regions are sequentially formed in the deep trenches. Floor. After that, fill in the polycrystalline ♦ as the electric electrode, and complete the production of the ditch. Then, the hard fresh layer is removed, and a plurality of electric _ and its _ _ _ _ _ _ _ _ _ The most complicated ones form a contact plug and complete the production of DRAM. _々,, it is worth noting that 'the method provided by the present invention is based on the hard mask layer and the shallow trenches as the material, and the bribe is defined as the ray mask. Photomask. That is to say, it is only necessary to reuse an initial mask to define the pattern required by the present invention. In addition, there is a tendency to integrate semiconductor components, and many wafers tend to have f different types of designs at the same time. Therefore, according to the method provided by the present invention, it is easier to carry out the exposure process on the system, and it is possible to reduce the possibility of failure of the w-shift during the exposure process of the high-density arrangement of the mask pattern. The above described objects, features, and advantages of the invention will be apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Referring to Figs. 4 to π, Figs. 4 to 13 are views showing a first preferred embodiment of the φ trench capacitor of the present invention. Please refer to Figure 4 and Figure 5 first. Figure 5 is a schematic cross-sectional view along line 5-5 in Figure 4. First, a substrate 300 is provided, for example, a p-type doped semiconductor substrate (semic_u gamma:, a stone swain or a smcon on insuiat 〇r) substrate having a grid thereon The shallow trench isolation (shau〇w such as is-STI) 3〇2, and a plurality of active regions 3〇3 defined and isolated by the shallow trench isolation 302. wherein each active region 303 is covered with a surface A hard mask layer 304 composed of a material such as a nitrogen ruthenium compound, and each active region 303 is arranged in a tight array along the X direction and the γ direction. Further, each active region 303 is a strip-shaped region. And the longer side is set along the X direction. Please refer to Fig. 6 and Fig. 7, Fig. 7 is a schematic cross-sectional view taken along line 7_7 in Fig. 6. Then, using photoresist coating, exposure, development, curing ( a process such as curing, forming a plurality of strip-shaped photoresists 4 平行 parallel to each other on the surface of the substrate 300, respectively covering a portion of the shallow trench isolation 3 〇 2 and portions of each of the hard mask layers 3 〇 4 Any of the active regions 303 between the two adjacent photoresists 400 are respectively determined Out of a deep ditches at 1261337. It is worth noting that the 'different ratios are different from each other. Therefore, in the present embodiment, the shallow ditch containing the compound of the cerium oxide is isolated from her and the hard mask composed of nitrogen and Wei compound. The layer 304' is used as a side mask for the subsequent money service. Therefore, the trench of the present invention can be defined by the need for the alignment of the χ direction and the Y amount with high seam requirements. In other words, this issue should use a 乂# direction to align with the initial mask of the test 〇owgrademask) to form a plurality of parallel and long-edge systems. In the Y direction, the strip-shaped photoresist is placed 4 〇〇, and the hard trenches are arranged in the shallow trenches of the grid and the hard mask layers 3〇4 arranged in the array of the crucibles, so that the active regions can be self-aligned to the deep trenches ( Active t0 trench self_align) is used to define the position of each trench required by the present invention. Subsequently, as shown in Fig. 7, the photoresist 4 is used and the shallow trench isolation 3〇2 is used as a residual mask for the side The process is used to remove the portions of each of the hard mask layers that are not covered by the light. • After removing the photoresist 400, please refer to Fig. 8 and Fig. 9, and Fig. 9 is the edge of Fig. 8 along 9_9. A cross-sectional view of the tangent line. As shown in FIGS. 8 and 9, the shallow trench isolation 302 and the remaining hard mask layer 304 are used as a mask to etch the substrate 300' to form the active regions 303, respectively. A deep trench 5〇2. As shown in Figure 10, the arsenic silicate glass (ASG) 1261337 diffusion technique, ion implantation or oblique ion implantation is used in the doping process. The surface sidewalls and the bottom substrate 3 are doped with a high concentration of n+ to form a diffusion region 504. Then, using a deposition, thermal oxidation process, a capacitor dielectric layer 5〇6 is formed on the sidewalls and the bottom surface of each trench 502, for example, a niobium oxide niobium oxide_oxidized oxide (〇N〇) dielectric layer, but not limited to this. Then fill a deep germanium layer 502 with a polysilicon layer 5〇3, and then use etchback or chemical mechanical polishing (CMP) to remove some of the polycrystalline stone.夕5〇3, and the remaining polycrystalline layer _ 503 is slightly lower than the hard mask layer 3〇4 and the shallow trench isolation 302, so as to form a lower valley electrode in each deep trench 502 (capacitor bottom) Electrode) 508, the fabrication of the trench capacitor is completed. The invention can then perform the process of horizontal or vertical metal oxide semiconductor (MOS) transistor to meet the requirements of product design, process specifications and electrical performance. The MOS transistor and the word line are electrically connected to the drain capacitors to form the required DRAM or even a single transistor static random access memory (1_Sistor Random Random Access Memory, 1T-SRAM). Memory unit (memory cen). For example in After removing the hard mask layer 3〇4, a standard logic process is performed to form a gate dielectric layer 70〇 on the surface of the exposed substrate 3 and the surface of the capacitor lower electrode 508 by thermal oxidation or deposition, such as As shown in Fig. 12, referring to Fig. 12, a polysilicon layer (not shown) is formed on the gate dielectric layer 700, and the polysilicon layer is defined as a gate structure 512 by a yellow light etch process (PEP). Using the gate structure 512 as a mask, a lightly doped drain (6) 2 system 1261337 is performed. Next, the spacer 803 is fabricated, and the gate structure 5i2 and the sidewall spacer 803 are used as masks, and a heavily doped source/drain 8 〇 4 ion implantation process is performed. Then, as shown in FIG. 13, a self-aligned metal silicide process (salidde) is performed by using a self-aligned salicide-blocked (SAB mask) or an diffusion mask. Metal telluride layers 812, 814 are formed on the surface of gate structure 512 and source/drain 804. Moreover, the self-aligned metal halide barrier mask or diffuser can be used as a mask for exposing the photoresist to the photoresist 4 in FIG. At this point, the process of the single-crystal random access memory (IT SRAM) trench is completed. Finally, an interlayer dielectric layer (ILD) 808' is deposited and a bit line interposer 806 is formed, thereby electrically connecting the source 8〇4 with other electric circuits. The steps of pure 12® and 13th _expo are It is well known to those of ordinary skill, so it is not mentioned here. It should be noted that, as described above, the method provided by the present invention is not only applicable to the trench capacitor of the dynamic random access memory, but also to the trench capacitance structure of the single transistor static access memory (1T_SRAM). . Next, please refer to Fig. 14 to Fig. 18, Fig. 14 to Fig. 18, which are schematic diagrams showing a second embodiment of the fabrication of the trench capacitor of the present invention. The main difference between the second embodiment of the present invention and the first embodiment shown in FIGS. 4 to 13 is the structure of the trench capacitor of FIG. 9 and thereafter, so that it can be applied to a double transistor. In the process of double capacitance memory. For convenience of explanation, the following description is only for the detailed description of the process after the ninth figure, and the 11 1261337 other component process steps are the same as the first embodiment shown in FIGS. 4 to 9, and therefore will not be further described. As shown in FIG. 14, after removing the photoresist 4, the shallow trench isolation 322 and the remaining hard mask layer 3〇4 are used as an etch mask to etch the substrate 3〇〇 to be adjacent to each other. A deep trench 522 and 523 are formed in the active region 3〇3, respectively. Please note that in the second preferred embodiment, the present invention adjusts the etching parameters of the etching process to simultaneously isolate the shallow trench isolation 322 and the substrate 300, such that the side deep trenches 522, 523, shallow trench isolation 322 It is also etched to a position approximately the same as the surface of the substrate 3〇〇. Next, please refer to Figure 15, _ kinds of glass (ASG) diffusion technology, ion implantation or oblique scale planting and other doping processes, on the surface of the deep trenches 522, 523 and the bottom of the base 3G0 for high concentration N+ doping forms a diffusion region 524. Thereafter, a process such as deposition and thermal oxidation is used to form a capacitor dielectric layer 526 on the sidewalls and bottom of the hard mask layer and the deep trench 522, for example, oxygen cut_nitrogen coal oxide oxide (夕) Electrical layer. Then fill a polycrystalline stone layer in the deep trench cut, and then use the process of returning money or chemical mechanical polishing (CMp) to remove part of the polycrystalline layer 52, and make the remaining polycrystalline dream The layer 52() still covers the shallow trench isolation cut to form a connected capacitor _ 528 in the deep trenches 522, 523, and the 1st drain electrode of each deep trench disposed along the γ direction is a phase The structure of the connection. After removing the hard = Yang Gang, a standard logic process is then performed to form a gate dielectric layer 700 on the surface of the substrate 300 and the surface of the capacitor lower electrode 528 which are thermally oxidized or deposited, as shown in FIG. 12 1261337 Qingcha read Figure 17, forming a polycrystalline layer on the 7 〇〇 gate oxide layer (not shown) 'Asian yellow light and side process to define this gate structure 525 And 527, with the gate structures 525 and 527 as masks, a lightly doped drain 8 〇 2 process. Next, the fabrication of the sidewall spacers 8〇3 is performed, and the gate structure 525, 527 and the sidewall spacers 803 are used as masks to perform a heavily doped secret/dip 804 ion implantation process, and the ion implantation process is also applied to The surface of the capacitor lower electrode 528 connected to the shallow trench isolation 322 is covered.
Ik後如第18圖所示，進行一自行對準金屬石夕化物製程 (.cide)以於閘極結構525、527、源極級極綱與淺溝隔離您 之口卩刀電谷下電極528表面，分別形成金屬矽化物層822、824、 826、828。至此，完成雙電晶體雙電容記憶胞之製程。最後再沉 積=層間介電層(ILD)808，並形成位元線插塞8〇6，將源極8〇4與 其匕電路相電連接，而第17圖和帛18圖所揭露之步驟為具有通 常知識者職知’故在此亦衫加贅述。 、相車乂於驾知技術，本發明之深溝渠圖案僅需要利用一 X方向對 準考量之初階光罩，形成複數條平行且長邊係沿γ方向設置之長 條狀光阻，並配合柵狀之淺溝隔離以及呈陣列排列之各硬遮罩 P可彻主動區域對深溝渠自鮮⑽化論。她self_align) 中•式來定義出本發明所需之各深溝渠的位置。不同於習知技術 而要具挪列式之溝渠難的光罩巾定義出溝渠陣列；然後 又需要再糊另-具有陣辦STI圖案之光罩，以於形成淺溝隔 13 1261337 離本發明所提供之辦法可避免使用具有高積集度要求之χ方向 及Υ方向之對準考量之兩次光罩，且可避免增加兩次光罩在曝光 及顯影之步驟失敗之可能性，進而簡化製程並提高製程良率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖為習知製作溝渠電容之剖面示意圖。 第4圖至第13圖係顯不本發明之製作溝渠電容之第一較佳實施例 的示意圖。 第I4圖至« 圖為本發明之製作溝渠電容之第二較佳實施例的 示意圖。 14 1261337After Ik, as shown in Figure 18, a self-aligned metallization process (.cide) is performed to isolate the gate electrode of the valley electrode 525, 527, the source-level pole and the shallow trench. On the surface of 528, metal telluride layers 822, 824, 826, and 828 are formed, respectively. So far, the process of double-crystal dual-capacitor memory cell is completed. Finally, the interlayer dielectric layer (ILD) 808 is deposited, and the bit line plug 8〇6 is formed, and the source 8〇4 is electrically connected to the germanium circuit, and the steps disclosed in FIGS. 17 and 18 are It has the knowledge of the general knowledge, so it is also mentioned here. The deep trench pattern of the present invention only needs to utilize an initial mask of an X-direction alignment to form a plurality of strip-shaped photoresists which are parallel and have long sides arranged along the γ direction, and The shallow trench isolation and the array of hard masks P can be used to form a deep trench (10). Her self_align) formula defines the locations of the deep trenches required by the present invention. Different from the conventional technology, it is necessary to define a ditch array with a masked towel having a misplaced ditch; then it is necessary to further paste a photomask having an STI pattern to form a shallow trench 13 13261337. The method provided avoids the use of two masks with high integration requirements in the direction of the χ and Υ directions, and avoids the possibility of two mask failures in the exposure and development steps, thereby simplifying Process and increase process yield. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simple description of the drawings] Fig. 1 to Fig. 3 are schematic cross-sectional views showing the fabrication of the trench capacitors. 4 to 13 are schematic views showing a first preferred embodiment of the fabrication of the trench capacitor of the present invention. Figures I4 through « are schematic views of a second preferred embodiment of the fabrication of the trench capacitor of the present invention. 14 1261337
【主要元件符號說明】 100 矽基底 10 溝渠電容 102 開口 104 硬遮罩層 106 擴散區域 108 電容介電層 110 電容下電極 204 閘極 206 側壁子 208 源極/沒極 202 淺溝隔離 300 矽基底 302 淺溝隔離 303 主動區域 304 硬遮罩層 400 光阻 502 深溝渠電容 503 多晶矽層 504 擴散區域 506 電容介電層 508 電容下電極 700 閘極氧化層 512 閉極 802 輕摻雜源極/没極 803 側壁子 804 重掺雜源極/汲極 806 接觸插塞 808 層間介電層 812、 814金屬矽化層 522、 523深溝渠電容 322 淺溝隔離 520 多晶矽層 524 擴散區域 526 電容介電層 528 電容下電極 525、 527閘極 822、 824、826、828金屬矽化層 15[Main component symbol description] 100 矽 substrate 10 trench capacitor 102 opening 104 hard mask layer 106 diffusion region 108 capacitor dielectric layer 110 capacitor lower electrode 204 gate 206 sidewall 208 source/nopole 202 shallow trench isolation 300 矽 substrate 302 shallow trench isolation 303 active region 304 hard mask layer 400 photoresist 502 deep trench capacitor 503 polysilicon layer 504 diffusion region 506 capacitor dielectric layer 508 capacitor lower electrode 700 gate oxide layer 512 closed pole 802 lightly doped source / no Polar 803 sidewall spacer 804 heavily doped source/drain 806 contact plug 808 interlayer dielectric layer 812, 814 metal germanium layer 522, 523 deep trench capacitor 322 shallow trench isolation 520 polysilicon layer 524 diffusion region 526 capacitor dielectric layer 528 Capacitor lower electrode 525, 527 gate 822, 824, 826, 828 metal deuteration layer 15