TWI258828B - Multi-bump semiconductor carrier structure and its production method - Google Patents

Abstract

This invention provides a multi-bump semiconductor carrier structure and its production method, in which multiple etching/deep-control forming is utilized on a metal plate containing a 1st surface and a 2nd surface to form a plurality of notches on the 1st surface and form a plurality of bump arrangements on the 2nd surface, and install a partition within the metal plate and adjacent to the bumps. The partition is exposed within each notch, such that by means of different partition material, every bump has conductivity/non-conductivity. Thus, the present invention has characteristics of the pre-formed conductive bump and excellent thermal dissipation, and utilizes preparation of the partition and the supporting structure such that the layout of chip becomes more diversified; and the pre-formed conductive bump can reduce the production costs and the number of steps.

Description

1258828

V. INSTRUCTIONS (1) • [Technical field to which the invention belongs] Multi-bump type semiconductor carrier structure of body plate type and manufacturing method thereof [Prior Art] According to advances in electronic technology, electric hand products are more user-friendly The function is good, and it is designed to be light, thin, short and small. Currently, in the semiconductor 'four-way' chip carrier, the chip carrier is a commonly used component. However, the wafer carrier is mainly composed of a plurality of patterned wiring layers and a plurality of dielectric "family" and the wafer carrier has the advantages of fine wiring and compact assembly, so that it becomes a wafer structure. One of the most commonly used carrier types. Green trash: In the chip package structure, the wafer is mainly connected by flip chip bonding or bonding: the pad is electrically connected to a substrate, and the surface of the substrate has multiple ports (B〇ndlnS Pad) for respectively correspondingly connecting. Conductive bump layer: the structure bond 5 is, for example, a copper pad which is patterned by the outermost layer, and the trace of the patterned trace layer of the outer layer is more protected by an f-way protection layer. The protective layer is, for example, a fresh cover, Sol^(Solder Mask). However, the two-stage accumulation of the joint 塾3 in the hood process causes the wafer to be sealed; the production is complicated, resulting in a decrease in yield and an excessively high manufacturing cost: In view of the above, the present invention is directed to the above problems. Multi-convex

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i, issued W description (2) J-type semiconductor plant structure and its manufacturing methods, to the problem of packaging technology.乂 effectively solving the above-mentioned conventional composite panel, the composite panel surface and a second surface are provided with a plurality of bump arrangement spacers, and the spacers are exposed to provide a conductive structure for each of the bumps, The composite conductive plate is used by using the etching. The 'system is provided, using spacers, so it can be applied, it is provided, which makes a crystal make the wafer good, so that the manufacturing cost is provided by the metal-loaded process, making the bump type The semiconductor is formed by the first surface of the plurality of metal layers and is formed in the in-situ/non-conductivity of the composite plate in each of the grooves, and a multi-bump type semiconductor engraving method is used to form a metal semi-bump and heat dissipation is good. The hairboard structure and the conductor carrier board represent the existing crystal structure and the structure of the wafer and the wafer board structure and the metal carrier board pre-issue board structure and the packaging process ^ The present invention is the main purpose of the manufacturing method 'The other method of manufacturing the film is made more versatile, and the manufacturing method is more diversified. The manufacturing method is on the carrier board, and the conductive bumps are made clear. A multi-bump and support structure, various semiconductors, a multi-bump piece, a heat dissipation path and a step of directly installing a multi-bump plate to reduce the pre-conduction cost and the step carrier board. And having a plurality of grooved junction formed within and adjacent to the 'production and by that between the semiconductor package carrier. The semiconductor is loaded into a finished fabric and replaced by a gold-based semiconductor-loaded bump. The structure includes a first table and the second surface of the bump is provided with a spacer material

Page 6 1258828 V. Description of the Invention (3) • The present invention provides a metalized photoresist layer and a curtain to the metal plate groove, and then the r metal plate is placed on the surface of the spacer to form a first Layer, the surface of the second light 0 is I-insected as the bottom of the joint, by easily understanding the effect of the multi-bump plate, in a first-type semiconductor, the metal plate photoresist layer, engraved or deep-controlled first patterning The photoresist surface and the pattern of each metal layer are resisted by the first or deep control wafer or the specific one, and the three photoresists are formed in the gold photoresist layer to form a technical concave carrier plate and the following table. Forming, layering, and forming a mask in the first layer and the first groove, forming a circuit board attached to the surface, and forming a pattern to form a light blocking a surface and a gold-to-metal wiring layer The package forms a first layer of photoresist, a spacer, a patterned layer of the plate, and a step of the gold and the plurality of steps. The first picture is a cover-concave in the lower surface of the lower surface of the photoresist. figure DETAILED DESCRIPTION OF THE INVENTION When more features and achievements are achieved [Embodiment] The present invention is a multi-bump semiconductor carrier structure having many types of semiconductor carrier structures, and first introduced a three-layer multi-bump semiconductor The carrier structure is as shown in the first figure. The semiconductor carrier is a composite board 1. The composite board is composed of a spacer 4 and a plurality of metal layers 7. The composite board has a first surface and a second surface. The surface is formed with a plurality of grooves 2 on the first surface, and the second surface is provided with a plurality of bumps 3 arranged, and spacers 4 are disposed in the composite plate 1 and adjacent to the bumps 3, and the spacers 4 are packed at each moment. In the groove 2, each of the bumps 3 is electrically conductive/non-conductive by the material of the spacers 4. In addition, in

1258828 V. INSTRUCTIONS (4) First. Road: The surface and the surface of each bump 3 can be subjected to a surface treatment. The surface treatment is selected from the group consisting of electroless plating or electroplating. It is reasonable to be on the first surface of the composite panel 1 and located in the three layers of the spacer mask 6, thus completing the simple explanation of the structure of the + + V body carrier. f The second type is a multi-layer multi-bump type semiconductor carrier structure. If not, the multi-layer semiconductor carrier is substantially the same as the three-layer semiconductor carrier structure, such as forming a plurality of body carriers on the first surface.:: 1 (There are plexiforms on the upper block 3, wherein the difference lies in the complex = 2 or ϋ / structure'. This multi-layer composite plate is made up of multiple times. The complex metal layer 7 and the spacer 4 are alternately stacked. There is another type of embossed multi-bump semiconductor carrier structure. Please refer to the third figure. This type is in the first table = ^ = or deep-controlled molding, which will be a complex metal layer. 7 and spacer 4 are interlaced in the second figure at the two ends of the first surface, so the setting of multi-layer metal sound can be changed according to the needs of the product. However, in the production of multi-layer multi-bumps, the process, the structure and the process are all three-layered. The manufacturing process of the semiconductor carrier structure is i. The fabrication process is based on the three-layer semiconductor carrier structure. The second (:) super-graph to the fourth (4) shows the '(four) board structure package, including - Jin Hao The metal plate 1 has a first surface 12, a second surface 14, a 2 and a second surface 14 Each of the upper-first patterned photoresists is provided with a first photoresist layer 18', and the first patterned photoresist is used as a mask to etch the metal plate 10 to form a plurality of first recesses. 2〇, this surname is step by step

Page 8 1258828 V. Description of the invention (5) After the process is completed, the resist layer 18 is removed and then selectively etched or the first pattern is patterned after the etching is completed. ) shown in the picture. Referring to the first surface 12 of the fourth (e) to fourth (h) and each of the first recesses 2, the photoresist layer 16 and the first photo material 22 are formed in a single manner. Or the combination then removes the sub-layer 2 4, and uses a wall for setting a board 10, transferring the residual or spacer 2 2 dew. Please refer to a metal layer 24 contact slots 3 4 surface 14 and solder mask 2 The surface of the resist layer 3 8 f is 14 in. The second pattern bumps 40 and each of the blocks are selected from the group consisting of electroless ore, tin alloy, conductive material, and special matching 'and are disposed on the spacer 2 2 on the metal plate 10 first. The surface 12 is formed with a plurality of second recesses 26, and is removed in the second metal layer 28 as a conduction and then deep-controlled forming of the surface portion of the spacer 22, as shown in the third (h) diagram. Show. A solder mask layer 32 is further disposed on the fourth (i) to fourth (!) diagrams, and this is used as an electrical contact to form a second pattern on the layer 32: A photoresist layer 36 is etched by the mask to make the second surface 14 form the photoresist layer 36 and the second photoresist layer 38 a contact groove 34 for metal surface treatment process wiring or soldering, and plating or One of the electroplating electroplating silver, electric gold and no electric key is shown, in the metal spacer 2 2, the electrical material plate 10 is separated by one of the first metal layer 24, the spacer 22 and the first gold Each of the second recessed metal layers 2 4 and a metal layer 24 is formed into a groove 20 of the groove 26 and the metal is imaged so that the second surface of the plurality of metal plates 10 is disposed in the spacer 22 and the solder mask layer 32. The photoresist layer 36 and a first, opposite plurality of bumps 40 of the metal plate 10 are removed. Finally, in each way, a conductive layer 42 is disposed, such as electroless tin, nickel immersion gold, and the like.

1258828 V. Invention Description (6) It is a surface treatment, such as a ~~-^ In addition to the above-mentioned carrier board Du Erzhi = f bump type semiconductor carrier structure. r^VlZAm^ spacer 22 is a special electrical property. 4U is electrically conductive, if

Great conductivity. The convex portion, corresponding to the bump 40, has a special feature so that each line has a metal layer 28 to be connected to each layer, and the structure is very important. ...therefore the difference of the spacers 22 is the same in the carrier plate: two and a half 2 = the semiconductor carrier can be applied to the wafer structure, the first show, the implementation of the sample - see the fifth figure on the 24 The five-ply piece 4 is disposed on the solder mask layer 32 or the first metal layer of the metal plate 10, and the soldering layer 14 is used to relocate the wafer 44 and the conductive layer 42 located in the contact groove 34, where Each of the bumps 4 can be made to have a different function by providing different spacers 22, and a protective layer 4 6 is disposed on the solder mask layer 3 2 . The protective layer 46 is made of epoxy resin (epoxy res i η ) to provide mechanical protection against external damage. Following the second embodiment, as shown in the sixth and seventh figures, the embodiment is a multi-layer patterned carrier, which is used multiple times on a surface 12 or an area. The first metal layer 24 or the second metal layer ^8' is disposed and the multi-layered pattern is used to complete the multi-layer pattern "case carrier structure, so the process only repeats the foregoing steps multiple times, so no longer Repeatedly described, the multi-layer patterned carrier is applied to the wafer structure. Similarly, the wafer 44 is placed on the solder mask layer 32 or the metal layer, and the wafer 44 and the conductive layer 42 are electrically connected by wire bonding. In addition, the carrier structure can also be applied to the flip chip structure.

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1P Chip Package Substrate), as in the third embodiment, reference is made to the eighth embodiment. In the figure, a multilayer semiconductor carrier is taken as an example, and the solder balls 48 are disposed on the bumps 40, and are also utilized. Tin' connects metal layer 42. Electric 5, the invention description (7) Therefore, the present invention is to have the first surface 12 and the second surface 14 of the metal, ▲ plate ί, multiple etching and metal layer, forming a plurality of grooves on the first surface i2 30, and a plurality of bumps 4 〇 are arranged on the second surface 14 , and a spacer 22 is disposed in the metal plate 10 adjacent to the bumps 4 , and the spacers 22 are exposed in each of the grooves Within 30, each block 40 is electrically conductive/non-conductive by the material of the spacers 22. Therefore, the present invention improves the application of the spacer structure by changing the material of the spacer 22, and fabricates a metal semiconductor carrier by etching/uncontrolled molding to have both complex-number conductive bumps and The heat dissipation is good to replace the carrier board of the existing wafer package. In addition, the spacer 22 is changed and the support structure is designed to make the wiring of the wafer more diverse, so that it can be applied to various semiconductor packages, and since the present invention directly applies the wafer 44 to the metal carrier, the wafer 44 is good. The heat dissipation 'pathway' and pre-made conductive bumps by metal carrier plates reduce manufacturing costs and steps. The above description is based on the embodiments of the present invention, and the objects of the present invention can be understood by those skilled in the art and are not limited to the scope of the present invention. Equivalent modifications or modifications made from the spirit of the present invention should still be included in the scope of the claims described below.

1258828

• [Simple diagram description]

The first circle is a single-layer semiconductor of the present invention. The second figure is a multilayer semiconductor of the present invention. The third figure is a cross-sectional view showing the steps of the fourth embodiment (a) to the fourth (1) of the present invention. Schematic diagram of the carrier plate. Schematic diagram of the carrier plate. A schematic cross-sectional view of a patterned carrier. The fifth drawing of the present invention is a cross-sectional view of the wafer assembly of the present invention. Fig. / is a schematic cross-sectional view showing another application of the multi-layer patterned carrier in the present invention.

Figure 7 is a cross-sectional view showing another application of the multi-layer patterned carrier of the present invention. Figure 8 is a cross-sectional view showing another application of the multi-layer patterned carrier. [Main component symbol description]

1 composite plate 2 groove 3 bump 4 spacer 5 conductive J6 solder mask layer 7 metal layer 10 metal plate 12 first surface 14 second surface 16 first patterned photoresist layer 18 first photoresist layer 20 first Groove 22 spacer 24 metal layer 26 second recess 28 second metal layer page 12 1258828 illustration simple description 30 groove 32 solder mask layer 34 contact groove 36 second patterned photoresist layer 38 second photoresist Layer 40 bump 42 conductive layer 44 wafer 46 protective layer 48 solder ball

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Claims (1)

1258828 6. Patent application scope A multi-bump type arrangement, the multi-convex composite surface and a second surface are provided, a spacing and the spacing] 吏 each of the convex applications 2, such as 10, conductivity 3. As in it, electrical. Bu, for example, has 5, if the application of the block half board, its surface, a plurality of convex objects, its exposed block with a patented patent system patent parallel system 螽 中Ψ 设The special application is intended to be a first guide, such as a surface 7, such as a Lifan system, a conductive surface layer, a semiconductor layer carrier, and a semiconductor carrier for at least one of the wafers. The metal layer is formed and has a first surface forming a plurality of grooves on the first surface, and the second block is arranged; and is disposed between the metal layers and adjacent to the protrusions, in the grooves, The spacer material is different in electrical/non-conductive properties. When the multi-bump type semiconductor carrier according to the first item is an insulating material, the corresponding bump is a non-bump type semiconductor carrier as described in the first item, and is a conductive material. Corresponding to the bump is a multi-bump type semiconductor carrier as described in the first item, and the bump is corresponding to a material having a special electrical property. The multi-bump type semiconductor carrier as described in item 1 and the surface of the bumps may be subjected to a surface treatment, and the multi-bump type semiconductor carrier according to item 5 is selected from electroless plating or electrification. One of the gold applications for electroplating is specifically for conductive processing. The multi-bump semiconductor carrier board described in claim 1 Page 14 1258828 VI. Patent Application Range The first surface of the composite panel and the spacer are further formed with a solder mask. 8. The multi-bump type semiconductor carrier according to claim 1, wherein the grooves and the bumps are formed by a plurality of selective etching methods. 9. The multi-bump semiconductor carrier according to claim 1, wherein the metal layer and the spacer are disposed on the first surface a plurality of times, and the J is etched or deeply The way to complete the multi-bump multi-layer patterned carrier. The multi-bump type semiconductor carrier according to claim 9, wherein the multi-bump multi-layer patterned carrier is formed by providing a plurality of layers on the first surface or at least one region. a metal layer and the spacer. 11. The multi-bump semiconductor carrier of claim 10, wherein the region is at the two ends of the first surface. 1 . The multi-bump semiconductor carrier according to claim 1, wherein the wafer is disposed in a line (W ire ο ding nding ) or a flip chip (F 1 i ρ Chip). Bump type semiconductor carrier. 13. The multi-bump type semiconductor carrier of claim 12, wherein the wafer is provided on the protrusion of the composite board by flip chip. 4. The multi-bump type semiconductor carrier-plate as described in claim 12, wherein a protective layer is further disposed on the wafer to prevent the wafer from being damaged by external force. 15. A method of fabricating a multi-bump semiconductor carrier, comprising the following steps Page 15