TW550831B - Photo sensor and method of forming the same - Google Patents
Photo sensor and method of forming the same Download PDFInfo
- Publication number
- TW550831B TW550831B TW91113444A TW91113444A TW550831B TW 550831 B TW550831 B TW 550831B TW 91113444 A TW91113444 A TW 91113444A TW 91113444 A TW91113444 A TW 91113444A TW 550831 B TW550831 B TW 550831B
- Authority
- TW
- Taiwan
- Prior art keywords
- type
- region
- doped
- light
- area
- Prior art date
Links
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
550831 五、發明說明(1) 發明之領域 本發明係提供一種製作一感光二極體(photodiode)之 光感測區的方法,特別是一種對短波長光具有較佳感測靈 敏度的感光二極體之光感測區的製作方法。 背景說明 互補式金氧半導體(complementary metal-oxide semiconductor,CMOS)影像感測器(image sensor)係為現 今一種普遍的固態影像感測元件,且CMOS影像感測器已有 日漸取代載子偶合裝置(charge-coupled device, CCD)的 趨勢。此乃由於CMOS影像感測器的是以傳統的半導體製程 製作,因此具有製作成本較低以及元件尺寸較小的優點, 此外,C Μ 0 S影像感測器還具有高量子效率(q u a n t u m efficiency)以及低雜訊(read-out noise)等優勢,因此 已廣泛應用在個人電腦相機(PC camera)以及數位相機 (digital camera)等電子產品上。 典型的CMOS影像感測器包含有一個感光二極體,用來 感測光照的強度,以及三個金屬氧化半導體(m e t a 1 - ο X i d e semiconductor, MOS)電晶體,分別用來作為重置元件 (reset M0S)、電流汲取元件(current source follower) 以及列選擇開關(row selector)。其中感光二極體主要係550831 V. Description of the invention (1) Field of the invention The present invention provides a method for making a light sensing area of a photodiode, in particular a photodiode with better sensing sensitivity to short-wavelength light. Manufacturing method of body light sensing area. Background: Complementary metal-oxide semiconductor (CMOS) image sensors are a common solid-state image sensing device, and CMOS image sensors have gradually replaced carrier coupling devices. (Charge-coupled device, CCD) trend. This is because the CMOS image sensor is manufactured using a traditional semiconductor process, so it has the advantages of lower manufacturing cost and smaller component size. In addition, the C M 0 S image sensor also has high quantum efficiency. And low-noise (read-out noise) and other advantages, it has been widely used in personal computer cameras (PC camera) and digital cameras (digital camera) and other electronic products. A typical CMOS image sensor includes a photodiode to sense the intensity of light, and three metal oxide semiconductor (meta 1-ο X ide semiconductor, MOS) transistors, which are used as reset elements. (reset M0S), current source follower, and row selector. Among them, photodiodes are mainly
550831 五、發明說明(2) 依照其光感測區所產生之光電流來處理訊號資料,例如光 感測區於受光狀態所產生的漏遺電流Π ight current)代 表訊號(s i gna 1 ),而光感測區於不受光狀態所產生的漏遺 電流(dark current)則代表雜訊(noise),因此感光二極 體可以利用訊號雜訊比的強弱方式來處理訊號資料。 請參考圖一,圖一為習知一設於一半導體晶片表面之 感光二極體光感測區的結構示意圖。如圖一所示,半導體 晶片1 0包含有一石夕基底1 2,一 P型井1 4位於石夕基底1 2之 上,一光感測區1 6定義於p型井1 4的表層,以及一淺溝隔 離(shallow trench is〇lation,繞於光感測區 1 6周圍’用來隔絕光感測區丨6與其他電子元件,以避免短 路0550831 V. Description of the invention (2) Process signal data according to the photocurrent generated by the photo-sensing area, for example, the leakage current (Π ight current) generated by the photo-sensing area in the light receiving state represents the signal (si gna 1), The dark current generated by the light sensing area when it is not in the light state represents noise, so the photodiode can use the strength of the signal-to-noise ratio to process the signal data. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional photodiode light-sensing area on a semiconductor wafer. As shown in FIG. 1, the semiconductor wafer 10 includes a Shi Xi substrate 12, a P-type well 14 is located on the Shi Xi substrate 12, and a light sensing area 16 is defined on the surface of the p-type well 14. And a shallow trench isolation (around the photo-sensing area 16) to isolate the photo-sensing area 6 from other electronic components to avoid short circuits.
省知製作光感測區丨6的方法是利用一離子佈植製程在 P型井1 4表層形成一 _離子摻雜區2 〇,例如以砷(a s )作為 才f5貝 >佈^直忐置約為8 〇 Ke V,以使摻雜區2 0具有一約為1 0 撿能,植,辰度。而由於捧雜區2 0與P型井1 4具有不同的 :M心因此在摻雜區20與P型井1 4相鄰接之PN接合 區域會產生一空乏區(depieti〇n regi〇n)22, 作為感先一極體感應光電流之區域。 由於習知方法係利用古 ^ rv ^ ^ ^ ^ on j用回劑I與高能量之砷原子做為丰 負以形成摻雜區2 0,因扮t令,丨曰 u此问劑ϊ之摻雜區2 〇與ρ型井1 4接The province knows that the method of making the light sensing area 6 is to use an ion implantation process to form an _ ion doped area 2 on the surface of the P-type well 14. For example, arsenic (as) is used as the substrate. The setting is about 80 KeV, so that the doped region 20 has an energy pick-up, plant, and degree. However, since the doped region 20 and the P-type well 14 are different: the M center will generate a depleted region (depietión regi〇n) in the PN junction region where the doped region 20 and the P-type well 14 are adjacent to each other. ) 22, as the area where the photodiode is sensed by the pre-polar body. Because the conventional method uses the ancient ^ rv ^ ^ ^ ^ on j, the reductant I and the high-energy arsenic atom are used as the burden to form the doped region 20. Due to the order of t, The doped region 2 is connected to the p-type well 1 4
第6頁 550831 五、發明說明(3) 合後所形成之空乏區2 2將相對地產生比較窄的接合寬度, 而使得光感測區實際的受光區域(real active region 減少,亦即使付二之區2 2在感光二極體受光之狀態下所能 感應到的光電流下降’並降低訊號雜訊比,進而減弱感光 二極體的訊號感測度。 此外,由高佈植能量之離子佈植製程所形成的摻雜區 2 0相對地亦具有較深的接合深度。因此,當感光二極體受 到短波長光(例如藍光)的照射時,將會因為短波長光對石夕 晶片的穿透深度較淺,使得感光二極體之pN接合區域所能 感應到的光電流偏小’造成感光二極體對短波長光的感測 度不佳。而且高佈植能量之離子佈植製程亦可能導致摻雜 區2 0表面之晶格結構破壞,使得光電荷產生表面復合 (surface recombination)之機率大為提高,因而導致光 電荷的生命週期(life time)嚴重衰減,影響感光二極體 之訊號感測度。 發明概述 本發明的目的是提供一種 的方法,以有效改善感光二極 依據本發明之目的,本發 半導體晶片,該半導體晶片表 製作感光二極體之光感測區 體之訊號感測度。 明之較佳實施例係先提供一 面包含有一第一導電型式之Page 6 550831 V. Description of the invention (3) The empty area 2 2 formed after the combination will relatively produce a relatively narrow joint width, so that the actual light receiving area of the light sensing area (real active region decreases, even if it pays two) Zone 2 2 reduces the photocurrent that can be sensed when the photodiode is receiving light and reduces the signal-to-noise ratio, thereby weakening the signal sensitivity of the photodiode. In addition, the ion cloth with high energy is planted. The doped region 20 formed by the implantation process also has a relatively deep bonding depth. Therefore, when the photodiode is irradiated with short-wavelength light (such as blue light), the short-wavelength light will affect the Shi Xi wafer. The penetration depth is shallow, which makes the photocurrent that can be sensed by the pN junction area of the photodiode is too small, which causes the photodiode to have poor sensitivity to short-wavelength light. And the ion implantation process with high implantation energy It may also lead to the destruction of the lattice structure on the surface of the doped region 20, which greatly increases the probability of surface recombination of the photocharges, which causes the life time of the photocharges to be seriously attenuated. Responds to the signal sensitivity of the photodiode. SUMMARY OF THE INVENTION The object of the present invention is to provide a method to effectively improve the photodiode. According to the purpose of the present invention, a semiconductor wafer is produced. The signal sensing degree of the sensing area. A preferred embodiment of the invention is to first provide a bread containing a first conductive type
第7頁 550831Page 7 550831
遺後進H離;^ =光感測區周圍之該基底表面, 質於該光感二區表f “,以利用第二導電型式之摻 第二離;佈植製f以二數個第-摻雜區,之後再進行 感測區表面带士製 以利用第二導電型式之摻質於該光 i一換雜dlπ二第二摻雜區,並使該第二摻雜區與各該 乐得雜&之部分區域相重疊。 數個ΐ:ί ϊ=係利用第一離子佈植製程於基底中形成福^ = The surface of the substrate around the photo-sensing area, ^ = the surface of the photo-sensing area f ", in order to use the second conductive type doped second separation; fabricating f with two or more- Doped region, and then perform sensing on the surface of the sensing region to use the second conductivity type dopant in the light i-doped dlπ-second doped region, and make the second doped region and each of the gains Partial regions of the & are overlapped. Several ΐ: ί ϊ = is formed in the substrate using the first ion implantation process.
品,因此可以藉由增加各該第一摻雜區與其 ^ 土 &之間的接觸面積來有效增加感光二極體之感 光面積,進而改善感光二極體之訊號感測度。此外,由灰 本發明之第一摻雜區係重疊於各該第一摻雜區之上方區 域,因此由第二摻雜區與其相鄰接之基底所形成之空乏H 係設於鄰近基底表面之位置,以有效提昇感光二極體對灰 短波長光線(例如藍光)之靈敏度。 發明之詳細說明 請參考圖二至圖五,圖二至圖五為本發明於一半導體 晶片表面製作一感光二極體之光感測區的方法示意圖。如 圖二所示,半導體晶片3〇包含有一 P型基底32,以及複數 個絕緣層3 8,例如淺溝隔離結構,設於p型基底3 2表面, 以用來定義出光感測區之位置。在本發明之最佳實施例 中,P型基底3 2表面另包含有一 p型磊晶矽層3 4,且絕緣層Therefore, by increasing the contact area between each of the first doped regions and the soil, the light sensing area of the photodiode can be effectively increased, thereby improving the signal sensitivity of the photodiode. In addition, the first doped region of the present invention overlaps the region above each of the first doped regions. Therefore, the empty H formed by the second doped region and the substrate adjacent to it is disposed adjacent to the surface of the substrate. Position to effectively increase the sensitivity of the photodiode to gray short-wavelength light (such as blue light). Detailed description of the invention Please refer to FIGS. 2 to 5. FIGS. 2 to 5 are schematic diagrams of a method for fabricating a light sensing region of a photodiode on a semiconductor wafer surface according to the present invention. As shown in FIG. 2, the semiconductor wafer 30 includes a P-type substrate 32 and a plurality of insulating layers 38, such as a shallow trench isolation structure, provided on the surface of the p-type substrate 32 to define the position of the light sensing area. . In a preferred embodiment of the present invention, the surface of the P-type substrate 32 further includes a p-type epitaxial silicon layer 34, and an insulating layer.
第8頁 550831 五、發明說明(5) 3 8下方另設有一 P型井3 6,以利用P型井3 6來避免於光感測 區產生之接合電流擴散至相鄰之感測元件,造成跨越干擾 (cross talk)現象。 如圖三所示,隨後利用一微影製程於P型基底3 2表面 上形成一光阻層4 0,以於光感測區中定義出複數個輕摻雜 區的位置。接著進行一第一離子佈植製程,利用N型換 質,如砷原子(arsenic,As)或磷原子(phosphorus, P)等 來對P型基底32進行摻雜,以形成複數個摻雜區42。之 後,完全去除半導體晶片30表面的光阻層40。 如圖四所示,接下來再利用另一微影製程於p型基底 3 2表面上形成一光阻層4 4,以於光感測區中定義一重-區的位置。接著,利用光阻層4 4作為遮罩,進行一第二雜 子佈植製程,以於光感測區表面形成一摻雜區46, 雜區46與摻雜區42之上方區域相重疊。值彳日 使1乡 二離子佈植製程之能量應小於第一離子佈植製程之处旦第 以使換雜區4 6與Ρ型蠢晶碎層3 4產生之接人、、穴译 里Page 8 550831 V. Description of the invention (5) There is another P-well 36 under the 8 to use the P-well 36 to prevent the bonding current generated in the light sensing area from spreading to adjacent sensing elements. Causes cross talk. As shown in FIG. 3, a photolithography process is then used to form a photoresist layer 40 on the surface of the P-type substrate 32 to define the positions of a plurality of lightly doped regions in the photo-sensing region. Next, a first ion implantation process is performed, using N-type modification, such as arsenic (As) or phosphorus (P), to dope the P-type substrate 32 to form a plurality of doped regions. 42. After that, the photoresist layer 40 on the surface of the semiconductor wafer 30 is completely removed. As shown in FIG. 4, another photolithography process is next used to form a photoresist layer 4 4 on the surface of the p-type substrate 32 to define a heavy-area position in the light sensing area. Next, using the photoresist layer 44 as a mask, a second hetero-implantation process is performed to form a doped region 46 on the surface of the photo-sensing region, and the doped region 46 overlaps the region above the doped region 42. On the next day, the energy of the two-ion implantation process in the 1 township should be less than that of the first ion-implantation process so that the replacement area 4 6 and the P-type stupid crystal fragment 3 4 can be connected to the hole.
區42與Ρ型蟲晶石夕層34產生之接合深度。::於捧雜 佈植製程之摻質可與第一離子佈植製程所’二^子 同,亦即利用Ν型摻質,例如砷原子或磷原用貝相 質,然而第一離子佈植製程之摻質濃 乍為摻 植製程之摻質濃度。 丨Ή二離子佈The junction depth between the region 42 and the P-type wormwood layer 34. :: The dopant in the Yupin hybrid cloth planting process can be the same as that used in the first ion cloth planting process, that is, using N-type dopants, such as arsenic atoms or phosphorous shell materials, but the first ion cloth The concentration of the dopant in the planting process is the concentration of the dopant in the planting process.丨 ΉDual ion cloth
550831550831
與摻雜圖五所示,最後再進行一退火製程,以使摻雜區42 並且-、區46内之摻質趨入(driving-in)P型磊晶矽層34, 區於摻雜區4 2與P型磊晶矽層3 4相鄰接區域以及於摻雜 :P型蟲晶石夕層3 4相鄰接區域形成複數個空乏區4 8, 70成光感測區之製作。 3由於本發明係利用第一離子佈植製程於P型磊晶矽層 复中形成複數個摻雜區42,因此可以藉由增加摻雜區42與 j鄉接之p型磊晶矽層3 4之間的接觸面積來有效增加感 :,體之感光面積,亦即增加空乏區乜之面積,以增加 九電流並改善感光二極體之訊號感測度。此外,本發明另 =γ型磊晶矽層34表面設有一摻雜區46,因此可以藉由摻 1區46與其相鄰接之p型磊晶矽層34於摻雜區“下方形成 車乂久之空乏區,以有效提昇感光二極體對於短波長光 (例如藍光)之靈敏度。 再者’由於本發明之感光二極體結構係使摻雜區46覆 盍於複數個摻雜區42上方,因此可以利用摻雜區46來當作 連接光感測區之導線,並且使各個摻雜區4 2均獲得一相同 電壓。如此一來,由於空乏區4 8兩側的摻雜區4 2具有相同 電壓’因此可使空乏區48成為完全空乏區(亦即斷路 (open)的狀態),而獲得一約略為零之電容值,以增加集 光區域並降低遺漏電流(dark current)。而在提高空乏區 48之光電流並降低其電容值之情形下,則感光二極&之光As shown in FIG. 5, an annealing process is finally performed to make the doping regions in the doped regions 42 and-46 into the P-type epitaxial silicon layer 34 in the doped regions. 4 2 is adjacent to the P-type epitaxial silicon layer 3 4 and the doped: P-type spar stone layer 3 4 is adjacent to the area to form a plurality of empty regions 4 8 and 70 into the light sensing region. 3 Since the present invention uses the first ion implantation process to form a plurality of doped regions 42 in the p-type epitaxial silicon layer, the p-type epitaxial silicon layer can be connected to the p-type epitaxial silicon layer 3 by adding the doped region 42 The contact area between 4 can effectively increase the sense: the photosensitive area of the body, that is, the area of the empty area, to increase the nine currents and improve the signal sensitivity of the photodiode. In addition, the present invention also provides a doped region 46 on the surface of the γ-type epitaxial silicon layer 34, so that a p-type epitaxial silicon layer 34 adjacent to the γ-type epitaxial silicon layer 34 can be formed under the doped region. The long empty region effectively improves the sensitivity of the photodiode to short-wavelength light (eg, blue light). Furthermore, the doped region 46 is overlaid on the plurality of doped regions 42 due to the photodiode structure of the present invention. Therefore, the doped region 46 can be used as a wire connecting the light sensing region, and each doped region 4 2 can obtain the same voltage. In this way, the doped regions 4 2 on both sides of the empty region 4 8 Having the same voltage 'can therefore make the empty region 48 a completely empty region (ie, an open state), and obtain a capacitance value of approximately zero to increase the light collection region and reduce the dark current. In the case of increasing the photocurrent of the empty region 48 and reducing its capacitance value, the light of the photodiode &
550831 五、發明說明(7) 子轉換增益(photon conversion gain)亦隨之增加,以有 效改善感光二極體之效能。 請參考圖六’圖六係為本發明另一貫施例之'一感光-極體之光感測區的結構示意圖。此一實施例係藉由感光二 極體製程以及M0S電晶體製程之整合來簡化生產流程。如 圖六所示,一半導體晶片50包含有一 P型基底52,一光感 測區5 4以及一邏輯電路區5 6設於P型基底5 2表面,且光感 測區54以及一邏輯電路區56之間設有複數個絕緣層62,例 如淺溝隔離結構。其中光感測區5 4係用來形成一感光二極 體,而邏輯電路區56係用來形成一 M0S電晶體。為了改善 感光二極體之電性表現,本發明可選擇性於P型基底5 2上 設置一 P型蠢晶石夕層5 8,以及於絕緣層6 2下方設置複數個p 型井60 ° 光感測區5 4内包含有複數個輕摻雜區6 4,一重摻雜區 6 6覆蓋於輕摻雜區6 4表面,以及複數個由p型磊晶矽層5 8 與其相鄰接之摻雜區6 4、6 6内的N型摻質所形成之空乏區 7 2。邏輯電路區5 6内包含設有一閘極6 8,以及一輕摻雜汲 極(1 lght ly doped drain, LDD)70設於閘極 68兩側之 p型 蠢晶石夕層5 8中。值得注意的是,摻雜區6 6與輕摻雜汲極μ 係經由同一道離子佈植製程所形成,以減少摻雜區6 6表面 之晶格結構破壞,降低光電荷之表面復合以及漏電流現 象,並且整合感光二極體與M〇s電晶體之製程,降低生產550831 V. Description of the invention (7) The sub conversion gain (photon conversion gain) is also increased to effectively improve the performance of the photodiode. Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a light-sensing area of a photo-polar body according to another embodiment of the present invention. This embodiment simplifies the production process by integrating the photodiode process and the MOS transistor process. As shown in FIG. 6, a semiconductor wafer 50 includes a P-type substrate 52, a light-sensing region 54 and a logic circuit region 56 disposed on the surface of the P-type substrate 52, and a light-sensing region 54 and a logic circuit. A plurality of insulating layers 62 are provided between the regions 56, such as a shallow trench isolation structure. The light sensing area 54 is used to form a photodiode, and the logic circuit area 56 is used to form a MOS transistor. In order to improve the electrical performance of the photodiode, the present invention may optionally include a P-type stupid stone layer 58 on the P-type substrate 52, and a plurality of p-type wells 60 under the insulating layer 62. The light sensing region 5 4 includes a plurality of lightly doped regions 6 4, a heavily doped region 6 6 covers the surface of the lightly doped region 6 4, and a plurality of p-type epitaxial silicon layers 5 8 adjacent thereto. The empty region 7 2 formed by the N-type dopants in the doped regions 6 4 and 6 6. The logic circuit area 56 includes a gate 68, and a lightly doped drain (LDD) 70 disposed on both sides of the gate 68 in a p-type stupid evening layer 58. It is worth noting that the doped region 66 and the lightly doped drain μ are formed through the same ion implantation process to reduce the destruction of the lattice structure on the surface of the doped region 66 and reduce the surface recombination and leakage of photocharge Current phenomenon, and integrate the process of photodiode and Mos transistor to reduce production
550831550831
成本。 相較於習 基底中形成複 雜區與其相鄰 極體之感光面 外,由於本發 方區域’因此 區係設於鄰近 於短波長光線 區,因此可增 流與光子轉換 为口孜術,本發明係利用第— 數個輕摻雜區,因此可以# 佈植製程灰 接之基底之間的接觸面積^ =加各該輕才I 積,進^文善感光二極體之加感光二 明之重摻•區係ί疊於各該第:i:度。此 由重摻雜區與其相鄰接之 上 基底表面之位置,能有效提昇Γ光成;;ί 之靈敏度。並且因為各空乏區係為;= Κ先區域並&低遺漏電流’$而增加光電 實施例,凡依本發明申請 ,皆應屬本發明專利之涵cost. Compared with the complex surface in Xi base and the photosensitive surface of its adjacent polar body, the origin region is located near the short-wavelength light region, so the current can be increased and the photons can be converted into oral cavity. The invention uses the first-several lightly doped regions, so the contact area between the substrates in the graying process can be increased by ^ = the product of each light source is added, and the light sensitive photodiode is added to the light sensitive two light source. Remixing • Flora is superimposed on each rank: i: degree. The position of the substrate surface adjacent to the heavily doped region can effectively increase the photosensitivity; And because each empty area is; = κ the first area and & low leakage current '$ to increase the photoelectric embodiment, all applications according to the present invention should be covered by the patent of the present invention
以上所述僅為本發明之較佳 專利範圍所做之均等變化與修錦 蓋範圍。What has been described above are only equivalent changes and modifications to the scope of the preferred patent scope of the present invention.
550831 圖式簡單說明 圖示之簡單說明 圖一為習知一感光二極體之光感測區的結構示意圖。 圖二至圖五為本發明製作一感光二極體之光感測區的 方法示意圖。 圖六為本發明另一實施例之一感光二極體之光感測區 的結構示意圖。 圖示之符號說明 10 半導體晶片 12 砍基底 14 P型井 16 光感測區 18 淺溝隔離 20 摻雜區 22 空乏區 30 半導體晶片 32 P型基底 34 P型磊晶矽層 36 P型井 38 絕緣層 40 光阻層 42 第一摻雜區 44 光阻層 46 第二摻雜區 48 空乏區 50 半導體晶片 52 P型基底 54 光感測區 56 邏輯電路區 58 P型磊晶矽層 60 P型井 62 絕緣層 64 第一摻雜區 66 第二摻雜區 68 閘極 70 輕摻雜沒極550831 Brief description of the diagram Brief description of the diagram Figure 1 shows the structure of the light sensing area of a conventional photodiode. FIG. 2 to FIG. 5 are schematic diagrams of a method for fabricating a light sensing region of a photodiode according to the present invention. FIG. 6 is a schematic structural diagram of a light sensing region of a photodiode according to another embodiment of the present invention. Explanation of symbols in the figure 10 Semiconductor wafer 12 Cutting substrate 14 P-type well 16 Photo-sensing area 18 Shallow trench isolation 20 Doped area 22 Empty area 30 Semiconductor wafer 32 P-type substrate 34 P-type epitaxial silicon layer 36 P-type well 38 Insulating layer 40 Photoresist layer 42 First doped region 44 Photoresist layer 46 Second doped region 48 Empty region 50 Semiconductor wafer 52 P-type substrate 54 Photo-sensing region 56 Logic circuit region 58 P-type epitaxial silicon layer 60 P Well 62 Insulating layer 64 First doped region 66 Second doped region 68 Gate 70 Lightly doped electrode
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91113444A TW550831B (en) | 2002-06-20 | 2002-06-20 | Photo sensor and method of forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91113444A TW550831B (en) | 2002-06-20 | 2002-06-20 | Photo sensor and method of forming the same |
Publications (1)
Publication Number | Publication Date |
---|---|
TW550831B true TW550831B (en) | 2003-09-01 |
Family
ID=31713549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW91113444A TW550831B (en) | 2002-06-20 | 2002-06-20 | Photo sensor and method of forming the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW550831B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI427783B (en) * | 2011-10-28 | 2014-02-21 | Ti Shiue Biotech Inc | Multi-junction photodiode in application of molecular detection and discrimination, and method for fabricating the same |
TWI453902B (en) * | 2008-11-19 | 2014-09-21 | Omnivision Tech Inc | Lightly-doped drains (ldd) of image sensor transistors using selective epitaxy |
CN108415001A (en) * | 2018-02-12 | 2018-08-17 | 深圳市镭神智能系统有限公司 | It receives the photosensitive array of the flare of laser radar, receive system and method |
-
2002
- 2002-06-20 TW TW91113444A patent/TW550831B/en not_active IP Right Cessation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI453902B (en) * | 2008-11-19 | 2014-09-21 | Omnivision Tech Inc | Lightly-doped drains (ldd) of image sensor transistors using selective epitaxy |
US8859352B2 (en) | 2008-11-19 | 2014-10-14 | Omnivision Technologies, Inc. | Lightly-doped drains (LDD) of image sensor transistors using selective epitaxy |
TWI427783B (en) * | 2011-10-28 | 2014-02-21 | Ti Shiue Biotech Inc | Multi-junction photodiode in application of molecular detection and discrimination, and method for fabricating the same |
CN108415001A (en) * | 2018-02-12 | 2018-08-17 | 深圳市镭神智能系统有限公司 | It receives the photosensitive array of the flare of laser radar, receive system and method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100436067B1 (en) | Image sensor and method of fabricating the same | |
US7524695B2 (en) | Image sensor and pixel having an optimized floating diffusion | |
US6512280B2 (en) | Integrated CMOS structure for gate-controlled buried photodiode | |
KR100746222B1 (en) | Methods of fabricating image sensor | |
KR100760913B1 (en) | CMOS Image Sensor and Method for Manufacturing the same | |
JP2004165589A (en) | Cmos image sensor and method for manufacturing the same | |
US7973342B2 (en) | CMOS image sensor and method for manufacturing the same | |
JP2000031525A (en) | Pinned photodiode of image sensor, and its manufacture | |
KR100836507B1 (en) | Method for fabricating cmos image sensor | |
US6392263B1 (en) | Integrated structure for reduced leakage and improved fill-factor in CMOS pixel | |
JP2013020998A (en) | Semiconductor device and manufacturing method of the same | |
KR100884976B1 (en) | Method for Fabricating Image Sensor | |
US6621064B2 (en) | CMOS photodiode having reduced dark current and improved light sensitivity and responsivity | |
US20040002177A1 (en) | Photo sensor and method of forming the same | |
TW550831B (en) | Photo sensor and method of forming the same | |
CN100527429C (en) | CMOS image sensor and method for manufacturing the same | |
KR100595876B1 (en) | Method for fabricating photodiode of image sensor | |
KR100749098B1 (en) | Image sensor with high transfer and sensitivity characteristics and manufacturing method thereof | |
KR20070033718A (en) | CMOS image sensor and its manufacturing method | |
JPH08222719A (en) | Charge-coupled solid-state image pickup element and manufacture thereof | |
KR100318447B1 (en) | pinned photodiode in image sensor and method for fabricating the same | |
KR20010061356A (en) | method for fabricating pixel of image sensor to improved doping profile of low voltage photodiodes | |
TW511287B (en) | A CMOS image sensor device | |
TW437008B (en) | A method to fabricate photodiode and CMOS transistor at the same time | |
KR100700266B1 (en) | Fabricating method for Image sensor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |