TW527728B - Semiconductor storage device using single channel transistor to transport voltage for selected word line - Google Patents

Abstract

A semiconductor memory device disclosed in the present invention comprises a memory cell array, in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The above-mentioned row decoder circuit includes a plurality of first transistors of a first conductivity type, in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

Description

527728 A7 B7 V. Description of the Invention (1) Background of the Invention The present invention relates to semiconductor memory devices, and more specifically to non-volatile semiconductor memory devices such as NAND cells, NOR cells, DINOR cells, and AND-type EEPROMs. One of the conventionally known semiconductor memory devices is an electrically rewritable EEPROM. Among them, a NAND-type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell area is valued because it can be highly integrated. A memory cell of the NAND cell EEPROM has a FET-MOS structure, which is a semiconductor gate substrate which is laminated with a floating gate (charge storage layer) and a gate gate via an insulating film. In addition, a plurality of memory cells adjacent to each other are connected in series to form a NAND cell in the form of a shared source and drain, and are connected to the bit line as a unit. Such NAND cells are arranged in a matrix to form a memory cell array. The memory cell array is formed in a p-type semiconductor substrate or a p-well region. The drain electrodes on one end side of the NAND cell parallel to the row direction of the memory cell array are each connected to the bit line through the selection gate transistor, and the source electrode on the other end side is also connected to the common source line through the selection gate transistor. The control gate of the memory transistor and the gate of the selection gate transistor are connected in the column direction of the memory cell array as control gate lines (word lines) and selection gate lines. The operation of this NAND cell EEPROM is as follows. The data writing operation is mainly performed sequentially from the memory cells located farthest from the bit line contact. First, after the data writing operation is started, corresponding to writing data, 0 V (π 1 ”data writing bit line) or power supply voltage Vcc (Π0Π data writing bit line) is supplied to the bit line, and the selected The selection gate line on the contact side of the bit line is supplied to Vcc. In this case, the "1" data is written to the bit line and the selection is connected. -4- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm). (Centre) 527728 A7 B7 V. Description of the invention (2) In the NAND cell, the channel part in the NAND cell is fixed at 0 V by a selective gate transistor. On the other hand, the `` 0 '' data is written to the bit line to which it is connected. In the selected NAND cell, the channel part in the NAND cell is in a floating state after being charged to [Vcc-Vtsg] (where Vtsg is the threshold voltage of the selected gate transistor). Next, select the control gate line of the selected memory cell in the NAND cell from 0 V to Vpp (= approximately 20V ·· high voltage for writing), and select the other control gate line of the NAND cell from 0 V to Vmg (= (Approximately 10 V ·· intermediate voltage). In the selected NAND cell to which the π 1 '' data write bit line is connected, the channel part in the NAND cell is fixed at 0 V. Therefore, the control gate line (= Vpp potential) of the selected memory cell in the NAND cell and The channel part (= 0V) generates a large potential difference (= about 2 0 V), causing electrons to be injected into the floating gate from the channel part. According to this, the threshold voltage of the selected memory cell is shifted to the positive direction, and the writing of π 1 π data is completed. In contrast, "0" data is written into the selected NAND cell to which the bit line is connected. Because the channel part in the NAND cell is in a floating state, the capacitive coupling between the control gate line and the channel part in the selected NAND cell is selected. Influence, as the voltage of the control gate line rises (OV-Vpp, Vmg), the potential of the channel portion rises from the maintained floating state [Vcc-Vtsg) to Vmch (= about 8 V). At this time, since the potential difference between the control gate line (= Vpp potential) of the selected memory cell in the selected NAND cell and the channel portion (= Vmch) is about 1 2 V, electron injection does not occur, so The threshold voltage of the selected memory cell does not change, but is maintained in a negative state. The erasure of the data is for all the memory cells in the selected NAND cell block. -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7 _____ B7 V. Description of the invention (3) Simultaneously. That is, 'make all the control gate lines in the selected NAnd cell block to be 0 v', and apply a high voltage of about 20 V to all the selected gate lines of the control gate line in the non-selected NAND cell area. Based on this, in the selected memory cell of the selected NAND cell block, the electrons in the floating gate are discharged to the p-type well region (or P-type semiconductor substrate), and the threshold voltage is shifted to the negative direction (shift). . On the other hand, 'data read operation, set the control gate line of the selected memory cell to 0 V'. Set the control gate line and selection gate line of other memory cells to the intermediate voltage Vread (about 4V), by detecting whether the current flows in the selected memory cell. According to the above operation description, NAND cell EEPROM must apply Vpp (approximately 20 V) to the selected control gate line in the selection block and the non-selected control gate line in the selected area when the data is written. When Vmg (approximately 10 V) is applied, a voltage higher than the power supply voltage needs to be transmitted. In order to transmit the above-mentioned voltages Vpp and Vmg, in the column decoding circuit, two kinds of elements, NMOS transistors (η-channel MOS transistors) and PMOS transistors (ρ-channel μ MOS transistors) with different gate line polarities are controlled. The current path is connected in parallel and controlled such that: in the selected block, both the NMOS transistor and the PMOS transistor are 11 on (on., ON) state, and in the non-selected block both are "" Off π (cut, 0FF) state. FIG. 1 is a circuit diagram showing a configuration example of a part of a decoding circuit of a conventional semiconductor memory device. In the circuit shown in Fig. 1, one control gate line is connected to one NMOS transistor (Qnl to Qn8) and one PMOS transistor (Qpl to Qp8). The transistors Qnl ~ Qn8 and Qpl ~ QP8 are each provided by the nodes N1 and N2 with complementary control letters-6- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 27728 A7 B7 V. Invention Description (4).

When the data is written, if the power node VPPRW = [selected control gate line voltage] = 2 0 V, the power node VPPRW and the selected control gate line voltage are at the same level. In this case, for each control gate line, [NMOS transistor + PMOS transistor] is connected, and even when the power node VPPRW is 2 0 V, the control gate line can be transmitted 2 Ο V. Therefore, there is no need to raise the power node VPPRW to (20V + Vth), and the selection block can perform both 0V and Vpp voltage transmission. In the circuit shown in FIG. 1, the current paths of the memory cells M to M 8 are connected in series to form one NAND cell. One end of each of the above NAND cells is connected to the bit lines BL1 to BLm via the current path of the selection gate transistor S i, and the other end is connected to the source line (Cell-Source) through the current path of the selection gate transistor S2. . The control gate lines CG (1) ~ CG (8) are each connected to the memory cell in each NAND cell% ~] ^ 8 control gates, and the selection gate lines SG (1) and SG (2) are each connected to the selection gate in common. Gate of transistor Si, S2. Each of the signal input nodes CGD1 to CGD8, SGD, SGS, and SGDS is supplied with a decoding signal. The column decoder enable signal RDEC is V c c during normal data write / read / erase operations and 0 V during non-operation. The area address signals RA1, RA2, and RA3 are all Vcc in the selected block, and at least one of them is 0 V in the non-selected block. Here, all the PMOS transistors provided in the region Η V indicated by the dashed lines are formed in the η-well region to which the high voltage Vpp for writing is applied, at any one of the nodes N 1 and N 2. During the write operation, it must be at the same potential as V ρ ρ. The voltage of the node SGDS is 0 V during the write operation. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7 B7 V. Description of the invention (5) However, the above structure requires each control gate line CG (1) ~ CG (8) Because of the two transistors Qpl ~ Qp8 and Qnl ~ Qn8, the number of components in the column decoding circuit increases, and the pattern occupying area of the column decoding circuit increases, which causes problems due to the increase in chip cost. On the other hand, in order to prevent the number of components in the column decoding circuit from increasing, use it as shown in Figure 2: a circuit with one transistor connected to one control gate line (for example, only NMOS transistors QN1 to QN8). In the circuit shown in FIG. 2, the memory cell block 2 has the same structure as that in FIG. 1, except that it is part of the column decoding circuit (the control gate lines CG (1) to CG (8), and the voltage is transmitted to the selection gate. The transistor structure of the transistors Si and S2) 5 a and 5 b are different, and the pump circuit PUMP is provided. In the case of this circuit structure, in order to transmit the writing high voltage Vpp to the gate lines CG (1) to CG (8), the NMOS transistor QN1 connected to these control gate lines CG (1) to CG (8) The voltage applied to the gate of ~ QN8 must be [Vpp + Vtn] (where Vtn is the threshold voltage of the NMOS transistors QN1 ~ QN8 connected to the control gate lines CG (1) ~ CG (8)). Therefore, a pump circuit PUMP is provided in the column decoding circuit. The structure of the pump circuit PUMP includes: capacitors Cl, C2, NMOS transistors QN21 ~ QN23, inverter 6, NAND gate 7, and empty NMOS transistor QN24, QN25 and so on. In the circuit shown in FIG. 2, the signal OSCRD becomes an oscillating signal during the data writing and reading operations. The voltage boosted in the pump circuit PUMP is output to the node N1, and the voltage is passed through the transistors QN1 to QN8. The current path is transmitted to the control gate lines CG (1) to CG (8). In addition, the signal TRAN is usually fixed. -8- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7 B7 5. The invention description (6) is at 0V. However, the above pump circuit PUMP has a large circuit area because it includes a plurality of elements or capacitors Cl and C2. In particular, the two capacitors C1 and C2 usually require a larger pattern area than other components, so although the number of voltage-transmitting transistors can be reduced, the pattern area of the column decoding circuit cannot be sufficiently reduced, causing problems. . Thus, in the conventional EEPROM such as a NAND cell, it is necessary to have a function of sending a high voltage to a word line, and a transistor connected to a word line in a column decoding circuit must be connected to a plurality of word lines. Therefore, a problem arises in that the pattern area of the column decoding circuit increases. In addition, in order to solve this problem, if the transistor connected to the word line in the column decoding circuit is connected to one word line, a pump circuit is required in the column decoding circuit, and the pattern area of the pump circuit is changed. Large, still causes the problem that the pattern area of the column decoding circuit increases. In addition, in the column decoding circuit, a transistor connected to a word line is connected to one word line, and when a pump circuit is not provided in the column decoding circuit, the high voltage for writing cannot be lowered. The risk of insufficient data writing operation due to transmission to the word line is increased, which causes a problem. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device that can transmit a high voltage to a word line without reducing the potential, and can reduce a pattern area of a column decoding circuit. Another object of the present invention is to provide a semiconductor memory device which can realize a low-cost and high-reliability chip. -9 · This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 5 527728, description of invention (lower-purpose is to provide-semiconductor memory device 'It does not have to move ^ will send electricity to the word line , Can achieve sufficient data writing tools: hair :: VI is achieved by a semiconductor device, which is 1M Θ 4s F column, which is the memory cells are arranged in a matrix; and column it electrical; In: is the word line selected to the memory cell array of r, except this ... Those who are blessed by electrocution; the above-mentioned decoding circuit has: first lead two = electric first: conductor: = ^^ who chooses the word / + Γ ·, ② The second soil-transistor transistor transmits voltage to the gate of the first transistor connected to it when it performs a voltage transmission operation on the selected t-line, and forms a phase with the first conductivity type. It is characterized in that the electricity input to the selected zigzag line = operation is only performed on the first transistor of the first conductivity type. The purpose of the :: is to achieve a code circuit through a semiconductor device, which is a selection Before: Γ into a matrix; and translating the voltage transmission line 'in addition and generalizing, ^ is a side-by-side Ze code The circuit has: the first conductive type plural <diode 1 transistor, which is the current path of the end-each acre, each word line; and the second conductive type of the second transistor, which == to the J line for voltage transmission When in operation, the voltage is transmitted to the phase connection <the aforementioned! The polarities between the transistors; It is characterized by the opposite polarity of the aforementioned second conductivity type = tied to the first, the conductive type of the crystal into the system to apply To the closed electrode of the aforementioned second transistor in the non-selected block 10-This paper is suitable for the standard ® time standard (CN?)-_A4 specification (2i〇X2 ^ 7 binding mm) 527728 A7 B7 V. Description of the invention (8) The voltage is lower than the power supply voltage. The above object of the present invention is achieved by a semiconductor device having a memory cell array in which the memory cells are arranged in a matrix. And a column decoding circuit that selects the word line of the aforementioned memory cell array and transmits voltage to the word line; the column decoding circuit has: a first transistor of the first conductivity type, Its one end of the current path is directly connected to each word line; the first voltage switch Circuit, which includes a second transistor of the second conductivity type, which transmits a voltage to the gate of the first transistor connected to the selected word line when performing a voltage transmission operation on the selected word line. Those who have the opposite polarity to the first conductivity type and apply voltage to the gate of the first transistor; a logic circuit that receives a column address signal and outputs the result of the selection and non-selection of the block And a second voltage switching circuit that receives the output signal of the logic circuit and outputs the signal to the first voltage switching circuit; characterized in that the voltage transmission to the selected word line is only based on The first transistor of the first conductivity type is performed, and the highest voltage level in the second voltage switching circuit is lower than the surface voltage level in the first voltage switching circuit. According to the above structure, the voltage transmission to the selected word line is performed only on the first transistor of the first conductivity type. The transistor connected to the word line in the column decoding circuit is one word line. Connect one to reduce the pattern area of the column decoding circuit. The second transistor of the second conductivity type transmits a voltage to the gate of the first transistor. For example, the n-channel type is used for the first conductivity type and the p-channel type transistor is used for the second conductivity type. Prevents the potential reduction of the transmission voltage based on the threshold voltage of the second transistor. The -11-this paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 527728 A7

The south voltage is not reduced to the word line, and the gate of the transistor can be set to high voltage. Therefore, the potential can be transferred to the word line. Therefore, it is possible to transmit a high voltage to a pattern area of a few rows of decoding circuits without lowering the potential. In addition, since a column decoding circuit having a small pattern area can be realized, an inexpensive and highly reliable chip can be realized. Moreover, it is possible to transmit a high voltage to the word line without lowering the potential, and a sufficient data writing operation can be realized. Schematic description FIG. 1 is a circuit diagram of a configuration example of a part of a decoding circuit and a memory cell array of a conventional semiconductor memory device, and FIG. 2 is a drawing of one of the decoding circuit and a memory cell array of a conventional semiconductor memory device. 3 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, which is a block diagram of a schematic structure of a NAND cell EEPROM, and FIG. 4A is a NAND cell of the memory cell array shown in FIG. 3 Figure 4B is a plan view of a part of the pattern. Fig. 4B is an equivalent circuit diagram of a nanD cell portion of the 1-cell array shown in Fig. 3. Fig. 5A is a cross-sectional view taken along line 5A-5A of Fig. 4A. A cross-sectional view taken along line 5B-5B. FIG. 6 is an equivalent circuit diagram of the above-mentioned NAND cells arranged in a matrix memory cell array. FIG. 7 is a column decoding of a semiconductor memory device according to the first embodiment of the present invention. 12- This paper Standards apply to Chinese National Standard (CNS) A4 specifications (210X297 public love) 527728 A7

527728

FIG. 19 is a diagram showing a second example of a memory cell array J and a row arrangement of a horse memory road and a shape of a η_well region of a semiconductor memory device according to an embodiment of the present invention. FIG. 20 is the present invention &amp; The block arrangement of the memory cell array and the column decoding circuit of the semiconductor memory device in accordance with the morphology, and the third example representation of the shape of the η-well region are shown in FIG. 21 and FIG. 21A to 2E, each being the first of the present invention! The explanatory diagrams of the block arrangement and the shape of the n · well region of the semiconductor memory device of the fourth to fourth embodiments and the semiconductor memory device of other plural embodiments are illustrated in FIG. 22. 4 is a circuit diagram of the structure of a block address decoding section and a voltage switching circuit in a column decoding circuit of a semiconductor memory device of another embodiment, or a semiconductor memory device of other plural embodiments. (2) Circuit diagrams of the second structure of the block address decoding section and the voltage switching circuit in the semiconductor memory device of the fourth embodiment and the decoding circuits of the semiconductor memory devices of other plural embodiments. The circuit diagrams of the third structure of the semiconductor memory device of the fourth to fourth embodiments of the present invention, the decoding circuit of the semiconductor memory device of other plural implementations, the block address zemao and the voltage switching circuit, Figure 2 5 shows the semiconductor memory devices of the first to fourth embodiments of the present invention, and other semiconductor memory devices in a plurality of embodiments. Decoding circuits =, block address decoding And the circuit diagram of the fourth structure of the voltage switching circuit, FIG. 26 is a block diagram of the semiconductor memory device in most other embodiments, and a diagram illustrating the configuration of the block and the shape of the η-well region. FIG. 2 7 is the list of other semiconductor memory devices in most other forms. -14-Compatible with paper standards S ® Home Standard (CNS) A4 specification (⑽X 297 public luxury) 527728 A7 B7 V. Description of the invention (12) Block configuration of the road And η-well region shape, FIG. 28 is a block configuration of a column decoding circuit of a semiconductor memory device in most other embodiments, and η-well region shape is illustrated. 'Figure 2 9 A and 2 9 Each of Β is an explanatory diagram of a block arrangement of a decoding circuit of a semiconductor memory device in many other embodiments and a shape of an η-well region. FIG. 30 is a translation of a semiconductor memory device in a fifth embodiment of the present invention. Circuit diagrams of other configuration examples of the code circuit. FIGS. 31A to 31D are circuit diagrams of specific configuration examples of the voltage switching circuit of the circuit shown in FIG. 30. FIG. 3 2 is a list of the semiconductor memory device according to the sixth embodiment of the present invention. Decode Circuit diagrams of other configuration examples of the circuit 'FIGS. 33A to 33D are circuit diagrams of specific configuration examples of the voltage switching circuit of the circuit shown in FIG. 32' FIG. 34 is an explanatory diagram of a semiconductor memory device according to another embodiment of the present invention. It is a circuit diagram showing a circuit part that supplies a high voltage to the voltage switching circuit of the foregoing embodiments, and FIG. 35 is an explanatory diagram of a semiconductor memory device according to another embodiment of the present invention. The circuit diagram of the voltage switching circuit supplied to the high-voltage circuit is drawn out. Figure 36 is an equivalent circuit diagram of a memory cell array of a NOR cell EEPROM, and Figure 37 is an equivalent circuit diagram of a memory cell array of a DINOR cell EEPROM, w Fig. 38 is an equivalent circuit diagram of a memory cell array of an AND cell EEPROM, and Fig. 39 is a memory cell array of an N Ο R cell EEPROM with a selection transistor -15- This paper applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) 527728 A7 ^ ___ B7 f Invention Note (Is) ^-Equivalent circuit diagram of the column. Detailed description of the invention FIG. 3 is a block diagram for explaining a schematic structure of a semiconductor memory device according to an embodiment of the present invention, which is a NAND cell type EEPROM. Yu ^ memory = array 1 ο 1 connected bit line control circuit (sensor amplification and data latch) ι〇2, which is used for data writing, reading, re-writing and discrimination (German Office) reading By. This bit line control circuit 102 is connected to the data input / output buffer 106, and receives the output of the row decoding circuit 103 as an input. The row decoder 103 receives the address from the address buffer 丨 〇4. Signaler. In addition, the memory cell array i 〇i is connected: a column decoding circuit 丨 05, which is used to control the control gate and select the gate; and a substrate potential control circuit 107, which is used to control the formation of the memory The potential of the p-type silicon substrate (or P-type well region) of the cell array. In addition, during the data writing operation, a writing high voltage generating circuit 109 and a writing voltage are provided in order to generate a writing high voltage Vpp (about 20v) and an intermediate voltage Vmg (about ιv). The intermediate voltage generating circuit 110 is again provided to generate a reading intermediate voltage Vread when a shell material is out, and a reading intermediate voltage generating circuit i 丨 i is provided. In addition, at erasing 2, in order to generate erasing high voltage Vpp (approximately 20V), a erasing high voltage generating circuit 112 is provided. The bit-line circuit 丨 〇2 mainly includes a CMOS flip-flop (flip_fi). p), the latching of data for writing purpose, the sensing action for reading the bit line potential, or the sensing action for judging reading after writing, and the latch for rewriting data. 4A and 4B are each a pattern plan view and an equivalent circuit diagram of a NAND cell portion of the above-mentioned memory cell array. Figures 5A and 5B are shown in Figure 4-8 and 5-8. -16- This paper size is applicable _ Tsukasa Standard (CNS) A4 specifications (21GX29; ^ 527728 A7 B7 V. Description of the invention (14) 5 A line, and 5 B- A cross-sectional view taken along line B. On the p-type broken substrate (or p-type well region) 11 surrounded by the element separation oxide film 2, a memory cell array including a plurality of N AND cells is formed. If one looks at one NAND cell, In this embodiment, 8 memory cells are connected in series to form a NAND cell. The memory cells are respectively formed on the substrate 11 through a gate insulating film 13 to form a floating gate 14 (⑷, 142, ..., 148). A control gate 16 (= word line:%, 162, ..., 168) is formed thereon with an insulating film 5 interposed therebetween. The source of the memory cells and the n-type diffusion layer 19 (19., ...) ..19ι〇) are connected in the form of neighbors sharing with each other, so that the memory cells are connected in series. On the drain side and source side of the NAND cell, there are selection gates I%, 109 and 14ι0, 1610. It is formed at the same time as the floating gate and the control gate of the memory cell. The substrate 11 on which the element is formed is covered with a CVD oxide film 17 and a bit line 18 is arranged thereon. The bit line 18 is connected to one end of the NAND cell. The side diffusion layer 19 is in contact. The control gates i 6 of the NAND cells parallel to the column direction are commonly configured as the control gate lines CG (1), CG (2), ... 00 (8). The Wait for the control gate system to become the Feng line. The selection gates I%, I69, and 1410 and 1610 are each provided as the selection gate lines SG (1) and SG (2) that are continuous in the column direction. Figure 6 shows this NAND cell matrix. Equivalent circuit of a matched memory cell array. A group of NAND cells that share the same word line or selection gate line is called a block. The area enclosed by the dotted line in Figure 6 is defined as 丨 blocks. In general readout · During the write operation, only one of the plurality of blocks is selected (called a "select block"). Fig. 7 shows a structure of a part of a decoding circuit and a memory cell array of the semiconductor memory device according to the first embodiment of the present invention. For example, Figure 7 shows the case where the components in the circuit of block i are arranged on both sides of block 2 of memory cell -17- This paper size applies to China National Standard (CNS) A4 specification (210X297 public director) 527728 A7 B7 V. Description of the invention (15) Structure. The characteristics of the circuit shown in Figure 7 are: control gate lines CG (1) to CG (8) and select gate lines SG (1), SG ( 2) The transistors QNO ~ QN10 connected to it are only η-channel type; the transistors QNO ~ QN8 connected to the control gate lines CG (1) ~ CG (8) are connected to one control gate line; Between the output node N 1 of the voltage switching circuit 5 4 A and the power node VPPRW, PMOS transistors QP11 and QP12 are set. The voltage switching circuit 54A is used to set the control gate line CG (1) ~ CG (8) or select the gate line. The gate voltage of the transistors QNO ~ QN10 connected to SG (1) and SG (2). That is, the current paths of the NMOS transistors QN1 to QN8 are connected between the control gate lines CG (1) to CG (8) and the signal input nodes CGD1 to CGD8. In addition, a current path between the gate line SG (1) and the signal input nodes SGD and SGDS is connected to each of the NMOS transistors QNO and QN9. A current path of the NMOS transistor QN10 is connected between the selection gate line SG (2) and the signal input node SGS. The structure of the voltage switching circuit 54A includes: PMOS transistors QP11, QP12, NMOS transistors QN11, QN12, and inverter 55. The PMOS transistors QP11, QP12, and NMOS transistors QN11 and QN12 are connected as flip-flops 56. One end of the current path of the PMOS transistors QP11 and QP12 and the back gate are each connected to one power node VPPRW. The current paths of the NMOS transistors QN11 and QN12 are connected to the other end of the current paths of the PMOS transistors QP11 and QP12 and the other power node, for example, between ground points. The gate of the PMOS transistor QP11 is connected to the other end of the current path of the PMOS transistor QP12 and the node N1, and the gate of the PMOS transistor QP12 is connected to the other end of the current path of the PMOS transistor QP11. Inverter 5 5 of -18- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 527728 A7 B7

The output terminal is connected to the gate of NMOS transistor QN12, and the input terminal is connected to the gate of NMOS transistor QN11. The first input terminal of the NAND gate 57 is supplied with a signal RDEC, and the second through fourth input terminals are each supplied with signals RA1, RA2, RA3. The output terminal of this NAND gate 57 is connected to the input terminal of the inverter 58 and the node 1 ^ 2. In addition, the output terminal (node NO) of the inverter "is connected to the input terminal of the inverter 55 and the gate of the 1 ^^ 3 electric body QN11. Also, the signal RDEC in Fig. 7 is a column decoding start. The signal is Vcc in the general data writing = · reading · erasing action, and 0v in the non-acting action: RA1, RA2, and RA3 are block address signals, and all are VCC in the selected block. In the non-selected block, at least i are 0v. Therefore, only the node N0 of the selected block in the action is Vcc. In the non-acted or non-selected block, the node N0 is always kept as 0v. The timing table of the data writing, data reading, and data erasing operations in the case where the under table π uses the circuit of FIG. 7 is shown in FIGS. 8 to 10. The following briefly describes each operation (timing. Also, the following figures 8 and 9) The data read and write operations are described by taking the case of selecting the control gate line CG (2) <among the eight control gate lines CG⑴ ~ CG⑻ in the selection block as an example, but the case of selecting other control gate lines is also Figure 8. In the operation of writing the required data, after the operation starts, first, select the column code circuit of the block. In the selection state, the node N 0, n operation or V ..., and the node N2 becomes 0 V. Also, the written data is &quot; 〇, and the bit line of the data is self-charged to Vcc, and the block in the block is selected. sg⑴ becomes. Then, the power node VPPRW series Vcc becomes (20V + Vtn) (where vth is -19- 527728 A7 B7 V. Description of the invention (17) Directly connected to the control gate line CG (1) ~ CG (8) The NMOS transistor QN1 ~ QN8 is near the threshold voltage), so that the output node N 1 of the voltage switching circuit 5 4 A also becomes (20V + Vtn) from Vcc. Then, the signal input node CGD2 changes from 0V to 20V, the signal After the input nodes CGD1, CGD3 ~ CGD8 have changed from 0V to 10V, the gate voltage of the NMOS transistor connected to the control gate line is (20V + Vtn) at this time, so the voltage is transmitted from the signal input node CGDi to the control gate line CG ( i), and the potential does not drop, the control gate line CG (2) becomes 20V from 0V, and the control gate lines CG (1), CG (3) ~ CG (8) become 10V from 0V. At this time, "1" The channel voltage Vchannel of the NAND cell in the selection block connected to the write bit line is fixed at 0 V, and "n" is n in the selection block connected to the write bit line. The voltage Vchannel of the channel part of the AND cell rises to about 8 V due to the influence of the capacitive coupling with the control gate line. By keeping in this state for a period of time, the floating gate of the memory cell with data written as π 1 π is injected with electrons. Perform data writing. Then, after all the control gate lines CG (1) to CG (8) in the selected block become 0 V, `` 0 '' data is written into the bit line or the selection gate line SG (1) 0V. In addition, the power node VPPRW also becomes 0V. Finally, the source line (Cell_Source) becomes 0V, and the nodes NO, Nl, and N2 become 0V, 0V, and Vcc respectively. The data writing operation ends. In the data reading operation shown in FIG. 9, after the operation starts, first, select The decoding circuit of the block column is selected, and the node N 0, n 1 or V cc and the node N 2 become 0 V. In addition, the bit lines for data reading are pre-charged to Vcc. Next, the power node VPPRW or node N is 10% (4V + Vtn). In addition, the signal input nodes CGm, cgd3 ~ CGD8 -20-This paper size applies Chinese National Standards (CNs) A4 specifications (210 X 297 public) (Centi) 527728 A7 ______B7 V. Description of the invention (18) or the signal input node commits 0, 3 and still becomes 4V from 〇 ¥. After the signal input node CGD2 is fixed at 0V, the control gate or selects the NMOS connected to the gate. Because the high voltage of 4V plus the impeding voltage is applied to the gate of the sun, the voltage is transmitted to the control gate line or the selected gate line without potential reduction. Therefore, at this time, the non-selected control gate lines CG (i), CG (3) ~ CG (8), selection gate lines, and SG⑺ in the selection block have become 4V from 0v, and the selected control gate The line is fixed at ov. By staying in this state for a while, the data of the selected cell is read out. Then, the control gate lines CG (1) to CG (8) and the selection gate lines sg (1) and SG (2) in the selected block all become ον. In addition, the power node VPPRW | (4V + Vtn) becomes Vcc, bit 7G line becomes 0V, and nodes N0, N1, and N2 become 0V, 0V, and Vcc, respectively. Accordingly, the data reading operation ends. In the data erasing operation shown in FIG. 10, after the operation starts, First, the selection code of the block code circuit is selected, and the nodes N 0 and N 1 become V cc and the node N 2 becomes 0 V. In addition, the signal input nodes sgd, SGS, and SGDS all become Vcc, so the block is selected. Both the selection gate line SG (1) and the selection gate line (2) of the non-selected block are charged to (Vcc_Vtn) and become floating. Also, at this time, in the non-selected block All the control gate lines or selective gate lines SG (2) are kept at about 0V, and then they are directly floated. Then, the p-well block (Cell-pwell) constituting the memory cell array is changed from 0V to 20V. The selection gates SG (1), SG (2) in both the selected and non-selected blocks in the floating state or the control gates in the non-selected blocks are all related to the P-type wells. The effect of the capacitive coupling of the block rises to about 20V, and only the control gate line in the selected block is fixed at 0V. By maintaining in this state for a period of -21-This paper standard applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 527728

= Κτ From the memory cell floating gate in the selected block to the (Tv sub ,, and / or data erasure of the p-type well area. Then, according to the P-type well 11 domain, it becomes' Yu Zhezhong <select block · The selection gates SG (1) SG (2) in both non-selected blocks or the control gate lines in non-selected blocks are all 'reduced to approximately' ~ Vee voltage due to the effect of being far away from the p-type well block, It is fixed: at 0V. Finally, the nodes N0, ni, and N2 each become ov, ov, and Vcc, and the material erasing operation is completed. As above, in the decoding circuit shown in FIG. ^ When the material is bought, the maximum voltage of the power node vppRw is higher than the highest voltage of the applied & system and the spring selection gate line by vt η (electricity of the transmission voltage QNO ~ QN1. The limit is 値High power calendar with more than ten days, even if the control line is not selected. The transistor connected to the idle line is only a MOS transistor. It can also apply high voltage for writing or high voltage for reading without reducing the potential. Controlling the brake wire can achieve highly reliable operation. J, the transistor connected to the control brake wire is set to WNM0S Tun India Sa 彳 to achieve a small number of TG Decoding circuit, because the pattern area of the column decoding circuit is reduced to reduce the size of the chip, which can reduce the cost of the chip. The voltage switching circuit 54A (which is connected to the control gate or the selection gate by the electric circuit) The pM0s transistor 0pii, 0P12 of the opposite polarity, output "high" (High level voltage), can form a voltage switching circuit 54 with a small number of components and a small area for pattern 5, and can achieve the number of components The column decoding circuit with a small area and a small area for the pattern 5 can reduce the cost of the wafer because the pattern area of the column decoding circuit is reduced to reduce the size of the wafer. FIG. 11 shows the generality of the present invention. ; Columns of Semiconductor Memory Devices-22-

527728 A7 B7 V. Description of the Invention (20) Examples of the structure of the other parts of the decoding circuit. The part of the circuit of Fig. 1 different from that of Fig. 7 is the circuit structure of the voltage switching circuit 5 4B. An empty NMOS transistor QD1 is provided between the power node VPPRW and the transistors QP11 and QP12. The timing chart showing the operations of data writing, reading, and erasing when the circuit of FIG. 11 is used is the same as that of FIGS. 8 to 10. The advantages obtained by providing the transistor Q P 1 will be described below. In the circuit of FIG. 7, the potential level of the direct power supply node VPPRW is applied to the sources of the PMOS transistors QP11 and QP12 or to the n-well region constituting QP11 and QP12. It has nothing to do with the selected block or the non-selected block. The source and n-well regions of the transistors QP11 and QP12 in all the blocks must be charged to the potential level of the power node VPPRW. Generally, the number of blocks in a chip ranges from several to several. The source or n-well area of hundreds to thousands of components is charged at the same time, so that the capacitance of the power node VPPRW becomes very small. Great tadpole. The data write operation or read operation is because the boost voltage of (20V + Vtn) or (4V + Vtn) is applied to the power node VPPRW. If the capacitance of the power node VPPRW becomes larger, it will generate a boost voltage generating circuit. Problems such as increased area, increased power consumption, and longer time required for charging the boosted voltage result in longer operation times. On the other hand, in the circuit of FIG. 11, the voltage of the node NO in the selection block is “high” (male §11) level (= Vcc), so it is input to the node N of the gate of the transistor QP1. The voltage of 1 becomes "high" level (= VPPRW potential level), the source of transistor QP11, QP12 · η well potential, that is, the potential of N3 becomes "high π level (= VPPRW potential level). The transistor QP 1 is irrelevant, and can realize the actions of Figure 8 to Figure 10. In the non-selected block of the circuit of Figure 11 when used, -23- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 Mm) 527728 A7

527728 A7 B7 V. Description of the Invention (22) The structure of the switching circuit 54C includes: empty NMOS transistor QD2, PMOS transistor QP13, and empty NMOS transistor QD3, QD4. One end of the current path of the NMOS transistor QD2 is connected to the power node VPPRW, and the gate is connected to the node N1. One end of the current path of the PMOS transistor QP13 and the back gate are connected to the other end of the current path of the NMOS transistor QD 2, the other end of the current path is connected to the node N 1, and the gate is connected to Output of N AND gate 57. One end of the current path of the above NMOS transistor Q D 3 is connected to the node N 1, and the gate is applied with a power supply voltage Vcc. One end of the current path of the NMOS transistor QD4 is connected to the other end of the current path of the NMOS transistor QD 3, and the other end of the current path is connected to the output end of the inverter 58. The gate is supplied with the signal TRAN. . The operation waveform of the circuit in FIG. 13 is the same as the waveforms shown in FIGS. 8 to 10, and the voltage of the node N 4 in FIG. 13 is the same as the node N 3 in FIG. 11. Therefore, in the case where the circuit of FIG. 13 is used, it is the same as the case of using the circuit of FIG. 11 in the selection block. Between non-selected blocks, the voltage of node N 4 is different, that is, the voltage of the source of PMOS transistor QP13 or the area of η well that transmits "high" level (= boosted voltage) to node N 1 is selected or not. The selected blocks are different. Therefore, the η well structure as shown in Figure 1 2 B can be used, so the load capacitance of the boosted voltage can be reduced. In addition, the signal TRAN is usually used as 0V fixed, and the node NO in non-selected blocks For 0V, 0V is transmitted to node N1 via the empty NMOS transistors QD4 and QD3. Also, in the selection block, node N 0 = Vcc, node N 1 2 Vcc, and NMOS transistor QD 4 becomes “OFF” ", Keep the" high "level of node N1. -25- This paper size applies to China National Standard (CNS) A4 (210X 297mm) 527728

The other advantages of the above-mentioned circuit of FIG. 13 are: i. The number of components constituting the voltage switching circuit 54C is less than that of the circuit in FIG. The potential difference between the source · D ·· n well regions becomes smaller. Regarding the latter, in the transistor? 13 is, in the case of, on, has always been the source = drain well area, in the case of "off", it is the source = η well area (quasi V td is based on the gate voltage of QD 2 = 0v, can be The highest voltage transmitted by the transistor qp 2 is usually a voltage below Vcc), and it is pumped. Therefore, whether or not a high voltage (approximately 20v) for writing is applied, the source, pump and η well area Even the highest potential difference will only reach about Vw. In the above embodiment, as shown in FIGS. 7, 丨 丨, and 丨 3, it is the case in which the decoding circuit of the control gate line and the selection gate line in the driving block 1 is arranged on both sides of the memory cell array. The invention is illustrated as an example, but in other cases, such as shown in FIG. 14, the invention is also effective in a case where a column decoding circuit corresponding to one block is arranged on one side of the memory cell array. Although the circuit structure of the voltage switching circuit 5 4 D is not specifically shown in FIG. 4, various circuits can be used for the circuits shown in FIGS. 7, 1 i, and 3. Next, the arrangement examples of the column decoding circuits are shown in Figs. 15 to 17. Fig. I5 shows that the arrangement of the control gate and selection gate line decoding circuits in one block is arranged on both sides of the memory cell array, which is equivalent to the performance of the implementation of Figs. Figures 16 and 17 both show the case where the column decoding circuits corresponding to the i blocks are arranged on one side of the memory cell array, which is equivalent to Figure 14. As the width (spacing) of the decoder pattern of the block-by-block column, in the case of using the method of FIG. 15, it is a NAND cell length (a NAND cell bit line direction length), and. In the case of using the method of FIGS. 16 and 17, it is two 1 ^ eight ^^ £ &#; Cell • 26-

527728

It is long to ensure a wide pitch. Adding the η well region for P M s transistor formation to the above figures 5 to i 7 is not shown in FIGS. 18 to 20. 15 to 17 each correspond to FIGS. 18 to 20. As can be seen from FIGS. U to 20, in the case of using the method of FIG. 14, the pitch for pattern formation of the column decoding circuit is doubled compared to the case of using the drawings &quot; and Fig. 13. The PMOS circuit in this case The distance between the n-well regions for crystal formation is also 2-7. As a result, design rules can be relaxed, and chips with higher reliability and better yields of 5F can be realized. In the future, the design rules can be further reduced. In the case of using the method of Figure ^, it is more likely than the method of Figure u and Figure 13 to divide the η region into a parent block (or High accuracy). However, the above-mentioned arrangement of the η well region may also have an arrangement method other than the above-mentioned method. For example, it may be arranged as shown in Figs. 2A to 2E. Figures 2 1 Α to 2 1 Ε are representations of column decoding areas. Only blocks adjacent to the patterning area of the column decoder are shown. Fig. 21A shows the method of Figs. 18, 19, and 20 (that is, the method of applying the method of Fig. 21A to the block configuration of Figs. 15 to 17).

Within each of Block-i and Block-j, n-well regions NWi and NWj are formed. Fig. 2IB, 21C, and 2ID are for the decoder area corresponding to each block, and the η well area NWi and NWj are formed across the plurality of blocks 31 ° (^-丨, Blck-j). In the case where the design rules around the areas NWi and NWj cannot be included in the interval of 1 block for the formation of the column decoder, as shown in Figure 2 丨 B, 21C, and 2 1 D, in the area of 2 blocks The method of forming a η well area is effective. In the future, when the design rules are changed severely, as shown in Figure 2 1 ε, as long as it is in 4 blocks -27- This paper size applies the Chinese National Standard (CNS) Α4 specification (210 X 297 (Mm)

Binding

527728 A7 ______ V. Description of the invention (25) It is only necessary to form i well areas Nwi ~ nwi in the area of B1ock-i ~ Block-L, as in the area of 3 or more blocks Various methods can be applied to form one 11-well area. In this way, the method of Figs. 21B to 21E is applied to the area configuration of Figs. ^ To 口, which is very effective when the design rules are reduced. In particular, as described above for the PMOS transistors QP11, qP12, qpu, etc., it is difficult to narrow the design rules in the n-well area where a voltage higher than the power supply voltage (boost voltage, etc.) is applied. A method that works great ... 11, 12A, 12B, 13, 14 and 18 and 20, and 21A to 2 1E, it is explained that the PMOS transistor formation n is provided for a block-by-block decoding circuit at a ratio of i. Implementation of the situation in the well area. However, the present invention is also effective in other cases, such as a case where there are η well regions between adjacent blocks. Figures 22 to 25 show the address decoding unit and voltage switching in the column decoding circuit of the two adjacent columns showing the case of the above circuit and the case where there is a η-well region between adjacent blocks. An example of a circuit structure of the circuit section 54 (54A, 54B, 54c, 54D). FIG. 22 corresponds to the circuit of FIG. 11, and FIG. 23 corresponds to the circuit of FIG. 13. Fig. 24 is an example of a circuit structure in the case where there are n well regions between adjacent blocks, and the circuit of Fig. 11 is used as a basic example. Fig. 25 is an example of a circuit structure in the case where there are η well regions between adjacent blocks, and the circuit of Fig. 13 is used as a basic example. Figure 24 is based on Figure 22, although the number of components has not increased, Figure 25 is for Figure 23, and an empty NMOS transistor is added to each block. -28- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 527728 A7

When using the Taimei Road shown in Figs. 24 and 25 to go to the road, if either or both of the two blocks of the η well area are selected, the η well area becomes Lightning pressure during selection (20V + Vtn when writing, 4V + Vtn when reading out the neck and Vc when erasing, Vc when erasing; otherwise, n-well area humming) Voltage Vtd. In this October condition, the boosted voltage is applied to the common open area (including only the selection area). Therefore, the boosted voltage of the load is larger than that of the private situation (equivalent to Figure 12). In addition, FIGS. 22 to 25 (adjacent blocks) are described by taking the case where blocks of consecutive addresses are adjacent to each other in the column decoding circuit area as an example. Invention, but even in the case of blocks with discontinuous addresses, the case where the n-well region is common between adjacent blocks in the 歹 decoding circuit region, the present invention is effective. Tables 28 to 28 show examples of the formation of the n-well area when the circuit structure shown in Figs. 24 and 25 is used, which is a structure with a total of one 11-well area between adjacent blocks. Figs. 24, 25, and 26 to 28 are used. This method can be compared with the case of using Figures 22, 23, and 18 to 20 to widen the distance between the well areas of η, so it can be eased. The design rules for the perimeter of the well area can improve reliability and yield. Especially, such as The PMOS transistor QPU, (^ 12, (^ 13, etc.) are applied with a voltage (boost voltage, etc.) higher than the power supply voltage in the well region. Because the design rules are difficult to reduce, it is extremely effective to increase the spacing and relax the design rules according to the above method. In addition, if the method of Figs. 24, 25, and 26 to 28 is used, the n-well area is halved, and a pattern of a reduction column decoding circuit is provided. The advantage of area. In addition, the method of easing the design rules is shown in Figure 29 Α and 2 9B. There is a method to set the η well area common to the two blocks at a distance of 3 to 4 blocks. 〇 Pair of deer-29- This paper size applies Chinese National Standard (CNS) Α4 specification (210 X 297 mm)

Line 527728 A7 B7 5. The idea of the same way as in Figures 21B to 21D of the description of the invention (27). The method of Figures 29A and 29B is also very effective. Fig. 30 shows a configuration example of other parts of the decoding circuit of the semiconductor memory device according to the fifth embodiment of the present invention. The circuit shown in FIG. 30 is a structure in which a voltage switching circuit 5 4 E is added to the circuit shown in FIG. 14. That is, the column decoder start signal RDEC is supplied to the first input terminal of the NAND gate 57, and the area address signals RA1, RA2, RA3 are supplied to the second and fourth input terminals, respectively. The output terminal of the NAND gate 57 is connected to the input terminal of the inverter 58 / the output signal ini of the inverter 58 is supplied to the voltage switching circuits 54D and 54E. The voltage switching circuit 54E is applied with a voltage Vm as an operation power supply voltage. The output signal out 1 of the voltage switching circuit 5 4 E is supplied to the voltage switching circuit 54D. Since other circuit portions are the same as those shown in FIG. 14, the same portions are denoted by the same reference numerals and detailed descriptions thereof are omitted. 31A to 31D are circuit diagrams each showing a specific configuration example of the voltage switching circuit 5 4 E of the circuit shown in FIG. 30 described above. The output signal in 1 of the inverter 5 8 is input to any of the voltage switching circuits 5 4 E. When the signal in 1 is at a high level, 0V is output, and when the signal i η 1 is at a low level, V m is output. Signal out 1. The circuit structure shown in FIG. 31A includes an inverter INVa, NMOS transistors QN13, QN14, and PMOS transistors QP14, QP15. The output signal in 1 of the inverter 58 is supplied to the input terminal of the inverter INVa and the gate of the NMOS transistor QN14. The output terminal of the inverter INVa is connected to the gate of the NMOS transistor QN13. The sources of the NM0S transistors QN13 and QN14 are connected to the other power node such as a ground point. Between the drain and voltage nodes V m, the drain and source of the PMOS transistors QP14 and QP15 are connected to each other. -30- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 527728 A7 __ B7 V. Description of the invention (28) The gate of the above PMOS transistor QP14 is connected to the pM0s transistor at 15 and The common connection point of the NMOS transistor QN14, the gate of the pM0s transistor QP15, is connected to the common connection point of the PM0S transistor (^ 14 and 1 ^^ 1 (^ transistor QN13). Also, the above The output signal 0ut 1 obtained from the common connection point of the transistors qp15 and 卩 14 is supplied to the input terminal of the voltage switching circuit 54D. In addition, the structure of the circuit shown in FIG. 31B includes an inverter INVb and an NMOS circuit. Crystals QN15, QN16, PMOS transistors QP16, QP17, and empty-type NMOS transistor QD5. Output signals inl of inverter 58 are each supplied to the input of inverter INVb and the gate of NMOS transistor QNi6. The output terminal of the phase INVb is connected to the gate of the NMOS transistor QN15. The sources of the NMOS transistors qN15 and qN16 are connected to the ground in common, and each drain is connected to the PMOS transistor QP16 and (^ 17). The above PMOS The gate of transistor QP16 is connected to PMOS transistor QP17 and NMOS transistor Q N16 common terminal, the gate of the above pMOS transistor Qpi7 is connected to the common connection point of the drain of PMOS transistor QP16 and NMOS transistor QN15. The source and voltage node Vln of the above PMOS transistor QP16 and QP17 In between, the drain and source of the empty NMOS transistor QD5 are connected, and its gate is connected to the common connection point of the drains of the transistors QP17 and QP16. Furthermore, the drains of the QP17 and QP16 transistors are connected in common The output signal out 1 obtained at the point is supplied to the input terminal of the voltage switching circuit 5 4 d. The structure of the circuit shown in FIG. 31C includes: nmOS transistor QN17, PM0S transistor QP18, and empty NMOS transistor QD6. The above The current paths of the transistors QN17, QN18, and QD6 are connected to the ground point with the voltage -31-527728 A7 B7. 5. Description of the invention (29) The node V m is connected in series. The output signal i η of the inverter 5 8 is It is supplied to the gates of the transistors QN17 and QN18. The gate of the transistor QD6 is connected to the common connection point of the drains of the transistors QN17 and QN1 8. The drains of the transistors QN17 and QN18 are also connected. Output signal from common connection point o Ut 1 is supplied to the input terminal of the voltage switching circuit 5 4 D. In addition, the structure of the circuit shown in FIG. 31D includes an inverter INVd, an NMOS transistor QN18, a PMOS transistor QP19, and an empty NMOS transistor QD7. The output signal ini of the inverter 58 is supplied to the input / input terminal of the inverter INVd and the gate of the PMOS transistor QN19. An output terminal of the above-mentioned inverter INVd is connected to one end of a current path of an NMOS transistor QN18, and a gate of this transistor QN18 is applied with a power supply voltage Vcc. Between the other end of the current path of the transistor QN18 and the voltage node Vm, the current paths of the PMOS transistor QN19 and the empty NMOS transistor QD7 are connected in series. The gate of the transistor QD7 is connected to the connection point of the current path of the transistor QN18 and QN19. The output signal out 1 obtained from the connection points of the current paths of the transistors QN18 and QN19 is supplied to the input terminal of the voltage switching circuit 5 4 D. In addition, the circuit configuration of the voltage switching circuit 54D may be any of the following circuits: voltage switching circuit 54A in the circuit shown in FIG. 7, voltage switching circuit 54B in the circuit shown in FIG. 11, and voltage switching in the circuit shown in FIG. 13. Circuit 54C, or any one of the modes shown in Figs. 22 to 25. The voltage of the voltage node V m of the circuit shown in FIG. 30 above can be arbitrarily higher than the power supply voltage (or the power supply voltage of the NAND gate 57 or the inverter 58), and higher than the highest voltage level of the power node VPPRW (usually High voltage for writing Vpp -32- This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) 527728 A7

4 Ping) low voltage. In the case of using the method shown in FIG. 3G, the voltage level in the “high” state of the signal “2” of Hiroyuki in the two voltage switching circuits 541) is /. The voltage Vm in FIG. 30 is: , Non-selected block power: rise south to low voltage %%, so bluff 0Utl to Vm level. Therefore, the two signals are input to the voltage switching circuit 54D. ^ 十 之 = described in the circuit method of FIG. 30 In this case, it is particularly effective to switch. The switching circuit is the case where the switching circuit Me in the circuit shown in “13” or the circuit structure shown in FIGS. 2 3 and 25 is used. Next, the effect of the example in the case where the voltage switching circuit 54C in the circuit shown in FIG. 13 is used will be described. In the case of using the circuit structure shown in FIG. 3, the voltage input to the gate of the transistor QP13 in the column decoder corresponding to the non-selected block is raised from the power supply voltage to the Vm level. Can reduce the advantages of transistor QP13i leakage current. Generally, there are hundreds to tens of thousands of column decoding circuits in the chip. Even if the leakage current in the column decoding circuit is not large, the chip as a whole has a large leakage current. Therefore, using the leakage current reduction method of the circuit shown in FIG. 30 can achieve great political results. This result is not only in the case where the voltage switching% circuit 540 in the circuit shown in FIG. 13 is used in the voltage switching circuit 54D in FIG. 30, but the same can be obtained in the case of using the circuit method of FIGS. 2 3 and 25. The effect. In addition, the circuits shown in FIGS. 31B to 31D use an empty nmOS transistor QD5 to QD7. The maximum two 値 Vm 'ratios of the voltage levels applied to the transistors QD5 to QD7 are applied to the circuits shown in Figures 11 and 13, and Figures 22 to 25. -33- This paper scale applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) 527728 A7 B7 V. Description of the invention (31) The highest voltage level of the NMMOS transistor QD1 ~ QD4, the highest level of VPPRW (usually Vpp) )low. Therefore, the gate oxide film thickness of the transistors QD5 to QD7 can be made thinner than the gate oxide film thickness of the transistors to QD4. Therefore, the area of the transistors QD5 to QD7 can be reduced compared to the case where the gate oxide film is thicker (because the lower the maximum applied voltage, the thinner the gate oxide film thickness is, the larger the current per unit area of the transistor is. , The pattern occupied area of the transistor can be reduced). For the same reason, the transistor (^^ ~ (^^, (^^ ~ (^) can also be made thinner than the transistor QP11 ~ QP13, qN13 ~ qN18. Therefore, in this case The pattern occupancy area of the transistor can be made smaller than the thickness of the gate oxide film. Although it has been described so far using the fifth embodiment of FIGS. 30 and 3 1 to 3 1 D, the present invention can have various For example, when the circuit structure of FIGS. 32 and 33 to 33D is used, the present invention also has an effect. FIG. 3 shows the column decoding circuit of the semiconductor memory device according to the sixth embodiment of the present invention. An example of a part of the structure. The circuit shown in FIG. 3 and FIG. 2 respectively supplies the output signal ini of the inverter 58 and the output signal of the gate 57 of the circuit shown in the above FIG. 30 to the voltage switching circuit 54F. The output signals out 1 and out 2 of the voltage switching circuit 5 4 F are supplied to the voltage switching circuit 54D.-FIGS. 33A to 33D are circuit diagrams each showing a specific configuration example of the voltage switching circuit 5 4 F of the circuit shown in FIG. 32 described above. Equivalent voltage switching circuit $ * F, input signal ini of inverter 58 and output signal of NAND gate 57 2. In the circuits shown in Figures 33A and 33B, the signal inl is,, high, and level (signal -34-

527728 A7 B7 V. Description of the Invention (32) When the signal i η 2 is “low” level, the signal out 1 is 0 V, the signal out 2 is V m level, and the signal i η 1 is `` low '' When the level signal i η 2 is “high” level), the signal out 1 is at the V m level and the signal out 2 is at 0 V. Also, in the circuits shown in FIGS. 33C and 33D, the signal i η 1 is' f When the “high” level (signal i η 2 is “low” level), the signal out 1 is 0V and the signal out 2 is Vcc level, and the signal in 1 is “low” level (the signal i η 2 is “high”). f 'level), the signal out 1 is at V m level, and the signal out 2 is at 0 V 0 The structure of the circuit shown in Figure 33A includes: NMOS transistors QN13, QN14 and PMOS transistors QP14, QP15. Inverter 5 The output signal in 1 of 8 is supplied to the gate of NMOS transistor QN14, and the output signal in2 of NAND gate 5 7 is supplied to the gate of NMOS transistor QN13. The sources of the above NMOS transistors QN13 and QN14 are connected to the ground point Between the drain and the voltage node Vm, the PMOS transistors QP14, QP15i are connected between the drain and the source. The gate of the PMOS transistor QP14 is connected to the PMOS transistor QP15 and the NMOS transistor QN14. The common connection points of the drains of the transistors. In addition, the output signal out 1 obtained from the common connection points of the drains of the transistors QP15 and QN14, and the output signal out 2 obtained from the common connection points of the drains of the transistors QP14 and QN13i. It is supplied to the input terminal of the voltage switching circuit 5 4 D. In addition, the structure of the circuit shown in FIG. 33B includes: NMOS transistors QN15, QN16, PMOS transistors QP16, QP17, and empty NMOS transistor QD 5. Inverter 5 The output signal i η 1 of 8 is supplied to the gate of the NMOS transistor QN16, and the output signal in2 of 7 is supplied to the gate of the NMOS transistor QN15. The sources of the above NMOS transistors QN15 and QN16 are connected to Location, the drain is connected to the PMOS transistor QP16, QP17 -35- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7

V. Description of the invention (33 and core. The gate of the above PMOS transistor QP16 is connected to the common connection point of the drain of the PMOS transistor QP17 and the NMOS transistor QN16. The gate of the above PMOS transistor QP17 is connected to the pmos transistor QP16 and The drain of the NMOS transistor QN15 is between the source of the above-mentioned PMOS transistor QP16 and QP17 and the voltage node Vm. The drain and source of the empty NMOS transistor QD5 are connected, and its gate is connected to the transistor QP17. , QN16 common drain connection point. Also, the output signal out 1 obtained from the common drain connection point of the above-mentioned transistors qP17 and QN16, and output signal out obtained from the common drain connection point of the above-mentioned transistors QP16 and QN15. 2. Each is supplied to the input terminal of the voltage switching circuit 54D. The structure of the circuit shown in FIG. 33C includes: an inverter INVe, a NMOS transistor QN17, a PMOS transistor QP18, and an empty NMOS transistor QD6. The current paths of the crystals QN17, QP 18, and QD6 are connected in series between the ground and the voltage node Vm, and the output signal in i of the inverter 58 is supplied to the gates of the transistors QN17 and QP18. In addition, the above-mentioned transistors Gate connection of crystal 0D6 To the common connection point of the drains of the transistors qn17 and QP18. The output signal in2 of the NAND gate 57 is supplied to the input terminal of the inverter 1NVe. In addition, the drains of the transistors QN17 and QP18 are connected in common. The output signal out 1 obtained at the point and the output signal OUT 2 obtained from the output terminal of the above-mentioned inverter INVe are each supplied to the input terminal of the voltage switching circuit 54D. The structure of the circuit shown in FIG. 33D includes: Phaser iNVf, NMOS transistor QP18, PMOS transistor QP19, and empty NMOS transistor QD7 ° Inverter 5 8 The output signal in 1 is supplied to the PMOS transistor _ -36- This paper size applies to Chinese national standards ( CNS) A4 size (210 X 297 mm) 527728

= Two poles, the output signals w of N and 57 are each supplied to one end of the current path of N-Shan Jing_18 and the input of the inverter Li

= Between the other end of the private mud path and the voltage node Vm, the current path of the PMOS QP19 body and the empty Gujing transistor 01) 7 is connected. The gate of the transistor QD7 is connected to the transistor 卩 ^ 8 and (^ &gt; 19 <connection point of the current path. ", The output signal _ i obtained from the transistor QN18, QP1R, and HH / f, and from the above Each of the 仏 谠 out 2 output by the inverter INVk output ooli is supplied to the input terminal of the voltage switching circuit 5 4 d. In the case of using the circuit structure of the above-mentioned Fig. 32 and Fig. 33 (8 to 331), it also has the same characteristics as described above. 30 and 31A to 31D have substantially the same features as the aforementioned circuit structures. Also, the n-well regions of the PMOS transistors QP14 to QP19 used to constitute the circuits shown in FIGS. 31A to 31D and FIGS. 33 A to 33D are described in the case of the circuits shown in FIGS. 31A and 33B. For application of the voltage VPPRW in the n-well region, the aforementioned structure of FIG. 12A can be used. On the other hand, in the structures shown in Figs. 31B to 31D and Figs. 33B to 33D, the n-well voltage is not common. Figs. 12B, 18, 19, 20, 21A to 21E, 26, 27, 28, 29A, and The structure shown in 29B. Figs. 3 4 and 3 5 are for explaining a semiconductor memory device according to another embodiment of the present invention, and are circuit sections that apply a voltage VPPRW to the voltage switching circuits 5 4 (54A to 54D) of the aforementioned fifth to fifth embodiments. It is drawn out. These circuits are based on the signal Active, during stand-by and activation -37- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

527728 A7 _ B7 V. Description of the Invention (35) Switch the state of the power node VPPRW. That is, the structure of the circuit shown in FIG. 34 includes a high-voltage generating circuit 60, an inverter 61, a PMOS transistor QP20, and an empty NMOS transistor QD8. The output terminal of the above-mentioned high-voltage generating circuit 60 is connected to the power supply node VPPRW of the voltage switching circuit 54. Between this node VPPRW and the power supply voltage v c c, the current paths of the transistors QD8 and QP20 are connected in series. The gate of the pM0s transistor QP20 is supplied with a signal Active via an inverter 61, and the gate of the empty NMOS transistor QD 8 is supplied with a signal Active. In the above-mentioned structure, the signal Active is a signal of 0 V at the time of preparation and V c c level at the time of activation, and is generated based on, for example, a chip enable signal inputted from a / CE pin. The structure of the high-voltage generating circuit 60 described above is a non-operating state during standby. At the time of preparation, according to 0V of the above-mentioned signal Active, the transistor QP20 becomes the π off π (OFF) state, so the power node VPPRW becomes a floating state. On the other hand, when the signal Active becomes Vcc level and the transistor QP20 becomes f'on '(ON) state during activation, the node VPPRW is charged to the power supply voltage Vcc. Thereafter, according to the high-voltage generating circuit 60, the node VPPRW is set to a high voltage. In addition, the signal Active becomes 0 V, the transistor QD 8 is turned off, and the power node VPPRW is switched from the power source V cc. from. Therefore, the leakage current can be suppressed during the preparation, and the voltage rise of the power supply node VPPRW can be accelerated during the activation (the reason for high-speed charging to V c c). On the other hand, the structure of the circuit shown in FIG. 35 includes a high-voltage generating circuit 60 and an empty NMOS transistor QD9. Input to the high-voltage generating circuit 60-38- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7 B7 V. Description of the invention (36) The output end is connected to the voltage switching circuit 5 4 Power node VPPRW. The current path between transistor QD 9 is connected between this node VPPRW and power source V cc. Furthermore, a signal Active is supplied to the gate of the empty NMOS transistor QD9. Even in this structure, the same operation as that of the circuit of Fig. 34 described above is performed, and the same effect can be obtained. Although the present invention has been described using the embodiments, the present invention is not limited to the above-mentioned embodiments, but various modifications can be made. For example, in the above embodiment, the present invention is described by taking a case where a voltage of 0 V or more is transmitted to the selected word line, but when the polarity is opposite, that is, a case where a voltage of 0 V or less is transmitted to the selected word line The present invention is also effective. In this case, by changing the NMOS transistor in the voltage switching circuit to a PMOS transistor, and changing the PMOS transistor in the voltage switching circuit to an NMOS transistor, and the transistor connected in series with the word line The present invention can be applied to a method in which the NMOS transistor is changed to a PMOS transistor so that its polarity is reversed. In the above embodiment, the present invention is described by taking the case where the present invention is used in a column decoding circuit as an example, but in other cases, for example, in other peripheral circuits, the voltage switching circuit or characters in the above embodiment are used. Various changes can be made to the structure and connection relationship of the line-connected transistor and the case of voltage transmission. In the above-mentioned embodiment, a case where the number of memory cells connected in series in one NAND cell is eight is described, but even if the number of memory cells connected in series is not eight, for example, 2, 4, 1, 6, 2, 3, 6 In four cases, the present invention can also be used. In addition, in the case where the number of memory cells between the gate transistors is selected, -39- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 527728 A7 B7 ___ V. Description of the invention (37) The invention can also be used. Also, in the above embodiment, although the present invention is described by taking a NAND cell EEPROM as an example, the present invention is not limited to the above embodiment, and can also be used in other devices such as a NOR cell EEPROM, a DINOR cell EEPROM, and an AND cell. Type EEPROM, NOR cell type EEPROM with selection transistor, etc. Figure 36 shows an equivalent circuit diagram of a memory cell array of a NOR cell EEPROM. This memory cell array is arranged at the intersections of the word lines WLj, WLj + 1, WLj + 2, ... and the bit lines BLO, BL1, ..., BLm, and NOR cells MjO ~ Mj + 2m are set, and each NOR cell MjO The control gate of ~ Mj + 2m is connected to the word lines WLj, WLj + 1, WLj + 2, ... in each column, and the drain is connected to the bit lines BL0, BL1, ..., BLm in each row. The source is common Connect to source line SL. Fig. 37 is an equivalent circuit diagram of a memory cell array of DINOR cell EEPROM. The DINOR cell type memory cell array is provided with a DINOR cell corresponding to each main bit line D0, D1, ..., Dn. The structure of each DINOR cell includes: selection of gate transistors SQ0, SQ0, ..., SQn and memory cells M00 ~ M31n. The drains of the above-mentioned selection gate memory cells SQ0, SQ0 ..... SQn are each connected to the main bit lines DO, D1, ..., Dn, the gates are connected to the selection gate line ST, and the sources are each connected to a local (l 〇cal) bit lines LB0, LB1, ..., LBn. The drains of the memory cells M00 ~ M3 In are connected to the local bit lines LB0, LB1, ..., LBn in each row, and the control gates are connected to the word lines wo ~ W31 in each column. The source is connected to the source line SL in common. . Fig. 38 shows an equivalent circuit diagram of a memory cell array of an AND cell type EEPROM. Set each major bit line DO, D1, ..., -40 in the AND cell type memory cell array. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527728 A7 ______ B7 V. Description of the invention C 38)

Dn corresponds to AND cells. The structure of each AND cell includes: a first selection gate transistor SQ10, SQ11, ..., SQln; a memory cell M00 ~ M31n; and a second selection gate transistor SQ20, SQ21, ..., SQ2n. The terminals of the first selection gate transistors SQ10, SQ11,..., SQln are connected to the main bit lines DO, D1 ..... Dn, the gate is connected to the first selection gate line ST1, and the source is connected to Local bit lines 1 ^ 0, 1 ^ 1,. &Quot;, 1 ^ 11. Each memory cell] ^ 00 ~ 1 ^ 3111 The drain electrode is connected to the local bit lines LB0, LB1, ..., LBn in each row, the control gate is connected to the word lines W0 to W3 1 in each column, and the source is connected to the local Source lines L30, LSI, ..., LSn. The drains of the second selection gate transistors SQ20, SQ21 ..... SQ2n are connected to the local source lines LS0, LSI, ..., LSn, respectively. The gates are connected to the second selection gate line ST2, and the sources are connected in common. To the main source line MSL. Fig. 39 shows an equivalent circuit diagram of a memory cell array of a NOR cell EEPROM with a selection transistor. This memory cell array is formed by arranging a selection transistor SQ and a memory cell MC formed by a hand-held memory cell transistor M into a matrix. The drain of each selection transistor SQ is connected to the bit lines BL0, BL1, ..., BLn in each row, the gate is connected to the selection gate ST in each column, and the source is connected to the corresponding memory cell transistor μ Drain. The control gate of the above-mentioned memory cell M is connected to the word line W L in each column, and the source is connected to the source line S L in common. Please refer to "H. Onoda et al., IEDM Tech. Digest, 1992, ρ · 599-602" for the detailed description of DINOR cell EEPROM, and please refer to "η · Kume et al. , IEDM Tech. Digest, 1992, pp. 991-993 ,, -41-This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 527728 A7 B7 V. Description of the invention (39) Although the embodiments described above take the non-volatile semiconductor memory device that can be rewritten electrically as an example to explain the present invention, the present invention can also be used in other devices, such as other non-volatile memory devices or DRAM, SRAM, etc. Device. Although the present invention has been described using the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the implementation stage. The above embodiments include various stages. Various inventions can be obtained by appropriately combining the plural constituent elements disclosed ^ For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the solution of the present invention can be solved. In the case where at least one of the problems listed in the problem column can obtain at least one of the effects described in the effect column of the invention, the structure to be deleted can be extracted as an invention. As described above, according to the present invention, By providing a voltage switching circuit including a PMOS transistor in the column decoding circuit, even if the transistor connected to the word line is set as one word line in the column decoding circuit, it is only one NMOS transistor. In addition, the gate of the NMOS transistor can be set to a high voltage without providing a pump circuit. Therefore, the high voltage can be transmitted to the word line without reducing the potential, and a pattern area that can reduce the column decoding circuit can be obtained. In addition, a semiconductor memory device having a small pattern area can be realized, and a semiconductor memory device capable of realizing a low-cost and high-reliability chip can be obtained. In addition, a high voltage can be transmitted to the semiconductor device without reducing the potential. Character line, a semiconductor memory device can be obtained to achieve sufficient data writing. -42- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

527728 527728 Patent application 1L which has: memory cell array, which is a memory cell 1. ,, semiconducting, ………, are arranged into Xintong | Zhuang I /, Zigzag cell = zigzag line of the cell array, in addition to passing the voltage == the body circuit has: the first conductivity type complex number The first electric line says: "! ...", the-end of the path is directly connected to each word line. 2 conductive type &gt; 筮 〇., Inside; and when the voltage is transmitted, it is based on the selected The word line is carried out, followed by the above-mentioned! The connection between the electric θ 'and the selected word line; 5 is performed with the &lt; gate, and the word line selected with the opposite polarity to the first conductivity type is performed only on the first The first conductive type of the κ-day is performed by the body. Chuan Qiao, 2. For the semiconductor memory device of the first scope of the patent application, when the voltage transmission action of the word line is performed on the word line, Voltage. Brother 2 ... 'Transfer is more than the selected zigzag line 3. ^ Please refer to the semiconductor memory device of the first item of patent scope, which has a switching circuit, which is located in the decoding circuit of the front panel. 1 黾 The voltage is applied to the gate of the crystal; 述 The second transistor system is set in the voltage switching circuit described above. When the line performs voltage transmission operation, a voltage higher than the voltage of the line is input to the aforementioned voltage switching circuit, and the second transistor is transmitted to the first circuit connected to the selected word line via the ^ rule. Gate of the crystal. A -43 ------ i ----- Awl ^ -------- ^ --------- 1 .. (Please read the note on the back first Please fill in this page again) The K paper standard printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (21G X 297) 527728 Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economics A8 B8 C8 ^-~~-^ __ Patent application scope: The semiconductor memory device of item 3 of the patent claim is cleared, in which the two above = the circuit has a third transistor of the i-conductivity type, which is connected: '' Return to 2 The gate of the third transistor is set to the same potential as the gate of the crystal between the clad crystal and a voltage node higher than the voltage of the selected zigzag line. % 5 · ^ The scope of patent application! Item of the semiconductor memory device, wherein the aforementioned memory cell array is composed of a plurality of blocks, and each block is composed of a memory cell connected to one or a plurality of word lines. The circuit is located in each block. &quot; 6. ttPlease request the semiconductor memory device according to item 5 of the patent, wherein the well region formed by the aforementioned second transistor is an i-conducting type, and the well region is formed separately in each of the aforementioned blocks. 7 · = Semiconductor memory device in the scope of application for patent No. 5, wherein the well area formed by the aforementioned second electric body is the first conductive type, so that the two blocks adjacent to the aforementioned pattern area of the circuit = circuit are adjacent. A ratio of 1 is allocated to form the aforementioned well area, and only elements in the column decoding circuits corresponding to the aforementioned 2 blocks are formed in the aforementioned well area. 8. The semiconductor memory device according to item 5 of the scope of patent application, wherein the elements constituting the aforementioned row of decoding circuits corresponding to the aforementioned blocks are collected and arranged at one end side of the word line of the aforementioned blocks. 9 · If the semiconductor memory device according to item 丨 of the patent application scope, wherein the transistor directly connected to the aforementioned word line has only the first conductivity type. 10. The semiconductor memory device according to item 1 of the scope of patent application, wherein the transistor directly connected to the aforementioned word line is only one transistor of the first conductivity type. -44- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----- • '------ AWI ^ -------- Order ---- ----- line (please read the precautions on the back before filling this page) 527728 6. The scope of patent application is like the semiconductor memory device under the patent application item No.!, Where the sub-line is selected for the front center The aforementioned first transistor (gate voltage) during the voltage transmission operation is a voltage equal to or greater than the sum of the voltage of the selected zigzag line and the threshold threshold voltage of the aforementioned first transistor. -The semiconductor memory device in which the voltage transfer action performed on the selected word line is a data write action.-13 .: The semiconductor memory device with the scope of patent application No.!, Wherein the memory cell is provided with a selection gate. The memory cell of the non-volatile semiconductor memory device of the transistor. 14. = The semiconductor memory device of the full-time item 1, wherein the aforementioned memory t is a memory cell of a ^ nAND) 3 ^ eepr0m. It is arranged as ^^ ; And a column decoding circuit, which selects the aforementioned ^: word line of the cell array And the voltage is transmitted to the word line in the foregoing column. The decoding circuit has: a complex body of the first conductivity type, which is a pure material at the-end of the current source μ = a second transistor of the second conductivity type, which is connected to the When it is selected, and the voltage transmission action, the voltage is transmitted to the plate line for 7, "1" and "Contains to 4" the gate of the first transistor described above, and it is the same as the first one; The opposite is extremely characteristic: the + performed on the previously selected zigzag line is only performed on the first transistor of the first conductivity type, the pressure is transmitted, and it has a movement, 15 ·-a kind of semi-conducting ' It has: memory cell array, which is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs -45 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 527728 6. Scope of patent application The voltage applied to the non-selected block will be a voltage between the aforementioned second transistor in t 乂 and the voltage higher than the power supply voltage. The semiconductor memory device circuit of the scope of application for patent No. 15 is a receiving area Address signal, and block: select: two select The discriminating signal corresponding to the discriminating result is output as a ghost ^ two switching circuit, which includes the discriminating signal of the aforementioned second transistor = ::: output, and each of the aforementioned first heart I: and the second voltage switching circuit is set, It is to receive the above-mentioned discriminant signals of I and Si, and to give the level of the discriminant signals to the non-selected block; $ = the person who switches the circuit; applied to the above-mentioned ghosts. Turn, is the voltage level of the discrimination signal output by the virgin voltage switching circuit. 17. For example, for a semiconductor memory device under the scope of application for patent No. 16, and:! Of the aforementioned second transistor in the aforementioned non-selected block When the applied voltage of the gate is operated at a voltage higher than the power supply voltage, the applied voltage is a voltage higher than the highest voltage in the logic circuit. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 18. If a semiconductor memory device with the scope of patent application No. 15 is provided, it also has: a logic circuit 'It is a receiving area address signal, which will be selected with the block, and non-selected. The corresponding discriminant corresponding to the result is output; 1 voltage switching circuit including the aforementioned second transistor, each of which sets the gate voltage of the first transistor; and a second voltage switching circuit that receives The determination signal output by the logic circuit is used to convert the level of the determination signal to the above-mentioned voltage switching circuit; 1 is applied to the voltage between the second transistors in the non-selected block 46- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 public love) 527728 patent application range voltage, which is based on the above-mentioned second voltage voltage level. 19% of the discriminative signals that have been rotated out. For example, the semiconductor of item 8 in Yin ’s patent application is added to # ^ ^ # thinking device, in which Shi Wang described the aforementioned second voltage in the non-selected block to become Μ «Electrical voltage = 1 pole of the applied voltage is higher than that in the aforementioned logic circuit, the aforementioned application 20. Such as the semi-conductor of item 15 of the patent application park * the voltage is higher. ^ ^ Dry亨 # 忆 装置 ， 装 成 成 武 fcb2 Heart :: The action of high voltage voltage is the data nesting operation. 1Γ = Semiconductor memory device in the range of 15 items, in which the power is applied :: select area When the application of the interrogator of the aforementioned second transistor in the block = an operation with a voltage higher than the power supply voltage that can be described, the aforementioned application = low ~ the voltage of the aforementioned first transistor in the stomach selection block 22. = = _Set, which has: memory cell array, which is a memory cell array and a column decoding circuit, which selects the aforementioned note: the word line of the cell array, and transmits voltage to the word line. The above-mentioned decoding circuit has: a plurality of i-th conductive crystals of the i-th conductivity type, each of which is at one end of a current path Those directly connected to each word line; the first switching voltage switching circuit, which contains the second transistor of the second conductivity type, is used for transmitting voltage to the selected word line when transmitting voltage to the selected one. The gate of the aforementioned first transistor connected to the word line has a polarity opposite to that of the first conduction type, and a voltage _ is applied to the gate of the aforementioned first transistor; a logic circuit that receives a column address Signal, the -47- scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) Please read the note on the back I # Fill in I Page II W7728