TW526540B - Phase shift mask and system and method for making the same - Google Patents

Abstract

A phase shift mask and a system and method for making the same are provided. The phase shift mask comprises a number of phase shifters (173, 176) that define a number of active gate areas (113). Each of the active gate areas (113) is associated with one of a number of active regions (103) of a predefined circuit. The phase shift mask also includes at least one joined phase shifter (183) defining at least two of the active gate areas (113). The joined phase shifter (183) extends between at least two of the active regions (103).

Description

526540

[Technical Field] The field of circuit manufacturing is particularly related to manufacturing. The present invention is generally related to the masks used in the fabrication of integrated circuits. [Background Art] In the manufacture of traditional integrated circuits, there is an indispensable process β. Now it is the second from the right, a necessary and necessary lithography technology is used in incubation, and usually all

Materials so that radiation-sensitive lines or shapes such as photoresist can be selected. The required geometry, fine structure, and a well-known lithography method are optical lithography. The optical lithography process begins by forming a photoresist layer on the upper surface of a semiconductor wafer. A mask including an opaque area where light is not transmitted and a transparent area where light is completely transmitted is then placed on the photoresist-coated wafer. The light-opaque opaque areas are usually made of chromium, and the light-transparent and transparent areas are usually made of quartz. The mask is then irradiated with light from a visible light source or an ultraviolet light source. In almost all cases, light is reduced and focused using an optical lens system that includes one or more lenses, filters, and / or reflectors. Light passes through the transparent area of the mask and illuminates the underlying photoresist layer. The opaque area of the mask broadcasts the same light, so that the corresponding portion of the lower photoresist layer is not illuminated by the light. Then, a chemical agent is usually used to remove the light-irradiated / non-light-irradiated area of the photoresist layer and

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526540 V. Description of the invention (2) The developed photoresist layer is developed. The end result is a semiconductor wafer covered with a photoresist layer showing the desired pattern. This pattern can then be used to etch the underlying areas of the wafer. Since the first integrated circuit was made, it has driven the electronics industry to increase the number of transistors on a particular size wafer. Therefore, integrated circuit designers continue to design circuits with smaller minimum sizes. However, in

Levenson et al., IEEE Transactions on Electronic Devices (Vol. ED -29, November 12, December 1992, pages 1 828 to 1 836), "Improving the Resolution of Lithography with Phase Shift Masks ( Improving Resolution in Photolithography with a Phase Shifting Mask ”was previously considered to be a practical limitation on the smallest achievable size due to diffraction effects in traditional optical lithography processes. More specifically, at 0.5 microns or less In order to obtain the best resolution under the integrated circuit design features of the integrated circuit, the maximum numerical aperture (NA) of the lens system has been required. However, the depth of field of the lens system is inversely proportional to NA, and The surface of the integrated circuit may not be optically flat. When good resolution is obtained, good focus may not be obtained, and vice versa. Therefore, when the minimum achievable size is continuously reduced in the semiconductor manufacturing process, Gradually approaching the limits of optical lithography. Especially when the minimum size is close to 0-1 micron, traditional optical lithography will not work effectively. The minimum size desired break down the barriers, a technique has been developed known as phase one kind described in Levenson et al offsets in the phase shift 'using two adjacent transparent regions of the photolithography mask caused by

92016.ptd Page 6 526540 V. Description of the invention (3) 'Destructive interference, and the photoresist layer will be exposed to unexposed areas. The above-mentioned work is accomplished using the following characteristics: Light passing through a transparent region on a mask has a wave characteristic, so the amplitude phase of the light emitted from the mask material is a function of the distance of the light passing through the mask material. This distance is equal to the thickness of the masking material. Place two transparent areas next to each other in a mask. One of the transparent areas has a thickness of ti and the other transparent area has a thickness of t 2. A desired interference can be obtained on the photoresist layer by using light interference. Unexposed area. In particular, if the thickness is specified as t2, (n-i) (t2) is exactly equal to 1/2 of the time, where λ is the wavelength of light passing through the mask material, and ^ is the refractive index of the material with a thickness of 1. The amplitude of the light of the material of h and the amplitude of the light emitted from the material of thickness h are 180 degrees. Because the photoresist material responds to the intensity of light and the opposite phases of light cancel out where they overlap, a dark area illuminated by light will be formed at the point between two transparent areas of different thicknesses on the photoresist layer . Phase shift masks are well known and have been published in B, J_ Lin's paper "Circuits and Devices" (March 1993, pages 28 to 35). "Phase shift mask gain and Phase-Shifting Masks Gain and Edge ”uses phase shifting masks in various configurations. The configuration described in the above paper is called Phase Shift Masking (PSM). In comparing various phase offset configurations, researchers have shown that the PSM method can achieve a resolution of 0 25 microns or less. The phase-shift nose method used in the design of the phase-shift mask according to the principle described above usually defines a phase-shift region, and the phase-shift region extends just beyond the active regions of the active layer. For example, usually

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526540 V. Description of the invention (4) The remaining length of polycrystalline silicon is defined by the image field and the mask (ie, fieid i ^ sk). However, the alignment shift between the field masks may cause a transition in the polysilicon circuit when it changes to the image field mask area. This: Bu ’is because the image field mask is used to print the polycrystalline lines. The image field mask becomes critical and difficult as it is outside the 2 area. ~ For the shift mask [disclosure of the present invention] In view of the foregoing, in the present invention, the phase shift mask includes the gate region in the embodiment. Each-active gate :: = two dry active combined phase shifters, which are used to define at least two: f masks also include at least -a junction-a combined phase shifter is a phase-extended active closed-pole region. The at least phase offset masks provide between two such active areas. Mask definition and predetermined circuit information & = the following advantages: The phase shift masks and defines the active H positions; t ... For this, there is no need to strictly determine the polygon of the polycrystalline silicon with the image field. . Because the previous art uses polygons that match these active intervals. Any errors caused are therefore reduced to masks and field masks to define the polygon method. The party: ld: The invention of column t provides a further boundary for designing the phase shift region of the phase shift mask ": Step: Define a number of phase shift regions. These bounds are right gate active gate regions, each of which Etc. 92016.ptd Page 8 526540 V. Description of the invention (5) If the method of moving gate region and predetermined circuit also includes the following steps: define the phase shifters by dividing the region. The combination includes at least two phase shifters, and each phase shifter has a specified phase with the phase shifters in the active area. In addition, the present invention also provides a phase shift mask for designing Defining a number of active gate regions for defining a number of phase offset regions, wherein one of the active regions of the circuit actively assigns a phase to each of these phase series, and by combining at least two logics, wherein the two Two coherent active regions are associated, and one of the two zero-bit active regions is associated. The phase is assigned to each of these phase offset methods further comprising the following steps: knot definition combined with a phase shifter, wherein the two different active areas are associated and are in phase. A computer program implemented in computer-readable media. The computer program includes logic 'the phase shift regions further each of the active gate regions is associated with a predetermined region. The computer program also includes an offset region and defines a number of phase shifters. The phase shifters and the combination phase shifters are different from the active phase shifters if the same phase shifters have the same specified relative term. Those skilled in the art can easily understand other features and advantages of the present invention by referring to the following drawings and detailed descriptions. Such additional features and advantages will be included in the scope of the present invention. [Mode for Carrying Out the Invention] Please refer to FIG. 1 for a plan view of a pre-defined integrated circuit M leaf (100). The integrated circuit design (100) is used as an example to explain how A phase mask is created according to one aspect of the invention. The pre-defined integrated circuit design (100) includes an active area (103a)

526540, invention description (6) fdMb), and polycrystalline silicon polygons (106a), (106b), and 106c). The active area (103a) & (103b) may be part of the active layer, and is replaced by == such as the active areas (1033) and (1031)) included in the active layer. Doped with a certain amount of silicon to produce the active layer. As is generally understood by those skilled in this art =: general knowledge, polygons (^ and even phantoms are used as conductors. &Amp; Polygons (106a to c) and the active area (103) & (1 〇31)) The overlapping product # or partly forms the active gate region of the transistor. These sections of the polygon are often referred to as "act i ve poly". . The remaining sections or parts of the polygons (106a to c) that are not associated with any active area (103 &) and 〇3b) are often referred to as "field polycrystalline stones (^ 丨 e 1 辻 P 〇 1 y). As generally understood by those with general knowledge of this technology, poly = shape (106a to c) represents various circuit elements that can be generated in integrated circuits in order to generate multilateral openings> (106a to c) The phase shift mask will be used, and the situation in the eighth middle school will be explained below. Using integrated circuit design (〇〇〇) as an example, the design of the phase shift mask to self-integrate the circuit will be explained with reference to the subsequent drawings. Design 〇〇〇) Refer to Figure 2 for the steps involved in generating the actual integrated circuit. The figure shows a plan view of the integrated circuit design to illustrate the first step of generating a phase shift mask (110) Wherein the phase shift mask is used to generate an exemplary integrated circuit design (100) according to an aspect of the present invention. In a first step (110), an active gate of a polygon (106 & to c) is identified The polar region (113). It exists in any polygons 〇06 & to c) and the active region (103a) and (l "Active polysilicon" 3B) overlap to identify

526540 V. Description of the invention (7) Active gate area (11 3). Please refer to FIG. 3, which shows a plan view of the integrated circuit design to explain the second step (1 2 0) of generating a phase shift mask, in which the active gate region (1 1 3) is identified The edge (1 2 3). The edge (1 2 3) is defined as the edge of the polygon (106a to c) that overlaps with the active areas (103a) and (103b). As shown in Figure 3, the edge (123) of the active gate region (11 3) is indicated by dots. ○ Please refer to Figure 4, which shows a plan view of the integrated circuit design to explain the design phase shift The third step of the mask (1 3 0). In this step, several straight edges (1 3 3) of the polygon (1 0 6 a to c) directly extending from the edge (1 2 3) of the active gate region (1 1 3) are identified. Note that in Figure 4, the straight edges (1 3 3) are represented by hollow points. Please refer to Fig. 5, which shows a plan view of the integrated circuit design for explaining the fourth step (140) of generating a phase shift mask. In a fourth step (140), a number of phase offset regions (146) on either end of the active gate region (丨 丨 3) are identified. An edge (123) defined from the polygons (106a to c) extends a rectangle with a predetermined phase width to generate a phase offset region (46). Then, the edges of the phase shift region (46), which is not the boundary of the polygons (106a to c), are extended just outside the active regions (103 &) and (103b). Combining any two phase offset regions defined in this way and overlapping (46). In addition, any two phase offset regions (/ 46) separated by a predetermined minimum gap are also combined. As shown in Figure 5, all the relevant phase offset regions (146) or 疋 重 ® 'or isolated the predetermined minimum gap, and combined with these phase offset regions (146). Please note that the

92016.ptd Page 11 526540 V. Description of the invention (8) "-The characteristics of the light of the mask and other factors generally known to those skilled in the art ' to determine the predetermined phase width and minimum gap. Please refer to FIG. 6 for a plan view of the integrated circuit design, which is used to explain the fifth step of generating a phase shift mask (50). In a fifth step (150), a number of first phase offset extension regions (153) extending from the phase offset region (146) along the continuous edge (133) are identified. It then includes a first phase offset extension region (1 5 3) as part of the phase offset region (丨 4 6). 0 Please refer to Figure 7, which shows a plan view of the integrated circuit design to explain the design phase The sixth step of shifting the mask (6o). In the sixth step (160) ', a plurality of second phase shift extension regions (163) extending from the phase shift region (146) to the end cover (166) of the polygon to c) are identified. Then, the second phase shift extension regions (063) are added as a part of the phase shift region (146). 'Then refer to Figure 8 for a plan view of the integrated circuit design to illustrate the seventh step (17) of designing a phase shift mask. In the seven step (170), the first and second phase shifters (173) and (17) are obtained with a specific phase, rendering, and phase offset region (146) (Figure 7). (173) and (176) make the passing light have a predetermined phase shift. For example, if the second phase shifter (17 3) is designed to generate a phase shift of zero degrees, and the second phase shifter (176) It is designed to produce a phase shift of 180 degrees. This technique is generally understood by those skilled in the art. The two of them have a destructive interference of 纟 = 5-and can accurately report the J. Volunteer Pole Zone 3). In alternative embodiments,

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526540 V. Description of the invention (9)

Other phase shifts of the fruit. -Normally f, the phase offset regions (146) associated with the features (103a) & (103b) are rendered in an alternating manner. In terms of motion, phase shifters (173) and (176) are alternately arranged so that different bodies appear at the opposite ends of the phase shift regions (丨 丨 3). Please Zhuyin. Phase One of the several times < One way is to specify a specific order of the phases of $ to the two possible zones (146). For example, the offset start phase can be assigned to the leftmost phase offset region (46) and the remaining & (173) and (176) in an alternate manner 1. 15 Please refer to FIG. 9, which shows a plan view of the integrated circuit design, which is used to explain the eighth step of designing a phase shift mask (8o). In the eighth step (180), a corresponding phase shifter, which is associated with different active areas (103a) & (103b) and has the same phase and is isolated for an undefined area, (1 7 3), (1 7 6) are coupled to the combined phase shifter (1 8 3). The combined phase shifter (183) thus extends through the active area (103a) & (103b). This step can advantageously form a polygon (丨 0a to c) between the active area (103a) and (103b) without using an image field mask, and can combine two phase shifts (173), (176). Please refer to FIG. 10, which shows a plan view of the integrated circuit design, which is used to explain the ninth step of designing a phase shift mask (9o). In the ninth step (190), each section of the polygon (106 & to c) is identified, and both ends of the sections are surrounded by phase shifters (173), (176) having the same phase. . The sections are widened to form "widened sections" (193). As generally understood by those with general knowledge of this technology, in a similar way,

92016.ptd Page 13 526540 V. Description of the invention (ίο) All sections of the polygon (106a to c) are shown and are surrounded by a phase shifter (173), (1 7 6), or (1 8 3) Wait for one end of the sections, and use the image field to shield the undefined area illuminated by light around the other end of the sections. This segment becomes a widened segment (196). Widen the widened sections (193) and (196) so as to ensure that the width of these sections is not degraded by the phase shift mask and the image field mask. More specifically, when phase shift = masks and image field masks are placed adjacent to each other in this manner, constructive interference may occur, and thus the shape of the polygons (106a to c) may be adversely affected. Therefore, the foregoing description referring to FIGS. 2 to 10 provides various aspects related to designing and generating a phase offset mask using the phase offset regions (173), (176), and (183) shown in FIG. step. After knowing the above matters, please refer to FIG. 丨, which shows a block diagram of a phase shift mask according to an embodiment of the present invention (the generation system (200) by P. The PSM generation system (200) Contains a processor circuit with a processor (203) and a memory U 0 6), the processor (203) and the memory (206) are all face-to-face interface (2009) . As generally understood by those with general knowledge of this technology, the regional interface (2009) can be such as a data bus and accompanying control bus. Therefore, the pSM generation system (200) can be, for example, a computer system, or other system with similar capabilities. The psM generation system (200) also includes a display interface (213) and various input / output interfaces (216) for connecting the area interface (209) to various peripheral devices. Peripheral devices that can accompany the PSM generation system (200) include, for example, a display device (223), a keyboard (226), a mouse (229), or a printer (233). The display device (223) is coupled to the area interface via the display interface (213).

Page 14 526540 V. Description of the invention (11) 1 --- Sample, keyboard (226), mouse (229), and printer (233) Two 'in' / wheel out interface (216) and handle Go to the regional interface (209). The display interface (213) and the input / output interface (216) may include such devices as the interface. In addition, other peripheral devices that can be used in conjunction with the PSM generation system (2000) can include various users such as key sets, touchpads, touchscreen microphone scanners, joysticks, or one or more buttons Enter ^ Set. Similarly, the user output device may include an indicator light, a control light, and the like. The display device (223) may include, for example, a cathode ray tube (WRT), a liquid crystal display screen, a plasma flat panel display, or a light emitting diode. According to an aspect of the present invention, the operating system (243) and the psM generation logic (246) are stored in a memory (206) and executed by a processor (203).

As is generally understood by those with ordinary knowledge in this technology, the operating system (243) controls the general functions of the PSM generation system (2000). Therefore, the operation of the operating system (243) will not be detailed in this article. The processor (203) executes psM generation logic (24 6), so as to design a phase shift mask according to the principle described above with reference to the figures i to 丨 0. "Memory (206) can include volatile and non-volatile memory components. Volatile components are components that cannot retain data when power is lost. Non-volatile components are those that retain data when power is lost Therefore, the memory (206) may include, for example, random access memory (RAM), read-only memory (ROM), hard disk drives, floppy disks accessed via associated floppy disk drives, via optical disks Discs accessed by a computer, tapes accessed via a suitable tape drive, and / or other memory components, or any two or more of these

526540 V. Description of the invention (12) One of these memory components. In addition, the processor (203) may represent multiple processors, and the memory (206) may represent multiple memories operating in parallel. In this case, the local interface (209) may be a suitable network that facilitates communication between any two of the multiple processors or between any processor and any memory. . The regional interface (209) can also facilitate memory-to-memory communication. The processor (203), the memory (206), and the local interface (209) may be electrical or optical. Moreover, the nature of the memory (206) may be magnetic. Please refer to FIGS. 12A and 12B, which illustrate an aspect of the present invention.

Flow chart of PSM generation logic (246). In addition, the flowcharts of FIGS. 12A and 12B can also be regarded as steps of a method for designing a phase shift mask according to another aspect of the present invention. Initially, the PSM generation logic (246) defines the shape, size, and location of the active areas corresponding to the active areas (103a) (Fig. 1) and (io3b) (Fig. 1). Then in step (306), the shape, size, and position of the polygons (106a to c) used to represent the active part and field polycrystalline silicon part of the integrated circuit to be generated are defined. Please note that, as generally understood by those with ordinary knowledge of this technology, the pre-existing integrated circuit design stored in the memory (206) (Figure ii) can be skipped (3 0 3) and (3 0 6). Then in step (309), the active gate region (丨 丨 3 κ in Fig. 2) is identified as the polygon in the polygons (106a to c) and the active regions (103 &) and (1〇31)). Those areas where an active area overlaps. Then in step (3 丨 3), the edge (123) of the active gate region (113) is identified (Fig. 3). Then in step (316)

92016.ptd Page 16 526540 5. In the description of the invention (13), the polygons (丨 2 3) identified from the edge of the active gate area (丨 丨 3) directly extend to the polygons outside the active areas (103a) and (103b). (I06a to c) straight edges (133) (Figure 4). In step (319), a number of phase offset regions (14β) are defined (Figures 5 to 7). More specifically, Lv 'is a rectangle that extends from the edge (123) by a predetermined phase width, and defines a phase offset region (146). In addition, the edge of the phase offset region (146) just generated perpendicular to the edge (123) is extended just outside the active regions (103 a) and (103). Then in step (3 2 3), a first phase offset extension area (1 5 3) (Figure 6) extending along the previously identified straight edge (133) is added, and the phase offset area (1 4 6). Then in step (326), the second phase shift extension area (163) (FIG. 7) is added to any of the polygons (106a to c) outside the active areas (103a) and (103b). Phase shift region (146) outside the end cap (166) (Fig. 7). ^ The PSM generates logic (246) and then proceeds to step (329). At this time, the phase is assigned to the phase offset regions (146), and the first and second phase shifters (173) are defined (Figure 3). And (176) (Figure 8). Then in step (33 ″), any phase shifter (173) associated with different active areas (103a) & (103b) and also having the same phase and isolating the undefined area (173 ), (176) are combined to the combined phase shifter 〇83) (Figure 8). Then / step (336) I, so that the two phase shifters (173), 〇76) are in the same phase, and The polygons (^ "to" in the active area (103 &) and (1031)) are changed to m%. Perform the above steps to ensure that the resulting phase shift mask is applied in subsequent lithography These sections are being formed in the integrated circuit.

526540 V. Description of the invention (14) -------- Finally, in step (339), the polygon located between the undefined areas made by a phase shifter (173) and / or image field mask Any section (196) (Fig. 10) from 106 to (:) is widened in order to ensure that the polygon is correctly formed in these positions. Then after defining this phase shift mask with phase shifters (1 73) and (1 76), the psm generation logic (246) terminates. The phase shift mask can then be constructed using a design generated by the PSM generation logic (246). The phase shift mask designed according to the present invention provides a clear advantage in that it is no longer necessary to make the polygons (106a to c) that are normally used to form areas outside the active areas (103a) and (103b) Field mask. As a result, the inaccuracies that may arise from using two masks in this manner are reduced or eliminated. Although the software implemented by the general-purpose hardware described above implements the PSM generation logic of the present invention (246), the PSM generation can also be implemented by dedicated hardware or a combination of software / general-purpose hardware and dedicated hardware Logic (246) as an alternative. If the PSM generation logic (246) is implemented in dedicated hardware, the PSM generation logic (246) can be implemented as a circuit or state machine using any one of several technologies or a combination. These technologies can include (but are not limited to): discrete logic circuits with logic gates that perform various logic functions on one or more data signals applied, application-specific integrated circuits with appropriate logic gates, programmable Gate Array (PGA), Field Programmable Gate Array (FPGA), or other component specific. Those with general knowledge of this technology have a general understanding of this technology, so this technology will not be described in detail in this article.

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526540 V. Description of the invention (15) Figures 1 2 A and 1 2 B of the renminbi diagram + the structure and function of the example of the mountain, and the execution of the PSMf generation logic (246) as a single order can represent the use of it来 实; refers to; = software implementation, then each or every step of the execution of the module $ ,, section, or "-one or more can be implemented, then each-step can be used to represent the cost of hardware to the palladium A circuit that specifies the editing function, or a number of phases. Although the flowcharts in Figures 12 and 12B show a specific order of execution, 'but we should understand that the order of execution may be different from the one shown, for example' You can mix two or more of the steps shown in the figure

Execution sequence ^ This / bu_ 'can perform two or more steps that are not shown in Figures 2A and 12B consecutively or simultaneously. We should understand that all such changes still hurt Taishi &

The flowchart of the figure has a clear scope. In addition, the various logics described in paragraphs m and i2B make hardware and / or software in order to execute the logic described in this article. You can use any logic (246) to implement PSM such as electronically readable media to produce the computer. Read the 婵 H brain, a system equipped with a processor, or can issue self-contained instructions to fetch or obtain the logic and execute the generated logic in the logic (240 ', the instruction execution system with m can use the PSM Production (246). In this article, the implementation of the system and the use of the PSM generation logic is included and stored in the context. The "computer-readable media" can execute the system's ϊ-style support for PSM generation Logic (246) to be the body of the instruction. The computer may run any media used by the instruction execution system. The media may include any one or more physical media,

526540 5. Description of the invention (16) For example, electronic media, magnetic media, optical media, electromagnetic media, infrared media, or semiconductor media. More specific examples of suitable computer-readable media may include, but are not limited to, portable computer disks such as floppy disks or hard drives, random access memory (RAM), read-only memory (ROM) ), You can erase programmable read-only memory, or portable discs. Many variations and modifications may be made to the above-described embodiments of the invention without substantially departing from the spirit and principles of the invention. All such modifications and variations will still be included within the scope of the invention.

92016.ptd Page 20 526540 Brief description of the drawings [Brief description of the drawings] The present invention can be understood by referring to the following drawings. Components in a drawing are not necessarily drawn to scale. In addition, in these drawings, the same code is used to mark the corresponding parts in all the drawings. Figure 1 is a plan view of an integrated circuit structure with several active regions in the active layer, in which there are several polycrystalline silicon polygons arranged on the active layer; Figure 2 is the product shown in Figure 1 which further identifies the active gate region Plane view of the body circuit structure; Figure 3 is a plan view of the integrated circuit structure shown in Figure 2 to further identify the edge of the active gate region; Figure 4 is to further identify the polycrystalline silicon polygons that extend directly from the edge of the active gate region Figure 3 is a plan view of the integrated circuit structure shown in Figure 3 with a straight edge; Figure 5 is a plan view of the integrated circuit structure shown in Figure 4 which further identifies a phase offset region that extends just outside the active region; Figure 6 is a plan view of the integrated circuit structure shown in Figure 5 where the phase shift region has extended beyond the active region along the straight edge of the polycrystalline silicon polygon; Figure 7 is the phase shift region has been extended to the selected A plan view of the integrated circuit structure shown in FIG. 6 outside the end cover of the polycrystalline silicon polygon; FIG. 8 is a structure of the integrated circuit shown in FIG. 7 in which a phase is assigned to each phase offset region, thereby generating a phase shifter Head-up Figure 9 is a plan view of the integrated circuit structure shown in Figure 8 combining a phase shifter located on different active areas and a phase shifter isolated by an undefined area;

92016.ptd Page 21 526540 Brief description of the drawings Figure 10 is a plan view of the integrated circuit structure shown in Figure 8 which widens the section of the polycrystalline silicon polygon; Figure 11 is a phase according to an aspect of the invention Block diagrams of the offset mask generation system; and Figs. 12A and 12B are flowcharts of the phase offset mask design logic such as that performed in the phase offset mask generation system shown in Fig. 11. [Description of component symbols] 10 0 Integrated circuit design 110, 120, 130, 140, 150, 160 '170' 180 '190' 200 steps

Phase shift mask (PSM) generation systems 103, 103a, 103b Active areas 106a, 106b, 10 6c Polycrystalline slab 113 Active gate area 133 Straight edge 153 Phase offset extension area 1 7 3, 1 7 6, 1 8 3 Phase shifter 200 2 0 3 Processor 2 0 9 Area interface 216 Input / output interface 22 6 Keyboard 233 Printer 246 PSM generates logical polygon 123 Edge 1 4 6, 1 6 3 Phase offset zone 166 End cover 193 196 Widened area 2 0 6 Memory 213 Interface 223 Display device 22 9 Mouse 243 Operating system

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Claims (1)

526540 6. Scope of patent application1. A method for generating a phase shift mask, including the following steps: Defining a number of phase shift regions (146), the phase shift regions (146) further define a number of active gates A polar region (113), wherein each of the active gate regions (113) is associated with one of the active regions (103) of a predetermined circuit; a phase is assigned to each of the phase offset regions (丨 4 6), and define a number of phase shifters (1 7 3, 1 7 6); and combine at least two such phase shifters (173, 176), and define a combined phase shifter (183), where The at least two phase shifters (173, 176) are associated with different active regions in the active regions (103) 'and the at least two phase shifters (173, 176) have the same designation as Phase. 2. The method according to item 1 of the patent application scope, further comprising the steps of: extending each phase offset region of the phase offset regions (1 4 6) to the end of at least one polygon (106) adjacent thereto Hood 066) outside 'where the at least one polygon (106) is specified in the pre-defined circuit. 3 The method according to the scope of patent application, wherein the step of defining a combined phase shifter (1 8 3) further comprises the following steps: identifying a number of direct extensions from several respective edges of the active gate region (1 1 3) Several straight edges (133) of the polygon (106); and extending the phase offset regions (1 4 6) along the straight edges (1 3 3) to the active region associated with the phase offset regions (丨 〇3). 4. The method in item 3 of the patent scope, which defines a combined phase shifter 92016.ptd Page 23 526540 VI. This step of patent application scope (183) further includes the following steps: Identification with the phase shifter (173, 176) in the active zone (103) One of the first phase-shifting / associated second phase states, one of the phases associated with the second active zone in the active zone (103), one of the second phase shifters (173, 176), The first and second phase shifters in the complex phase-finding phase shifter (173, 176) = 15 the phase of the undefined area between the two phase shifters. The phase of Ν ^^^^ Λψ The first phase shifter 5_ (173, 176) is combined through the undefined area, thus defining the combined phase shifter (183). 6. If the method of applying for the third item of the patent scope, further includes the following steps: Make a polygon I section of the polygons (106) ^ If the method of applying for the fifth aspect of the patent scope 'further includes the following steps: A part of one of the polygons (106) is positioned outside the active areas (103) and between two phase shifters having the same phase in the phase shifters (173, 176), and Identify the section. 〃 7. A phase shift mask for generating a predetermined circuit having a plurality of active regions (103), characterized in that: a plurality of phase shifters (173, 176) define a plurality of active gate regions (113) The active gate regions (113) are associated with one of the active regions (103) of the predetermined circuit; and at least one combined phase shifter (183) defines at least two of the active gates Zone (11 3), where the at least one combined phase shifter (1 8 3) extends between at least two of the active zones (丨 03). 8 If the phase shift mask of item 7 of the patent application scope, 92016.ptd Page 24 526540 6. The scope of patent application (173, 176) extends beyond the end cover (166) of at least one of the polygons (106). 9 • The phase shift mask of item 7 in the scope of patent application, wherein the phase is assigned to each of these phase shifters (1 7 3, 1 7 6). 1 0 If the phase shift mask of item 7 of the scope of the patent application, further includes a number of polygons (1 0 6) at least partially defined by the phase shifters (1 73, 1 7), the polygons (丨 〇6) having a first section between two such phase shifters (173, 176) having the same phase, and between two such phase shifters (73, 176) having different phases A second section, wherein the first section is wider than the second section. 92016.ptd Page 25