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TW441020B - Method for forming cap layer of self-aligned copper interconnect - Google Patents

Method for forming cap layer of self-aligned copper interconnect Download PDF

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TW441020B
TW441020B TW89103231A TW89103231A TW441020B TW 441020 B TW441020 B TW 441020B TW 89103231 A TW89103231 A TW 89103231A TW 89103231 A TW89103231 A TW 89103231A TW 441020 B TW441020 B TW 441020B
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metal
item
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TW89103231A
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Chinese (zh)
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Jr-Rung Chen
Jau-Jing Shie
Yu-Lin Liang
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United Microelectronics Corp
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Abstract

There is provided a method for forming a cap layer of self-aligned copper interconnect, which comprises using a metal atom implantation step and a chemical mechanical polishing step to form a metal doped layer on the surface of the copper damascene structure; and performing an annealing step in a nitrogen or ammonia environment to selectively grow a barrier layer on the surface of the copper damascene structure. Because there is formed copper silicide, it is able to not only improve the adhesion between the copper and the cap layer, but also prevent the copper from being diffused and oxidized.

Description

4 4 1 U 2 Ο 57 4 3 twf. doc/0 08 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(/ ) 本發明是有關於一種半導體元件的製造方法,且特 別是有關於一種形成自動對準銅金屬內連線之蓋層的方 法。 隨著積體電路元件的高度積集化,元件的尺寸逐漸 縮小,其所需的金屬內連線數目也隨之而增加。由於銅金 .屬本身具有低電阻率、高抗電遷移性以及可以以化學氣相 沈積與電鍍方式成長的優點,因此,目前半導體元件製程 常使用銅金屬作爲金屬內連線之材料,而且銅金屬於深次 微米元件之多層金屬連線的運用上備受矚目。 形成多重金屬內連線的方法之一爲雙重金屬鑲嵌製 程,第1圖即繪示習知一種銅雙重金屬鑲嵌結構的剖面圖。 其係在基底100上先形成一介電層102後,依照所需之金 屬導線的圖案以及介層窗開口的位置,蝕刻介電層102, 以形成一水平溝渠104和一垂直介層窗開口 106;亦即倉虫 刻下層絕緣層至暴露出其下方基底之元件區或導線,以形 成一垂直介層窗開口 106,並且蝕刻上層絕緣層,而形成 一水平溝渠104。然後,於基底100上沈積一銅金屬層107, 使其塡滿水平溝渠104與垂直介層窗開口 106,以同時形 成導線與介層窗。最後,以化學機械硏磨法將元件的表面 平坦化。上述形成水平溝渠104與垂直介層窗開口 106的 金屬鑲嵌開口即爲一雙重金屬鑲嵌製程。 使用銅做爲雙重金屬鑲嵌結構之材料時,通常於銅 雙重金屬鑲嵌結構上會形成一層氮化矽蓋層108,以防止 銅於製程過程中發生氧化。然而,由於銅金屬106與氮化 3 (請先聞讀背面之注意事項再填寫本頁) J=° Τ 本紙張尺度適用中國國家標準(CNS }Α4規格(210 X297公釐) 4 41 0 2 0 A7 5743twf<doc/008 β7 經濟部智慧財產局員工消費合作社印製 五、發明説明(τ) 矽蓋層108不會發生界面反應,因此其界面的黏著性 (adhesion)不佳,常會有剝落(peeling)的現象。 而且,銅金屬產生擴散的活化能在晶格(lattice)、晶 粒邊界(grain boundary)與表面(surface)分別爲 2.3 eV、 1.2eV、與0.8eV,因銅擴散之活化能以表面最低,故電致 遷移很容易在銅金屬的表面產生。因此,當銅與氮化矽蓋 層的界面黏著性(adhesion)不佳而造成剝落的現象時,其 表面便很容易因銅的擴散而產生電致遷移的現象,進而影 響元件的可靠性。 此外,當後續欲於銅雙重金屬鑲嵌結構上形成另一 介層窗開口,並暴露出銅雙重金屬鑲嵌結構時,於進行的 介層窗開口之鈾刻步驟過程中,常會使銅發生氧化,而生 成鬆散之氧化銅,造成金屬連線的導電性降低以及介層窗 之阻値增加等問題。而且,一般於介層窗開口形成之後, 通常會進行溶劑淸洗步驟,以去除沉積於介層窗開口側壁 之聚合物。然而,一般有機溶劑容易使銅金屬受損,而導 致銅雙重金屬鑲嵌結構產生孔隙(void),致使元件的可靠 性降低。 因此,本發明的目的就是提出一種形成自動對準銅 金屬內連線之蓋層的方法,可增加銅金屬與其蓋層之黏著 性,以避免其界面產生剝落現象。 再者,本發明的另一目的就是提出一種形成自動對 準銅金屬內連線之蓋層的方法,可提高銅表面產生電致遷 移的阻値,避免電致遷移現象的發生,進而提升元件的可 4 ----.---„---^------,玎------^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家榡準(CNS ) A4規格(210X297公嫠) 441020 5743twf,doc/008 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明説明(4) 靠性。 本發明之再一目的就是提出一種形成自動對準銅金 屬內連線之蓋層的方法,當後續欲於銅金屬內連線上形成 一介層窗開口時,可防止銅發生氧化,以及避免介層窗形 成之後,因淸洗所使用的有機溶劑使銅金屬受損,而導致 銅金屬內連線結構產生孔隙等問題。 根據本發明之上述目的,提出一種形成自動對準銅 金屬內連線之蓋層的方法,其係於基底上形成一具有雙重 金屬鑲嵌開口的介電層,續依序形成共形的第一阻障層與 銅金屬層。接著,進行一金屬原子之植入步驟,於銅金屬 層中形成一摻雜層,此摻雜層之表面高度大致約與雙重金 屬鑲嵌開口之表面高度相等,且位在雙重金屬鑲嵌開口中 之摻雜層的表面高度低於位在雙重金屬鑲嵌開口外之摻雜 層的表面高度。然後,進行一平坦化步驟,去除部分介電 層表面上過多的銅金屬層與第一阻障層,以形成一銅金屬 鑲嵌結構,此時銅金屬鑲嵌結構表面還殘留部分的摻雜 層°之後,於充滿含氮氣體的環境下進行一回火步驟,以 於銅金屬層表面形成一第二阻障層,然後於第二阻障層與 介電層上形成一蓋層。由於本發明於銅金屬鑲嵌結構表面 形成一自動對準的阻障層,因此可避免習知所發生的問 題。 爲讓本發明之上述目的'特徵、和優點能更明顯易 懂’下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 5 ----'-----^------ΐτ------# (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼(CNS ) Α4規格(210Χ297公釐) 經濟部智慧財是局員工消費合作社印製 4 4102 0 A7 5743twf 4 d〇c/008 ____B7 五、發明説明(4 ) 第1圖繪示習知一種銅金屬內連線的剖面圖。 第2A至2E圖繪示依照本發明一較佳實施例的一種 銅金屬內連線的製造流程剖面圖。 圖式之簡單說明: 100、200 :基底 102、2〇4 :介電層 104、210 :溝渠 106、 208 :介層窗 107、 2丨4 :銅金屬層 108、 220 :蓋層 202 :導線 206 :雙重金屬鑲嵌開口 212 :阻障層 216、216a :摻雜層 218 :自動對準阻障層 實施例 第2A至2E圖繪示依照本發明一較佳實施例的一種 銅金屬內連線的製造流程剖面圖。 請參照第2A圖,首先,提供一基底200,基底200 上例如已形成元件或導線202。然後,於基底200上形成 一介電層204。之後,於介電層204中形成一雙重金屬鑲 嵌開口 2〇6。雙重金屬鑲嵌開口 2〇6包括—垂直的介層窗 開口 208與一水平溝渠210。習知技藝中有多種形成雙重 金屬鑲嵌開口的方法,而本發明之雙重金屬鑲嵌開口可以 6 本紙張尺度適用中國國家CNS ) A4規格(21〇ί297$^) '" ----.-------裝------訂------線 (諸先閱讀背面之注意事項存填寫本買) 經濟部智慧財產局員工消費合作社印裂 ^41 Ο 2 〇 5743twf.doc/008 五、發明説明(4) 習知任何一種方法來形成,由於形成雙重金屬鑲嵌開口之 步驟並非本發明之重點,因此此處並不詳加描述其形成方 法。介層窗開口 208暴露出下方基底2〇〇中之元件或導線 202。然後,於基底200上形成一共形之阻障層212,此阻 障層212覆盍介層窗閧口 208與溝渠210之側壁。阻障層 之材質例如包括氮化鈦(TiN)、氮化鎢(WN)或氮化钽 (TaN) ’而其例如以化學氣相沈積法形成。接著,於阻障 層212上沈積一銅金屬層214,塡滿包括水平溝渠21〇與 垂直介層窗開口 208之雙重金屬鑲嵌開口 206,以同時形 成導線與介層窗插塞,而與基底200中之元件或導線202 作電性的連接。銅金屬層214例如以濺鍍法形成,銅金屬 層之厚度約爲400埃。 請參照第2B圖,進行一金屬原子之植入步驟,以於 銅金屬層214中形成一摻雜層216。此植入步驟可以使用 鉅(Ta)、鈦(Ti)或鎢(W)之金屬原子來進行植入,而其使用 的能量與劑量需視銅金屬層214的厚度來決定,藉由控制 金屬原子之能量與劑量,使所形成之摻雜層216的表面高 度大致約與雙重金屬鑛嵌開口 208的表面高度相等。由於 位在雙重金屬鑲嵌開口 208附近之銅金屬層214爲結晶 (crystal)狀態,而介電層204與阻障層212之結構較接近 於非結晶(amorphous)狀態’當進行金屬植入時,藉由離子 於銅的穿隧(tunneling)效果比在介電層204與阻障層212 之穿隧效果佳,以及氮化鉬阻障層212可作爲植入原子之 終止層的特性,藉由控制植入的能量,將佈植的深度約控 7 -------..--衣 —-----V------..Λ {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0X297公釐) 經濟部智慧財產局員工消費合作社印製 4 41 02 0 . A7 5743twf.doc/008 五、發明説明(么) 制於阻障層212的下方’且使位在雙重金屬鑲嵌開口 208 中之摻雜層216之表面高度低於位在雙重金屬鑲嵌開口 208外之摻雜層216的表面高度,兩者之深度差較佳 係控制在約500至1000埃左右。 請參照第2C圖’之後,進行一平坦化步驟,去除部 分介電層2〇4表面上過多的銅金屬層214與阻障層212, 以及部分金屬摻雜之介電層2〇4,以形成一銅金屬鑲嵌結 構。由於銅金屬鑲嵌開口 208中之摻雜層216的摻質深度 較深,因此於平坦化步驟之後,銅金屬鑲嵌結構的表面還 殘留有部分之摻雜層2l6a,殘留的摻雜層216a厚度約爲 300至500埃。此平坦化步驟較佳係以化學機械硏磨法來 進行。 請參照第2D圖,之後,於充滿含氮氣體的環境下進 行一回火步驟,此時銅金屬鑲嵌結構表面摻雜層216a中 的金屬原子,例如鉅、鈦或鎢等金屬原子,將會擴散出來, 與含氮氣體反應,而於銅金屬鑲嵌結構表面自動對準形成 一材質例如爲氮化鉬、氮化鈦或氮化鎢的阻障層218。此 回火步驟例如於充滿氮氣或氨氣的環境下進行。 請參照第2E圖,於自動對準阻障層218與介電層204 上形成一蓋層220。蓋層220之材質比如爲氮化矽。如此, 由於銅雙重金屬鑲嵌結構的表面上形成有阻障層218,銅 金屬層214與蓋層220間的黏著性可因此而獲得改善。 本;發明之特徵在於利用離子於雙重金屬鑲嵌開口中 之銅金屬與介電層及阻障層中穿隧效果的不同,以及化學 8 本紙張尺度通用中國國家標準(CNS〉Μ規格(210X297公釐) --------.——^------II------i (請先閱讀背面之注意事項再填寫本頁) A7 B7 Λά] 0 2 0 5743twf.doc/008 五、發明説明(9) 機械硏磨步驟,於銅金屬鑲嵌結構之表面形成一金屬摻雜 層,續於氮氣或氨氣的環境下進行回火步驟,使摻雜層中 的金屬擴散出來,而與氮氣或氨氣發生反應,而選擇性地 於銅雙重金屬鑲嵌結構的表面上成長例如爲氮化鉅之阻障 層,如此可增加銅與氮化矽蓋層間的黏著性,避免因其黏 著性不佳而導致剝落的現象。 再者,本發明由於於銅雙重金屬鑲嵌結構的表面上 形成一自動對準的阻障層,可增加銅擴散的阻値,使銅表 面產生電致遷移的阻値增加,以避免電致遷移現象的發 生,進而提升元件的可靠性。 此外,因銅雙重金屬鑲嵌結構的表面上形成有阻障 層,使得銅金屬不會外露,如此當後續欲於銅金屬內連線 上形成一介層窗開口時,便可防止銅發生氧化,而且,也 可於介層窗形成後進行溶劑淸洗的過程中保護銅金屬,避 免因有機溶劑造成銅的受損,而導致銅金屬內連線結構產 生孔隙等問題,藉以保障元件之可靠性。 本發明當有其他優點、目的及特徵,顯示於上文和 後述之專利申|靑範圍之中,或是在實施本發明的過程中 顯示出來。 雖然本發明已以一較佳實施例揭露如上,然其並非 用以限定本發明’任何熟習此技藝者,在不脫離本發明之 精神和範圍內,當可作各種之更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準° 9 ----:---^------ir------义 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度通用中国國家樣準(CNS)八4規格(2I0x297公慶)4 4 1 U 2 〇 57 4 3 twf. Doc / 0 08 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor device, and in particular A method for forming a cap layer for automatically aligning copper metal interconnects. With the integration of integrated circuit components, the size of the components has gradually decreased, and the number of metal interconnects required has also increased. Copper-gold metal has the advantages of low resistivity, high resistance to electromigration, and can be grown by chemical vapor deposition and electroplating. Therefore, the current semiconductor device manufacturing process often uses copper metal as the material of metal interconnects, and copper The use of metal in multilayer metal connections for deep sub-micron devices has attracted much attention. One method of forming multiple metal interconnects is a dual metal damascene process. Figure 1 is a cross-sectional view of a conventional copper dual metal damascene structure. First, a dielectric layer 102 is formed on the substrate 100, and then the dielectric layer 102 is etched to form a horizontal trench 104 and a vertical dielectric window opening according to the required pattern of the metal wires and the position of the dielectric window opening. 106; that is, the worms engraved the lower insulating layer to expose the component areas or wires of the underlying substrate to form a vertical via window opening 106, and etched the upper insulating layer to form a horizontal trench 104. Then, a copper metal layer 107 is deposited on the substrate 100 so as to fill the horizontal trench 104 and the vertical via window opening 106 to form a conductive line and a via window at the same time. Finally, the surface of the element is planarized by chemical mechanical honing. The aforementioned metal inlaid opening forming the horizontal trench 104 and the vertical via window opening 106 is a double metal inlaid process. When using copper as the material for the dual metal damascene structure, a silicon nitride cap layer 108 is usually formed on the copper dual metal damascene structure to prevent copper from oxidizing during the manufacturing process. However, due to copper metal 106 and nitride 3 (please read the precautions on the back before filling in this page) J = ° Τ This paper size applies to the Chinese national standard (CNS) Α4 (210 X297 mm) 4 41 0 2 0 A7 5743twf < doc / 008 β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (τ) The silicon cap layer 108 does not undergo interfacial reactions, so its interface adhesion is poor and often peels off. Moreover, the activation energy for the diffusion of copper metal at the lattice, grain boundary, and surface are 2.3 eV, 1.2 eV, and 0.8 eV, respectively. The activation energy is the lowest on the surface, so electromigration can easily occur on the surface of copper metal. Therefore, when the interface adhesion between copper and the silicon nitride cap layer is not good and the phenomenon of peeling occurs, the surface is easy The phenomenon of electromigration due to the diffusion of copper affects the reliability of the device. In addition, when another interlayer window opening is to be formed on the copper double metal damascene structure and the copper double metal damascene structure is exposed, During the uranium engraving step of the opening of the interlayer window, copper is often oxidized to generate loose copper oxide, which causes the conductivity of the metal connection to decrease and the resistance of the interlayer window to increase. After the layer window opening is formed, a solvent washing step is usually performed to remove the polymer deposited on the sidewall of the interlayer window opening. However, the general organic solvent easily damages the copper metal, resulting in voids in the copper double metal mosaic structure. ), Which reduces the reliability of the component. Therefore, an object of the present invention is to provide a method for forming a capping layer for automatically aligning copper metal interconnects, which can increase the adhesion between the copper metal and its capping layer to prevent the interface from peeling off. Furthermore, another object of the present invention is to propose a method for forming a capping layer for automatically aligning copper metal interconnects, which can increase the resistance of electromigration on the copper surface, avoid the occurrence of electromigration, and further The lifting element can be 4 ----.--- „--- ^ ------, 玎 ------ ^ (Please read the precautions on the back before filling this page) This paper size applies in National Standards (CNS) A4 specification (210X297 public address) 441020 5743twf, doc / 008 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, consumer cooperation. Du 5. Production Description (4) Reliability. Another purpose of the present invention is to propose A method for forming a cap layer for automatically aligning copper metal interconnects. When a via window is to be subsequently formed on the copper metal interconnects, the copper can be prevented from being oxidized, and after the formation of the via window, it is prevented from being washed. The organic solvent used causes damage to the copper metal, resulting in problems such as voids in the copper metal interconnect structure. According to the above object of the present invention, a method for forming a capping layer for automatically aligning copper metal interconnects is proposed, which is to form a dielectric layer with a double metal inlaid opening on a substrate, and sequentially form a conformal first Barrier layer and copper metal layer. Next, a metal atom implantation step is performed to form a doped layer in the copper metal layer. The surface height of the doped layer is approximately equal to the surface height of the double metal damascene opening and is located in the double metal damascene opening. The surface height of the doped layer is lower than the surface height of the doped layer located outside the double damascene opening. Then, a planarization step is performed to remove a portion of the excessive copper metal layer and the first barrier layer on the surface of the dielectric layer to form a copper metal mosaic structure. At this time, a portion of the doped layer remains on the surface of the copper metal mosaic structure. Then, a tempering step is performed in an environment filled with a nitrogen-containing gas to form a second barrier layer on the surface of the copper metal layer, and then a cap layer is formed on the second barrier layer and the dielectric layer. Since the present invention forms a self-aligned barrier layer on the surface of the copper metal mosaic structure, it can avoid the problems that occur conventionally. In order to make the above-mentioned object of the present invention 'characteristics and advantages more obvious and easy to understand', a preferred embodiment is given below, and it will be described in detail with the accompanying drawings as follows: 5 ----'----- ^ ------ ΐτ ------ # (Read the precautions on the back before filling in this page) This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm) Printed by the Bureau's Consumer Cooperatives 4 4102 0 A7 5743twf 4 doc / 008 ____B7 V. Description of the Invention (4) The first figure shows a cross-section of a conventional copper metal interconnect. Figures 2A to 2E show cross-sectional views of a manufacturing process of a copper metal interconnect according to a preferred embodiment of the present invention. Brief description of the drawings: 100, 200: substrate 102, 204: dielectric layer 104, 210: trench 106, 208: dielectric window 107, 2 丨 4: copper metal layer 108, 220: cover 202: wire 206: Double metal damascene opening 212: Barrier layers 216, 216a: Doped layer 218: Automatic alignment of the barrier layer Embodiments 2A to 2E illustrate a copper metal interconnect according to a preferred embodiment of the present invention Sectional view of the manufacturing process. Please refer to FIG. 2A. First, a substrate 200 is provided. For example, a component or a wire 202 is formed on the substrate 200. Then, a dielectric layer 204 is formed on the substrate 200. After that, a double metal embedding opening 206 is formed in the dielectric layer 204. The double metal inlaid opening 206 includes a vertical via window opening 208 and a horizontal trench 210. There are various methods for forming a double metal inlaid opening in the conventional art, and the double metal inlaid opening of the present invention can be 6 paper sizes applicable to the Chinese national CNS) A4 specification (21〇ί297 $ ^) '" ----.- ------ install ------ order ------ line (read the notes on the back first and fill in this purchase) The employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints ^ 41 Ο 2 〇5743twf .doc / 008 V. Description of the invention (4) Any method is known for forming. Since the step of forming the double metal damascene opening is not the focus of the present invention, the formation method is not described in detail here. The via window 208 exposes the components or wires 202 in the underlying substrate 2000. Then, a conformal barrier layer 212 is formed on the substrate 200, and the barrier layer 212 covers the sidewalls of the via window opening 208 and the trench 210. The material of the barrier layer includes, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN) 'and it is formed, for example, by a chemical vapor deposition method. Next, a copper metal layer 214 is deposited on the barrier layer 212 to fill the double metal inlaid opening 206 including the horizontal trench 21 and the vertical via window 208, so as to form a wire and a via plug at the same time as the substrate. The components or wires 202 in 200 are electrically connected. The copper metal layer 214 is formed by, for example, a sputtering method, and the thickness of the copper metal layer is about 400 angstroms. Referring to FIG. 2B, a metal atom implantation step is performed to form a doped layer 216 in the copper metal layer 214. This implantation step can use giant (Ta), titanium (Ti), or tungsten (W) metal atoms for implantation, and the energy and dose used depend on the thickness of the copper metal layer 214, and by controlling the metal The energy and dose of the atoms make the surface height of the doped layer 216 formed to be approximately equal to the surface height of the double metal ore inlay opening 208. Because the copper metal layer 214 located near the double metal damascene opening 208 is in a crystal state, and the structures of the dielectric layer 204 and the barrier layer 212 are closer to an amorphous state. When metal implantation is performed, The tunneling effect of ions to copper is better than that of the dielectric layer 204 and the barrier layer 212, and the characteristics of the molybdenum nitride barrier layer 212 as a stop layer for implanting atoms, by Control the implanted energy, and control the depth of implantation about 7 -------..-- clothing ------- V ------ .. Λ {Please read the precautions on the back first (Fill in this page again) This paper size applies Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 41 02 0. A7 5743twf.doc / 008 5. Description of the invention ( What) is made under the barrier layer 212 and the surface height of the doped layer 216 located in the double metal damascene opening 208 is lower than the surface height of the doped layer 216 located outside the double metal damascene opening 208, both The depth difference is preferably controlled at about 500 to 1000 angstroms. After referring to FIG. 2C, a planarization step is performed to remove a portion of the excessive copper metal layer 214 and the barrier layer 212 on the surface of the dielectric layer 204, and a portion of the metal-doped dielectric layer 204. A copper metal mosaic structure is formed. Since the doping layer 216 in the copper metal damascene opening 208 has a deeper dopant depth, after the planarization step, a part of the doping layer 21a remains on the surface of the copper metal damascene structure, and the thickness of the remaining doping layer 216a is approximately It is 300 to 500 Angstroms. This planarization step is preferably performed by a chemical mechanical honing method. Please refer to FIG. 2D, and then perform a tempering step in an environment full of nitrogen-containing gas. At this time, the metal atoms in the surface doped layer 216a of the copper metal damascene structure, such as giant, titanium, or tungsten metal atoms, will be It diffuses out, reacts with the nitrogen-containing gas, and automatically aligns on the surface of the copper metal mosaic structure to form a barrier layer 218 made of, for example, molybdenum nitride, titanium nitride, or tungsten nitride. This tempering step is performed, for example, in an atmosphere filled with nitrogen or ammonia. Referring to FIG. 2E, a capping layer 220 is formed on the auto-alignment barrier layer 218 and the dielectric layer 204. The material of the cover layer 220 is, for example, silicon nitride. In this way, since the barrier layer 218 is formed on the surface of the copper dual metal damascene structure, the adhesion between the copper metal layer 214 and the capping layer 220 can be improved accordingly. The invention is characterized by utilizing the difference between the tunneling effect of copper metal in the double metal inlaid opening with the dielectric layer and the barrier layer, and the chemistry. The paper size is generally Chinese national standard (CNS> M specification (210X297) Li) --------.—— ^ ------ II ------ i (Please read the notes on the back before filling this page) A7 B7 Λά] 0 2 0 5743twf. doc / 008 V. Description of the invention (9) Mechanical honing step, a metal doped layer is formed on the surface of the copper metal mosaic structure, and the tempering step is continued under the environment of nitrogen or ammonia to make the metal in the doped layer Diffuses out, reacts with nitrogen or ammonia gas, and selectively grows on the surface of the copper dual metal damascene structure, such as a barrier layer of giant nitride, so as to increase the adhesion between the copper and the silicon nitride cap layer, Avoiding the phenomenon of peeling due to its poor adhesion. Furthermore, the invention forms an automatically aligned barrier layer on the surface of the copper double metal damascene structure, which can increase the resistance of copper diffusion and cause copper surface. Increased resistance to electromigration to avoid the occurrence of electromigration In addition, the reliability of the component is improved. In addition, a barrier layer is formed on the surface of the copper double metal mosaic structure, so that the copper metal will not be exposed. Therefore, when a subsequent interlayer window opening is formed on the copper metal interconnect, It can prevent copper from oxidizing, and can also protect copper metal during the solvent washing process after the formation of the interlayer window, avoiding copper damage caused by organic solvents and causing voids in the copper metal interconnect structure. In order to ensure the reliability of the components, the present invention should have other advantages, objects and features, which are shown in the scope of the patent application above and below, or in the process of implementing the invention. Although the invention has been The above is disclosed in a preferred embodiment, but it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention It shall be subject to the definition of the scope of the patent application attached below. 9 ----: --- ^ ------ ir ------ meaning (please read the precautions on the back before filling this page) ) Ministry of Economy Property Office employees consumer cooperatives paper printed this kind of quasi-national scale GM China (CNS) eight 4 Specifications (2I0x297 public celebration)

Claims (1)

441020 574 3twf. doc/008 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 1. 一種形成自動對準銅金屬內連線之蓋層的方法*包 括: 於一基底上形成一介電層,該介電層已形成有一雙 重金屬鑲嵌開口,其中該雙重金屬鑲嵌開口包括一介層窗 開口與一溝渠,該介層窗開口暴露出下方部分之該基底; 於該基底上形成一共形之第一阻障層; 於該第一阻障層上形成一銅金屬層,塡滿該雙重金 屬鑲嵌開口; 進行一金屬原子之植入步驟,以於該銅金屬層中形 成一摻雜層,該摻雜層之表面高度大致約與該雙重金屬鑲 嵌開口之表面高度相等,且位在該雙重金屬鑲嵌開口中之 摻雜層之表面高度低於位在該雙重金屬鑲嵌開口外之摻雜 層的表面高度; 進行一平坦化步驟,去除部分該介電層表面上過多 的銅金屬層與第一阻障層,以形成一銅金屬鑲嵌結構,其 中該銅金屬鑲嵌結構表面還殘留部分之該摻雜層; 於充滿含氮氣體的環境下進行一回火步驟,使殘留 之該摻雜層與含氮氣體反應,以於該銅金屬層表面形成一 第二阻障層;以及 於該第二阻障層與該介電層上形成一蓋層。 2. 如申請範圍第1項所述之方法’其中該金屬原子之 植入步驟係使用鉅金屬原子來作爲摻質,則第二阻障層之 材質爲氮化鉅。 3. 如申請範圍第1項所述之方法’其中該金屬原子之 ----------- ---------訂--------I ^ . (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 經濟部智慧財產局員工消費合作社印*1衣 441020 A8 B8 C8 5743twf.doc/008 D8 、申請專利範圍 植入步驟係使用鈦金屬原子來作爲摻質,則第二阻障層之 材質爲氮化駄。 4. 如申請範圍第1項所述之方法,其中該金屬原子之 植入步驟係使用鎢金屬原子來作爲摻質,則第二阻障層之 材質爲氮化鎢。 5. 如申請範圍第1項所述之方法,其中該金屬原子植 入步驟所使用的能量與劑量需視該銅金屬層的厚度來決 定。 6. 如申請範圍第1項所述之方法,其中該金屬原子植 入步驟係藉由控制植入的能量,使該摻雜層約深及該阻障 層的下方。 7. 如申請範圍第1項所述之方法,其中該金屬原子植 入步驟係藉由控制植入的能量,使該雙重金屬鑲嵌開口中 之摻雜層之表面高度與位在該雙重金屬鑲嵌開口外之摻雜 層的表面高度之高度差控制在約500至1000埃左右。 8. 如申請範圍第1項所述之方法,其中該平坦化步驟 包括化學機械硏磨法。 9. 如申請範圍第1項所述之方法,其中該銅金屬鑲嵌 結構表面殘留之部分該摻雜層厚度約爲300至500埃。 10. 如申請範圍第1項所述之方法,其中該回火步驟 係於充滿氮氣的環境下進行。 11. 如申請範圍第1項所述之方法,其中該回火步驟 係於充滿氨氣的環境下進行。 12. 如申請範圍第1項所述之方法,其中該蓋層之材 ----------1 -裝-------訂---I I---^L (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 441〇20 '7 4 3 t w f . d < / 0 0 8 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 質包括氮化矽。 13. 如申請範圍第1項所述之方法,其中該基底包括 一導線,該介層窗開口暴露出部分之該導線,且該銅金屬 層與該導線作電性連接。 14. 一種防止銅擴散之雙重金屬鑲嵌結構的方法,其 適用於在一基底上形成一介電層,而該介電層已形成有一 雙重金屬鑲嵌開口,其中該雙重金屬鑲嵌開口包括一第一 介層窗開口與一溝渠,在該溝渠與該介層窗開口的側壁形 成一第一阻障層,於該溝渠與該介層窗開口中塡入一銅金 屬層,該方法包括下列步驟: 進行一金屬原子之植入步驟,以於該銅金屬層中形 成一摻雜層,該摻雜層之表面高度大致約與該雙重金屬鑲 嵌開口之表面高度相等,且位在該雙重金屬鑲嵌開口中之 摻雜層之表面高度低於位在該雙重金屬鑲嵌開口外之摻雜 層的表面高度; 進行一平坦化步驟,去除部分該介電層表面上過多 的銅金屬層與第一阻障層,以剩下部分之該摻雜層於該銅 金屬的表面; 於充滿含氮氣體的環境下進行一回火步驟’以於該 銅金屬層表面形成一第二阻障層;以及 於該第二阻障層與該介電層上形成一蓋層。 15. 如申請範圍第14項所述之方法,其中該金屬原子 之植入步驟係使用鉬金屬原子來作爲摻質,則第二阻障層 之材質爲氮化鉅。 ------—----•裝·-------訂·--------#' <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ί ' 4 4 10 2 0 經濟部智慧財產局員工消費合作社印製 Α8 Β8 C8 5743twf.doc/008 08六、申請專利範圍 16. 如申請範圍第14項所述之方法,其中該金屬原子 之植入步驟係使用鈦金屬原子來作爲摻質,則第二阻障層 之材質爲氮化鈦D 17. 如申請範圍第14項所述之方法,其中該金屬原子 之植入步驟係使用鎢金屬原子來作爲摻質,則第二阻障層 之材質爲氮化鶴。 18. 如申請範圍第14項所述之方法,其中該金屬原子 植入步驟所使用的能量與劑量需視該銅金屬層的厚度來決 定。 19. 如申請範圍第14項所述之方法,其中該金屬原子 植入步驟係藉由控制植入的能量,使該摻雜層約深及該阻 障層的下方。 20. 如申請範圍第14項所述之方法,其中該金屬原子 植入步驟係藉由控制植入的能量,使該雙重金屬鑲嵌開口 中之摻雜層之表面高度與位在該雙重金屬鑲嵌開口外之摻 雜層的表面高度之高度差控制在約500至1000埃左右。 21. 如申請範圍第14項所述之方法,其中該平坦化步 驟包括化學機械硏磨法。 22. 如申請範圍第14項所述之方法,其中該銅金屬鑲 嵌結構表面殘留之部分該摻雜層厚度約爲300至500埃。 23. 如申請範圍第14項所述之方法,其中該回火步驟 係於充滿氮氣的環境下進行。 24. 如申請範圍第14項所述之方法,其中該回火步驟 係於充滿氨氣的環境下進行。 ----------- -^if-----訂 *------- 麵0-- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) A8 B8 CS D8 4 41 0 2 0 5"M3twf.doc/008 六、申請專利範圍 25. 如申請範圍第14項所述之方法’其中該蓋層之材 質包括氮化砂。 26. 如申請範圍第14項所述之方法,其中該基底包括 一導線,該介層窗開口暴露出部分之該導線,且該銅金屬 層與該導線作電性連接。 • — — — — — — I I (請先閱讀背面之注意事項再填寫本頁) 訂---------銬 經濟部智慧时產局員工消費合作社印製 1 4 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)441020 574 3twf. Doc / 008 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for patent scope 1. A method for forming a cover layer that automatically aligns copper metal interconnects * includes: on a substrate Forming a dielectric layer, the dielectric layer has formed a double metal inlaid opening, wherein the double metal inlaid opening includes a dielectric window opening and a trench, and the dielectric window opening exposes a portion of the substrate below; on the substrate Forming a conformal first barrier layer; forming a copper metal layer on the first barrier layer to fill the double metal damascene opening; performing a metal atom implantation step to form a copper metal layer Doped layer, the surface height of the doped layer is approximately equal to the surface height of the double metal damascene opening, and the surface height of the doped layer located in the double metal damascene opening is lower than that of the double metal damascene opening The surface height of the doped layer; performing a planarization step to remove part of the excessive copper metal layer and the first barrier layer on the surface of the dielectric layer to form a copper metal Embedded structure, in which a part of the doped layer still remains on the surface of the copper metal mosaic structure; performing a tempering step in an environment filled with a nitrogen-containing gas, so that the remaining doped layer reacts with the nitrogen-containing gas, so that the copper Forming a second barrier layer on the surface of the metal layer; and forming a capping layer on the second barrier layer and the dielectric layer. 2. The method according to item 1 of the scope of application, wherein the implantation step of the metal atom uses a giant metal atom as a dopant, and the material of the second barrier layer is a nitrided giant. 3. The method described in item 1 of the scope of application 'wherein the metal atom ----------- --------- order -------- I ^. (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 1 clothing 441020 A8 B8 C8 5743twf. doc / 008 D8. The patent application implantation step uses titanium metal atoms as dopants. The material of the second barrier layer is hafnium nitride. 4. The method according to item 1 of the application scope, wherein the step of implanting the metal atoms uses tungsten metal atoms as a dopant, and the material of the second barrier layer is tungsten nitride. 5. The method as described in item 1 of the scope of application, wherein the energy and dose used in the metal atom implantation step depends on the thickness of the copper metal layer. 6. The method according to item 1 of the application scope, wherein the metal atom implantation step is to control the implantation energy to make the doped layer approximately deep and below the barrier layer. 7. The method according to item 1 of the application scope, wherein the metal atom implantation step is to control the implantation energy so that the surface height of the doped layer in the double metal damascene opening and the double metal damascene are located in the double metal damascene. The height difference of the surface height of the doped layer outside the opening is controlled to be about 500 to 1000 angstroms. 8. The method according to item 1 of the scope of application, wherein the planarizing step includes a chemical mechanical honing method. 9. The method according to item 1 of the scope of application, wherein the thickness of the doped layer remaining on the surface of the copper metal damascene structure is about 300 to 500 Angstroms. 10. The method as described in item 1 of the scope of application, wherein the tempering step is performed in a nitrogen-filled environment. 11. The method according to item 1 of the scope of application, wherein the tempering step is performed in an ammonia-filled environment. 12. The method described in item 1 of the scope of application, wherein the material of the cover layer --------- 1-equipment --------- order --- I I --- ^ L (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 441〇20 '7 4 3 twf. D < / 0 0 8 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of patent applications includes silicon nitride. 13. The method according to item 1 of the scope of application, wherein the substrate includes a wire, a portion of the opening of the interlayer window exposes the wire, and the copper metal layer is electrically connected to the wire. 14. A method of double metal damascene structure for preventing copper diffusion, which is suitable for forming a dielectric layer on a substrate, and the dielectric layer has formed a double metal damascene opening, wherein the double metal damascene opening includes a first A via window opening and a trench. A first barrier layer is formed on the sidewall of the trench and the via window opening, and a copper metal layer is inserted into the trench and the via window opening. The method includes the following steps: A metal atom implantation step is performed to form a doped layer in the copper metal layer. The surface height of the doped layer is approximately equal to the surface height of the double metal inlaid opening, and is located in the double metal inlaid opening. The surface height of the doped layer is lower than the surface height of the doped layer located outside the double metal damascene opening; a planarization step is performed to remove part of the excessive copper metal layer and the first barrier on the surface of the dielectric layer Layer, with the remaining portion of the doped layer on the surface of the copper metal; performing a tempering step in an environment filled with a nitrogen-containing gas to form a second barrier on the surface of the copper metal layer A layer; and forming a capping layer on the second barrier layer and the dielectric layer. 15. The method according to item 14 of the application scope, wherein the step of implanting the metal atom uses a molybdenum metal atom as a dopant, and the material of the second barrier layer is nitrided giant. ------------ • Installation · ------- Order · -------- # '< Please read the notes on the back before filling in this page) This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ί '4 4 10 2 0 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 Β8 C8 5743twf.doc / 008 08 The method described in item 14 of the application scope, wherein the step of implanting the metal atom uses a titanium metal atom as a dopant, and the material of the second barrier layer is titanium nitride D 17. As described in the item 14 of the application scope The method described above, wherein the step of implanting the metal atoms uses tungsten metal atoms as a dopant, and the material of the second barrier layer is a nitrided crane. 18. The method according to item 14 of the scope of application, wherein the energy and dose used in the metal atom implantation step depend on the thickness of the copper metal layer. 19. The method according to item 14 of the scope of application, wherein the metal atom implantation step is to make the doped layer approximately deep below the barrier layer by controlling the implantation energy. 20. The method according to item 14 of the application, wherein the metal atom implantation step is to control the implantation energy so that the surface height of the doped layer in the double metal damascene opening and the double metal damascene are located in the double metal damascene opening. The height difference of the surface height of the doped layer outside the opening is controlled to be about 500 to 1000 angstroms. 21. The method according to item 14 of the scope of application, wherein the planarizing step includes a chemical mechanical honing method. 22. The method according to item 14 of the scope of application, wherein a thickness of the doped layer remaining on the surface of the copper metal insert structure is about 300 to 500 angstroms. 23. The method according to item 14 of the scope of application, wherein the tempering step is performed in a nitrogen-filled environment. 24. The method according to item 14 of the scope of application, wherein the tempering step is performed in an ammonia-filled environment. ------------^ if ----- Order * ------- Side 0-- (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 Specification (210 X 297 mm) A8 B8 CS D8 4 41 0 2 0 5 " M3twf.doc / 008 6. Application for Patent Scope 25. The method described in item 14 of the scope of application 'where the The material of the capping layer includes nitrided sand. 26. The method according to item 14 of the scope of application, wherein the substrate includes a wire, a portion of the opening of the dielectric window exposes the wire, and the copper metal layer is electrically connected to the wire. • — — — — — — — II (Please read the notes on the back before filling out this page) Order --------- Printed by the Employees ’Cooperative of Wisdom and Time Bureau of the Ministry of Economic Affairs 1 4 This paper is for China National Standard (CNS) A4 specification (210 X 297 mm)
TW89103231A 2000-02-24 2000-02-24 Method for forming cap layer of self-aligned copper interconnect TW441020B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906422B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
US7915734B2 (en) 2001-12-13 2011-03-29 Megica Corporation Chip structure and process for forming the same
USRE43674E1 (en) 2000-10-18 2012-09-18 Megica Corporation Post passivation metal scheme for high-performance integrated circuit devices

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906422B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
US7906849B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
USRE43674E1 (en) 2000-10-18 2012-09-18 Megica Corporation Post passivation metal scheme for high-performance integrated circuit devices
US7915734B2 (en) 2001-12-13 2011-03-29 Megica Corporation Chip structure and process for forming the same
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US8008776B2 (en) 2001-12-13 2011-08-30 Megica Corporation Chip structure and process for forming the same
US8546947B2 (en) 2001-12-13 2013-10-01 Megica Corporation Chip structure and process for forming the same

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