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TW430970B - Copper damascene method for ultra large scale integration circuits - Google Patents

Copper damascene method for ultra large scale integration circuits

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Publication number
TW430970B
TW430970B TW88113205A TW88113205A TW430970B TW 430970 B TW430970 B TW 430970B TW 88113205 A TW88113205 A TW 88113205A TW 88113205 A TW88113205 A TW 88113205A TW 430970 B TW430970 B TW 430970B
Authority
TW
Taiwan
Prior art keywords
copper
palladium
layer
imd
cowp
Prior art date
Application number
TW88113205A
Other languages
Chinese (zh)
Inventor
Jiung-Sheng Shiung
Wen-Yi Shie
Huo-Tie Lu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW88113205A priority Critical patent/TW430970B/en
Application granted granted Critical
Publication of TW430970B publication Critical patent/TW430970B/en

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Abstract

The present invention relates to a manufacturing method which applies the copper-palladium alloy damascene technology to the fabrication of ultra large scale integration (ULSI) circuits. First, a TaN barrier is formed on an oxide layer which is known as inter metal dielectric (IMD) layer. Then, a copper-palladium seed is formed on the TaN barrier, and a copper-palladium gap-fill electroplating layer is formed on the dielectric oxide layer. Next, a copper-palladium annealing process is carried out. The copper-palladium gap-fill electroplating layer is able to depress the oxidization in the thermal process due to the existence of the palladium, thereby providing a higher oxidization output schedule in comparison with the conventional copper gap-fill electroplating layer. Then, the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is selectively deposited on the copper-palladium electroplating layer, wherein the palladium is a catalyst or accelerator in the self oxidation reduction step of the electrochemistry reaction. The self-alignment process of CoWP will decrease the capacitance of the IMD, and eliminate the peeling issues between the Si3N4 capped barrier layer and the copper-palladium dielectric layer. Furthermore, because of the low resistance of the CoWP, a step of etching conductive holes is not required, and thus there is nor short circuit problem caused by sputtering the copper. Fourth, a second IMD is formed on the first IMD. Finally, the steps of the above method are repeated to continue the deposition step, thereby completing the whole manufacturing process of the device.
TW88113205A 1999-08-03 1999-08-03 Copper damascene method for ultra large scale integration circuits TW430970B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88113205A TW430970B (en) 1999-08-03 1999-08-03 Copper damascene method for ultra large scale integration circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88113205A TW430970B (en) 1999-08-03 1999-08-03 Copper damascene method for ultra large scale integration circuits

Publications (1)

Publication Number Publication Date
TW430970B true TW430970B (en) 2001-04-21

Family

ID=21641757

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88113205A TW430970B (en) 1999-08-03 1999-08-03 Copper damascene method for ultra large scale integration circuits

Country Status (1)

Country Link
TW (1) TW430970B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256499B1 (en) 2003-10-02 2007-08-14 Advanced Micro Devices, Inc. Ultra low dielectric constant integrated circuit system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256499B1 (en) 2003-10-02 2007-08-14 Advanced Micro Devices, Inc. Ultra low dielectric constant integrated circuit system

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