425723 2388twfl.doc/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（（） 本發明是有關於一種主動式圖素感測器晶胞，且特別 是有關於電路與半導體之元件，用以接收光並且轉換光至 一電子訊號以代表光之強度。本發明更是有關於瓛路與半 導體的元件，用以消除由過量電荷造成之影像過亮以及由 在上述元件中的殘餘電荷造成的影像落後問題。 傳統影像電路包括一二維的感光器陣列。每一感光 器包括一影像要素（圖素）。從物體放射或反射的光能撞擊 感光器的陣列。光能藉由感光器轉換成電子訊號。影像電 路掃描各個感光器以讀出電子訊號。影像的電子訊號藉由 外部電路處理得以被顯示出來。 目前使用最普遍的單晶片影像技術是電荷耦合裝置 (Charged Couple Device 以下稱爲 CCD)相機。CCD 藉由累 積在半導體基底中的感光器井產生之電荷來操作。井的深 度是由位於半導體基底表面閘極電位所控制。藉由改變閘 極電位，電荷可以在半導體基底表面移動到感測點D電荷 就被放大成影像的電子訊號。 目前之金屬氧化物半導體（以下稱爲M0S)製程技術允 許CCD構中之電荷的傳送，能以近乎完美的效率用視頻完 成。然而，一小部份累積的電荷在沿表面移動時會流失掉。 每個井所累積的電荷在每一框時會被移動和感測。一般這 時間是每秒30-60圖框的數量級。 CCD技術有缺陷。在被感測與放大前’由光撞擊產生 的電荷會被直接移走。因爲此過程沒有效率’此裝置的增 益（電子輸出對光子輸入）是小於1。因此’會限制每一井 λ 閲 讀 背· 意 事 項 再 填 寫裝 頁 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 425723 2388twfl.doc/008 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明) 儲存的電荷量。可被感測到的最小電荷量爲在感測放大器 噪音之上可被感測放大器所感測到的量。最大的感測電荷 量則侷限於實質可產生且可由一井移到另一井中的電荷 量。 要克服這些CCD動態範圍的限制，要用光電晶體來感 測入射光。在美國專利案號No.5,260,592(Mead人等）， 美國專利案號No.5,324,958(Mead人等），以及"A High Resolution CMOS Imager With Active Pixel Using Capacitively Coupled BiPolar Operation",Chi 人等， paper #82 ，以及 Proceedings of International Conference on VLSI - technology, systems, and applications, Taipei, Taiwan, June 1997,所描述的高 解析度影像，有一如圖示la，lb，lc所繪的簡單結構。 這些圖素結構採用典型CMOS邏輯技術的標準製程技術。 N型雜質植入一 P型基底5用以形成一N型井10。場 氧化物20在半導體基底的表面成長，用以界定圖素的邊 界。在場氧化物20內P型雜質被植入形成光電晶體Q1 60 的P型基極15。N型井10連接到一電源供應器，做爲光 電晶體Q1 60的集極。下一步，將一閘極氧化物的薄層在 P型基極15的表面成長，用以形成電容器C65的電容器介 電質30。一層多晶矽35沉積在整個P型基極15上。用以 形成電容器C65的第二極板。在邊緣再氧化與氧化物間隙 形成之後，一 N型雜質被植入做爲光電晶體Q1 60的射極 25。P型基極15保持浮置。它的電位由耦合電容C6'5電位 請· 先 閱 讀 r 之 注 意 事 項 再 填 寫 本 頁 裝 訂 線 本紙張尺度適用中國國家標準（CNS)Al規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 425 7 2 3 2 3 8 8 twf 1 * doc/008 五、發明說明（、） 所決定。多晶矽物質層連接到列致能電路V_62。列 致能電路V_62將使光電晶體Q1 60轉移光電晶體Q1 60 所收集的電荷。 如二氧化矽之第二絕緣物沉積在半導體基底的表面用 以形成介電質40。一金屬層45與雙載子電晶體Q1 60的 射極25置於接觸50。該金屬層45做爲連接到感測放大器 SA 70之內連線。上述的製程明顯地可用來製作CMOS電晶 體。例如，多晶矽物質35可用以形成CMOS電晶體的閘極， 用來做爲該射極25之N型植入物可用來做源極/汲極區。 與用製造CCD的製程方法比較，製造雙載子圖素與CMOS 電晶體的相容性是一很大的優點。 從外界反射或放射的光量子L1 105撞擊到P型基極的 主動區Π。光量子L1 105在集極-基極接合區12與射極-基極接合區22的附近被吸收後形成電子-電洞對。電子-電洞對會在最近p-n接合區被收集。少量的載子被集在集 極-基極接合區12或射極-基極接合區22做爲基極電流。 基極電流乘上電晶體的電流增益爲集極電流。在電晶體Q1 60的射極25上的訊號電流Iscl〇〇爲光量子L1 105轉換 成電子-電洞對所產生的基極電流與集極電流之和。訊號 電流Isc100在某些條件下被傳到感測放大器SA 70。 現請參照第Id圖以了解光電晶體圖素結構的操作。在 積分期間102列致能電路V_62保持在一固定電位用以將 電晶體Q1 60的基極-射極接合區22反向偏壓。在此情形 下，光量子L1 105轉換成電子·電洞對所產生的電流會聚 6 本紙張又度適用中國國家標準（CNS)A4規格（2]0 X 297公梦） -.------------ ^--------訂---------線 丨 (本先閱讀r面之注急事項再填寫本頁) 425723 經濟部智慧財產局員工消費合作社印製 五、發明說明u ) 積在電容器C65上。 當想讀取在積分期間107產生的電荷量時，列致能電 路V_62在讀取時間104間其電位會達高準位。藉由耦合 到電容器C65至V_62，P型基極位能上升，竝且根據射 極25變成順向偏壓。在電容器C65的電荷會流入電晶體Q1 60的基極15並形成射極電流，亦即訊號電流Ise 100。 其他包括光二極體和MOS電晶體的結構可參考"Image Capture Circuits in CMOS"E. Fossum, Paper #B1, Proceedings of International Conference on VLSI-Technology, Systems, and Appl ications, Taipei, Taiwan, June 1997。一被動式圖素電路，包含一光二極體與一 MOS 傳遞電晶體。光二極體將光轉換成電荷。M0S傳遞電晶體 使電荷通過到一電荷累積放大器。一主動式圖素電路包含 一光二極體、一 M0S傳遞電晶體以及一源極隨耦器做爲電 荷累積放大器之暫存放大器。被重置訊號所致能的一 M0S 電晶體被放入主動式圖素電路，用以重置光二極體使之做 爲一電子開關。 與Chi所述的CMOS圖素電路比較起來，第la，lb和 lc所繪示的主動式雙載子圖素電路具有高感測性、簡化圖 素佈局以及降低製造成本的優點。然而，雙載子主動式圖 素有過亮與影像落後的缺點^ 請參照第2圖以了解過亮的現象。在一圖素陣列中（圖 素A80-圖素X85)，一列圖素A80會累積從光量子L1 105 撞擊光電晶體Q1 60a產生的電荷。此時，列致能電路VrDwa 7 (請先間讀背面之注意事項再填寫本頁) .¾------ 訂---------線 本紙張尺度適用中國國家標準（CNS)A..l規格（2〗0 X 297公釐） A7 425723 2388twfl.doc/008 __W_ 五、發明說明u ) 達到低準位75，把光電晶體Q1 60a的基極-射極接合區反 向偏壓；並且讓電荷集聚在電容器C65a上。此時，另一 列圖素X85會被讀取以感測目前在電容器C65b的電荷準 位。 若撞擊在圖素A80上的光量子L1 105能量夠大的話， 電荷開始將電晶體Q1 60a的基極-射極接合區順向偏壓。 這會引起一滿溢電流（over flow cur rent) Icfe95流向行內 連線90。感測放大器感測到的總電流ItC)tll〇爲滿溢電流 1^95與訊號電流Isc100之和。被讀取的圖素（圖素X85) 將會比它該有的亮度還亮。這會引起影像中亮源過亮。 現請參考第3圖以了解影像落後的原因。在此圖中圖 素X，最後一圖框200，在目前的圖框時之前的圖框時被 讀取。當列致能電路由高準位達到低準位185時，根 據射極，藉由電容器C165的耦合，該P型基極爲反相偏 壓。在影像積分時間一開始時，並非所有列的所有圖素皆 有相同的P型基極位能。在一讀取動作一開始，VmW由高 準位轉移到低準位時（即脈衝高度）時P型基極位能之下降 爲· △VB=(脈衝高度）Χ(偶合率） 電容C165的耦合率定義爲：425723 2388twfl.doc / 008 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (() The present invention relates to an active pixel sensor cell, and in particular, it relates to components of circuits and semiconductors. It is used to receive light and convert it to an electronic signal to represent the intensity of light. The present invention is also related to the elements of the circuit and the semiconductor to eliminate the over-brightness of the image caused by the excessive charge and the residual in the above-mentioned elements The problem of image backwardness caused by electric charge. Traditional imaging circuits include a two-dimensional array of photoreceptors. Each photoreceptor includes an image element (pixel). Light energy emitted or reflected from an object hits the array of photoreceptors. The photoreceptor is converted into an electronic signal. The image circuit scans each photoreceptor to read out the electronic signal. The electronic signal of the image is displayed by external circuit processing. The most commonly used single-chip imaging technology is the Charge Coupled Device (Hereinafter referred to as a CCD) camera. The CCD operates by the charge generated by a photoreceptor well accumulated in a semiconductor substrate. The depth of the well is controlled by the gate potential located on the surface of the semiconductor substrate. By changing the gate potential, the charge can move to the sensing point on the surface of the semiconductor substrate. The charge D is amplified into an electronic signal of the image. Current metal oxidation The physical semiconductor (hereinafter referred to as MOS) process technology allows the transfer of charges in the CCD structure, which can be completed with video with near perfect efficiency. However, a small part of the accumulated charges will be lost as they move along the surface. Each well The accumulated charge will be moved and sensed at each frame. Generally this time is on the order of 30-60 frames per second. CCD technology is defective. Before being sensed and amplified, the charge generated by the impact of light will be It is directly removed. Because this process is not efficient, the gain of this device (electronic output vs. photon input) is less than 1. Therefore, it will limit each well λ. National Standard (CNS) A4 specification (210x297 mm) 425723 2388twfl.doc / 008 Λ7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention The amount of charge stored. The minimum amount of charge that can be sensed is the amount that can be sensed by the sense amplifier above the noise of the sense amplifier. The maximum amount of sensed charge is limited to the amount of charge that can be substantially generated and can be moved from one well to another. To overcome the limitations of these CCDs' dynamic range, photoelectric crystals are used to sense the incident light. In US Patent No. 5,260,592 (Mead et al.), US Patent No. 5,324,958 (Mead et al.), And " A High Resolution CMOS Imager With Active Pixel Using Capacitively Coupled BiPolar Operation ", Chi et al., Paper # 82, and the high-resolution image described in Proceedings of International Conference on VLSI-technology, systems, and applications, Taipei, Taiwan, June 1997, has a simple structure as shown in the figure la, lb, lc. These pixel structures use standard process technology of typical CMOS logic technology. An N-type impurity is implanted into a P-type substrate 5 to form an N-type well 10. The field oxide 20 grows on the surface of the semiconductor substrate to define the boundaries of the pixels. A P-type impurity is implanted in the field oxide 20 to form a P-type base 15 of the photo-crystal Q1 60. The N-well 10 is connected to a power supply as a collector of the phototransistor Q1 60. Next, a thin layer of gate oxide is grown on the surface of the P-type base 15 to form the capacitor dielectric 30 of the capacitor C65. A layer of polycrystalline silicon 35 is deposited on the entire P-type base 15. Used to form the second plate of capacitor C65. After the edge re-oxidation and the formation of the oxide gap, an N-type impurity is implanted as the emitter 25 of the photovoltaic crystal Q1 60. The P-type base 15 remains floating. Its potential is determined by the coupling capacitor C6'5 potential. Please read the precautions of r before filling in this page. Binding line This paper size applies to Chinese National Standard (CNS) Al specification (210x297 mm). System 425 7 2 3 2 3 8 8 twf 1 * doc / 008 V. Description of the invention (,). The polycrystalline silicon material layer is connected to the column enable circuit V_62. The column enable circuit V_62 will cause the photo-crystal Q1 60 to transfer the charge collected by the photo-crystal Q1 60. A second insulator such as silicon dioxide is deposited on the surface of the semiconductor substrate to form the dielectric 40. A metal layer 45 is placed in contact with the emitter 25 of the bipolar transistor Q1 60. The metal layer 45 is used as an interconnection to the sense amplifier SA 70. The above process can obviously be used to make CMOS transistors. For example, the polycrystalline silicon material 35 can be used to form the gate of a CMOS transistor, and the N-type implant used as the emitter 25 can be used as the source / drain region. Compared with the manufacturing process of manufacturing CCD, the compatibility of manufacturing bipolar pixels and CMOS transistors is a great advantage. The light quantum L1 105 reflected or emitted from the outside hits the active region Π of the P-type base. The photon quantum L1 105 is absorbed near the collector-base junction region 12 and the emitter-base junction region 22 to form an electron-hole pair. Electron-hole pairs are collected at the nearest p-n junction. A small amount of carriers are collected in the collector-base junction region 12 or the emitter-base junction region 22 as a base current. The base current multiplied by the current gain of the transistor is the collector current. The signal current Iscl00 at the emitter 25 of the transistor Q1 60 is the sum of the base current and the collector current generated by the conversion of the photon quantum L1 105 into an electron-hole pair. The signal current Isc100 is transmitted to the sense amplifier SA 70 under certain conditions. Please refer to Figure Id to understand the operation of the pixel structure of the photoelectric crystal. During the integration period, the 102-column enabling circuit V_62 is maintained at a fixed potential to reverse-bias the base-emitter junction 22 of the transistor Q1 60. In this case, the light quantum L1 105 is converted into an electron-hole pair to converge the current generated. 6 This paper is again applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 public dream) -.----- ------- ^ -------- Order --------- line 丨 (Read the urgent matters on r side before filling out this page) 425723 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative V. Description of the invention u) Accumulated on the capacitor C65. When it is desired to read the amount of charge generated during the integration period 107, the potential of the column enable circuit V_62 reaches a high level during the reading time 104. By coupling to capacitors C65 to V_62, the P-type base potential can rise and become forward biased according to the emitter 25. The charge in the capacitor C65 flows into the base 15 of the transistor Q1 60 and forms an emitter current, that is, the signal current Ise 100. For other structures including photodiodes and MOS transistors, please refer to "Image Capture Circuits in CMOS" E. Fossum, Paper # B1, Proceedings of International Conference on VLSI-Technology, Systems, and Applications, Taipei, Taiwan, June 1997 . A passive pixel circuit includes a photodiode and a MOS pass transistor. A photodiode converts light into an electric charge. MOS passes a transistor to pass the charge to a charge accumulation amplifier. An active pixel circuit includes a photodiode, a MOS pass transistor, and a source follower as a temporary storage amplifier for a charge accumulation amplifier. An M0S transistor enabled by the reset signal is put into an active pixel circuit to reset the photodiode as an electronic switch. Compared with the CMOS pixel circuit described by Chi, the active bipolar pixel circuits shown in la, lb, and lc have the advantages of high sensitivity, simplified pixel layout, and reduced manufacturing costs. However, the double-carrier active pixels have the disadvantages of being too bright and the image lagging. Please refer to Figure 2 for the phenomenon of over-brightness. In a pixel array (pixel A80-pixel X85), a row of pixels A80 accumulates the charges generated by the photon L1 105 hitting the photo-crystal Q1 60a. At this time, the column enable circuit VrDwa 7 (please read the precautions on the back before filling this page). ¾ ------ Order --------- The size of the paper is applicable to Chinese national standards ( CNS) A..l specifications (2〗 0 X 297 mm) A7 425723 2388twfl.doc / 008 __W_ V. Description of the invention u) Reaching a low level of 75, invert the base-emitter junction of the photo-crystal Q1 60a Biased; and let the charge accumulate on capacitor C65a. At this time, another column of pixels X85 will be read to sense the current charge level in capacitor C65b. If the energy of the photon quantum L1 105 hitting the pixel A80 is large enough, the charge starts to bias the base-emitter junction of the transistor Q1 60a forward. This will cause an over flow cur rent Icfe95 to flow to inline 90. The total current ItC) t110 detected by the sense amplifier is the sum of the overflow current 1 ^ 95 and the signal current Isc100. The read pixel (pixel X85) will be brighter than it should be. This will cause the bright source in the image to be too bright. Please refer to Figure 3 to understand why the image lags. In this figure, pixel X and the last frame 200 are read at the time of the current frame and the previous frame. When the column enable circuit reaches a low level of 185 from a high level, the P-type base is extremely reverse-biased according to the emitter through the coupling of the capacitor C165. At the beginning of the image integration time, not all pixels in all columns have the same P-type base potential. At the beginning of a reading operation, when the VmW is shifted from a high level to a low level (ie, the pulse height), the P-type base potential energy drops to △ VB = (pulse height) × (coupling rate) The coupling rate is defined as:
CC
c + c BE + c BC 8 -------------裝--------J1T--------- (I先閱讀f·面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國囷家標準（CNS)A4規格（21CU297公釐） 經濟部智慧財產局員工消費合作社印製 d25 7 2 3 A7 2 3 8 Stwf 1 .doc/008 __B7_ 五、發明說明（& ) 其中： <：扯是電晶體Q1 160的基極-射極的接合電容 CBC是電晶體Q1 160的基極-集極的接合電容 P型基極電位是由電位\^„與耦合率（γ)所控制。因此，從 電容器C165移走的電荷並不完全，且會在電晶體Q1 160 的射極引起一部份殘餘電流IRe210。 殘餘電流IRC210的第二部分會成爲，從在先前的讀取 時間之間電晶體Q1 160之順相偏壓的基極-射極接合區的 注入電子遺留在P-基極之少部分載子的一殘餘物。殘留在 P型基極的電荷繼續與電流增益流向電晶體Q1 160的射 極，並加上目前讀取時間的訊號電流Isc215。這在尾隨移 動物體或明亮物體之後會形成一鬼影。殘餘的電荷最後在 一段時間過後，會因重組或少數載子離開P型基極而消失。 影像落後的時間大約是少數載子的生命期（即大約100毫 秒），並且它可持續幾個圖框。 雜質可加在P型基極用來做爲"生命期殺手''（lifetime killer) 用以減少重組時間。 生命期殺手”的困難是 它會增加接合區間的漏電流，減低影像的靈敏度。 美國專利案號No.5,097,305(Mead人等）所提之光感測 器具有一光電晶體和一耦合至光電晶體基極的電容器。一 傳遞電晶體放在光電晶體射極用以選擇性地耦合訊號電流 至感測放大器。 美國專利案號No. 5,288,988( Hashimo人等）描述一類 9 j------------ •裝--------訂---------線 - (請先閱讀-r面之江意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇χ297公釐） 經濟部智慧財產局員工消費合作社印製 425723 2 3 8 8 twf 1 . d〇c/ 0 0 8 A’ _ B7 五、發明說明（/^ ) 似於第la，lb和lc圖所繪的光感測器電路。該元件加入 一 MOS電晶體在其光轉換元件中。當m〇S電晶體致能，藉 由消除從光電晶體的基極的殘餘電荷使得上述的殘餘電流 被阻絕。 因此本發明的主要目的就是在提供一種主動式圖素感 測器元件用以轉換光量子能量成爲一電子訊號，表示該光 量子能量的大小。 本發明的另一主要目的是在提供一種主動式圖素感測 器元件用來避免影像過亮的問題。 本發明的另一主要目的是在提供一種主動式圖素感測 器元件用來減少殘餘電荷以減少影像落後的問題。 根據本發明的目的，提出一種主動式圖素感測器元件 包括一光二極體，一雙載子電晶體以及一 MOS電晶體。一 光二極體，有一陰極連接到一具電源供應器和一陽極。光 量子會撞擊在陽極上並在光二極體中產生電荷。MOS電晶 體會避免影像過亮。MOS電晶體有一汲極連接到光二極體 的陽極，源極和閘極。閘極連接到感測器控制電路，用以 選擇性使MOS電晶體致能與失效用來阻止或允許電荷流經 M〇S電晶體。雙載子電晶體會放大電荷產生電子訊號。雙 載子電晶體具有一集極連接至電源供應器，一基極連接到 M〇S電晶體的源極用以當MOS電晶體被致能時接收電荷， 以及一射極連接到外部電路將電子訊號傳送給外部電路。 主動式圖素感測器更包含一寄生MOS電晶體。此寄生 之MOS電晶體具有一汲極，是光二極體的陽極；一源極， ----------I--衣--------訂---------線 . (請先閱讀r面之注意事項再填寫本頁) 本紙張反度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 425723 A7 2 3 8 8 twfl.doc/ 0 0 8 Βΐ_ 五、發明說明（名） 是在一個主動式圖素感測器陣列中的一列主動式圖素感測 器得一相鄰之主動式圖素感測器的光二極體之陽極。寄生 MOS電晶體具有一閘極連接到一重置電路用以將寄生MOS 電晶體導通，使之重置在一列有相同位能準位的光二極體 之陽極的位能，因此由不相同的陽極電位造成的影像落後 現象在重置後可在主動式圖素感測器上消除。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第la和lb圖繪示傳統光感測器晶胞的上視圖以及半 導體基底的剖面圖。 第lc圖繪示第la和lb圖中繪示傳統光感測器晶胞的 電路圖。 第Id圖繪示第la和lb圖中繪示傳統光感測器晶胞的 時序圖。 第2圖繪示傳統技術之光感測器陣列晶胞的兩個晶胞 之電路圖圖示，用以說明滿溢電流造成影像過亮。 第3圖繪示傳統技術之光感測器陣列晶胞之電路圖， 用以說明殘餘電流所引起的影像落後。 第4a和4b圖繪示依照本發明之主動式圖素感測器的 上視圖與半導體基底之剖面圖。 第4c圖繪示第4a和4b圖中本發明之主動式圖素感測 (請先閱讀背面之注意事項再填寫本頁) 表--------訂---------線 本紙張尺度適用中國國家標準（CNS)A.1規格（2〗〇χ297公t ) 425723 2388twfl.doc/008 A7 B7 五、發明說明（，） 器晶胞的4路圖。 第4d圖繪示本發明之主動式圖素感測晶胞的時序圖。 第5圖繪示本發明之主動式圖素感測器陣列晶胞的兩 個晶胞之電路圖圖示，用以說明消除滿溢電流。 第6a，6b和6c圖繪示本發明之主動式圖素感測器陣 列晶胞中三個晶胞元件之上視圖與剖面圖，用以說明光二 極體重置操作以減少影像落後。 實施例 請參照第4a，4b和4c圖，其繪示依照本發明一較佳 實施例的一種圖。用以了解本發明之主動式圖素感測器的 結構。本裝置的製造從一典型的矽晶圓P型基底305開始。 然後將P基底305表面遮罩以及植入一 N型雜質做爲N 型井310。一絕緣區或場氧化物315成長以界定主動式圖 素晶胞的區域。在主動式圖素感測器晶胞的區域之中用光 罩定義光二極體D1 420之P型陽極330。N型井與電源να 接觸並做爲光二極體D1 420的陰極。 在主動式圖素感測器晶胞的區域之中的第二區用光罩 定義雙載子電晶體Q1 410的Ρ型基極320的區域。植入 一 Ρ型雜質以形成Ρ型基極320。之後，在Ρ型基極320 的區域中遮罩第三塊區域並植入Ν型雜質做爲雙載子電晶 體Q1 410的射極325。雙載子電晶體Q1 410的集極是Ν 型井310。 雙載子電晶體Q1 410的Ρ型基極320與光二極體D1 420 之Ρ型陽極330分別形成MOS電晶體Ml 415的源極和汲 12 (請先閱讀背面之注意事項再填寫本頁) 一衣·-------訂·-------- 經濟部智慧財產局員工消費合作社印製 衣紙張尺度適用中國國家標準（CNS)A4規格（21CJ X 297公釐） 2 3 B7 4 25 2388twfl . doc/008 五、發明說明（/0) 極。閘極氧化層340，在源極320與汲極330間的通道區 337上方成長=一多晶矽物質335放置在閘極氧化層340 上並鈾刻以形成M0S電晶體Ml 415的閘極。 一絕緣物沉積在半導體基底的表面上用以形成介電質 350。與N+射極325之接點327在介電質350中的一開口 形成。沉積一金屬層355用以連接電晶體Q1 410的射極325 和感測放大器SA 425，爲一主動式圖素感測器陣列的外部 電路。形成MOS電晶體Ml 415閘極之多晶矽物質335連 接到列致能電路V_416，爲一感測器控制電路。顯而易見 地，上面描述的流程可用來做成CMOS電晶體。例如多晶 矽物質335可以作爲CMOS電晶體的閘極，用來做射極325 之N型植入物以形成源極/汲極區。與用來製造CCD方法 的過程比較起來，製造雙載子圖素與CMOS電晶體的相容 性有非常大的優點。 現請參照第4d圖以了解主動式圖素感測器晶胞的操作 原理。光量子L1 334撞擊二極體D1 420的P型陽極330。 光量子L1 334會給予足夠的能量產生電子-電洞對，類似 於在第la，lb和lc圖描述之光電晶體Q1 60。電洞會移 往光二極體D1 420的P型陽極330。電子會集聚在光二極 體D1 420的陰極（N型井310)並且經由電源Vcc移走。帶 正電的電洞累積在光二極體D1 420的P型陽極330，圖示 是一遞增的位能487。列致能電路V~W416從一高電位變成 低電位，然後導通PM0S電晶體Ml 415。由光量子LI 334(影 像）產生的電荷Qs494以P型陽極的電位V p.an(5de表示，會 I—--------III --------> — — — — — — — — ► (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 $紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B? 4 25 7 2 3c + c BE + c BC 8 ------------- install -------- J1T --------- (I first read f · face (Fill in this page again) Printed by the Intellectual Property Bureau Employees ’Cooperatives of the Ministry of Economics This paper is printed on the Chinese Family Standard (CNS) A4 (21CU297 mm) Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economics d25 7 2 3 A7 2 3 8 Stwf 1 .doc / 008 __B7_ 5. Description of the invention (&) Where: <: The base-emitter junction capacitor of transistor Q1 160 CBC is the base-collector junction of transistor Q1 160 The potential of the capacitor P-type base is controlled by the potential \ ^ „and the coupling rate (γ). Therefore, the charge removed from capacitor C165 is not complete, and it will cause a part of the residual current at the emitter of transistor Q1 160 IRe210. The second part of the residual current IRC210 will be that the injected electrons from the forward-biased base-emitter junction of transistor Q1 160 between the previous read times are left in a small portion of the P-base A residue of the carrier. The charge remaining in the P-type base continues to flow with the current gain to the emitter of transistor Q1 160, plus the signal current Isc215 at the current reading time. This will form a ghost after trailing moving or bright objects. The residual charge will eventually disappear after a period of time due to recombination or minority carriers leaving the P-type base. The time behind the image is about minority carriers Lifetime (ie, about 100 milliseconds), and it can last several frames. Impurities can be added to the P-type base as a "lifetime killer" to reduce the reorganization time. Lifetime killer The difficulty is that it will increase the leakage current in the junction section and reduce the sensitivity of the image. The light sensor proposed in U.S. Patent No. 5,097,305 (Mead et al.) Has a photo-crystal and a capacitor coupled to the base of the photo-crystal. A pass transistor is placed at the emitter of the phototransistor to selectively couple the signal current to the sense amplifier. U.S. Patent No. 5,288,988 (Hashimo et al.) Describes a class of 9 j ------------ • equipment -------- order --------- line- (Please read the matter on the page of -r before filling out this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 425723 2 3 8 8 twf 1. Doc / 0 0 8 A '_ B7 V. Description of the invention (/ ^) Similar to the photo sensor circuit shown in Figures la, lb and lc. This element incorporates a MOS transistor in its light conversion element. When the MOS transistor is enabled, the above residual current is blocked by eliminating the residual charge from the base of the phototransistor. Therefore, the main object of the present invention is to provide an active pixel sensor element for converting light quantum energy into an electronic signal, indicating the magnitude of the light quantum energy. Another main object of the present invention is to provide an active pixel sensor device to avoid the problem of excessively bright images. Another main object of the present invention is to provide an active pixel sensor element for reducing residual charges to reduce the problem of image backwardness. According to the purpose of the present invention, an active pixel sensor element is proposed, which includes a photodiode, a bi-carrier transistor, and a MOS transistor. A photodiode has a cathode connected to a power supply and an anode. Light quanta impinge on the anode and generate a charge in the photodiode. The MOS transistor prevents the image from being too bright. The MOS transistor has a drain connected to the anode, source and gate of the photodiode. The gate is connected to the sensor control circuit to selectively enable and disable the MOS transistor to prevent or allow charge to flow through the MOS transistor. A bipolar transistor will amplify the charge and generate an electronic signal. The bipolar transistor has a collector connected to the power supply, a base connected to the source of the MOS transistor to receive charge when the MOS transistor is enabled, and an emitter connected to an external circuit to Electronic signals are transmitted to external circuits. The active pixel sensor further includes a parasitic MOS transistor. This parasitic MOS transistor has a drain, which is the anode of a photodiode; a source, ---------- I-- 衣 -------- Order ----- ---- Line. (Please read the precautions on the r side before filling out this page) This paper is inversely applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425723 A7 2 3 8 8 twfl.doc / 0 0 8 Βΐ_ 5. Description of the invention (name) is a row of active pixel sensors in an active pixel sensor array to obtain an adjacent active image Anode of the photodiode of the element sensor. The parasitic MOS transistor has a gate connected to a reset circuit to turn on the parasitic MOS transistor to reset the potential energy of the anodes of the photodiodes with the same potential level in a row. The image lag caused by the anode potential can be eliminated on the active pixel sensor after reset. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figures 1a and 1b A top view of a conventional light sensor cell and a cross-sectional view of a semiconductor substrate are shown. Figure lc shows the circuit diagrams of the conventional photo sensor cell in Figures la and lb. Figure Id shows the timing diagrams of the conventional light sensor cell in Figures la and lb. FIG. 2 is a circuit diagram of two cells of a conventional photo sensor array cell, which is used to explain that the image is too bright due to overflow current. FIG. 3 is a circuit diagram of a conventional photo sensor array cell, which is used to explain the image lag caused by the residual current. Figures 4a and 4b show a top view and a cross-sectional view of a semiconductor substrate of an active pixel sensor according to the present invention. Figure 4c shows the active pixel sensing of the present invention in Figures 4a and 4b (please read the precautions on the back before filling this page) Table -------- Order --------- -The paper size of the paper is applicable to the Chinese National Standard (CNS) A.1 specification (2〗 〇χ297 公 t) 425723 2388twfl.doc / 008 A7 B7 V. Description of the invention (4) 4-way diagram of the unit cell. FIG. 4d shows a timing diagram of the active pixel sensing unit cell of the present invention. FIG. 5 shows a circuit diagram of two unit cells of the active pixel sensor array unit cell of the present invention, which is used to explain the elimination of overflow current. Figures 6a, 6b, and 6c are top and cross-sectional views of three cell elements in the active pixel sensor array cell of the present invention, which are used to illustrate the photodiode reset operation to reduce image lag. Embodiments Please refer to Figs. 4a, 4b and 4c, which show a diagram according to a preferred embodiment of the present invention. To understand the structure of the active pixel sensor of the present invention. The fabrication of this device begins with a typical silicon wafer P-type substrate 305. Then, the surface of the P substrate 305 is masked and an N-type impurity is implanted as the N-type well 310. An insulating region or field oxide 315 grows to define the area of the active pixel cell. A mask is used to define the P-type anode 330 of the photodiode D1 420 in the area of the active pixel sensor cell. The N-well is in contact with the power source να and serves as the cathode of the photodiode D1 420. A photomask defines a region of the P-type base 320 of the bipolar transistor Q1 410 with a photomask in a second region among the regions of the active pixel sensor cell. A P-type impurity is implanted to form a P-type base 320. After that, a third region is masked in the region of the P-type base 320 and an N-type impurity is implanted as the emitter 325 of the bipolar transistor Q1 410. The collector of the bipolar transistor Q1 410 is an N-well 310. The P-type base 320 of the bipolar transistor Q1 410 and the P-type anode 330 of the photodiode D1 420 respectively form the source and drain of the MOS transistor Ml 415 (please read the precautions on the back before filling this page) Yiyi · -------- Order · -------- The size of the printed paper for the consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to the Chinese National Standard (CNS) A4 (21CJ X 297 mm) 2 3 B7 4 25 2388twfl .doc / 008 V. Description of the invention (/ 0) pole. The gate oxide layer 340 grows above the channel region 337 between the source 320 and the drain 330 = a polycrystalline silicon material 335 is placed on the gate oxide layer 340 and etched with uranium to form the gate of the MOS transistor Ml 415. An insulator is deposited on the surface of the semiconductor substrate to form a dielectric 350. A contact 327 with the N + emitter 325 is formed in an opening in the dielectric 350. A metal layer 355 is deposited to connect the emitter 325 of the transistor Q1 410 and the sense amplifier SA 425, which is an external circuit of an active pixel sensor array. The polycrystalline silicon substance 335 forming the gate of the MOS transistor Ml 415 is connected to the column enable circuit V_416, which is a sensor control circuit. Obviously, the process described above can be used to make a CMOS transistor. For example, polycrystalline silicon material 335 can be used as the gate of a CMOS transistor and used as an N-type implant of emitter 325 to form a source / drain region. Compared with the process used to fabricate the CCD method, the compatibility of manufacturing bipolar pixels with CMOS transistors has great advantages. Please refer to Figure 4d for the operating principle of the active pixel sensor cell. The photon quantum L1 334 hits the P-type anode 330 of the diode D1 420. Photon quantum L1 334 will give enough energy to generate an electron-hole pair, similar to photonic crystal Q1 60 described in Figures la, lb and lc. The hole moves to the P-type anode 330 of the photodiode D1 420. The electrons are collected at the cathode (N-well 310) of the photodiode D1 420 and removed by the power source Vcc. The positively charged holes are accumulated in the P-type anode 330 of the photodiode D1 420. The figure shows an increasing potential 487. The column enable circuits V ~ W416 are changed from a high potential to a low potential, and then the PMOS transistor Ml 415 is turned on. The charge Qs494 generated by the photon quantum LI 334 (image) is represented by the potential of the P-type anode V p.an (5de, which will be I --------- III -------- > — — — — — — — — ► (Please read the notes on the back before filling out this page) Duty printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed $ Paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) A7 B? 4 25 7 2 3
238 8 twf1 , doc/OOB 五、發明說明（（丨） 流入電晶體Q1 410的P型基極320形成基極電流IB1417。 基極電流IBI417會被電晶體以410放大並形成訊號電流 ISC412。在感測到訊號電流後，列致能電路v_416會回復 到低電位485，此時會有一殘餘電荷imduai496遺留在光 二極體D1 420的P型基極320。之後，光二極體D1 420 的P型陽極330會以下文所描述的重置操作重置到一電 位。 先請參照第5圖以了解本發明之主動式圖素感測器避 免圖素影像過亮的操作原理。圖素A43〇與圖素X435是主 動式圖素感測器陣列的兩個主動式圖素感測器。圖素A430 與圖素X435 —起連接到行460與共同的感測放大器SA 425。 該圖素A430觸發控制由列致能電路V_a440經由內連 線Row a450控制’且圖素X435觸發控制由列致能電路 Vrowx445經由內連線Rowx455控制。當列致能電路v_440 達高電位442，圖素A430會處於累積時間489。此時若光 量子L2 470撞擊圖素X435的光二極體D1 420b產生的累 積電荷被讀取，列致能電路V_x445會達低電位477以導 通PM0S電晶體Ml 415b =訊號電流Isc412b會從圖素X435 的電晶體Q1 410b之射極流出。 既使撞擊在光二極體D1 420a的光量子L1 465非常強， 也不會有第2圖中的滿溢電流1心95。？1«05電晶體141415& 會被無作用並且沒有電流會流過該電晶體Q1 420a。在極 強的光量子L1 465作用下電洞會累積在P型陽極上，快 (請先閱讀背面之注意事項再填寫本頁) f 1 I — — 訂 ---------_ 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規袼（21ϋχ 297公釐） A7 B7 4257 2 3 2388twfl.doc/008 五、發明說明（（V) 速地增加P型陽極的位能直到光二極體有一點點順向偏 壓，且一"滿溢電流'1會流向接在光二極體的陰極之電源 vcc。因此，總電流ItDt413不會有不相干的部分並且僅由 訊號電流Isc412b所構成。因爲感測放大器SA 425只會接 收適當大小的電流，所以可以防止影像過亮的形成。 請在參考第4a ’ 4b，4c和4d圖來了解重置作用。一 第二多晶矽物質360沉積在一層當閘極氧化層34〇成長時 所形成的絕緣物質365上。重置多晶矽360連接到一重置 電路V reset。重置電路V reset會施〜低電位480用以重置 多晶矽360,這將使由鄰近的主動式圖素感測器所形成的 寄生PMOS電晶體導通並且使所有P型陽極330重置到相 同的位能。關於寄生P-MOS電晶體與重置作用之細節，在 以下的第6a，6b和6c圖會加以說明。 第6a，6b和6c圖展現出在一由行與列構成的主動式 圖素感測器陣列中的一列上的三個主動式圖素感測器 500a，500b’ 500c。各該些主動式圖素感測器5〇〇a，5〇〇b， 500c 的 PMOS 電晶體 Ml 515a ’ 515b，515c 之閘極 505a， 505b，505c由該共同的列多晶矽物質335連接到列致能電 路Vr()W。重置多晶矽360與各主動式圖素感測器500a， 500b，500c的重置多晶矽360互相連接，並連接到重置控 制電路V reset535。在一列主動式圖素感測器的端末，一 邊緣接合區525由一 p型物質植入到半導體基底3〇5所形 成。該邊緣接合區連接到一偏壓電源Vp+33〇。當閘極氧化 層成長時所形成的氧化層365，會把重置多晶矽層360與 本紙張尺度適用中國國家標準（CNS)A4思格（21〇 X 297公g ) •Η------------ -------訂----I----線， (請^閱讀"面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 B7 425723 23B8twfl.doc/003 五、發明說明（/>) P-陽極 330a，330b，330c 隔絕。 各P型陽極330a，330b，330c做爲各主動式圖素感測 器 50〇a，500b，500c 的 PMOS 電晶體 Ml 515a ’ 515b ’ 515c 的汲極/源極。當重置電路\^set530偏壓至一低電位時， 各主動式圖素感測器500a，500b，500c的各該PMOS電晶 體Ml 515a，515b，515c會被導通並且所有的P型陽極 330a，330b，330c的電位被重置到與邊緣接合區525相同 的電位，偏壓電源Vp+530。 一 VT植入物535選擇性地被置於寄生電晶體P1 550 的通道區用以定義一寄生MOS電晶體P1 550的截止電位VT 到想要的値。該植入物可爲N型雜質或P型雜質端賴寄生 MOS電晶體P1 550是當作增強或缺乏MOS電晶體。 寄生電晶體P1 550動作，藉由重置一列所有P型陽極 的電位到與偏壓於電位Vp+530之邊緣接合區相同，會部分 消除影像落後的問題，如在傳統技術所描述的。 請再參考第4c和4d圖。在讀取動作期間，影像電荷 Qs494會流入P型基極做爲一基極電流，使電晶體Q1 410 的P型基極順向偏壓並且啓始雙載子電晶體動作。影像電 荷qs494形成的基極電流會被放大成爲射極電流Ise412， 其會流入感測放大器SA 425。感測放大器SA 425所集聚 的總電荷，被放大的影像電荷Qs494，用來表示撞擊在光 二極體D1 420的光量子L1 334的強度。 該光二極體D1 420之陽極面積設計成比雙載子電晶體 Q1 410之基極還大。這會迫使雙載子電晶體Q1 410之基 16 -r — — — — — —— — — — — ，衣·---丨 — II 訂·----I--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印*'1^ 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） A7 425723 2388twfl .doc/008 _B7_ 五、發明說明（从） 極具有和光二極體D1 420之陽極相同的電壓。注入的少 數載子（從射極注入的電子）被束縛在雙載子電晶體Q1 410 之基極，而且無法流經反向P型通道MOS電晶體而到達光 二極體D1 420之陽極。 一相應的圖素，具有一 PNP雙載子電晶體與一 NMOS 電晶體可藉由反轉該植入的矽物質之極性很容易地達成。 操作偏壓也會適當地反向。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 (請先閱讀背面之注意事項再填寫本頁> "-------訂·-------線 經濟部智慧財產局員工消費合作社印5^ 本紙張尺度適用中國國家標準（CNS)A4規格t210 X 297公釐）238 8 twf1, doc / OOB 5. Description of the invention ((丨) The P-type base 320 flowing into the transistor Q1 410 forms a base current IB1417. The base current IBI417 is amplified by the transistor at 410 and forms a signal current ISC412. In After the signal current is sensed, the column enable circuit v_416 will return to the low potential 485, and a residual charge imduai496 will be left on the P-type base 320 of the photodiode D1 420. After that, the P-type of the photodiode D1 420 will be left. The anode 330 will be reset to a potential as described in the following reset operation. Please refer to FIG. 5 to understand the operation principle of the active pixel sensor of the present invention to prevent the pixel image from being too bright. Pixel A43〇 and Pixel X435 is two active pixel sensors of the active pixel sensor array. Pixel A430 and pixel X435 are connected together to line 460 and a common sense amplifier SA 425. The pixel A430 triggers The control is controlled by the column enable circuit V_a440 via the interconnected Row a450 'and the pixel X435 trigger control is controlled by the column enable circuit Vrowx445 via the interconnected Rowx455. When the column enable circuit v_440 reaches a high potential 442, the pixel A430 will be at Accumulated time 489. At this time Ruoguang The accumulated charge generated by the L2 470 hitting the photodiode D1 420b of the pixel X435 is read, and the column enable circuit V_x445 will reach a low potential 477 to turn on the PM0S transistor Ml 415b = the signal current Isc412b will be removed from the pixel of the pixel X435 The emitter of Q1 410b flows out. Even if the photon quantum L1 465 hitting the photodiode D1 420a is very strong, there will be no overflow current in the second figure 1 center 95. 1 «05 transistor 141415 & And no current will flow through the transistor Q1 420a. Under the action of the extremely strong optical quantum L1 465, holes will accumulate on the P-type anode, fast (please read the precautions on the back before filling this page) f 1 I — — Order ---------_ Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed paper standards applicable to Chinese National Standard (CNS) A4 (21ϋχ 297 mm) A7 B7 4257 2 3 2388twfl.doc / 008 5. Description of the invention ((V) The potential energy of the P-type anode is increased rapidly until the photodiode has a slight forward bias, and a " full overflow current '1 will flow to the cathode connected to the photodiode Power supply vcc. Therefore, the total current ItDt413 does not have irrelevant parts and is only Current Isc412b formed. Since the sense amplifier SA 425 will receive the appropriate current magnitude, it is possible to prevent too bright image is formed. Please refer to Section 4a '4b, 4c and 4d reset to understand the role of FIG. A second polycrystalline silicon material 360 is deposited on a layer of insulating material 365 formed when the gate oxide layer 34 grows. The reset poly 360 is connected to a reset circuit V reset. The reset circuit V reset will apply ~ low potential 480 to reset the polycrystalline silicon 360, which will turn on the parasitic PMOS transistors formed by adjacent active pixel sensors and reset all P-type anodes 330 to the same Bit energy. The details of the parasitic P-MOS transistor and reset function will be explained in Figures 6a, 6b and 6c below. Figures 6a, 6b and 6c show three active pixel sensors 500a, 500b '500c on one column in an active pixel sensor array of rows and columns. Each of the active pixel sensors 500a, 500b, and 500c is a PMOS transistor Ml 515a ′ 515b, and the gates 505a, 505b, and 505c of the 515c are connected to the column by the common column polycrystalline silicon material 335. Enable the circuit Vr () W. The reset polysilicon 360 is connected to the reset polysilicon 360 of each of the active pixel sensors 500a, 500b, and 500c, and is connected to the reset control circuit V reset535. At the end of a row of active pixel sensors, an edge junction 525 is formed by implanting a p-type substance into the semiconductor substrate 305. The edge land is connected to a bias power source Vp + 33. The oxide layer 365 formed when the gate oxide layer grows will apply the reset polycrystalline silicon layer 360 and the paper size to the Chinese National Standard (CNS) A4 Sigma (21 × X 297 g) • Η ----- ------- ------- Order ---- I ---- line, (please ^ read " Notes on the front then fill out this page > Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed B7 425723 23B8twfl.doc / 003 V. Description of the invention (/ >) P-anodes 330a, 330b, 330c are isolated. Each P-type anode 330a, 330b, 330c is used as each active pixel sensor 50〇a , 500b, 500c PMOS transistor Ml 515a '515b' 515c Drain / Source. When the reset circuit \ set530 is biased to a low potential, the active pixel sensors 500a, 500b, 500c Each of the PMOS transistors Ml 515a, 515b, and 515c will be turned on and the potentials of all the P-type anodes 330a, 330b, and 330c are reset to the same potential as the edge junction region 525, and the bias power source Vp + 530. A VT plant The implant 535 is selectively placed in the channel region of the parasitic transistor P1 550 to define the cut-off potential VT of a parasitic MOS transistor P1 550 to the desired level. The implant can be The N-type impurity or P-type impurity terminal depends on the parasitic MOS transistor P1 550 as an enhanced or lacking MOS transistor. The parasitic transistor P1 550 operates by resetting the potential of all the P-type anodes in a row to the bias voltage Vp The edge joint area of +530 is the same, which will partially eliminate the problem of image backwardness, as described in the conventional technology. Please refer to Figures 4c and 4d again. During the reading operation, the image charge Qs494 will flow into the P-type base as A base current causes the P-type base of transistor Q1 410 to be forward biased and initiates the operation of the bipolar transistor. The base current formed by the image charge qs494 will be amplified into the emitter current Ise412, which will flow into the sense Sense amplifier SA 425. The total charge accumulated by the sense amplifier SA 425, the amplified image charge Qs494, is used to indicate the intensity of the photon quantum L1 334 impinging on the photodiode D1 420. The anode area design of the photodiode D1 420 It is larger than the base of the bipolar transistor Q1 410. This will force the base of the bipolar transistor Q1 410 16 -r — — — — — — — — — — —, II Order · ---- I --- (Please read the first Please fill in this page for the matters needing attention) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * '1 ^ This paper size applies to the Chinese National Standard (CNS) A4 specification (210x297 mm) A7 425723 2388twfl .doc / 008 _B7_ V. Description of the invention ( The secondary electrode has the same voltage as the anode of photodiode D1 420. The injected few carriers (electrons injected from the emitter) are bound to the base of the double-carrier transistor Q1 410, and cannot flow through the reverse P-channel MOS transistor to reach the anode of photodiode D1 420. A corresponding pixel with a PNP bipolar transistor and an NMOS transistor can be easily achieved by reversing the polarity of the implanted silicon material. The operating bias will also be appropriately reversed. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page> " --------- Order · ------- Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 ^ This paper size applies to China Standard (CNS) A4 size t210 X 297 mm)