TW405191B - Wafer level packaging method and device formed - Google Patents

Abstract

This invention provides a wafer level packaging method and device which is capable of simultaneously packaging all dies in the wafer and separating each die by slicing from the wafer to reduce the cost of packaging. According to the technology of this invention, a top surface is provided to form a silicon wafer having a plurality of integrated circuit dies wherein each die has at least one peripheral I/O bond pad on the insulating layer, and then a metal conductive post is formed on the forgoing I/O bond pad, and coat an elastic layer with sufficiently elasticity and insulation onto the surface of the foregoing wafer; and deposit and form a metal wire on the elastic layer, and then produce an I/O bond pad with matrix array at the corresponding end of the metal wire. Finally, a solder ball is formed on the foregoing solder bump on the I/O bond pad, wherein the foregoing elastic layer acts as a stress buffering layer to produce a highly reliable integrated circuit having low-cost integrated circuit device by the wafer level packaging.

Description

V. Description of the invention (1) [Scope of the invention] The present invention relates to a manufacturing method and structure of a wafer size structure, and particularly relates to a kind of integrated circuit-die which can simultaneously 'Packaging' and then cutting each die to reduce integrated circuit packaging-a cost-producing method. [Background of the Invention] In the current semiconductor element manufacturing technology, most of the semiconductor elements are obtained by increasing the circuit density of the semiconductor element or reducing the size of the element to obtain a high-density semiconductor element. As a result, the requirements for the reliability of packaging technology and interconnecting technology have become increasingly stringent. One of the methods used to package wafers is Flip-Chip Interconnection Method. This flip-chip bonding technology is A metal conductor is used to replace the lead frame, that is, a technology in which the bare crystal is connected to the substrate with the surface facing downward. The metal conductor may be metal bumps, tape-automated bonding ), Anisotropic conductive adhesives (Anisotropic Conductive Adhesives), polymer bumps (Polymer Bump), etc., among which metal bumps are the mainstream of flip-chip bonding technology, and the material of metal bumps is mainly tin-lead alloy, Therefore, metal bumps made of tin-lead alloy are also called tin-lead bumps. The method of using tin-lead bumps to connect ^ is A tin-lead bump contact is formed on the surface of the semiconductor die, and then the aluminum pad (A1 Bonding Pad) of the wafer is bonded to the substrate circuit by melting the tin bumps to complete the assembly. Among the above-mentioned tin boat bumps The contacts are arranged in a surface matrix (Area Array) on the surface of the grain, which can increase the

V. Description of the invention (2) 405191 --- Pitch to improve manufacturing yield. The current methods for producing tin-lead bumps include evaporation, electroplating, and printing. Under the requirements of reducing and reducing the pitch of tin-lead bumps, 'solder paste printing becomes more impractical when applied to fine-pitch products due to the following reasons. The first point is because of solder paste ( s〇 丨 der Paste) is formed by Flux and Solder alloy particles. Therefore, it is very difficult to control the composition and uniformity of the solder paste compound when the volume of tin-lead bumps is reduced. ' In response to this, it has been disclosed that a fine particle with a uniform particle size is disclosed to improve the above-mentioned disadvantages, but this will inevitably increase the production cost; the second point is when using this solder paste printing technology to manufacture the surface The density of the semiconductor element will make the distance between the two tin bumps very limited. This is because the volume of tin will decrease significantly when the tin changes from a fluid state to a solid state, which makes tin taste printed holes (Scree η ο ο 1 e As a result, the diameter will become larger than the actual tin-lead bumps. The drastic reduction in the volume of the above-mentioned tin-lead bumps will also cause difficulties in solder paste printing technology in manufacturing high-density components. Other technologies that can produce tin bumps include C4 (Controlled Col lapse Chip Connection Technique) and Electrodeposition Technology (Electrodeposition Technique), which have also been applied to the manufacture of semiconductor components in recent years, of which C 4 technology is limited In the manufacturing process, a molybdeum mask must be used to define the welding metallurgy layer (Under Bump Metallurgy, UBM, where UBM can also be called Ball Limiting Metallurgy, BLM) and the size of the tin bump.

-4115191- V. Explanation of the invention (3) The accuracy of the alignment of the molybdenum mask is not high, so it is difficult to manufacture the fine-pitch (that is, the pitch < 1 50 / zm) tin-lead bumps by C 4 technology. thing. Similarly, electroplating technology is also limited to the need to deposit a UB M layer and coat it on the process-a layer of thick photoresistor, because the thickness of the photoresistor is poor in alignment, so it also has the same Disadvantages of making fine-pitch tin-lead bumps. The manufacturing flow chart of conventionally used electroplating technology to manufacture tin-lead balls is shown in "Figure 1A ~ 1F". One of the conventional semiconductor structures 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 and its manufacturing method is to first form a solder on the top surface 16 of the silicon substrate 12. Bond pad 14 is used as an electrical connection between the silicon substrate 12 and the outer substrate circuit. The solder pad 14 is made of a conductive metal material (such as any one of aluminum, copper, aluminum alloy, or copper alloy). (1), and then deposit a protective layer 20 on the exposed areas of the silicon substrate 12 and the pads 14 to protect the pads 14, wherein the protective layer 20 is made of an insulating material such as oxidation Made of metal, nitride or organic material, and then using the lithography technology to open the window 22 to be electrically connected on the protective layer 20. Next, a UBM layer 26 is deposited on the top surface 24 of the protective layer 20 and the exposed top surface 18 of the bonding pad 14 (as shown in FIG. 1B). The UBM layer 26 is composed of an adhesion / diffusion barrier layer (Adhesion / Diffusion Barrier Layer) 30 and a wet layer (W e 11 ing Layer, also known as a tin dip layer) 2 8, wherein the adhesion / diffusion barrier layer 30 can be made of titanium (T i), titanium nitride (T i N), chromium (Cr), or one of other metal materials, and the wet layer 28 may be made of one of copper (Cu) or nickel (Ni) and other materials, wherein the UBM layer 26 is mainly used to improve The adhesion between the formed tin-lead ball and the top surface 18 of the solder pad 14

System 0 As shown in FIG. 1C, on the surface of + Bat + UM layer 26, a thick / resistive layer 34 is deposited on the window opening 8 of the tin oblique ball using this / flower step / /, first, The * formula / definition of / 1 is-to grow to form-tin fault bump 4. And ί 3 opens a hole 38 戸 / two in this window by electric ore method. Fortunately, Jiaojiao is maintained at about 50 ^. This— "Resistance: Whether ffi can be made into fine-pitch tin-lead The bump 40 is related to the problem; = r: r; rf, the worse the alignment accuracy is, the more difficult it is to make: Cheng = degree becomes positive t [relationship, πϊί: ;; and the thickness of J34 and tin fault bump 40 The high-level 34 must have a booster: the reliability of the tin boat bump 40, the spread of the photoresistance, and the degree of Α ΐ U =, so the photoresistive layer 34 must be selected carefully. The photoresist layer 34 is thick enough to form a tin-lead bump 40 in the shape of a mushroom, as shown in FIG. Photoresistance I 'After the tin-lead bump is formed at 4 °, the photoresist layer 34 is removed by wet wet removal (PPlng Pr0cess). At this time, both the tin-lead bump 40 and the UBM layer 26 remain intact. Then proceed to the next engraving: 柃 TombΪ Figure 1F *, in this step, the tin-lead bump 40 is used as an etching layer, and the mask is used to etch the excess ubm layer 2 6 dry using a wet etching process.

The Mine uses a reflow process (Refl0w Process) to heat the tin-lead bump 40 at a temperature higher than the tin-lead bump ^, so that the tin-lead bump 40 changes from solid to sad, and finally in the cooling process The tin-lead bump 40 is made into a spherical tin-lead ball 42 due to its own cohesion. At this step, the manufacturing of the tin-lead ball 42 is completed, as shown in FIG. 1F. In the past 4 years, the chip scale packages (Chip Scale Packages,

V. Description of the invention (5) CSP) has been regarded as a one-piece Compan Array) Packaging multiple things, the same method, and using this crystal traditional chip scale to provide a number of tighter packaging methods than circuit chip y. This mi It combines chip-size crystal packaging, which is larger than most purposes. -4 € 5191-a low-cost packaging technology for high-capacity manufacturing. 'One of the wafer-size packaging is by Tessera' They also call this technology as micro-BGA (Ball Grid, this mi cro-BGA packaging method is applied at the same time _ regular arrangement of the to-be-packaged cro-BGA packaging method located above the circuit board or substrate is a high-density packaging chip-on-chip assembly and surface adhesive packaging The advantage of this technology is that the packaging technology can package the entire chip at the same time without the need for special bonding processes such as forming tin-lead balls. In addition, the traditional four-sided square structure (Q uad FU t) technology can input / output contacts. Terminal It is absorbed in layers, so it can only be used in different ways. It can be used in the middle, and it can be installed in the middle, and it can be made with the PO material. nt ruler (I crystal of the flexible dielectric sheet can here, with soft soft neutral with one having

Outside the base and between the grains; the crystal is the layer in the BGec, but also slowed down to 0-, allow the expansion crnt expandable miou more hot and hot, and ce. The force-generating layer is also used as a production punch, and the Ur machinery is slow to color (S with the same equipment as the special force equipment should not be used. The number of skilled students is its production. The color of the expansion plate is sticky. Expansion of the watch and electrical equipment and the step-by-step structure make it possible to seal this rule when the equipment is installed. T) In the connection, the SM plate layer is in-phase packaged. k 有 ί m Electrically-containing soft blood C M is soft and soft in the interpositional layer and the intermediary layer 1 The surface of the surface of the lead surface of the tin sheet is sealed and welded. rc at ci e e bl qin i then X to e

V. Description of the invention (6) 405191 pieces, in which the thickness of the flexible circuit board is about 25 # ιη, which is composed of a polymer material such as polyimide and a silicon rubber layer with a thickness of about 150. Elastomeric Layer). This silicone elastomer layer can provide flexibility and flexibility in the triaxial direction to reduce the stress generated during the manufacturing process and the thermal expansion caused by the improper cooperation between the crystal grains and the substrate. Among them, in order to further reduce the cost of integrated circuit component packaging, the crystal grains on the surface of the crystal chip can be packaged at the same time, and the chips are cut after the packaging is completed. In this way, it not only has the advantages of chip packaging but also reduces the Packaging costs for bulk circuit die. Current integrated circuit chips are designed to have I / O pads in a peripheral array. For today's high-density semiconductor components, the pitch between the I / 〇 pads is constantly shrinking, so In order to improve the spacing between I / 0 pads, an I / O Pad Redistribution Process is often used to enable the I / O pads to be arranged from the peripheral matrix to the surface matrix. (Area Array) arrangement, and in the process of I / O pad redistribution, I / O pads are often extended from the periphery of the die to the middle of the die by a metal wire, in order to determine The reliability of the wafer will form a stress buffer layer under the metal line to buffer the stress generated during the manufacturing process. [Objective and Summary of the Invention] Therefore, the main object of the present invention is to provide a method for packaging integrated circuit components in a wafer-size assembly method to improve the shortcomings and disadvantages caused by conventional packaging integrated circuit components. Office.

V. Description of the Invention (7) 405191 Another object of the present invention is to provide a method for fabricating a wafer size structure, which comprises performing a I / 〇 pad re-arrangement process on a plurality of integrated circuit wafers. Another object of the present invention is to provide a method for fabricating a wafer size structure, which comprises depositing an elastic material as an insulating layer, thereby the insulating layer serves as a stress buffer to buffer the stress generated by the wafer during the manufacturing process. Another object of the present invention is to provide a manufacturing method of wafer size structure, which includes forming a plurality of metal lines on an insulating layer, whereby the metal lines connect the peripherally arranged I / 0 pads and the surface matrix. Arranged I / 0 solder pads. Another object of the present invention is to provide a method for fabricating a wafer size structure, which includes forming a plurality of I / 0 pads arranged in a surface matrix, and forming solder balls on each of the I / O pads. Another object of the present invention is to provide a method for fabricating a wafer-size structure, which includes forming a plurality of metal wires on an elastic layer having insulation properties, so that the influence of stress caused during the structure can be reduced. At the lowest level, another object of the present invention is to provide a method for fabricating a wafer size structure, which includes a plurality of integrated circuit wafers, and each integrated circuit wafer is formed with a metal wire in an elastic layer, thereby The metal wire is subjected to the I / 0 pad redistribution process so that the I / 0 pad can be changed from a peripheral arrangement to a surface matrix arrangement. A final object of the present invention is to provide a method for fabricating a wafer size structure, which includes an elastic layer having insulation properties. The elastic layer has

Page 10 V. Description of the invention (8) A sufficiently low Young's mode ′ s mol d u 1 u s) is used as a stress buffer layer for a plurality of metal wires. In order to achieve the above purpose, the method for wafer size fabrication disclosed in the present invention includes at least the following steps: providing a silicon wafer with a plurality of integrated circuits formed on the top surface thereof, and each integrated circuit The die has at least one first I / O pad formed on a first insulating layer; at least one conductive metal post (Metal Plug) made of a first conductive metal is formed on the first I / O pad and the bare pad is exposed on Outside; coating a second insulating layer with sufficient elasticity on the top of the silicon wafer so that one top surface of the conductive metal pillar can be exposed outside the second insulating layer; depositing a conductive layer on the second insulating layer On top of which the conductive layer is made of a second conductive metal; forming at least one metal wire, wherein the metal wire has a first end and a second end extending from the first end, and the first end is used for conducting metal pillars Forming an electrical connection; depositing a third insulating layer on top of the metal line; defining and exposing at least one second I / O pad at the second end of the metal line; and forming at least one solder ball on the second I / 〇 pad Above. Wherein, in the manufacturing step of forming the solder ball, the method further includes depositing a UBM layer on the second I / O pad; and placing the solder ball on the UBM layer or forming at least one layer in a pick and place manner. An opening is formed on the second I / 0 pad, and solder is deposited in the opening to form a solder bump; and the solder bump is reflowed to form a solder ball, wherein the solder bump is formed in the opening. The manufacturing method can be made by one of methods such as Screen Printing J, Screen Printing J, Stencil Printing, Electrodeposition, and Electroless Deposition.

Page 11 405191 V. Description of Invention (9). In the manufacturing method of the wafer size structure disclosed in the present invention, the second insulating layer is made of an elastic material with a sufficiently low Young's modulus, and the first I / 〇 pads are arranged in a peripheral matrix manner. The plurality of integrated circuit dies are on top of the plurality of integrated circuit dies, and the second I / 0 pads are arranged on the plurality of integrated circuit dies in a face matrix manner, and the first I / O pads and the second I / O The pads can be made of any one of aluminum (A1), copper (Cu), Ill alloy, and copper alloy, and the conductive metal pillars are formed by photolithography technology, which is made of aluminum, copper, The aluminum or copper alloy is one of the metals, and the conductive layer is made of aluminum, copper, or other metals. According to the above manufacturing method, the wafer size structure disclosed in the present invention includes at least: a silicon wafer having a plurality of integrated circuit dies on its top surface, wherein each integrated circuit die has at least one A first I / O pad formed on a first insulating layer; at least one conductive metal pillar made of a first conductive metal is exposed on the first I / O pad; and one is formed on the top of a wafer A second insulating layer with sufficient elasticity, wherein a top surface of one of the conductive metal pillars is exposed outside the second insulating layer; a conductive layer formed on top of the second insulating layer; at least one metal wire, wherein the metal wire has A first end and a second end extending from the first end, and the first end is used to form an electrical connection with the conductive metal pillar; a third insulating layer formed on top of the metal wire; at least one from the third insulating layer The exposed second I / O pad, wherein the second I / O pad is used to form an electrical connection with the second end of the metal wire; and at least one solder ball formed on the second I / 0 pad Where solder balls are used to communicate with the second I / O pads make electrical connections.

5. Description of the invention on page 12 (10) 405191 In the wafer size structure, the solder ball further includes a UBM layer, which is deposited on the second I / O pad. The two insulation layers are made of a material with sufficient elasticity, so the second insulation layer is also an elastic layer. At the same time, in the above structure, the first I / 0 pads are arranged on a plurality of integrated circuit grains in a peripheral matrix manner. Above, and the second I / 0 pads are arranged on a plurality of integrated circuit dies in a surface matrix manner. Although the manufacturing method of the wafer size structure of the present invention has been disclosed in the foregoing description, the foregoing manufacturing method is not unique and can be replaced by other embodiments. The manufacturing method at least includes: providing a top surface to form A silicon wafer having a plurality of integrated circuit dies, wherein each integrated circuit die has at least one I / 0 pad formed on a first insulating layer, and the I / 0 pads are arranged in a peripheral matrix A plurality of integrated circuit dies; forming at least one conductive metal pillar made of a first conductive metal on the first I / O pad exposed outside; and coating a second insulation with sufficient elasticity Layer on top of the wafer so that one top surface of the conductive metal pillar can be exposed outside the second insulating layer; depositing a conductive layer on top of the second insulating layer, wherein the conductive layer is made of a second conductive metal Forming at least one metal line, wherein the metal line has a first end and a second end extending from the first end, and the first end is used to form an electrical connection with the conductive metal pillar; depositing a third insulating layer on the metal line Define and expose at least one I / O pad arranged in a face matrix, wherein the I / O pad is used to form an electrical connection with the second end of the metal wire; and forming at least one solder ball on the I arranged in a face matrix / 0 above the welding pad. Among the manufacturing steps for forming a solder ball described above,

Page 13 V. Description of the invention (η) 405191 Before the solder ball, a U BM layer is deposited on top of the I / 0 pad. Of course, the above-mentioned manufacturing method further includes the following steps, such as coating an elastic material A second insulating layer formed by forming at least one I / 0 pad arranged in a peripheral matrix and an area matrix, and the I / 0 pad is made of aluminum metal, or is made of aluminum, copper, aluminum alloy or It is one of the conductive metals such as a copper alloy to form at least one conductive metal pillar. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Simplified description of the drawings] Section 1 A ~ Figure 1 F is a conventional manufacturing flow chart for the use of electroplating technology to manufacture tin-lead balls; and Figures 2 A to 2 N are cross-sectional views of each step of the manufacturing method of the wafer size configuration of the present invention. [Explanation of the embodiment] The manufacturing method of the wafer size structure disclosed in the present invention is to first apply a photoresist layer or other organic insulating layer on the wafer surface, and then use lithography to form the photoresist layer or the insulating layer. A column-shaped opening, and then a conductive metal is deposited on the column-shaped opening to form a conductive metal column, and then an insulating layer having sufficient elasticity is coated, and the top surface of the conductive metal column can be exposed by an etching process. In addition to the insulating layer, a metal line is then formed on this insulating layer to perform the I / 0 pad redistribution process so that the I / 0 pads can be changed from a peripheral matrix arrangement to a surface matrix arrangement, and finally to a surface A solder ball is formed over the I / 0 pads in a matrix arrangement. Up to this step, most of the wafer surface

Page 14 V. Description of the invention (12) 405191 integrated circuit die are packaged at the same time, and then as long as each die is cut, the subsequent bonding with the substrate circuit can be continued. In the following description, in order to distinguish the I / 〇 pads arranged in a peripheral matrix manner and the I / 〇 pads arranged in a surface matrix manner, the I / 〇 pads arranged in a peripheral matrix manner are specifically referred to as the first I / 〇 pads. 〇 Pads, I / O pads arranged in a face matrix manner are called second I / O pads. In the present invention, in order to extend the I / O pads from the periphery of the die to the middle of the die, An I / 0 pad is extended from the periphery of the integrated circuit die to the center of the die through a metal wire, and is used as an electrical connection between the first I / O pad and the second I / O pad. An insulating layer is formed below the metal line, and the insulating layer has sufficient elasticity to be used as a stress buffer layer. The present invention further discloses a wafer-sized structure manufactured according to the above manufacturing method. The structure has a plurality of metal wires to extend the I / 0 pads from the periphery of the integrated circuit die to the center of the die. The plurality of metal wires are formed on a stress buffer layer. The stress buffer layer is made of an elastic material and is deposited on the top of the integrated circuit die. Metal pillars are connected from the integrated circuit wafer to the external circuit board, wherein the connection to the external circuit board is via solder pads and solder balls arranged in a surface matrix. In the manufacturing method disclosed in the present invention, a UBM layer must be formed over the I / O pads by a deposition and patterning process before forming solder balls over the pads arranged in a face matrix. The method of implanting solder balls on the corresponding ends of the metal wires can be formed by one of low-cost manufacturing techniques such as screen printing, stencil printing, electrodeposition, or electroless deposition.

Page 15 V. Description of the invention (13) 405191 The insulating layer described is preferably made of an elastic material, such as silicon rubber (Si 1 ic ο ne Rubber) or fluorosilicone rubber, and this The Young's modulus of the elastic material is preferably lower than 20 M pa, and the conductive metal pillar is preferably formed by photolithography technology and it is made of aluminum, copper, aluminum alloy or copper alloy. One of the metals such as gold , And I / O pads are made of one of metals such as aluminum or copper. According to the method disclosed above, the manufacturing method of the entire wafer size configuration will be described with the cross-sectional view of each manufacturing step shown in "Figures 2a ~ 2N". The manufacturing method is as follows: First, please Refer to "Figure 2A." ? As shown, an -I / O pad 54 is formed on the top surface 52 of the silicon substrate 58 and an insulating layer is deposited on the top surface 52) 5 6 so that the solder pad 54 is buried in the dielectric substrate. ， = 二 = 54 is made of conductive ... or copper and then connected to the electricity 'while the top surface 62 of the I / O pad 54 of the I / O pad 54 can be exposed; in addition, the dielectric layer 56 should be defined so that Display, and then by coating d) one of the f-plane views such as "Figure 2B" Laminating and other methods such as P1 (Printing) or deposition-organic material layer 64 'this-organic materials, welding The top of the pad 54 is made of a material such as polyimide, which can be a photoresist or =, preferably 75 ^. The thickness of the :: product is 25, as shown in the figure, among which organic materials. The layer 64 preferably has a cross-sectional view such as "2C for subsequent definition procedures. After Shen = made of light-sensitive materials to define this organic material layer 64 and the use of wet or organic material layer 64, the top surface 6 2 Can be exposed to the outside, =, the second c-type surface is engraved with 丨 / 〇 pad 5 4 to form a columnar opening 66, which ;; Figure 4 as

40Siyi V. Description of the invention (14) "Figure 2D". Please refer to "Figure 2E". In this step, a conductive metal is deposited in the columnar opening 6 6 by electroplating to form a conductive metal pillar 68. The conductive metal pillar 68 is used for welding with I / O. The pad 54 forms an electrical connection, and the above-mentioned conductive metal pillar may be one of metals such as aluminum, copper, aluminum alloy, or copper alloy. The method for forming the conductive metal pillar 68 is not limited to electroplating, and may be other methods, such as screen printing. It is made by printing or stencil printing. After the conductive metal pillar 68 is formed and planarized, the organic material layer 64 is removed by etching. The cross-sectional view is shown in FIG. 2F. Please refer to "Figure 2G". This step plays a very important role in the manufacturing method disclosed in the present invention. In this step, the thickness of a layer is about 25 / by one of the methods of printing, coating or bonding. The elastic material layer 70 of zm ~ 150 / im covers the top of the wafer 50. The elastic material layer 70 is made of one of silicon rubber or fluorosilicone rubber, and the elastic material layer 70 The top surface 7 2 is subjected to an etch-back process so that the top surface 7 4 of the conductive metal pillar 6 8 can be exposed outside, and the cross-sectional view thereof is shown in FIG. 2; and then the next step is performed. A photolithography technique is used to extend the I / 0 pads 5 4 from the periphery of the integrated circuit die to the center of the die, that is, by performing an I / 0 pad redistribution process. In order that a plurality of I / O pads (not labeled) can be arranged on the surface of the die in the form of a surface matrix, when conducting the I / 0 pad redistribution process, a conductive layer must be deposited on top of the elastic material layer 70 Layer 7 6 can be deposited by sputtering to form a highly conductive metal (such as copper or aluminum) The top layer 70 of resilient material, such as a cross-sectional view of "FIG. 2 I of" shown, followed by conventional photolithography defined

Page 17 V. Description of the invention (15) The conductive layer 76 is shown as forming a metal. In this step, it is arranged on the surface of the die by surrounding the die of the integrated circuit. Please continue to refer to "2K deposits on top of wafer 50 to make the ends of metal wires 7 8 bare at this point. Please note that the center area of the formed die is arranged in a matrix manner on the die. The UBM layer 86 defines the top of the UBM pad 84. The method of section layer 8 6 can be made by wireless 7 8 and its cross-sectional view is the extension of the metal wire 7 8 as shown in Figure 2J. 5 4 can be extended to the center of the grain, and in a 2L pattern of the surface matrix. ”After the metal wire 78 is formed, the dielectric layer 82 is then defined to expose the dielectric layer 82—new 1 / 〇 Pad 84, the new I / O pad 84 must be located in the integrated circuit to make the new I / O pad 84 face to face; then deposit a layer 86 on top of the dielectric layer 82 to Make the U BM layer 86 deposited on the new 丨 / 〇 welding as shown in the "2M picture", where one of the methods such as deposition plating or thin film deposition is achieved, please refer to "2N picture" after the UBM layer 86 is formed , Using electroplating technology or any other known technology to form a solder bump (not labeled) above the U BM layer 86, and then reflow the solder Block form a cohesive force due to the solder balls 90 'coming to this all the grains to be encapsulated while the wafer 5 billion. In the manufacturing method disclosed in the present invention, the metal wire 7 8 is used as the 丨 / 〇 pad 5 4 arranged in a peripheral matrix and the new I / 0 pad 5 8 arranged in a face matrix. The electrical connection, and the bullet located below the metal wire 7 8 == the material layer 70 is used as a stress buffer layer, and a highly reliable packaged integrated circuit chip can be manufactured by the stress buffer layer.

Page 18 V. Description of the invention (16) 405191 The above-mentioned elastic material layer 70 is made of a lower Young's modulus elastic material, but the Young's modulus cannot be too low, because when the Young's modulus is too low This means that the nature of this material tends to be brittle, so when metal wires 68 are formed on top of this material, this material is prone to cracking due to its inability to withstand large stresses. It also causes reliability concerns. [Effects of the invention] According to the wafer size configuration method disclosed in the present invention, the die on the wafer surface can be packaged at the same time, and the die is cut after the package is completed. In this way, not only can the knowledge be improved The problems caused by die packaging can greatly reduce the packaging cost of integrated circuit die. [Explanation of Schematic Symbols] 10 .............................. ............... + # 体 名 吉 才 冓 12 ................. ........... silicon substrate 14 .............. ........................................ ..... welding 16 ............... ............. page 18 ............ ................. page Φ 20 ... ........................................ ..... protective layer 2 2 ............. ........... see f 24 ......... ......................................... τΐ ® 26 ........................................ ............. UBM layer 28 ........................ ............. m 'Ά ^ 30 ...... .................................................................................................................. ........................................ ... photoresist layer

38 ................................................. ...........% fn -fL

Page 19 V. Description of the invention (17) 405 191 4 ............................ ............. II ^ a ik 4 2 ........... ................. Pin 50 50 ... ........................................ ........... aBa Β 5 2 ......... ................ Top Φ 54 ...... ............................ I / O pad 5 6 ....................................... ............. Medium layer 5 8 ............... ...................... Silicon substrate 6 2 .............. ........................................ ..τΐ ® 64 ............................. ............ Organic material layer 66 ........................ .......................... 68 ...................................................................................... ........................................ Elastic material layer 72 ............... .... IS ® 7 4 .............. ..................... ττ φ 76 ..... ........................................ ........ ^ t Μ 7 8 ........................... ................ Golden Elephant 82 ... .......................... f yf 84 ..... ........................................ .. New I / O Pad 86 ............... ............ UBM ^ 90 ............... ............ n ^

Page 20

Claims (1)

6. Application Patent Scope 405191 1. A manufacturing method of wafer size structure, including at least the following steps: Provide a silicon wafer with a plurality of integrated circuit crystal grains formed on the top surface, each of which The chip has at least one first I / O pad formed on a first insulating layer; forming at least one conductive metal pillar made of a first conductive metal, and the at least one first I / O pad is exposed outside Coating a second insulating layer with sufficient elasticity on the top surface of the silicon wafer, and allowing one of the top surfaces of the at least one conductive metal pillar to be exposed outside the second insulating layer; depositing a conductive layer On top of the second insulating layer, wherein the conductive layer is made of a second conductive metal; forming at least one metal line, wherein the at least one metal line has a first end and a second end extending from the first end End, and the first end is for forming an electrical connection with the at least one conductive metal pillar; depositing a third insulating layer on top of the at least one metal line; defining and exposing at least one second I / 0 pad on The second end of the at least one metal wire; and forming at least one solder ball above the at least one second I / 0 pad. 2. The method for fabricating a wafer size structure as described in item 1 of the patent application scope, wherein before forming the at least one solder ball, further comprising depositing a UBM layer on the at least one second I / O pad. 3. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the step of forming the at least one solder ball includes at least: Page 21 VI. Application patent range 405191 Deposit a UBM layer on the at least one second I / O pad; form at least one opening on the at least one second I / O pad, and deposit a solder Forming at least one solder-bump in the at least one opening; and reflowing the at least one solder bump to form at least one solder ball. 4. The method for fabricating a wafer size structure as described in item 1 of the scope of patent application, wherein the step of forming the at least one solder ball includes at least: depositing a U BM layer on the at least one second I / 0 pad A solder ball is pre-formed on the UBM layer; and a solder ball is placed on the UBM layer by a ball planting method. 5. The manufacturing method of the wafer size structure as described in item 3 of the scope of the patent application, wherein the at least one opening can be made by one of processes such as screen printing, stencil printing, electrodeposition or electroless deposition. The at least one solder bump is formed. 6. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the second insulating layer is made of an elastic material. 7. The manufacturing method of wafer size structure as described in item 1 of the scope of patent application, wherein the second insulating layer is made of an elastic material having a Young's modulus of at least less than 20 M p a. 8. The method for fabricating a wafer size structure as described in item 1 of the scope of the patent application, wherein the at least one first I / 0 pad is arranged along the peripheral edge of the integrated circuit die. 9. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the at least one second I / 0 pad is arranged in a surface matrix manner Page 22 6. The scope of patent application 405191 is on the surface of these integrated circuit die. 10. The method for fabricating a wafer size structure as described in item 1 of the scope of the patent application, wherein the at least one second I / O pad and the surroundings of the integrated circuit crystal grains have a sufficient distance. 11. The method for fabricating a wafer size structure as described in item 1 of the scope of the patent application, wherein the at least one conductive metal is formed by a photolithography technique. 1 2. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the at least one first I / 0 pad and the at least one second I / O pad are made of aluminum, copper, A method for making a wafer size structure as described in Item 1 of the patent application scope, wherein the at least one conductive metal pillar is made of aluminum, copper, aluminum alloy, or aluminum alloy or copper alloy. It is formed by one of metals such as copper alloy. 14. The method for fabricating a wafer size structure as described in item 1 of the scope of patent application, wherein the conductive layer is formed of aluminum, copper or other metals. 15. A wafer-sized structure including at least: a silicon wafer having a plurality of integrated circuit dies formed on a top surface thereof, wherein each of the integrated circuit dies has at least one formed on a first A first I / 0 pad of an insulating layer; at least one conductive metal pillar made of a first conductive metal exposed on the at least one first I / O pad; one formed on a top surface of the wafer And a sufficiently elastic second insulation layer, wherein a top surface of one of the at least one conductive metal pillar is exposed from the second insulation Page 23 405191 6. Outside the patent application layer; a conductive layer formed on top of the second insulating layer; at least one metal wire, wherein the metal wire has a first end and a first end extending from the first end A second end, and the first end is used to form an electrical connection with the at least one conductive metal pillar; a third insulating layer formed on top of the at least one metal line; at least one exposed from the third insulating layer A second I / O pad, wherein the at least one second I / 0 pad is used to form an electrical connection with the second end of the at least one metal wire; and at least one formed on the at least one second I / 0 pad Solder balls above the pads, wherein the at least one solder ball is used to form an electrical connection with the at least one second I / O pad. 16. The wafer-size structure described in item 15 of the scope of patent application, wherein the at least one solder ball includes a UBM layer, and the UBM layer is deposited on the at least one second I / O pad on. 17. The structure of the wafer size structure described in item 15 of the scope of patent application, wherein the second insulating layer is an elastic material layer. 18. The wafer-size structure described in item 15 of the scope of patent application, wherein the at least one first I / 0 pad is arranged in a peripheral matrix manner, and the at least one second I / 0 pad is The pads are arranged in a face matrix manner. 19. A method for fabricating a wafer size structure, at least comprising: providing a silicon wafer having a plurality of integrated circuit dies formed on a top surface thereof, wherein each of the integrated circuit dies has at least one formed on a silicon wafer; I / 0 pads of the first insulation layer, and the at least one I / 0 pad is arranged in a peripheral matrix Page 24 405101 6. The scope of the patent application is listed on the integrated circuit die; forming at least one conductive metal pillar made of a first conductive metal on the at least one I / 0 pad; coating A second insulating layer having sufficient elasticity on the top of the wafer, and a top surface of the at least one conductive metal pillar can be exposed outside the second insulating layer; and a conductive layer is deposited on the second insulating layer Top, wherein the conductive layer is made of a second conductive metal; forming at least one metal line, wherein the at least one metal line has a first end and a second end extending from the first end, and the first A terminal is used to form an electrical connection with the at least one conductive metal pillar; a third insulating layer is deposited on top of the at least one metal line; at least one I / 0 pad arranged in a face matrix is defined and exposed, wherein the at least one I The / 0 pad is used to form an electrical connection with the second end of the at least one metal wire; and is formed above the at least one I / 0 pad with at least one solder ball arranged in a face matrix. 20. The method for manufacturing a wafer size structure as described in item 19 of the scope of patent application, wherein the step of forming the at least one solder ball further includes depositing a U BM layer on the at least one I arranged in a face matrix. / 0 pads above. 21. The method for manufacturing a wafer size structure as described in item 19 of the scope of patent application, further comprising coating a second insulating layer made of an elastic material. 2 2. The manufacturing method of wafer size structure as described in item 19 of the scope of patent application 6. Application method of patent range 405191, which further includes forming at least one I / 0 pad arranged in a peripheral matrix and an area matrix, and the at least one I / 0 pad is made of aluminum, copper, Made of one of metals such as aluminum alloy or copper alloy. 23. The manufacturing method of wafer size assembly as described in item 19 of the scope of patent application, wherein the at least one conductive metal pillar is formed of one of metals such as aluminum, copper, aluminum alloy or copper alloy. Page 26