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TW360945B - Semiconductor apparatus and manufacturing method - Google Patents

Semiconductor apparatus and manufacturing method

Info

Publication number
TW360945B
TW360945B TW086113393A TW86113393A TW360945B TW 360945 B TW360945 B TW 360945B TW 086113393 A TW086113393 A TW 086113393A TW 86113393 A TW86113393 A TW 86113393A TW 360945 B TW360945 B TW 360945B
Authority
TW
Taiwan
Prior art keywords
trench
manufacturing
semiconductor apparatus
substrate
oxide film
Prior art date
Application number
TW086113393A
Other languages
Chinese (zh)
Inventor
Hideo Miura
Makoto Kitano
Shuji Ikeda
Norio Suzuki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW360945B publication Critical patent/TW360945B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

In a semiconductor device having a trench isolation structure, after a trench surface is selectively oxidized by a conventional method, an oxidation prevention film is removed, the entire surface of the substrate is again oxidized while only an oxide film on the substrate or trench surface is exposed, and a radius of curvature is provided to the shape of the oxide film near the trench upper end portion.
TW086113393A 1996-09-17 1997-09-15 Semiconductor apparatus and manufacturing method TW360945B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24444596A JP3611226B2 (en) 1996-09-17 1996-09-17 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
TW360945B true TW360945B (en) 1999-06-11

Family

ID=17118766

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113393A TW360945B (en) 1996-09-17 1997-09-15 Semiconductor apparatus and manufacturing method

Country Status (6)

Country Link
JP (1) JP3611226B2 (en)
KR (1) KR100425064B1 (en)
CN (1) CN1161837C (en)
MY (1) MY129438A (en)
TW (1) TW360945B (en)
WO (1) WO1998012742A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW388100B (en) * 1997-02-18 2000-04-21 Hitachi Ulsi Eng Corp Semiconductor deivce and process for producing the same
US5811346A (en) * 1997-04-14 1998-09-22 Vlsi Technology, Inc. Silicon corner rounding in shallow trench isolation process
WO1999044223A2 (en) * 1998-02-27 1999-09-02 Lsi Logic Corporation Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing
JP3917327B2 (en) * 1999-06-01 2007-05-23 株式会社ルネサステクノロジ Method and apparatus for manufacturing semiconductor device
JP2004095886A (en) 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
TWI253746B (en) * 2003-10-24 2006-04-21 Fujitsu Ltd Semiconductor device group and method for fabricating the same, and semiconductor device and method for fabricating the same
KR100584776B1 (en) * 2004-03-05 2006-05-29 삼성전자주식회사 Method of forming active structure, isolation and MOS transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234534A (en) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd Manufacture of semiconductor element
KR960006714B1 (en) * 1990-05-28 1996-05-22 가부시끼가이샤 도시바 Semiconductor device fabrication process
JP3208575B2 (en) * 1991-08-16 2001-09-17 ソニー株式会社 Semiconductor device manufacturing method
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
JP2955459B2 (en) * 1993-12-20 1999-10-04 株式会社東芝 Method for manufacturing semiconductor device
US5536675A (en) * 1993-12-30 1996-07-16 Intel Corporation Isolation structure formation for semiconductor circuit fabrication

Also Published As

Publication number Publication date
JPH1092919A (en) 1998-04-10
MY129438A (en) 2007-04-30
KR100425064B1 (en) 2004-03-30
CN1231064A (en) 1999-10-06
WO1998012742A1 (en) 1998-03-26
JP3611226B2 (en) 2005-01-19
KR20000036123A (en) 2000-06-26
CN1161837C (en) 2004-08-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees